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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /* | |
22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
23 | * Supported commands/modes are: | |
24 | * - flash read | |
25 | * - flash write | |
26 | * - flash ID read | |
27 | * - sector erase | |
28 | * - chip erase | |
29 | * - unlock bypass command | |
30 | * - CFI queries | |
31 | * | |
32 | * It does not support flash interleaving. | |
33 | * It does not implement boot blocs with reduced size | |
34 | * It does not implement software data protection as found in many real chips | |
35 | * It does not implement erase suspend/resume commands | |
36 | * It does not implement multiple sectors erase | |
37 | */ | |
38 | ||
87ecb68b PB |
39 | #include "hw.h" |
40 | #include "flash.h" | |
41 | #include "qemu-timer.h" | |
42 | #include "block.h" | |
29133e9a FB |
43 | |
44 | //#define PFLASH_DEBUG | |
45 | #ifdef PFLASH_DEBUG | |
46 | #define DPRINTF(fmt, args...) \ | |
47 | do { \ | |
29133e9a FB |
48 | printf("PFLASH: " fmt , ##args); \ |
49 | } while (0) | |
50 | #else | |
51 | #define DPRINTF(fmt, args...) do { } while (0) | |
52 | #endif | |
53 | ||
54 | struct pflash_t { | |
55 | BlockDriverState *bs; | |
71db710f BS |
56 | target_phys_addr_t base; |
57 | uint32_t sector_len; | |
4fbd24ba AZ |
58 | uint32_t chip_len; |
59 | int mappings; | |
29133e9a FB |
60 | int width; |
61 | int wcycle; /* if 0, the flash is read normally */ | |
62 | int bypass; | |
63 | int ro; | |
64 | uint8_t cmd; | |
65 | uint8_t status; | |
66 | uint16_t ident[4]; | |
6725070d | 67 | uint16_t unlock_addr[2]; |
29133e9a FB |
68 | uint8_t cfi_len; |
69 | uint8_t cfi_table[0x52]; | |
70 | QEMUTimer *timer; | |
71 | ram_addr_t off; | |
72 | int fl_mem; | |
9c9bb6c8 | 73 | int rom_mode; |
29133e9a FB |
74 | void *storage; |
75 | }; | |
76 | ||
4fbd24ba AZ |
77 | static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
78 | { | |
79 | unsigned long phys_offset = pfl->fl_mem; | |
80 | int i; | |
81 | ||
82 | if (rom_mode) | |
83 | phys_offset |= pfl->off | IO_MEM_ROMD; | |
9c9bb6c8 | 84 | pfl->rom_mode = rom_mode; |
4fbd24ba AZ |
85 | |
86 | for (i = 0; i < pfl->mappings; i++) | |
87 | cpu_register_physical_memory(pfl->base + i * pfl->chip_len, | |
88 | pfl->chip_len, phys_offset); | |
89 | } | |
90 | ||
29133e9a FB |
91 | static void pflash_timer (void *opaque) |
92 | { | |
93 | pflash_t *pfl = opaque; | |
94 | ||
95 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
96 | /* Reset flash */ | |
97 | pfl->status ^= 0x80; | |
98 | if (pfl->bypass) { | |
99 | pfl->wcycle = 2; | |
100 | } else { | |
4fbd24ba | 101 | pflash_register_memory(pfl, 1); |
29133e9a FB |
102 | pfl->wcycle = 0; |
103 | } | |
104 | pfl->cmd = 0; | |
105 | } | |
106 | ||
71db710f | 107 | static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) |
29133e9a | 108 | { |
71db710f | 109 | uint32_t boff; |
29133e9a FB |
110 | uint32_t ret; |
111 | uint8_t *p; | |
112 | ||
e96efcfc | 113 | DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset); |
29133e9a | 114 | ret = -1; |
9c9bb6c8 AZ |
115 | if (pfl->rom_mode) { |
116 | offset -= (uint32_t)(long)pfl->storage; | |
117 | /* Lazy reset of to ROMD mode */ | |
118 | if (pfl->wcycle == 0) | |
119 | pflash_register_memory(pfl, 1); | |
120 | } else | |
121 | offset -= pfl->base; | |
4fbd24ba | 122 | offset &= pfl->chip_len - 1; |
29133e9a FB |
123 | boff = offset & 0xFF; |
124 | if (pfl->width == 2) | |
125 | boff = boff >> 1; | |
126 | else if (pfl->width == 4) | |
127 | boff = boff >> 2; | |
128 | switch (pfl->cmd) { | |
129 | default: | |
130 | /* This should never happen : reset state & treat it as a read*/ | |
131 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
132 | pfl->wcycle = 0; | |
133 | pfl->cmd = 0; | |
134 | case 0x80: | |
135 | /* We accept reads during second unlock sequence... */ | |
136 | case 0x00: | |
137 | flash_read: | |
138 | /* Flash area read */ | |
139 | p = pfl->storage; | |
140 | switch (width) { | |
141 | case 1: | |
142 | ret = p[offset]; | |
143 | // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret); | |
144 | break; | |
145 | case 2: | |
146 | #if defined(TARGET_WORDS_BIGENDIAN) | |
147 | ret = p[offset] << 8; | |
148 | ret |= p[offset + 1]; | |
149 | #else | |
150 | ret = p[offset]; | |
151 | ret |= p[offset + 1] << 8; | |
152 | #endif | |
153 | // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret); | |
154 | break; | |
155 | case 4: | |
156 | #if defined(TARGET_WORDS_BIGENDIAN) | |
157 | ret = p[offset] << 24; | |
158 | ret |= p[offset + 1] << 16; | |
159 | ret |= p[offset + 2] << 8; | |
160 | ret |= p[offset + 3]; | |
161 | #else | |
162 | ret = p[offset]; | |
163 | ret |= p[offset + 1] << 8; | |
29133e9a FB |
164 | ret |= p[offset + 2] << 16; |
165 | ret |= p[offset + 3] << 24; | |
166 | #endif | |
167 | // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret); | |
168 | break; | |
169 | } | |
170 | break; | |
171 | case 0x90: | |
172 | /* flash ID read */ | |
173 | switch (boff) { | |
174 | case 0x00: | |
175 | case 0x01: | |
176 | ret = pfl->ident[boff & 0x01]; | |
177 | break; | |
178 | case 0x02: | |
179 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
180 | break; | |
181 | case 0x0E: | |
182 | case 0x0F: | |
183 | if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) | |
184 | goto flash_read; | |
185 | ret = pfl->ident[2 + (boff & 0x01)]; | |
186 | break; | |
187 | default: | |
188 | goto flash_read; | |
189 | } | |
e96efcfc | 190 | DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret); |
29133e9a FB |
191 | break; |
192 | case 0xA0: | |
193 | case 0x10: | |
194 | case 0x30: | |
195 | /* Status register read */ | |
196 | ret = pfl->status; | |
197 | DPRINTF("%s: status %x\n", __func__, ret); | |
198 | /* Toggle bit 6 */ | |
199 | pfl->status ^= 0x40; | |
200 | break; | |
201 | case 0x98: | |
202 | /* CFI query mode */ | |
203 | if (boff > pfl->cfi_len) | |
204 | ret = 0; | |
205 | else | |
206 | ret = pfl->cfi_table[boff]; | |
207 | break; | |
208 | } | |
209 | ||
210 | return ret; | |
211 | } | |
212 | ||
213 | /* update flash content on disk */ | |
5fafdf24 | 214 | static void pflash_update(pflash_t *pfl, int offset, |
29133e9a FB |
215 | int size) |
216 | { | |
217 | int offset_end; | |
218 | if (pfl->bs) { | |
219 | offset_end = offset + size; | |
220 | /* round to sectors */ | |
221 | offset = offset >> 9; | |
222 | offset_end = (offset_end + 511) >> 9; | |
5fafdf24 | 223 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), |
29133e9a FB |
224 | offset_end - offset); |
225 | } | |
226 | } | |
227 | ||
71db710f | 228 | static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, |
29133e9a FB |
229 | int width) |
230 | { | |
71db710f | 231 | uint32_t boff; |
29133e9a FB |
232 | uint8_t *p; |
233 | uint8_t cmd; | |
234 | ||
95d1f3ed JM |
235 | cmd = value; |
236 | if (pfl->cmd != 0xA0 && cmd == 0xF0) { | |
237 | #if 0 | |
238 | DPRINTF("%s: flash reset asked (%02x %02x)\n", | |
239 | __func__, pfl->cmd, cmd); | |
240 | #endif | |
241 | goto reset_flash; | |
242 | } | |
243 | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__, | |
244 | offset, value, width, pfl->wcycle); | |
9c9bb6c8 AZ |
245 | /* WARNING: when the memory area is in ROMD mode, the offset is a |
246 | ram offset, not a physical address */ | |
247 | if (pfl->rom_mode) | |
71db710f | 248 | offset -= (uint32_t)(long)pfl->storage; |
29133e9a FB |
249 | else |
250 | offset -= pfl->base; | |
4fbd24ba | 251 | offset &= pfl->chip_len - 1; |
3b46e624 | 252 | |
e96efcfc JM |
253 | DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__, |
254 | offset, value, width); | |
29133e9a FB |
255 | boff = offset & (pfl->sector_len - 1); |
256 | if (pfl->width == 2) | |
257 | boff = boff >> 1; | |
258 | else if (pfl->width == 4) | |
259 | boff = boff >> 2; | |
260 | switch (pfl->wcycle) { | |
261 | case 0: | |
9c9bb6c8 AZ |
262 | /* Set the device in I/O access mode if required */ |
263 | if (pfl->rom_mode) | |
264 | pflash_register_memory(pfl, 0); | |
29133e9a FB |
265 | /* We're in read mode */ |
266 | check_unlock0: | |
267 | if (boff == 0x55 && cmd == 0x98) { | |
268 | enter_CFI_mode: | |
269 | /* Enter CFI query mode */ | |
270 | pfl->wcycle = 7; | |
271 | pfl->cmd = 0x98; | |
272 | return; | |
273 | } | |
6725070d | 274 | if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
e96efcfc | 275 | DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n", |
6725070d | 276 | __func__, boff, cmd, pfl->unlock_addr[0]); |
29133e9a FB |
277 | goto reset_flash; |
278 | } | |
279 | DPRINTF("%s: unlock sequence started\n", __func__); | |
280 | break; | |
281 | case 1: | |
282 | /* We started an unlock sequence */ | |
283 | check_unlock1: | |
6725070d | 284 | if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
e96efcfc JM |
285 | DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__, |
286 | boff, cmd); | |
29133e9a FB |
287 | goto reset_flash; |
288 | } | |
289 | DPRINTF("%s: unlock sequence done\n", __func__); | |
290 | break; | |
291 | case 2: | |
292 | /* We finished an unlock sequence */ | |
6725070d | 293 | if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
e96efcfc JM |
294 | DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__, |
295 | boff, cmd); | |
29133e9a FB |
296 | goto reset_flash; |
297 | } | |
298 | switch (cmd) { | |
299 | case 0x20: | |
300 | pfl->bypass = 1; | |
301 | goto do_bypass; | |
302 | case 0x80: | |
303 | case 0x90: | |
304 | case 0xA0: | |
305 | pfl->cmd = cmd; | |
306 | DPRINTF("%s: starting command %02x\n", __func__, cmd); | |
307 | break; | |
308 | default: | |
309 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); | |
310 | goto reset_flash; | |
311 | } | |
312 | break; | |
313 | case 3: | |
314 | switch (pfl->cmd) { | |
315 | case 0x80: | |
316 | /* We need another unlock sequence */ | |
317 | goto check_unlock0; | |
318 | case 0xA0: | |
e96efcfc | 319 | DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n", |
29133e9a FB |
320 | __func__, offset, value, width); |
321 | p = pfl->storage; | |
322 | switch (width) { | |
323 | case 1: | |
324 | p[offset] &= value; | |
325 | pflash_update(pfl, offset, 1); | |
326 | break; | |
327 | case 2: | |
328 | #if defined(TARGET_WORDS_BIGENDIAN) | |
329 | p[offset] &= value >> 8; | |
330 | p[offset + 1] &= value; | |
331 | #else | |
332 | p[offset] &= value; | |
333 | p[offset + 1] &= value >> 8; | |
334 | #endif | |
335 | pflash_update(pfl, offset, 2); | |
336 | break; | |
337 | case 4: | |
338 | #if defined(TARGET_WORDS_BIGENDIAN) | |
339 | p[offset] &= value >> 24; | |
340 | p[offset + 1] &= value >> 16; | |
341 | p[offset + 2] &= value >> 8; | |
342 | p[offset + 3] &= value; | |
343 | #else | |
344 | p[offset] &= value; | |
345 | p[offset + 1] &= value >> 8; | |
346 | p[offset + 2] &= value >> 16; | |
347 | p[offset + 3] &= value >> 24; | |
348 | #endif | |
349 | pflash_update(pfl, offset, 4); | |
350 | break; | |
351 | } | |
352 | pfl->status = 0x00 | ~(value & 0x80); | |
353 | /* Let's pretend write is immediate */ | |
354 | if (pfl->bypass) | |
355 | goto do_bypass; | |
356 | goto reset_flash; | |
357 | case 0x90: | |
358 | if (pfl->bypass && cmd == 0x00) { | |
359 | /* Unlock bypass reset */ | |
360 | goto reset_flash; | |
361 | } | |
362 | /* We can enter CFI query mode from autoselect mode */ | |
363 | if (boff == 0x55 && cmd == 0x98) | |
364 | goto enter_CFI_mode; | |
365 | /* No break here */ | |
366 | default: | |
367 | DPRINTF("%s: invalid write for command %02x\n", | |
368 | __func__, pfl->cmd); | |
369 | goto reset_flash; | |
370 | } | |
371 | case 4: | |
372 | switch (pfl->cmd) { | |
373 | case 0xA0: | |
374 | /* Ignore writes while flash data write is occuring */ | |
375 | /* As we suppose write is immediate, this should never happen */ | |
376 | return; | |
377 | case 0x80: | |
378 | goto check_unlock1; | |
379 | default: | |
380 | /* Should never happen */ | |
381 | DPRINTF("%s: invalid command state %02x (wc 4)\n", | |
382 | __func__, pfl->cmd); | |
383 | goto reset_flash; | |
384 | } | |
385 | break; | |
386 | case 5: | |
387 | switch (cmd) { | |
388 | case 0x10: | |
6725070d | 389 | if (boff != pfl->unlock_addr[0]) { |
e96efcfc | 390 | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n", |
29133e9a FB |
391 | __func__, offset); |
392 | goto reset_flash; | |
393 | } | |
394 | /* Chip erase */ | |
395 | DPRINTF("%s: start chip erase\n", __func__); | |
4fbd24ba | 396 | memset(pfl->storage, 0xFF, pfl->chip_len); |
29133e9a | 397 | pfl->status = 0x00; |
4fbd24ba | 398 | pflash_update(pfl, 0, pfl->chip_len); |
29133e9a | 399 | /* Let's wait 5 seconds before chip erase is done */ |
5fafdf24 | 400 | qemu_mod_timer(pfl->timer, |
29133e9a FB |
401 | qemu_get_clock(vm_clock) + (ticks_per_sec * 5)); |
402 | break; | |
403 | case 0x30: | |
404 | /* Sector erase */ | |
405 | p = pfl->storage; | |
406 | offset &= ~(pfl->sector_len - 1); | |
e96efcfc JM |
407 | DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__, |
408 | offset); | |
29133e9a FB |
409 | memset(p + offset, 0xFF, pfl->sector_len); |
410 | pflash_update(pfl, offset, pfl->sector_len); | |
411 | pfl->status = 0x00; | |
412 | /* Let's wait 1/2 second before sector erase is done */ | |
5fafdf24 | 413 | qemu_mod_timer(pfl->timer, |
29133e9a FB |
414 | qemu_get_clock(vm_clock) + (ticks_per_sec / 2)); |
415 | break; | |
416 | default: | |
417 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); | |
418 | goto reset_flash; | |
419 | } | |
420 | pfl->cmd = cmd; | |
421 | break; | |
422 | case 6: | |
423 | switch (pfl->cmd) { | |
424 | case 0x10: | |
425 | /* Ignore writes during chip erase */ | |
426 | return; | |
427 | case 0x30: | |
428 | /* Ignore writes during sector erase */ | |
429 | return; | |
430 | default: | |
431 | /* Should never happen */ | |
432 | DPRINTF("%s: invalid command state %02x (wc 6)\n", | |
433 | __func__, pfl->cmd); | |
434 | goto reset_flash; | |
435 | } | |
436 | break; | |
437 | case 7: /* Special value for CFI queries */ | |
438 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); | |
439 | goto reset_flash; | |
440 | default: | |
441 | /* Should never happen */ | |
442 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); | |
443 | goto reset_flash; | |
444 | } | |
445 | pfl->wcycle++; | |
446 | ||
447 | return; | |
448 | ||
449 | /* Reset flash */ | |
450 | reset_flash: | |
29133e9a FB |
451 | pfl->bypass = 0; |
452 | pfl->wcycle = 0; | |
453 | pfl->cmd = 0; | |
454 | return; | |
455 | ||
456 | do_bypass: | |
457 | pfl->wcycle = 2; | |
458 | pfl->cmd = 0; | |
459 | return; | |
460 | } | |
461 | ||
462 | ||
463 | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) | |
464 | { | |
465 | return pflash_read(opaque, addr, 1); | |
466 | } | |
467 | ||
468 | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) | |
469 | { | |
470 | pflash_t *pfl = opaque; | |
471 | ||
472 | return pflash_read(pfl, addr, 2); | |
473 | } | |
474 | ||
475 | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) | |
476 | { | |
477 | pflash_t *pfl = opaque; | |
478 | ||
479 | return pflash_read(pfl, addr, 4); | |
480 | } | |
481 | ||
482 | static void pflash_writeb (void *opaque, target_phys_addr_t addr, | |
483 | uint32_t value) | |
484 | { | |
485 | pflash_write(opaque, addr, value, 1); | |
486 | } | |
487 | ||
488 | static void pflash_writew (void *opaque, target_phys_addr_t addr, | |
489 | uint32_t value) | |
490 | { | |
491 | pflash_t *pfl = opaque; | |
492 | ||
493 | pflash_write(pfl, addr, value, 2); | |
494 | } | |
495 | ||
496 | static void pflash_writel (void *opaque, target_phys_addr_t addr, | |
497 | uint32_t value) | |
498 | { | |
499 | pflash_t *pfl = opaque; | |
500 | ||
501 | pflash_write(pfl, addr, value, 4); | |
502 | } | |
503 | ||
504 | static CPUWriteMemoryFunc *pflash_write_ops[] = { | |
505 | &pflash_writeb, | |
506 | &pflash_writew, | |
507 | &pflash_writel, | |
508 | }; | |
509 | ||
510 | static CPUReadMemoryFunc *pflash_read_ops[] = { | |
511 | &pflash_readb, | |
512 | &pflash_readw, | |
513 | &pflash_readl, | |
514 | }; | |
515 | ||
516 | /* Count trailing zeroes of a 32 bits quantity */ | |
517 | static int ctz32 (uint32_t n) | |
518 | { | |
519 | int ret; | |
520 | ||
521 | ret = 0; | |
522 | if (!(n & 0xFFFF)) { | |
523 | ret += 16; | |
524 | n = n >> 16; | |
525 | } | |
526 | if (!(n & 0xFF)) { | |
527 | ret += 8; | |
528 | n = n >> 8; | |
529 | } | |
530 | if (!(n & 0xF)) { | |
531 | ret += 4; | |
532 | n = n >> 4; | |
533 | } | |
534 | if (!(n & 0x3)) { | |
535 | ret += 2; | |
536 | n = n >> 2; | |
537 | } | |
538 | if (!(n & 0x1)) { | |
539 | ret++; | |
540 | n = n >> 1; | |
541 | } | |
542 | #if 0 /* This is not necessary as n is never 0 */ | |
543 | if (!n) | |
544 | ret++; | |
545 | #endif | |
546 | ||
547 | return ret; | |
548 | } | |
549 | ||
88eeee0a | 550 | pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
cf6d9118 | 551 | BlockDriverState *bs, uint32_t sector_len, |
4fbd24ba | 552 | int nb_blocs, int nb_mappings, int width, |
88eeee0a | 553 | uint16_t id0, uint16_t id1, |
6725070d AZ |
554 | uint16_t id2, uint16_t id3, |
555 | uint16_t unlock_addr0, uint16_t unlock_addr1) | |
29133e9a FB |
556 | { |
557 | pflash_t *pfl; | |
4fbd24ba | 558 | int32_t chip_len; |
29133e9a | 559 | |
4fbd24ba | 560 | chip_len = sector_len * nb_blocs; |
29133e9a | 561 | /* XXX: to be fixed */ |
95d1f3ed | 562 | #if 0 |
29133e9a FB |
563 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
564 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
565 | return NULL; | |
95d1f3ed | 566 | #endif |
29133e9a FB |
567 | pfl = qemu_mallocz(sizeof(pflash_t)); |
568 | if (pfl == NULL) | |
569 | return NULL; | |
570 | pfl->storage = phys_ram_base + off; | |
95d1f3ed JM |
571 | pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops, |
572 | pfl); | |
29133e9a | 573 | pfl->off = off; |
4fbd24ba AZ |
574 | pfl->base = base; |
575 | pfl->chip_len = chip_len; | |
576 | pfl->mappings = nb_mappings; | |
577 | pflash_register_memory(pfl, 1); | |
29133e9a FB |
578 | pfl->bs = bs; |
579 | if (pfl->bs) { | |
580 | /* read the initial flash content */ | |
4fbd24ba | 581 | bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
29133e9a FB |
582 | } |
583 | #if 0 /* XXX: there should be a bit to set up read-only, | |
584 | * the same way the hardware does (with WP pin). | |
585 | */ | |
586 | pfl->ro = 1; | |
587 | #else | |
588 | pfl->ro = 0; | |
589 | #endif | |
590 | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); | |
29133e9a | 591 | pfl->sector_len = sector_len; |
29133e9a FB |
592 | pfl->width = width; |
593 | pfl->wcycle = 0; | |
594 | pfl->cmd = 0; | |
595 | pfl->status = 0; | |
596 | pfl->ident[0] = id0; | |
597 | pfl->ident[1] = id1; | |
598 | pfl->ident[2] = id2; | |
599 | pfl->ident[3] = id3; | |
6725070d AZ |
600 | pfl->unlock_addr[0] = unlock_addr0; |
601 | pfl->unlock_addr[1] = unlock_addr1; | |
29133e9a FB |
602 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
603 | pfl->cfi_len = 0x52; | |
604 | /* Standard "QRY" string */ | |
605 | pfl->cfi_table[0x10] = 'Q'; | |
606 | pfl->cfi_table[0x11] = 'R'; | |
607 | pfl->cfi_table[0x12] = 'Y'; | |
608 | /* Command set (AMD/Fujitsu) */ | |
609 | pfl->cfi_table[0x13] = 0x02; | |
610 | pfl->cfi_table[0x14] = 0x00; | |
611 | /* Primary extended table address (none) */ | |
612 | pfl->cfi_table[0x15] = 0x00; | |
613 | pfl->cfi_table[0x16] = 0x00; | |
614 | /* Alternate command set (none) */ | |
615 | pfl->cfi_table[0x17] = 0x00; | |
616 | pfl->cfi_table[0x18] = 0x00; | |
617 | /* Alternate extended table (none) */ | |
618 | pfl->cfi_table[0x19] = 0x00; | |
619 | pfl->cfi_table[0x1A] = 0x00; | |
620 | /* Vcc min */ | |
621 | pfl->cfi_table[0x1B] = 0x27; | |
622 | /* Vcc max */ | |
623 | pfl->cfi_table[0x1C] = 0x36; | |
624 | /* Vpp min (no Vpp pin) */ | |
625 | pfl->cfi_table[0x1D] = 0x00; | |
626 | /* Vpp max (no Vpp pin) */ | |
627 | pfl->cfi_table[0x1E] = 0x00; | |
628 | /* Reserved */ | |
629 | pfl->cfi_table[0x1F] = 0x07; | |
630 |