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3cbee15b JM |
1 | /* |
2 | * QEMU PowerMac emulation shared definitions and prototypes | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #if !defined(__PPC_MAC_H__) | |
26 | #define __PPC_MAC_H__ | |
27 | ||
022c62cb | 28 | #include "exec/memory.h" |
95ed3b7c | 29 | #include "hw/sysbus.h" |
07a7484e | 30 | #include "hw/ide/internal.h" |
0d09e41a | 31 | #include "hw/input/adb.h" |
1e39101c | 32 | |
3cbee15b JM |
33 | /* SMP is not enabled, for now */ |
34 | #define MAX_CPUS 1 | |
35 | ||
bba831e8 | 36 | #define BIOS_SIZE (1024 * 1024) |
3cbee15b | 37 | #define BIOS_FILENAME "ppc_rom.bin" |
3cbee15b | 38 | #define NVRAM_SIZE 0x2000 |
e5d01b06 | 39 | #define PROM_FILENAME "openbios-ppc" |
992e5acd | 40 | #define PROM_ADDR 0xfff00000 |
3cbee15b JM |
41 | |
42 | #define KERNEL_LOAD_ADDR 0x01000000 | |
b9e17a34 | 43 | #define KERNEL_GAP 0x00100000 |
3cbee15b | 44 | |
7fa9ae1a BS |
45 | #define ESCC_CLOCK 3686400 |
46 | ||
3cbee15b | 47 | /* Cuda */ |
45fa67fb AF |
48 | #define TYPE_CUDA "cuda" |
49 | #define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA) | |
50 | ||
51 | /** | |
52 | * CUDATimer: | |
53 | * @counter_value: counter value at load time | |
54 | */ | |
55 | typedef struct CUDATimer { | |
56 | int index; | |
57 | uint16_t latch; | |
58 | uint16_t counter_value; | |
59 | int64_t load_time; | |
60 | int64_t next_irq_time; | |
61 | QEMUTimer *timer; | |
62 | } CUDATimer; | |
63 | ||
64 | /** | |
65 | * CUDAState: | |
66 | * @b: B-side data | |
67 | * @a: A-side data | |
68 | * @dirb: B-side direction (1=output) | |
69 | * @dira: A-side direction (1=output) | |
70 | * @sr: Shift register | |
71 | * @acr: Auxiliary control register | |
72 | * @pcr: Peripheral control register | |
73 | * @ifr: Interrupt flag register | |
74 | * @ier: Interrupt enable register | |
75 | * @anh: A-side data, no handshake | |
76 | * @last_b: last value of B register | |
77 | * @last_acr: last value of ACR register | |
78 | */ | |
79 | typedef struct CUDAState { | |
80 | /*< private >*/ | |
81 | SysBusDevice parent_obj; | |
82 | /*< public >*/ | |
83 | ||
84 | MemoryRegion mem; | |
85 | /* cuda registers */ | |
86 | uint8_t b; | |
87 | uint8_t a; | |
88 | uint8_t dirb; | |
89 | uint8_t dira; | |
90 | uint8_t sr; | |
91 | uint8_t acr; | |
92 | uint8_t pcr; | |
93 | uint8_t ifr; | |
94 | uint8_t ier; | |
95 | uint8_t anh; | |
96 | ||
293c867d | 97 | ADBBusState adb_bus; |
45fa67fb AF |
98 | CUDATimer timers[2]; |
99 | ||
100 | uint32_t tick_offset; | |
101 | ||
102 | uint8_t last_b; | |
103 | uint8_t last_acr; | |
104 | ||
105 | int data_in_size; | |
106 | int data_in_index; | |
107 | int data_out_index; | |
108 | ||
109 | qemu_irq irq; | |
110 | uint8_t autopoll; | |
111 | uint8_t data_in[128]; | |
112 | uint8_t data_out[16]; | |
113 | QEMUTimer *adb_poll_timer; | |
114 | } CUDAState; | |
3cbee15b JM |
115 | |
116 | /* MacIO */ | |
d037834a AF |
117 | #define TYPE_OLDWORLD_MACIO "macio-oldworld" |
118 | #define TYPE_NEWWORLD_MACIO "macio-newworld" | |
07a7484e AF |
119 | |
120 | #define TYPE_MACIO_IDE "macio-ide" | |
121 | #define MACIO_IDE(obj) OBJECT_CHECK(MACIOIDEState, (obj), TYPE_MACIO_IDE) | |
122 | ||
123 | typedef struct MACIOIDEState { | |
124 | /*< private >*/ | |
125 | SysBusDevice parent_obj; | |
126 | /*< public >*/ | |
127 | ||
128 | qemu_irq irq; | |
129 | qemu_irq dma_irq; | |
130 | ||
131 | MemoryRegion mem; | |
132 | IDEBus bus; | |
133 | BlockDriverAIOCB *aiocb; | |
134 | } MACIOIDEState; | |
135 | ||
136 | void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table); | |
137 | void macio_ide_register_dma(MACIOIDEState *ide, void *dbdma, int channel); | |
138 | ||
d037834a | 139 | void macio_init(PCIDevice *dev, |
07a7484e | 140 | MemoryRegion *pic_mem, |
07a7484e | 141 | MemoryRegion *escc_mem); |
3cbee15b | 142 | |
3cbee15b | 143 | /* Heathrow PIC */ |
23c5e4ca | 144 | qemu_irq *heathrow_pic_init(MemoryRegion **pmem, |
3cbee15b JM |
145 | int nb_cpus, qemu_irq **irqs); |
146 | ||
147 | /* Grackle PCI */ | |
0e655047 | 148 | #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost" |
1e39101c | 149 | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, |
aee97b84 AK |
150 | MemoryRegion *address_space_mem, |
151 | MemoryRegion *address_space_io); | |
3cbee15b JM |
152 | |
153 | /* UniNorth PCI */ | |
aee97b84 AK |
154 | PCIBus *pci_pmac_init(qemu_irq *pic, |
155 | MemoryRegion *address_space_mem, | |
156 | MemoryRegion *address_space_io); | |
157 | PCIBus *pci_pmac_u3_init(qemu_irq *pic, | |
158 | MemoryRegion *address_space_mem, | |
159 | MemoryRegion *address_space_io); | |
3cbee15b JM |
160 | |
161 | /* Mac NVRAM */ | |
95ed3b7c AF |
162 | #define TYPE_MACIO_NVRAM "macio-nvram" |
163 | #define MACIO_NVRAM(obj) \ | |
164 | OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM) | |
165 | ||
166 | typedef struct MacIONVRAMState { | |
167 | /*< private >*/ | |
168 | SysBusDevice parent_obj; | |
169 | /*< public >*/ | |
170 | ||
171 | uint32_t size; | |
172 | uint32_t it_shift; | |
173 | ||
174 | MemoryRegion mem; | |
175 | uint8_t *data; | |
176 | } MacIONVRAMState; | |
3cbee15b | 177 | |
3cbee15b | 178 | void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); |
3743cca7 AF |
179 | uint8_t macio_nvram_read(MacIONVRAMState *s, uint32_t addr); |
180 | void macio_nvram_write(MacIONVRAMState *s, uint32_t addr, uint8_t val); | |
3cbee15b | 181 | #endif /* !defined(__PPC_MAC_H__) */ |