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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
9a64fbe4 | 23 | */ |
75610155 | 24 | #include "hw/hw.h" |
0d09e41a PB |
25 | #include "hw/timer/m48t59.h" |
26 | #include "hw/i386/pc.h" | |
27 | #include "hw/char/serial.h" | |
28 | #include "hw/block/fdc.h" | |
1422e32d | 29 | #include "net/net.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
0d09e41a | 31 | #include "hw/isa/isa.h" |
75610155 AF |
32 | #include "hw/pci/pci.h" |
33 | #include "hw/pci/pci_host.h" | |
0d09e41a | 34 | #include "hw/ppc/ppc.h" |
75610155 | 35 | #include "hw/boards.h" |
1de7afc9 | 36 | #include "qemu/log.h" |
75610155 AF |
37 | #include "hw/ide.h" |
38 | #include "hw/loader.h" | |
0d09e41a PB |
39 | #include "hw/timer/mc146818rtc.h" |
40 | #include "hw/isa/pc87312.h" | |
4be74634 | 41 | #include "sysemu/block-backend.h" |
9c17d615 | 42 | #include "sysemu/arch_init.h" |
97c42c3c | 43 | #include "sysemu/qtest.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
97c42c3c | 45 | #include "elf.h" |
9fddaa0c | 46 | |
9a64fbe4 | 47 | //#define HARD_DEBUG_PPC_IO |
a541f297 | 48 | //#define DEBUG_PPC_IO |
9a64fbe4 | 49 | |
fe33cc71 JM |
50 | /* SMP is not enabled, for now */ |
51 | #define MAX_CPUS 1 | |
52 | ||
e4bcb14c TS |
53 | #define MAX_IDE_BUS 2 |
54 | ||
bba831e8 | 55 | #define BIOS_SIZE (1024 * 1024) |
b6b8bd18 FB |
56 | #define BIOS_FILENAME "ppc_rom.bin" |
57 | #define KERNEL_LOAD_ADDR 0x01000000 | |
58 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 59 | |
9a64fbe4 FB |
60 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
61 | #define DEBUG_PPC_IO | |
62 | #endif | |
63 | ||
64 | #if defined (HARD_DEBUG_PPC_IO) | |
001faf32 | 65 | #define PPC_IO_DPRINTF(fmt, ...) \ |
9a64fbe4 | 66 | do { \ |
8fec2b8c | 67 | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ |
001faf32 | 68 | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 | 69 | } else { \ |
001faf32 | 70 | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 FB |
71 | } \ |
72 | } while (0) | |
73 | #elif defined (DEBUG_PPC_IO) | |
0bf9e31a BS |
74 | #define PPC_IO_DPRINTF(fmt, ...) \ |
75 | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) | |
9a64fbe4 | 76 | #else |
001faf32 | 77 | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
9a64fbe4 FB |
78 | #endif |
79 | ||
64201201 | 80 | /* Constants for devices init */ |
a541f297 FB |
81 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
82 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
83 | static const int ide_irq[2] = { 13, 13 }; | |
84 | ||
85 | #define NE2000_NB_MAX 6 | |
86 | ||
87 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
88 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 89 | |
64201201 | 90 | /* ISA IO ports bridge */ |
9a64fbe4 FB |
91 | #define PPC_IO_BASE 0x80000000 |
92 | ||
64201201 FB |
93 | /* PowerPC control and status registers */ |
94 | #if 0 // Not used | |
95 | static struct { | |
96 | /* IDs */ | |
97 | uint32_t veni_devi; | |
98 | uint32_t revi; | |
99 | /* Control and status */ | |
100 | uint32_t gcsr; | |
101 | uint32_t xcfr; | |
102 | uint32_t ct32; | |
103 | uint32_t mcsr; | |
104 | /* General purpose registers */ | |
105 | uint32_t gprg[6]; | |
106 | /* Exceptions */ | |
107 | uint32_t feen; | |
108 | uint32_t fest; | |
109 | uint32_t fema; | |
110 | uint32_t fecl; | |
111 | uint32_t eeen; | |
112 | uint32_t eest; | |
113 | uint32_t eecl; | |
114 | uint32_t eeint; | |
115 | uint32_t eemck0; | |
116 | uint32_t eemck1; | |
117 | /* Error diagnostic */ | |
118 | } XCSR; | |
64201201 | 119 | |
36081602 | 120 | static void PPC_XCSR_writeb (void *opaque, |
a8170e5e | 121 | hwaddr addr, uint32_t value) |
64201201 | 122 | { |
90e189ec BS |
123 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
124 | value); | |
64201201 FB |
125 | } |
126 | ||
36081602 | 127 | static void PPC_XCSR_writew (void *opaque, |
a8170e5e | 128 | hwaddr addr, uint32_t value) |
9a64fbe4 | 129 | { |
90e189ec BS |
130 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
131 | value); | |
9a64fbe4 FB |
132 | } |
133 | ||
36081602 | 134 | static void PPC_XCSR_writel (void *opaque, |
a8170e5e | 135 | hwaddr addr, uint32_t value) |
9a64fbe4 | 136 | { |
90e189ec BS |
137 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
138 | value); | |
9a64fbe4 FB |
139 | } |
140 | ||
a8170e5e | 141 | static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) |
64201201 FB |
142 | { |
143 | uint32_t retval = 0; | |
9a64fbe4 | 144 | |
90e189ec BS |
145 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
146 | retval); | |
9a64fbe4 | 147 | |
64201201 FB |
148 | return retval; |
149 | } | |
150 | ||
a8170e5e | 151 | static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) |
9a64fbe4 | 152 | { |
64201201 FB |
153 | uint32_t retval = 0; |
154 | ||
90e189ec BS |
155 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
156 | retval); | |
64201201 FB |
157 | |
158 | return retval; | |
9a64fbe4 FB |
159 | } |
160 | ||
a8170e5e | 161 | static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) |
9a64fbe4 FB |
162 | { |
163 | uint32_t retval = 0; | |
164 | ||
90e189ec BS |
165 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
166 | retval); | |
9a64fbe4 FB |
167 | |
168 | return retval; | |
169 | } | |
170 | ||
0c90c52f AK |
171 | static const MemoryRegionOps PPC_XCSR_ops = { |
172 | .old_mmio = { | |
173 | .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, | |
174 | .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, | |
175 | }, | |
176 | .endianness = DEVICE_LITTLE_ENDIAN, | |
9a64fbe4 FB |
177 | }; |
178 | ||
b6b8bd18 | 179 | #endif |
9a64fbe4 | 180 | |
64201201 | 181 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
c227f099 | 182 | typedef struct sysctrl_t { |
c4781a51 | 183 | qemu_irq reset_irq; |
31688246 | 184 | Nvram *nvram; |
64201201 FB |
185 | uint8_t state; |
186 | uint8_t syscontrol; | |
da9b266b | 187 | int contiguous_map; |
9a183916 | 188 | qemu_irq contiguous_map_irq; |
fb3444b8 | 189 | int endian; |
c227f099 | 190 | } sysctrl_t; |
9a64fbe4 | 191 | |
64201201 FB |
192 | enum { |
193 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 194 | }; |
9a64fbe4 | 195 | |
c227f099 | 196 | static sysctrl_t *sysctrl; |
9a64fbe4 | 197 | |
a541f297 | 198 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 199 | { |
c227f099 | 200 | sysctrl_t *sysctrl = opaque; |
64201201 | 201 | |
aae9366a JM |
202 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
203 | addr - PPC_IO_BASE, val); | |
9a64fbe4 FB |
204 | switch (addr) { |
205 | case 0x0092: | |
206 | /* Special port 92 */ | |
207 | /* Check soft reset asked */ | |
64201201 | 208 | if (val & 0x01) { |
c4781a51 JM |
209 | qemu_irq_raise(sysctrl->reset_irq); |
210 | } else { | |
211 | qemu_irq_lower(sysctrl->reset_irq); | |
9a64fbe4 FB |
212 | } |
213 | /* Check LE mode */ | |
64201201 | 214 | if (val & 0x02) { |
fb3444b8 FB |
215 | sysctrl->endian = 1; |
216 | } else { | |
217 | sysctrl->endian = 0; | |
9a64fbe4 FB |
218 | } |
219 | break; | |
64201201 FB |
220 | case 0x0800: |
221 | /* Motorola CPU configuration register : read-only */ | |
222 | break; | |
223 | case 0x0802: | |
224 | /* Motorola base module feature register : read-only */ | |
225 | break; | |
226 | case 0x0803: | |
227 | /* Motorola base module status register : read-only */ | |
228 | break; | |
9a64fbe4 | 229 | case 0x0808: |
64201201 FB |
230 | /* Hardfile light register */ |
231 | if (val & 1) | |
232 | sysctrl->state |= STATE_HARDFILE; | |
233 | else | |
234 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
235 | break; |
236 | case 0x0810: | |
237 | /* Password protect 1 register */ | |
31688246 HP |
238 | if (sysctrl->nvram != NULL) { |
239 | NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); | |
240 | (k->toggle_lock)(sysctrl->nvram, 1); | |
241 | } | |
9a64fbe4 FB |
242 | break; |
243 | case 0x0812: | |
244 | /* Password protect 2 register */ | |
31688246 HP |
245 | if (sysctrl->nvram != NULL) { |
246 | NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); | |
247 | (k->toggle_lock)(sysctrl->nvram, 2); | |
248 | } | |
9a64fbe4 FB |
249 | break; |
250 | case 0x0814: | |
64201201 | 251 | /* L2 invalidate register */ |
c68ea704 | 252 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
253 | break; |
254 | case 0x081C: | |
255 | /* system control register */ | |
64201201 | 256 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
257 | break; |
258 | case 0x0850: | |
259 | /* I/O map type register */ | |
da9b266b | 260 | sysctrl->contiguous_map = val & 0x01; |
9a183916 | 261 | qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); |
9a64fbe4 FB |
262 | break; |
263 | default: | |
aae9366a JM |
264 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
265 | " => %02" PRIx32"\n", addr, val); | |
9a64fbe4 FB |
266 | break; |
267 | } | |
268 | } | |
269 | ||
a541f297 | 270 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 271 | { |
c227f099 | 272 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
273 | uint32_t retval = 0xFF; |
274 | ||
275 | switch (addr) { | |
276 | case 0x0092: | |
277 | /* Special port 92 */ | |
b6f54b31 | 278 | retval = sysctrl->endian << 1; |
64201201 FB |
279 | break; |
280 | case 0x0800: | |
281 | /* Motorola CPU configuration register */ | |
282 | retval = 0xEF; /* MPC750 */ | |
283 | break; | |
284 | case 0x0802: | |
285 | /* Motorola Base module feature register */ | |
286 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
287 | break; | |
288 | case 0x0803: | |
289 | /* Motorola base module status register */ | |
290 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
291 | break; |
292 | case 0x080C: | |
293 | /* Equipment present register: | |
294 | * no L2 cache | |
295 | * no upgrade processor | |
296 | * no cards in PCI slots | |
297 | * SCSI fuse is bad | |
298 | */ | |
64201201 FB |
299 | retval = 0x3C; |
300 | break; | |
301 | case 0x0810: | |
302 | /* Motorola base module extended feature register */ | |
303 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 304 | break; |
da9b266b FB |
305 | case 0x0814: |
306 | /* L2 invalidate: don't care */ | |
307 | break; | |
9a64fbe4 FB |
308 | case 0x0818: |
309 | /* Keylock */ | |
310 | retval = 0x00; | |
311 | break; | |
312 | case 0x081C: | |
313 | /* system control register | |
314 | * 7 - 6 / 1 - 0: L2 cache enable | |
315 | */ | |
64201201 | 316 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
317 | break; |
318 | case 0x0823: | |
319 | /* */ | |
320 | retval = 0x03; /* no L2 cache */ | |
321 | break; | |
322 | case 0x0850: | |
323 | /* I/O map type register */ | |
da9b266b | 324 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
325 | break; |
326 | default: | |
aae9366a | 327 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
9a64fbe4 FB |
328 | break; |
329 | } | |
aae9366a JM |
330 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
331 | addr - PPC_IO_BASE, retval); | |
9a64fbe4 FB |
332 | |
333 | return retval; | |
334 | } | |
335 | ||
da9b266b | 336 | |
64201201 | 337 | #define NVRAM_SIZE 0x2000 |
a541f297 | 338 | |
1bba0dc9 AF |
339 | static void ppc_prep_reset(void *opaque) |
340 | { | |
5c3e735f | 341 | PowerPCCPU *cpu = opaque; |
1bba0dc9 | 342 | |
5c3e735f | 343 | cpu_reset(CPU(cpu)); |
1bba0dc9 AF |
344 | } |
345 | ||
fd533eb5 JK |
346 | static const MemoryRegionPortio prep_portio_list[] = { |
347 | /* System control ports */ | |
348 | { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, | |
349 | { 0x0800, 0x52, 1, | |
350 | .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, | |
351 | /* Special port to get debug messages from Open-Firmware */ | |
352 | { 0x0F00, 4, 1, .write = PPC_debug_write, }, | |
353 | PORTIO_END_OF_LIST(), | |
354 | }; | |
355 | ||
848696bf KB |
356 | static PortioList prep_port_list; |
357 | ||
31688246 HP |
358 | /*****************************************************************************/ |
359 | /* NVRAM helpers */ | |
360 | static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) | |
361 | { | |
362 | NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); | |
363 | return (k->read)(nvram, addr); | |
364 | } | |
365 | ||
366 | static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) | |
367 | { | |
368 | NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); | |
369 | (k->write)(nvram, addr, val); | |
370 | } | |
371 | ||
372 | static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) | |
373 | { | |
374 | nvram_write(nvram, addr, value); | |
375 | } | |
376 | ||
377 | static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) | |
378 | { | |
379 | return nvram_read(nvram, addr); | |
380 | } | |
381 | ||
382 | static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) | |
383 | { | |
384 | nvram_write(nvram, addr, value >> 8); | |
385 | nvram_write(nvram, addr + 1, value & 0xFF); | |
386 | } | |
387 | ||
388 | static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) | |
389 | { | |
390 | uint16_t tmp; | |
391 | ||
392 | tmp = nvram_read(nvram, addr) << 8; | |
393 | tmp |= nvram_read(nvram, addr + 1); | |
394 | ||
395 | return tmp; | |
396 | } | |
397 | ||
398 | static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) | |
399 | { | |
400 | nvram_write(nvram, addr, value >> 24); | |
401 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); | |
402 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); | |
403 | nvram_write(nvram, addr + 3, value & 0xFF); | |
404 | } | |
405 | ||
406 | static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, | |
407 | uint32_t max) | |
408 | { | |
409 | int i; | |
410 | ||
411 | for (i = 0; i < max && str[i] != '\0'; i++) { | |
412 | nvram_write(nvram, addr + i, str[i]); | |
413 | } | |
414 | nvram_write(nvram, addr + i, str[i]); | |
415 | nvram_write(nvram, addr + max - 1, '\0'); | |
416 | } | |
417 | ||
418 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) | |
419 | { | |
420 | uint16_t tmp; | |
421 | uint16_t pd, pd1, pd2; | |
422 | ||
423 | tmp = prev >> 8; | |
424 | pd = prev ^ value; | |
425 | pd1 = pd & 0x000F; | |
426 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; | |
427 | tmp ^= (pd1 << 3) | (pd1 << 8); | |
428 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); | |
429 | ||
430 | return tmp; | |
431 | } | |
432 | ||
433 | static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) | |
434 | { | |
435 | uint32_t i; | |
436 | uint16_t crc = 0xFFFF; | |
437 | int odd; | |
438 | ||
439 | odd = count & 1; | |
440 | count &= ~1; | |
441 | for (i = 0; i != count; i++) { | |
442 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); | |
443 | } | |
444 | if (odd) { | |
445 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); | |
446 | } | |
447 | ||
448 | return crc; | |
449 | } | |
450 | ||
451 | #define CMDLINE_ADDR 0x017ff000 | |
452 | ||
453 | static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, | |
454 | const char *arch, | |
455 | uint32_t RAM_size, int boot_device, | |
456 | uint32_t kernel_image, uint32_t kernel_size, | |
457 | const char *cmdline, | |
458 | uint32_t initrd_image, uint32_t initrd_size, | |
459 | uint32_t NVRAM_image, | |
460 | int width, int height, int depth) | |
461 | { | |
462 | uint16_t crc; | |
463 | ||
464 | /* Set parameters for Open Hack'Ware BIOS */ | |
465 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); | |
466 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ | |
467 | NVRAM_set_word(nvram, 0x14, NVRAM_size); | |
468 | NVRAM_set_string(nvram, 0x20, arch, 16); | |
469 | NVRAM_set_lword(nvram, 0x30, RAM_size); | |
470 | NVRAM_set_byte(nvram, 0x34, boot_device); | |
471 | NVRAM_set_lword(nvram, 0x38, kernel_image); | |
472 | NVRAM_set_lword(nvram, 0x3C, kernel_size); | |
473 | if (cmdline) { | |
474 | /* XXX: put the cmdline in NVRAM too ? */ | |
475 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, | |
476 | cmdline); | |
477 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); | |
478 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); | |
479 | } else { | |
480 | NVRAM_set_lword(nvram, 0x40, 0); | |
481 | NVRAM_set_lword(nvram, 0x44, 0); | |
482 | } | |
483 | NVRAM_set_lword(nvram, 0x48, initrd_image); | |
484 | NVRAM_set_lword(nvram, 0x4C, initrd_size); | |
485 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); | |
486 | ||
487 | NVRAM_set_word(nvram, 0x54, width); | |
488 | NVRAM_set_word(nvram, 0x56, height); | |
489 | NVRAM_set_word(nvram, 0x58, depth); | |
490 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); | |
491 | NVRAM_set_word(nvram, 0xFC, crc); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
26aa7d72 | 496 | /* PowerPC PREP hardware initialisation */ |
3ef96221 | 497 | static void ppc_prep_init(MachineState *machine) |
a541f297 | 498 | { |
3ef96221 | 499 | ram_addr_t ram_size = machine->ram_size; |
3ef96221 MA |
500 | const char *kernel_filename = machine->kernel_filename; |
501 | const char *kernel_cmdline = machine->kernel_cmdline; | |
502 | const char *initrd_filename = machine->initrd_filename; | |
503 | const char *boot_device = machine->boot_order; | |
0c90c52f | 504 | MemoryRegion *sysmem = get_system_memory(); |
a9bf3df0 | 505 | PowerPCCPU *cpu = NULL; |
e2684c0b | 506 | CPUPPCState *env = NULL; |
31688246 | 507 | Nvram *m48t59; |
0c90c52f AK |
508 | #if 0 |
509 | MemoryRegion *xcsr = g_new(MemoryRegion, 1); | |
510 | #endif | |
d0b25425 | 511 | int linux_boot, i, nb_nics1; |
0c90c52f | 512 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
093209cd BS |
513 | uint32_t kernel_base, initrd_base; |
514 | long kernel_size, initrd_size; | |
8ca8c7bc | 515 | DeviceState *dev; |
8ca8c7bc | 516 | PCIHostState *pcihost; |
46e50e9d | 517 | PCIBus *pci_bus; |
506b7ddf | 518 | PCIDevice *pci; |
48a18b3c | 519 | ISABus *isa_bus; |
52a71bff | 520 | ISADevice *isa; |
28c5af54 | 521 | int ppc_boot_device; |
f455e98c | 522 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
64201201 | 523 | |
7267c094 | 524 | sysctrl = g_malloc0(sizeof(sysctrl_t)); |
a541f297 FB |
525 | |
526 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 527 | |
c68ea704 | 528 | /* init CPUs */ |
19fb2c36 BR |
529 | if (machine->cpu_model == NULL) |
530 | machine->cpu_model = "602"; | |
fe33cc71 | 531 | for (i = 0; i < smp_cpus; i++) { |
19fb2c36 | 532 | cpu = cpu_ppc_init(machine->cpu_model); |
a9bf3df0 | 533 | if (cpu == NULL) { |
aaed909a FB |
534 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); |
535 | exit(1); | |
536 | } | |
a9bf3df0 AF |
537 | env = &cpu->env; |
538 | ||
4018bae9 JM |
539 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
540 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
541 | cpu_ppc_tb_init(env, 7812500UL); | |
542 | } else { | |
543 | /* Set time-base frequency to 100 Mhz */ | |
544 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
545 | } | |
5c3e735f | 546 | qemu_register_reset(ppc_prep_reset, cpu); |
fe33cc71 | 547 | } |
a541f297 FB |
548 | |
549 | /* allocate RAM */ | |
e938ba0c | 550 | memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); |
0c90c52f | 551 | memory_region_add_subregion(sysmem, 0, ram); |
cf9c147c | 552 | |
a541f297 | 553 | if (linux_boot) { |
64201201 | 554 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 555 | /* now we can load the kernel */ |
dcac9679 PB |
556 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
557 | ram_size - kernel_base); | |
64201201 | 558 | if (kernel_size < 0) { |
2ac71179 | 559 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
a541f297 FB |
560 | exit(1); |
561 | } | |
562 | /* load initrd */ | |
a541f297 | 563 | if (initrd_filename) { |
64201201 | 564 | initrd_base = INITRD_LOAD_ADDR; |
dcac9679 PB |
565 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
566 | ram_size - initrd_base); | |
a541f297 | 567 | if (initrd_size < 0) { |
2ac71179 | 568 | hw_error("qemu: could not load initial ram disk '%s'\n", |
4a057712 | 569 | initrd_filename); |
a541f297 | 570 | } |
64201201 FB |
571 | } else { |
572 | initrd_base = 0; | |
573 | initrd_size = 0; | |
a541f297 | 574 | } |
6ac0e82d | 575 | ppc_boot_device = 'm'; |
a541f297 | 576 | } else { |
64201201 FB |
577 | kernel_base = 0; |
578 | kernel_size = 0; | |
579 | initrd_base = 0; | |
580 | initrd_size = 0; | |
28c5af54 JM |
581 | ppc_boot_device = '\0'; |
582 | /* For now, OHW cannot boot from the network. */ | |
0d913fdb JM |
583 | for (i = 0; boot_device[i] != '\0'; i++) { |
584 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { | |
585 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 586 | break; |
0d913fdb | 587 | } |
28c5af54 JM |
588 | } |
589 | if (ppc_boot_device == '\0') { | |
590 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
591 | exit(1); | |
592 | } | |
a541f297 FB |
593 | } |
594 | ||
dd37a5e4 | 595 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
2ac71179 | 596 | hw_error("Only 6xx bus is supported on PREP machine\n"); |
dd37a5e4 | 597 | } |
8ca8c7bc AF |
598 | |
599 | dev = qdev_create(NULL, "raven-pcihost"); | |
d0b25425 HP |
600 | if (bios_name == NULL) { |
601 | bios_name = BIOS_FILENAME; | |
602 | } | |
603 | qdev_prop_set_string(dev, "bios-name", bios_name); | |
604 | qdev_prop_set_uint32(dev, "elf-machine", ELF_MACHINE); | |
8558d942 | 605 | pcihost = PCI_HOST_BRIDGE(dev); |
f05f6b4a | 606 | object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); |
f424d5c4 | 607 | qdev_init_nofail(dev); |
8ca8c7bc AF |
608 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
609 | if (pci_bus == NULL) { | |
610 | fprintf(stderr, "Couldn't create PCI host controller.\n"); | |
611 | exit(1); | |
612 | } | |
9a183916 | 613 | sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); |
8ca8c7bc | 614 | |
506b7ddf AF |
615 | /* PCI -> ISA bridge */ |
616 | pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); | |
182735ef | 617 | cpu = POWERPC_CPU(first_cpu); |
506b7ddf | 618 | qdev_connect_gpio_out(&pci->qdev, 0, |
182735ef | 619 | cpu->env.irq_inputs[PPC6xx_INPUT_INT]); |
506b7ddf AF |
620 | sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); |
621 | sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); | |
622 | sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); | |
623 | sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); | |
2ae0e48d | 624 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); |
506b7ddf | 625 | |
52a71bff HP |
626 | /* Super I/O (parallel + serial ports) */ |
627 | isa = isa_create(isa_bus, TYPE_PC87312); | |
4a17cc4f AF |
628 | dev = DEVICE(isa); |
629 | qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ | |
630 | qdev_init_nofail(dev); | |
52a71bff | 631 | |
a541f297 | 632 | /* init basic PC hardware */ |
78895427 | 633 | pci_vga_init(pci_bus); |
a541f297 | 634 | |
a541f297 FB |
635 | nb_nics1 = nb_nics; |
636 | if (nb_nics1 > NE2000_NB_MAX) | |
637 | nb_nics1 = NE2000_NB_MAX; | |
638 | for(i = 0; i < nb_nics1; i++) { | |
5652ef78 | 639 | if (nd_table[i].model == NULL) { |
7267c094 | 640 | nd_table[i].model = g_strdup("ne2k_isa"); |
5652ef78 AJ |
641 | } |
642 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { | |
48a18b3c HP |
643 | isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], |
644 | &nd_table[i]); | |
a41b2ff2 | 645 | } else { |
29b358f9 | 646 | pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); |
a41b2ff2 | 647 | } |
a541f297 | 648 | } |
a541f297 | 649 | |
d8f94e1b | 650 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
81aa0647 | 651 | for(i = 0; i < MAX_IDE_BUS; i++) { |
48a18b3c | 652 | isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
653 | hd[2 * i], |
654 | hd[2 * i + 1]); | |
a541f297 | 655 | } |
48a18b3c | 656 | isa_create_simple(isa_bus, "i8042"); |
4556bd8b | 657 | |
182735ef AF |
658 | cpu = POWERPC_CPU(first_cpu); |
659 | sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; | |
fd533eb5 | 660 | |
848696bf KB |
661 | portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); |
662 | portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); | |
fd533eb5 | 663 | |
64201201 | 664 | /* PowerPC control and status register group */ |
b6b8bd18 | 665 | #if 0 |
2c9b15ca | 666 | memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); |
0c90c52f | 667 | memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); |
b6b8bd18 | 668 | #endif |
a541f297 | 669 | |
de77a243 | 670 | if (usb_enabled()) { |
afb9a60e | 671 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
0d92ed30 PB |
672 | } |
673 | ||
6de04973 | 674 | m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); |
3cbee15b | 675 | if (m48t59 == NULL) |
64201201 | 676 | return; |
3cbee15b | 677 | sysctrl->nvram = m48t59; |
64201201 FB |
678 | |
679 | /* Initialise NVRAM */ | |
31688246 HP |
680 | PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, |
681 | ppc_boot_device, | |
64201201 | 682 | kernel_base, kernel_size, |
b6b8bd18 | 683 | kernel_cmdline, |
64201201 FB |
684 | initrd_base, initrd_size, |
685 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
686 | 0, |
687 | graphic_width, graphic_height, graphic_depth); | |
a541f297 | 688 | } |
c0e564d5 | 689 | |
e264d29d | 690 | static void prep_machine_init(MachineClass *mc) |
f80f9ec9 | 691 | { |
e264d29d EH |
692 | mc->desc = "PowerPC PREP platform"; |
693 | mc->init = ppc_prep_init; | |
694 | mc->max_cpus = MAX_CPUS; | |
695 | mc->default_boot_order = "cad"; | |
f80f9ec9 AL |
696 | } |
697 | ||
e264d29d | 698 | DEFINE_MACHINE("prep", prep_machine_init) |