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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
e35704ba | 30 | #include "sysemu/numa.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
03dd024f | 32 | #include "qemu/log.h" |
71461b0f | 33 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 34 | #include "elf.h" |
1422e32d | 35 | #include "net/net.h" |
ad440b4a | 36 | #include "sysemu/device_tree.h" |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
9c17d615 PB |
38 | #include "sysemu/cpus.h" |
39 | #include "sysemu/kvm.h" | |
c20d332a | 40 | #include "sysemu/device_tree.h" |
e97c3636 | 41 | #include "kvm_ppc.h" |
ff14e817 | 42 | #include "migration/migration.h" |
4be21d56 | 43 | #include "mmu-hash64.h" |
3794d548 | 44 | #include "qom/cpu.h" |
9fdf0c29 DG |
45 | |
46 | #include "hw/boards.h" | |
0d09e41a | 47 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
48 | #include "hw/loader.h" |
49 | ||
0d09e41a PB |
50 | #include "hw/ppc/spapr.h" |
51 | #include "hw/ppc/spapr_vio.h" | |
52 | #include "hw/pci-host/spapr.h" | |
53 | #include "hw/ppc/xics.h" | |
a2cb15b0 | 54 | #include "hw/pci/msi.h" |
9fdf0c29 | 55 | |
83c9f4ca | 56 | #include "hw/pci/pci.h" |
71461b0f AK |
57 | #include "hw/scsi/scsi.h" |
58 | #include "hw/virtio/virtio-scsi.h" | |
f61b4bed | 59 | |
022c62cb | 60 | #include "exec/address-spaces.h" |
35139a59 | 61 | #include "hw/usb.h" |
1de7afc9 | 62 | #include "qemu/config-file.h" |
135a129a | 63 | #include "qemu/error-report.h" |
2a6593cb | 64 | #include "trace.h" |
34316482 | 65 | #include "hw/nmi.h" |
890c2b77 | 66 | |
68a27b20 | 67 | #include "hw/compat.h" |
f348b6d1 | 68 | #include "qemu/cutils.h" |
94a94e4c | 69 | #include "hw/ppc/spapr_cpu_core.h" |
2474bfd4 | 70 | #include "qmp-commands.h" |
68a27b20 | 71 | |
9fdf0c29 DG |
72 | #include <libfdt.h> |
73 | ||
4d8d5467 BH |
74 | /* SLOF memory layout: |
75 | * | |
76 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
77 | * device-tree, then position SLOF itself 31M below that | |
78 | * | |
79 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
80 | * and more | |
81 | * | |
82 | * We load our kernel at 4M, leaving space for SLOF initial image | |
83 | */ | |
38b02bd8 | 84 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 85 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 86 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
87 | #define FW_MAX_SIZE 0x400000 |
88 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
89 | #define FW_OVERHEAD 0x2800000 |
90 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 91 | |
4d8d5467 | 92 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 93 | |
0c103f8e DG |
94 | #define PHANDLE_XICP 0x00001111 |
95 | ||
7f763a5d DG |
96 | #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) |
97 | ||
c04d6cfa | 98 | static XICSState *try_create_xics(const char *type, int nr_servers, |
34f2af3d | 99 | int nr_irqs, Error **errp) |
c04d6cfa | 100 | { |
34f2af3d | 101 | Error *err = NULL; |
c04d6cfa AL |
102 | DeviceState *dev; |
103 | ||
104 | dev = qdev_create(NULL, type); | |
105 | qdev_prop_set_uint32(dev, "nr_servers", nr_servers); | |
106 | qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); | |
34f2af3d MA |
107 | object_property_set_bool(OBJECT(dev), true, "realized", &err); |
108 | if (err) { | |
109 | error_propagate(errp, err); | |
110 | object_unparent(OBJECT(dev)); | |
c04d6cfa AL |
111 | return NULL; |
112 | } | |
5a3d7b23 | 113 | return XICS_COMMON(dev); |
c04d6cfa AL |
114 | } |
115 | ||
446f16a6 | 116 | static XICSState *xics_system_init(MachineState *machine, |
1e49182d | 117 | int nr_servers, int nr_irqs, Error **errp) |
c04d6cfa | 118 | { |
27f24582 | 119 | XICSState *xics = NULL; |
c04d6cfa | 120 | |
11ad93f6 | 121 | if (kvm_enabled()) { |
34f2af3d MA |
122 | Error *err = NULL; |
123 | ||
446f16a6 | 124 | if (machine_kernel_irqchip_allowed(machine)) { |
27f24582 BH |
125 | xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, |
126 | &err); | |
11ad93f6 | 127 | } |
27f24582 | 128 | if (machine_kernel_irqchip_required(machine) && !xics) { |
b83baa60 MA |
129 | error_reportf_err(err, |
130 | "kernel_irqchip requested but unavailable: "); | |
131 | } else { | |
132 | error_free(err); | |
11ad93f6 DG |
133 | } |
134 | } | |
135 | ||
27f24582 BH |
136 | if (!xics) { |
137 | xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); | |
c04d6cfa AL |
138 | } |
139 | ||
27f24582 | 140 | return xics; |
c04d6cfa AL |
141 | } |
142 | ||
833d4668 AK |
143 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
144 | int smt_threads) | |
145 | { | |
146 | int i, ret = 0; | |
147 | uint32_t servers_prop[smt_threads]; | |
148 | uint32_t gservers_prop[smt_threads * 2]; | |
149 | int index = ppc_get_vcpu_dt_id(cpu); | |
150 | ||
6d9412ea | 151 | if (cpu->cpu_version) { |
4bce526e | 152 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); |
6d9412ea AK |
153 | if (ret < 0) { |
154 | return ret; | |
155 | } | |
156 | } | |
157 | ||
833d4668 AK |
158 | /* Build interrupt servers and gservers properties */ |
159 | for (i = 0; i < smt_threads; i++) { | |
160 | servers_prop[i] = cpu_to_be32(index + i); | |
161 | /* Hack, direct the group queues back to cpu 0 */ | |
162 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
163 | gservers_prop[i*2 + 1] = 0; | |
164 | } | |
165 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
166 | servers_prop, sizeof(servers_prop)); | |
167 | if (ret < 0) { | |
168 | return ret; | |
169 | } | |
170 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
171 | gservers_prop, sizeof(gservers_prop)); | |
172 | ||
173 | return ret; | |
174 | } | |
175 | ||
0da6f3fe BR |
176 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) |
177 | { | |
178 | int ret = 0; | |
179 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
180 | int index = ppc_get_vcpu_dt_id(cpu); | |
181 | uint32_t associativity[] = {cpu_to_be32(0x5), | |
182 | cpu_to_be32(0x0), | |
183 | cpu_to_be32(0x0), | |
184 | cpu_to_be32(0x0), | |
185 | cpu_to_be32(cs->numa_node), | |
186 | cpu_to_be32(index)}; | |
187 | ||
188 | /* Advertise NUMA via ibm,associativity */ | |
189 | if (nb_numa_nodes > 1) { | |
190 | ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, | |
191 | sizeof(associativity)); | |
192 | } | |
193 | ||
194 | return ret; | |
195 | } | |
196 | ||
28e02042 | 197 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 198 | { |
82677ed2 AK |
199 | int ret = 0, offset, cpus_offset; |
200 | CPUState *cs; | |
6e806cc3 BR |
201 | char cpu_model[32]; |
202 | int smt = kvmppc_smt_threads(); | |
7f763a5d | 203 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 204 | |
82677ed2 AK |
205 | CPU_FOREACH(cs) { |
206 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
207 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
208 | int index = ppc_get_vcpu_dt_id(cpu); | |
6e806cc3 | 209 | |
0f20ba62 | 210 | if ((index % smt) != 0) { |
6e806cc3 BR |
211 | continue; |
212 | } | |
213 | ||
82677ed2 | 214 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 215 | |
82677ed2 AK |
216 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
217 | if (cpus_offset < 0) { | |
218 | cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), | |
219 | "cpus"); | |
220 | if (cpus_offset < 0) { | |
221 | return cpus_offset; | |
222 | } | |
223 | } | |
224 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 225 | if (offset < 0) { |
82677ed2 AK |
226 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
227 | if (offset < 0) { | |
228 | return offset; | |
229 | } | |
6e806cc3 BR |
230 | } |
231 | ||
7f763a5d DG |
232 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
233 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
234 | if (ret < 0) { |
235 | return ret; | |
236 | } | |
833d4668 | 237 | |
0da6f3fe BR |
238 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); |
239 | if (ret < 0) { | |
240 | return ret; | |
241 | } | |
242 | ||
82677ed2 | 243 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, |
2a48d993 | 244 | ppc_get_compat_smt_threads(cpu)); |
833d4668 AK |
245 | if (ret < 0) { |
246 | return ret; | |
247 | } | |
6e806cc3 BR |
248 | } |
249 | return ret; | |
250 | } | |
251 | ||
5af9873d BH |
252 | |
253 | static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, | |
254 | size_t maxsize) | |
255 | { | |
256 | size_t maxcells = maxsize / sizeof(uint32_t); | |
257 | int i, j, count; | |
258 | uint32_t *p = prop; | |
259 | ||
260 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
261 | struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; | |
262 | ||
263 | if (!sps->page_shift) { | |
264 | break; | |
265 | } | |
266 | for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { | |
267 | if (sps->enc[count].page_shift == 0) { | |
268 | break; | |
269 | } | |
270 | } | |
271 | if ((p - prop) >= (maxcells - 3 - count * 2)) { | |
272 | break; | |
273 | } | |
274 | *(p++) = cpu_to_be32(sps->page_shift); | |
275 | *(p++) = cpu_to_be32(sps->slb_enc); | |
276 | *(p++) = cpu_to_be32(count); | |
277 | for (j = 0; j < count; j++) { | |
278 | *(p++) = cpu_to_be32(sps->enc[j].page_shift); | |
279 | *(p++) = cpu_to_be32(sps->enc[j].pte_enc); | |
280 | } | |
281 | } | |
282 | ||
283 | return (p - prop) * sizeof(uint32_t); | |
284 | } | |
285 | ||
b082d65a AK |
286 | static hwaddr spapr_node0_size(void) |
287 | { | |
fb164994 DG |
288 | MachineState *machine = MACHINE(qdev_get_machine()); |
289 | ||
b082d65a AK |
290 | if (nb_numa_nodes) { |
291 | int i; | |
292 | for (i = 0; i < nb_numa_nodes; ++i) { | |
293 | if (numa_info[i].node_mem) { | |
fb164994 DG |
294 | return MIN(pow2floor(numa_info[i].node_mem), |
295 | machine->ram_size); | |
b082d65a AK |
296 | } |
297 | } | |
298 | } | |
fb164994 | 299 | return machine->ram_size; |
b082d65a AK |
300 | } |
301 | ||
7f763a5d DG |
302 | #define _FDT(exp) \ |
303 | do { \ | |
304 | int ret = (exp); \ | |
305 | if (ret < 0) { \ | |
306 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
307 | #exp, fdt_strerror(ret)); \ | |
308 | exit(1); \ | |
309 | } \ | |
310 | } while (0) | |
311 | ||
a1d59c0f AK |
312 | static void add_str(GString *s, const gchar *s1) |
313 | { | |
314 | g_string_append_len(s, s1, strlen(s1) + 1); | |
315 | } | |
7f763a5d | 316 | |
3bbf37f2 | 317 | static void *spapr_create_fdt_skel(hwaddr initrd_base, |
a8170e5e AK |
318 | hwaddr initrd_size, |
319 | hwaddr kernel_size, | |
16457e7f | 320 | bool little_endian, |
74d042e5 DG |
321 | const char *kernel_cmdline, |
322 | uint32_t epow_irq) | |
9fdf0c29 DG |
323 | { |
324 | void *fdt; | |
9fdf0c29 DG |
325 | uint32_t start_prop = cpu_to_be32(initrd_base); |
326 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
a1d59c0f AK |
327 | GString *hypertas = g_string_sized_new(256); |
328 | GString *qemu_hypertas = g_string_sized_new(256); | |
7f763a5d | 329 | uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; |
9e734e3d | 330 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; |
6e806cc3 | 331 | unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; |
ef951443 | 332 | char *buf; |
9fdf0c29 | 333 | |
a1d59c0f AK |
334 | add_str(hypertas, "hcall-pft"); |
335 | add_str(hypertas, "hcall-term"); | |
336 | add_str(hypertas, "hcall-dabr"); | |
337 | add_str(hypertas, "hcall-interrupt"); | |
338 | add_str(hypertas, "hcall-tce"); | |
339 | add_str(hypertas, "hcall-vio"); | |
340 | add_str(hypertas, "hcall-splpar"); | |
341 | add_str(hypertas, "hcall-bulk"); | |
342 | add_str(hypertas, "hcall-set-mode"); | |
6cc09e26 TH |
343 | add_str(hypertas, "hcall-sprg0"); |
344 | add_str(hypertas, "hcall-copy"); | |
345 | add_str(hypertas, "hcall-debug"); | |
a1d59c0f AK |
346 | add_str(qemu_hypertas, "hcall-memop1"); |
347 | ||
7267c094 | 348 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
349 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
350 | ||
4d8d5467 BH |
351 | if (kernel_size) { |
352 | _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); | |
353 | } | |
354 | if (initrd_size) { | |
355 | _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); | |
356 | } | |
9fdf0c29 DG |
357 | _FDT((fdt_finish_reservemap(fdt))); |
358 | ||
359 | /* Root node */ | |
360 | _FDT((fdt_begin_node(fdt, ""))); | |
361 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 362 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
d63919c9 | 363 | _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); |
9fdf0c29 | 364 | |
ef951443 ND |
365 | /* |
366 | * Add info to guest to indentify which host is it being run on | |
367 | * and what is the uuid of the guest | |
368 | */ | |
369 | if (kvmppc_get_host_model(&buf)) { | |
370 | _FDT((fdt_property_string(fdt, "host-model", buf))); | |
371 | g_free(buf); | |
372 | } | |
373 | if (kvmppc_get_host_serial(&buf)) { | |
374 | _FDT((fdt_property_string(fdt, "host-serial", buf))); | |
375 | g_free(buf); | |
376 | } | |
377 | ||
378 | buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], | |
379 | qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], | |
380 | qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], | |
381 | qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], | |
382 | qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], | |
383 | qemu_uuid[14], qemu_uuid[15]); | |
384 | ||
385 | _FDT((fdt_property_string(fdt, "vm,uuid", buf))); | |
3dc0a66d AK |
386 | if (qemu_uuid_set) { |
387 | _FDT((fdt_property_string(fdt, "system-id", buf))); | |
388 | } | |
ef951443 ND |
389 | g_free(buf); |
390 | ||
2c1aaa81 SB |
391 | if (qemu_get_vm_name()) { |
392 | _FDT((fdt_property_string(fdt, "ibm,partition-name", | |
393 | qemu_get_vm_name()))); | |
394 | } | |
395 | ||
9fdf0c29 DG |
396 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
397 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
398 | ||
399 | /* /chosen */ | |
400 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
401 | ||
6e806cc3 BR |
402 | /* Set Form1_affinity */ |
403 | _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); | |
404 | ||
9fdf0c29 DG |
405 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); |
406 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
407 | &start_prop, sizeof(start_prop)))); | |
408 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
409 | &end_prop, sizeof(end_prop)))); | |
4d8d5467 BH |
410 | if (kernel_size) { |
411 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
412 | cpu_to_be64(kernel_size) }; | |
9fdf0c29 | 413 | |
4d8d5467 | 414 | _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); |
16457e7f BH |
415 | if (little_endian) { |
416 | _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); | |
417 | } | |
4d8d5467 | 418 | } |
cc84c0f3 AS |
419 | if (boot_menu) { |
420 | _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); | |
421 | } | |
f28359d8 LZ |
422 | _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); |
423 | _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); | |
424 | _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); | |
3384f95c | 425 | |
9fdf0c29 DG |
426 | _FDT((fdt_end_node(fdt))); |
427 | ||
f43e3525 DG |
428 | /* RTAS */ |
429 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
430 | ||
da95324e AK |
431 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { |
432 | add_str(hypertas, "hcall-multi-tce"); | |
433 | } | |
a1d59c0f AK |
434 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, |
435 | hypertas->len))); | |
436 | g_string_free(hypertas, TRUE); | |
437 | _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, | |
438 | qemu_hypertas->len))); | |
439 | g_string_free(qemu_hypertas, TRUE); | |
f43e3525 | 440 | |
6e806cc3 BR |
441 | _FDT((fdt_property(fdt, "ibm,associativity-reference-points", |
442 | refpoints, sizeof(refpoints)))); | |
443 | ||
74d042e5 | 444 | _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); |
79853e18 TD |
445 | _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", |
446 | RTAS_EVENT_SCAN_RATE))); | |
74d042e5 | 447 | |
226419d6 | 448 | if (msi_nonbroken) { |
a95f9922 SB |
449 | _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); |
450 | } | |
451 | ||
2e14072f | 452 | /* |
9d632f5f | 453 | * According to PAPR, rtas ibm,os-term does not guarantee a return |
2e14072f ND |
454 | * back to the guest cpu. |
455 | * | |
456 | * While an additional ibm,extended-os-term property indicates that | |
457 | * rtas call return will always occur. Set this property. | |
458 | */ | |
459 | _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); | |
460 | ||
f43e3525 DG |
461 | _FDT((fdt_end_node(fdt))); |
462 | ||
b5cec4c5 | 463 | /* interrupt controller */ |
9dfef5aa | 464 | _FDT((fdt_begin_node(fdt, "interrupt-controller"))); |
b5cec4c5 DG |
465 | |
466 | _FDT((fdt_property_string(fdt, "device_type", | |
467 | "PowerPC-External-Interrupt-Presentation"))); | |
468 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
b5cec4c5 DG |
469 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
470 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
471 | interrupt_server_ranges_prop, | |
472 | sizeof(interrupt_server_ranges_prop)))); | |
0c103f8e DG |
473 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
474 | _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); | |
475 | _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); | |
b5cec4c5 DG |
476 | |
477 | _FDT((fdt_end_node(fdt))); | |
478 | ||
4040ab72 DG |
479 | /* vdevice */ |
480 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
481 | ||
482 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
483 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
484 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
485 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
486 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
487 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
488 | |
489 | _FDT((fdt_end_node(fdt))); | |
490 | ||
74d042e5 DG |
491 | /* event-sources */ |
492 | spapr_events_fdt_skel(fdt, epow_irq); | |
493 | ||
f7d69146 AG |
494 | /* /hypervisor node */ |
495 | if (kvm_enabled()) { | |
496 | uint8_t hypercall[16]; | |
497 | ||
498 | /* indicate KVM hypercall interface */ | |
499 | _FDT((fdt_begin_node(fdt, "hypervisor"))); | |
500 | _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); | |
501 | if (kvmppc_has_cap_fixup_hcalls()) { | |
502 | /* | |
503 | * Older KVM versions with older guest kernels were broken with the | |
504 | * magic page, don't allow the guest to map it. | |
505 | */ | |
0ddbd053 AK |
506 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, |
507 | sizeof(hypercall))) { | |
508 | _FDT((fdt_property(fdt, "hcall-instructions", hypercall, | |
509 | sizeof(hypercall)))); | |
510 | } | |
f7d69146 AG |
511 | } |
512 | _FDT((fdt_end_node(fdt))); | |
513 | } | |
514 | ||
9fdf0c29 DG |
515 | _FDT((fdt_end_node(fdt))); /* close root node */ |
516 | _FDT((fdt_finish(fdt))); | |
517 | ||
a3467baa DG |
518 | return fdt; |
519 | } | |
520 | ||
03d196b7 | 521 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
522 | hwaddr size) |
523 | { | |
524 | uint32_t associativity[] = { | |
525 | cpu_to_be32(0x4), /* length */ | |
526 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 527 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
528 | }; |
529 | char mem_name[32]; | |
530 | uint64_t mem_reg_property[2]; | |
531 | int off; | |
532 | ||
533 | mem_reg_property[0] = cpu_to_be64(start); | |
534 | mem_reg_property[1] = cpu_to_be64(size); | |
535 | ||
536 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
537 | off = fdt_add_subnode(fdt, 0, mem_name); | |
538 | _FDT(off); | |
539 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
540 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
541 | sizeof(mem_reg_property)))); | |
542 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
543 | sizeof(associativity)))); | |
03d196b7 | 544 | return off; |
26a8c353 AK |
545 | } |
546 | ||
28e02042 | 547 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 548 | { |
fb164994 | 549 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
550 | hwaddr mem_start, node_size; |
551 | int i, nb_nodes = nb_numa_nodes; | |
552 | NodeInfo *nodes = numa_info; | |
553 | NodeInfo ramnode; | |
554 | ||
555 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
556 | if (!nb_numa_nodes) { | |
557 | nb_nodes = 1; | |
fb164994 | 558 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 559 | nodes = &ramnode; |
5fe269b1 | 560 | } |
7f763a5d | 561 | |
7db8a127 AK |
562 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
563 | if (!nodes[i].node_mem) { | |
564 | continue; | |
565 | } | |
fb164994 | 566 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
567 | node_size = 0; |
568 | } else { | |
7db8a127 | 569 | node_size = nodes[i].node_mem; |
fb164994 DG |
570 | if (node_size > machine->ram_size - mem_start) { |
571 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
572 | } |
573 | } | |
7db8a127 AK |
574 | if (!mem_start) { |
575 | /* ppc_spapr_init() checks for rma_size <= node0_size already */ | |
e8f986fc | 576 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
577 | mem_start += spapr->rma_size; |
578 | node_size -= spapr->rma_size; | |
579 | } | |
6010818c AK |
580 | for ( ; node_size; ) { |
581 | hwaddr sizetmp = pow2floor(node_size); | |
582 | ||
583 | /* mem_start != 0 here */ | |
584 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
585 | sizetmp = 1ULL << ctzl(mem_start); | |
586 | } | |
587 | ||
588 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
589 | node_size -= sizetmp; | |
590 | mem_start += sizetmp; | |
591 | } | |
7f763a5d DG |
592 | } |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
0da6f3fe BR |
597 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
598 | sPAPRMachineState *spapr) | |
599 | { | |
600 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
601 | CPUPPCState *env = &cpu->env; | |
602 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
603 | int index = ppc_get_vcpu_dt_id(cpu); | |
604 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
605 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
606 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
607 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
608 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
609 | uint32_t page_sizes_prop[64]; | |
610 | size_t page_sizes_prop_size; | |
22419c2a | 611 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 612 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
af81cf32 BR |
613 | sPAPRDRConnector *drc; |
614 | sPAPRDRConnectorClass *drck; | |
615 | int drc_index; | |
616 | ||
617 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); | |
618 | if (drc) { | |
619 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
620 | drc_index = drck->get_index(drc); | |
621 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); | |
622 | } | |
0da6f3fe | 623 | |
90da0d5a BH |
624 | /* Note: we keep CI large pages off for now because a 64K capable guest |
625 | * provisioned with large pages might otherwise try to map a qemu | |
626 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
627 | * even if that qemu runs on a 4k host. | |
628 | * | |
629 | * We can later add this bit back when we are confident this is not | |
630 | * an issue (!HV KVM or 64K host) | |
631 | */ | |
632 | uint8_t pa_features_206[] = { 6, 0, | |
633 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
634 | uint8_t pa_features_207[] = { 24, 0, | |
635 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
636 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
637 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
638 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; | |
639 | uint8_t *pa_features; | |
640 | size_t pa_size; | |
641 | ||
0da6f3fe BR |
642 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); |
643 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
644 | ||
645 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
646 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
647 | env->dcache_line_size))); | |
648 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
649 | env->dcache_line_size))); | |
650 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
651 | env->icache_line_size))); | |
652 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
653 | env->icache_line_size))); | |
654 | ||
655 | if (pcc->l1_dcache_size) { | |
656 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
657 | pcc->l1_dcache_size))); | |
658 | } else { | |
659 | fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); | |
660 | } | |
661 | if (pcc->l1_icache_size) { | |
662 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
663 | pcc->l1_icache_size))); | |
664 | } else { | |
665 | fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); | |
666 | } | |
667 | ||
668 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
669 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
fd5da5c4 | 670 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); |
0da6f3fe BR |
671 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); |
672 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); | |
673 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
674 | ||
675 | if (env->spr_cb[SPR_PURR].oea_read) { | |
676 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
677 | } | |
678 | ||
679 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
680 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", | |
681 | segs, sizeof(segs)))); | |
682 | } | |
683 | ||
684 | /* Advertise VMX/VSX (vector extensions) if available | |
685 | * 0 / no property == no vector extensions | |
686 | * 1 == VMX / Altivec available | |
687 | * 2 == VSX available */ | |
688 | if (env->insns_flags & PPC_ALTIVEC) { | |
689 | uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; | |
690 | ||
691 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); | |
692 | } | |
693 | ||
694 | /* Advertise DFP (Decimal Floating Point) if available | |
695 | * 0 / no property == no DFP | |
696 | * 1 == DFP available */ | |
697 | if (env->insns_flags2 & PPC2_DFP) { | |
698 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); | |
699 | } | |
700 | ||
701 | page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, | |
702 | sizeof(page_sizes_prop)); | |
703 | if (page_sizes_prop_size) { | |
704 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
705 | page_sizes_prop, page_sizes_prop_size))); | |
706 | } | |
707 | ||
90da0d5a BH |
708 | /* Do the ibm,pa-features property, adjust it for ci-large-pages */ |
709 | if (env->mmu_model == POWERPC_MMU_2_06) { | |
710 | pa_features = pa_features_206; | |
711 | pa_size = sizeof(pa_features_206); | |
712 | } else /* env->mmu_model == POWERPC_MMU_2_07 */ { | |
713 | pa_features = pa_features_207; | |
714 | pa_size = sizeof(pa_features_207); | |
715 | } | |
716 | if (env->ci_large_pages) { | |
717 | pa_features[3] |= 0x20; | |
718 | } | |
719 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
720 | ||
0da6f3fe | 721 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 722 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
723 | |
724 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
725 | pft_size_prop, sizeof(pft_size_prop)))); | |
726 | ||
727 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); | |
728 | ||
729 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, | |
730 | ppc_get_compat_smt_threads(cpu))); | |
731 | } | |
732 | ||
733 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
734 | { | |
735 | CPUState *cs; | |
736 | int cpus_offset; | |
737 | char *nodename; | |
738 | int smt = kvmppc_smt_threads(); | |
739 | ||
740 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
741 | _FDT(cpus_offset); | |
742 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
743 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
744 | ||
745 | /* | |
746 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
747 | * created by fdt_add_subnode() end up in the right order in FDT | |
748 | * for the guest kernel the enumerate the CPUs correctly. | |
749 | */ | |
750 | CPU_FOREACH_REVERSE(cs) { | |
751 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
752 | int index = ppc_get_vcpu_dt_id(cpu); | |
753 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
754 | int offset; | |
755 | ||
756 | if ((index % smt) != 0) { | |
757 | continue; | |
758 | } | |
759 | ||
760 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
761 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
762 | g_free(nodename); | |
763 | _FDT(offset); | |
764 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
765 | } | |
766 | ||
767 | } | |
768 | ||
03d196b7 BR |
769 | /* |
770 | * Adds ibm,dynamic-reconfiguration-memory node. | |
771 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
772 | * of this device tree node. | |
773 | */ | |
774 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
775 | { | |
776 | MachineState *machine = MACHINE(spapr); | |
777 | int ret, i, offset; | |
778 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
779 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
d0e5a8f2 BR |
780 | uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; |
781 | uint32_t nr_lmbs = (spapr->hotplug_memory.base + | |
782 | memory_region_size(&spapr->hotplug_memory.mr)) / | |
783 | lmb_size; | |
03d196b7 | 784 | uint32_t *int_buf, *cur_index, buf_len; |
6663864e | 785 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; |
03d196b7 | 786 | |
16c25aef | 787 | /* |
d0e5a8f2 | 788 | * Don't create the node if there is no hotpluggable memory |
16c25aef | 789 | */ |
d0e5a8f2 | 790 | if (machine->ram_size == machine->maxram_size) { |
16c25aef BR |
791 | return 0; |
792 | } | |
793 | ||
ef001f06 TH |
794 | /* |
795 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
796 | * or ibm,associativity-lookup-arrays | |
797 | */ | |
798 | buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) | |
799 | * sizeof(uint32_t); | |
03d196b7 BR |
800 | cur_index = int_buf = g_malloc0(buf_len); |
801 | ||
802 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
803 | ||
804 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
805 | sizeof(prop_lmb_size)); | |
806 | if (ret < 0) { | |
807 | goto out; | |
808 | } | |
809 | ||
810 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
811 | if (ret < 0) { | |
812 | goto out; | |
813 | } | |
814 | ||
815 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
816 | if (ret < 0) { | |
817 | goto out; | |
818 | } | |
819 | ||
820 | /* ibm,dynamic-memory */ | |
821 | int_buf[0] = cpu_to_be32(nr_lmbs); | |
822 | cur_index++; | |
823 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 824 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
825 | uint32_t *dynamic_memory = cur_index; |
826 | ||
d0e5a8f2 BR |
827 | if (i >= hotplug_lmb_start) { |
828 | sPAPRDRConnector *drc; | |
829 | sPAPRDRConnectorClass *drck; | |
830 | ||
831 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); | |
832 | g_assert(drc); | |
833 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
834 | ||
835 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
836 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
837 | dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); | |
838 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
839 | dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); | |
840 | if (memory_region_present(get_system_memory(), addr)) { | |
841 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
842 | } else { | |
843 | dynamic_memory[5] = cpu_to_be32(0); | |
844 | } | |
03d196b7 | 845 | } else { |
d0e5a8f2 BR |
846 | /* |
847 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
848 | * hotplug memory region -- all these are marked as reserved | |
849 | * and as having no valid DRC. | |
850 | */ | |
851 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
852 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
853 | dynamic_memory[2] = cpu_to_be32(0); | |
854 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
855 | dynamic_memory[4] = cpu_to_be32(-1); | |
856 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
857 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
858 | } |
859 | ||
860 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
861 | } | |
862 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
863 | if (ret < 0) { | |
864 | goto out; | |
865 | } | |
866 | ||
867 | /* ibm,associativity-lookup-arrays */ | |
868 | cur_index = int_buf; | |
6663864e | 869 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
870 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
871 | cur_index += 2; | |
6663864e | 872 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
873 | uint32_t associativity[] = { |
874 | cpu_to_be32(0x0), | |
875 | cpu_to_be32(0x0), | |
876 | cpu_to_be32(0x0), | |
877 | cpu_to_be32(i) | |
878 | }; | |
879 | memcpy(cur_index, associativity, sizeof(associativity)); | |
880 | cur_index += 4; | |
881 | } | |
882 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
883 | (cur_index - int_buf) * sizeof(uint32_t)); | |
884 | out: | |
885 | g_free(int_buf); | |
886 | return ret; | |
887 | } | |
888 | ||
889 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, | |
890 | target_ulong addr, target_ulong size, | |
891 | bool cpu_update, bool memory_update) | |
892 | { | |
893 | void *fdt, *fdt_skel; | |
894 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
895 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
896 | ||
897 | size -= sizeof(hdr); | |
898 | ||
899 | /* Create sceleton */ | |
900 | fdt_skel = g_malloc0(size); | |
901 | _FDT((fdt_create(fdt_skel, size))); | |
902 | _FDT((fdt_begin_node(fdt_skel, ""))); | |
903 | _FDT((fdt_end_node(fdt_skel))); | |
904 | _FDT((fdt_finish(fdt_skel))); | |
905 | fdt = g_malloc0(size); | |
906 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
907 | g_free(fdt_skel); | |
908 | ||
909 | /* Fixup cpu nodes */ | |
910 | if (cpu_update) { | |
911 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); | |
912 | } | |
913 | ||
16c25aef | 914 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ |
03d196b7 BR |
915 | if (memory_update && smc->dr_lmb_enabled) { |
916 | _FDT((spapr_populate_drconf_memory(spapr, fdt))); | |
03d196b7 BR |
917 | } |
918 | ||
919 | /* Pack resulting tree */ | |
920 | _FDT((fdt_pack(fdt))); | |
921 | ||
922 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
923 | trace_spapr_cas_failed(size); | |
924 | return -1; | |
925 | } | |
926 | ||
927 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
928 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
929 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
930 | g_free(fdt); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
28e02042 | 935 | static void spapr_finalize_fdt(sPAPRMachineState *spapr, |
a8170e5e AK |
936 | hwaddr fdt_addr, |
937 | hwaddr rtas_addr, | |
938 | hwaddr rtas_size) | |
a3467baa | 939 | { |
5b2128d2 | 940 | MachineState *machine = MACHINE(qdev_get_machine()); |
3c0c47e3 | 941 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 942 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
5b2128d2 | 943 | const char *boot_device = machine->boot_order; |
71461b0f AK |
944 | int ret, i; |
945 | size_t cb = 0; | |
946 | char *bootlist; | |
a3467baa | 947 | void *fdt; |
3384f95c | 948 | sPAPRPHBState *phb; |
a3467baa | 949 | |
7267c094 | 950 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
951 | |
952 | /* open out the base tree into a temp buffer for the final tweaks */ | |
953 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 | 954 | |
e8f986fc BR |
955 | ret = spapr_populate_memory(spapr, fdt); |
956 | if (ret < 0) { | |
957 | fprintf(stderr, "couldn't setup memory nodes in fdt\n"); | |
958 | exit(1); | |
7f763a5d DG |
959 | } |
960 | ||
4040ab72 DG |
961 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
962 | if (ret < 0) { | |
963 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
964 | exit(1); | |
965 | } | |
966 | ||
4d9392be TH |
967 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
968 | ret = spapr_rng_populate_dt(fdt); | |
969 | if (ret < 0) { | |
970 | fprintf(stderr, "could not set up rng device in the fdt\n"); | |
971 | exit(1); | |
972 | } | |
973 | } | |
974 | ||
3384f95c | 975 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
e0fdbd7c | 976 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); |
da34fed7 TH |
977 | if (ret < 0) { |
978 | error_report("couldn't setup PCI devices in fdt"); | |
979 | exit(1); | |
980 | } | |
3384f95c DG |
981 | } |
982 | ||
39ac8455 DG |
983 | /* RTAS */ |
984 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
985 | if (ret < 0) { | |
986 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
987 | } | |
988 | ||
0da6f3fe BR |
989 | /* cpus */ |
990 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 991 | |
71461b0f AK |
992 | bootlist = get_boot_devices_list(&cb, true); |
993 | if (cb && bootlist) { | |
994 | int offset = fdt_path_offset(fdt, "/chosen"); | |
995 | if (offset < 0) { | |
996 | exit(1); | |
997 | } | |
998 | for (i = 0; i < cb; i++) { | |
999 | if (bootlist[i] == '\n') { | |
1000 | bootlist[i] = ' '; | |
1001 | } | |
1002 | ||
1003 | } | |
1004 | ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); | |
1005 | } | |
1006 | ||
5b2128d2 AG |
1007 | if (boot_device && strlen(boot_device)) { |
1008 | int offset = fdt_path_offset(fdt, "/chosen"); | |
1009 | ||
1010 | if (offset < 0) { | |
1011 | exit(1); | |
1012 | } | |
1013 | fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); | |
1014 | } | |
1015 | ||
3fc5acde | 1016 | if (!spapr->has_graphics) { |
f28359d8 LZ |
1017 | spapr_populate_chosen_stdout(fdt, spapr->vio_bus); |
1018 | } | |
68f3a94c | 1019 | |
c20d332a BR |
1020 | if (smc->dr_lmb_enabled) { |
1021 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1022 | } | |
1023 | ||
3c0c47e3 | 1024 | if (mc->query_hotpluggable_cpus) { |
af81cf32 BR |
1025 | int offset = fdt_path_offset(fdt, "/cpus"); |
1026 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1027 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1028 | if (ret < 0) { | |
1029 | error_report("Couldn't set up CPU DR device tree properties"); | |
1030 | exit(1); | |
1031 | } | |
1032 | } | |
1033 | ||
4040ab72 DG |
1034 | _FDT((fdt_pack(fdt))); |
1035 | ||
4d8d5467 | 1036 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { |
730fce59 TH |
1037 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", |
1038 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
4d8d5467 BH |
1039 | exit(1); |
1040 | } | |
1041 | ||
ad440b4a | 1042 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); |
a3467baa | 1043 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
9fdf0c29 | 1044 | |
a21a7a70 | 1045 | g_free(bootlist); |
7267c094 | 1046 | g_free(fdt); |
9fdf0c29 DG |
1047 | } |
1048 | ||
1049 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1050 | { | |
1051 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1052 | } | |
1053 | ||
1b14670a | 1054 | static void emulate_spapr_hypercall(PowerPCCPU *cpu) |
9fdf0c29 | 1055 | { |
1b14670a AF |
1056 | CPUPPCState *env = &cpu->env; |
1057 | ||
efcb9383 DG |
1058 | if (msr_pr) { |
1059 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1060 | env->gpr[3] = H_PRIVILEGE; | |
1061 | } else { | |
aa100fa4 | 1062 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1063 | } |
9fdf0c29 DG |
1064 | } |
1065 | ||
e6b8fd24 SMJ |
1066 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1067 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1068 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1069 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1070 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1071 | ||
715c5407 DG |
1072 | /* |
1073 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1074 | */ | |
1075 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1076 | { | |
1077 | if (spapr->htab_fd >= 0) { | |
1078 | return spapr->htab_fd; | |
1079 | } | |
1080 | ||
1081 | spapr->htab_fd = kvmppc_get_htab_fd(false); | |
1082 | if (spapr->htab_fd < 0) { | |
1083 | error_report("Unable to open fd for reading hash table from KVM: %s", | |
1084 | strerror(errno)); | |
1085 | } | |
1086 | ||
1087 | return spapr->htab_fd; | |
1088 | } | |
1089 | ||
1090 | static void close_htab_fd(sPAPRMachineState *spapr) | |
1091 | { | |
1092 | if (spapr->htab_fd >= 0) { | |
1093 | close(spapr->htab_fd); | |
1094 | } | |
1095 | spapr->htab_fd = -1; | |
1096 | } | |
1097 | ||
8dfe8e7f DG |
1098 | static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
1099 | { | |
1100 | int shift; | |
1101 | ||
1102 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1103 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1104 | * that's much more than is needed for Linux guests */ | |
1105 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1106 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1107 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1108 | return shift; | |
1109 | } | |
1110 | ||
c5f54f3e DG |
1111 | static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1112 | Error **errp) | |
7f763a5d | 1113 | { |
c5f54f3e DG |
1114 | long rc; |
1115 | ||
1116 | /* Clean up any HPT info from a previous boot */ | |
1117 | g_free(spapr->htab); | |
1118 | spapr->htab = NULL; | |
1119 | spapr->htab_shift = 0; | |
1120 | close_htab_fd(spapr); | |
1121 | ||
1122 | rc = kvmppc_reset_htab(shift); | |
1123 | if (rc < 0) { | |
1124 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1125 | error_setg_errno(errp, errno, | |
1126 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1127 | shift); | |
1128 | /* This is almost certainly fatal, but if the caller really | |
1129 | * wants to carry on with shift == 0, it's welcome to try */ | |
1130 | } else if (rc > 0) { | |
1131 | /* kernel-side HPT allocated */ | |
1132 | if (rc != shift) { | |
1133 | error_setg(errp, | |
1134 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1135 | shift, rc); | |
7735feda BR |
1136 | } |
1137 | ||
7f763a5d | 1138 | spapr->htab_shift = shift; |
c18ad9a5 | 1139 | spapr->htab = NULL; |
b817772a | 1140 | } else { |
c5f54f3e DG |
1141 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1142 | size_t size = 1ULL << shift; | |
1143 | int i; | |
b817772a | 1144 | |
c5f54f3e DG |
1145 | spapr->htab = qemu_memalign(size, size); |
1146 | if (!spapr->htab) { | |
1147 | error_setg_errno(errp, errno, | |
1148 | "Could not allocate HPT of order %d", shift); | |
1149 | return; | |
7735feda BR |
1150 | } |
1151 | ||
c5f54f3e DG |
1152 | memset(spapr->htab, 0, size); |
1153 | spapr->htab_shift = shift; | |
e6b8fd24 | 1154 | |
c5f54f3e DG |
1155 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1156 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1157 | } |
7f763a5d | 1158 | } |
9fdf0c29 DG |
1159 | } |
1160 | ||
9e3f9733 AG |
1161 | static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) |
1162 | { | |
1163 | bool matched = false; | |
1164 | ||
1165 | if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { | |
1166 | matched = true; | |
1167 | } | |
1168 | ||
1169 | if (!matched) { | |
1170 | error_report("Device %s is not supported by this machine yet.", | |
1171 | qdev_fw_name(DEVICE(sbdev))); | |
1172 | exit(1); | |
1173 | } | |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
c8787ad4 | 1178 | static void ppc_spapr_reset(void) |
a3467baa | 1179 | { |
c5f54f3e DG |
1180 | MachineState *machine = MACHINE(qdev_get_machine()); |
1181 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1182 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1183 | uint32_t rtas_limit; |
259186a7 | 1184 | |
9e3f9733 AG |
1185 | /* Check for unknown sysbus devices */ |
1186 | foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); | |
1187 | ||
c5f54f3e DG |
1188 | /* Allocate and/or reset the hash page table */ |
1189 | spapr_reallocate_hpt(spapr, | |
1190 | spapr_hpt_shift_for_ramsize(machine->maxram_size), | |
1191 | &error_fatal); | |
1192 | ||
1193 | /* Update the RMA size if necessary */ | |
1194 | if (spapr->vrma_adjust) { | |
1195 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), | |
1196 | spapr->htab_shift); | |
1197 | } | |
a3467baa | 1198 | |
c8787ad4 | 1199 | qemu_devices_reset(); |
a3467baa | 1200 | |
b7d1f77a BH |
1201 | /* |
1202 | * We place the device tree and RTAS just below either the top of the RMA, | |
1203 | * or just below 2GB, whichever is lowere, so that it can be | |
1204 | * processed with 32-bit real mode code if necessary | |
1205 | */ | |
1206 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
1207 | spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; | |
1208 | spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; | |
1209 | ||
a3467baa DG |
1210 | /* Load the fdt */ |
1211 | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, | |
1212 | spapr->rtas_size); | |
1213 | ||
b7d1f77a BH |
1214 | /* Copy RTAS over */ |
1215 | cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, | |
1216 | spapr->rtas_size); | |
1217 | ||
a3467baa | 1218 | /* Set up the entry state */ |
182735ef AF |
1219 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1220 | first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; | |
1221 | first_ppc_cpu->env.gpr[5] = 0; | |
1222 | first_cpu->halted = 0; | |
1b718907 | 1223 | first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; |
a3467baa DG |
1224 | |
1225 | } | |
1226 | ||
28e02042 | 1227 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1228 | { |
2ff3de68 | 1229 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1230 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1231 | |
3978b863 | 1232 | if (dinfo) { |
6231a6da MA |
1233 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1234 | &error_fatal); | |
639e8102 DG |
1235 | } |
1236 | ||
1237 | qdev_init_nofail(dev); | |
1238 | ||
1239 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1240 | } | |
1241 | ||
28e02042 | 1242 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 DG |
1243 | { |
1244 | DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); | |
1245 | ||
1246 | qdev_init_nofail(dev); | |
1247 | spapr->rtc = dev; | |
74e5ae28 DG |
1248 | |
1249 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
1250 | OBJECT(spapr->rtc), "date", NULL); | |
28df36a1 DG |
1251 | } |
1252 | ||
8c57b867 | 1253 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1254 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1255 | { |
8c57b867 | 1256 | switch (vga_interface_type) { |
8c57b867 | 1257 | case VGA_NONE: |
7effdaa3 MW |
1258 | return false; |
1259 | case VGA_DEVICE: | |
1260 | return true; | |
1ddcae82 | 1261 | case VGA_STD: |
b798c190 | 1262 | case VGA_VIRTIO: |
1ddcae82 | 1263 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1264 | default: |
14c6a894 DG |
1265 | error_setg(errp, |
1266 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1267 | return false; | |
f28359d8 | 1268 | } |
f28359d8 LZ |
1269 | } |
1270 | ||
880ae7de DG |
1271 | static int spapr_post_load(void *opaque, int version_id) |
1272 | { | |
28e02042 | 1273 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1274 | int err = 0; |
1275 | ||
631b22ea | 1276 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1277 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1278 | * So when migrating from those versions, poke the incoming offset | |
1279 | * value into the RTC device */ | |
1280 | if (version_id < 3) { | |
1281 | err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); | |
1282 | } | |
1283 | ||
1284 | return err; | |
1285 | } | |
1286 | ||
1287 | static bool version_before_3(void *opaque, int version_id) | |
1288 | { | |
1289 | return version_id < 3; | |
1290 | } | |
1291 | ||
4be21d56 DG |
1292 | static const VMStateDescription vmstate_spapr = { |
1293 | .name = "spapr", | |
880ae7de | 1294 | .version_id = 3, |
4be21d56 | 1295 | .minimum_version_id = 1, |
880ae7de | 1296 | .post_load = spapr_post_load, |
3aff6c2f | 1297 | .fields = (VMStateField[]) { |
880ae7de DG |
1298 | /* used to be @next_irq */ |
1299 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1300 | |
1301 | /* RTC offset */ | |
28e02042 | 1302 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1303 | |
28e02042 | 1304 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1305 | VMSTATE_END_OF_LIST() |
1306 | }, | |
1307 | }; | |
1308 | ||
4be21d56 DG |
1309 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1310 | { | |
28e02042 | 1311 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1312 | |
4be21d56 DG |
1313 | /* "Iteration" header */ |
1314 | qemu_put_be32(f, spapr->htab_shift); | |
1315 | ||
e68cb8b4 AK |
1316 | if (spapr->htab) { |
1317 | spapr->htab_save_index = 0; | |
1318 | spapr->htab_first_pass = true; | |
1319 | } else { | |
1320 | assert(kvm_enabled()); | |
e68cb8b4 AK |
1321 | } |
1322 | ||
1323 | ||
4be21d56 DG |
1324 | return 0; |
1325 | } | |
1326 | ||
28e02042 | 1327 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1328 | int64_t max_ns) |
1329 | { | |
378bc217 | 1330 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1331 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1332 | int index = spapr->htab_save_index; | |
bc72ad67 | 1333 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1334 | |
1335 | assert(spapr->htab_first_pass); | |
1336 | ||
1337 | do { | |
1338 | int chunkstart; | |
1339 | ||
1340 | /* Consume invalid HPTEs */ | |
1341 | while ((index < htabslots) | |
1342 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1343 | index++; | |
1344 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1345 | } | |
1346 | ||
1347 | /* Consume valid HPTEs */ | |
1348 | chunkstart = index; | |
338c25b6 | 1349 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1350 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
1351 | index++; | |
1352 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1353 | } | |
1354 | ||
1355 | if (index > chunkstart) { | |
1356 | int n_valid = index - chunkstart; | |
1357 | ||
1358 | qemu_put_be32(f, chunkstart); | |
1359 | qemu_put_be16(f, n_valid); | |
1360 | qemu_put_be16(f, 0); | |
1361 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1362 | HASH_PTE_SIZE_64 * n_valid); | |
1363 | ||
378bc217 DG |
1364 | if (has_timeout && |
1365 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
1366 | break; |
1367 | } | |
1368 | } | |
1369 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
1370 | ||
1371 | if (index >= htabslots) { | |
1372 | assert(index == htabslots); | |
1373 | index = 0; | |
1374 | spapr->htab_first_pass = false; | |
1375 | } | |
1376 | spapr->htab_save_index = index; | |
1377 | } | |
1378 | ||
28e02042 | 1379 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 1380 | int64_t max_ns) |
4be21d56 DG |
1381 | { |
1382 | bool final = max_ns < 0; | |
1383 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
1384 | int examined = 0, sent = 0; | |
1385 | int index = spapr->htab_save_index; | |
bc72ad67 | 1386 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1387 | |
1388 | assert(!spapr->htab_first_pass); | |
1389 | ||
1390 | do { | |
1391 | int chunkstart, invalidstart; | |
1392 | ||
1393 | /* Consume non-dirty HPTEs */ | |
1394 | while ((index < htabslots) | |
1395 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
1396 | index++; | |
1397 | examined++; | |
1398 | } | |
1399 | ||
1400 | chunkstart = index; | |
1401 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 1402 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
1403 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1404 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
1405 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1406 | index++; | |
1407 | examined++; | |
1408 | } | |
1409 | ||
1410 | invalidstart = index; | |
1411 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 1412 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
1413 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
1414 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
1415 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
1416 | index++; | |
1417 | examined++; | |
1418 | } | |
1419 | ||
1420 | if (index > chunkstart) { | |
1421 | int n_valid = invalidstart - chunkstart; | |
1422 | int n_invalid = index - invalidstart; | |
1423 | ||
1424 | qemu_put_be32(f, chunkstart); | |
1425 | qemu_put_be16(f, n_valid); | |
1426 | qemu_put_be16(f, n_invalid); | |
1427 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1428 | HASH_PTE_SIZE_64 * n_valid); | |
1429 | sent += index - chunkstart; | |
1430 | ||
bc72ad67 | 1431 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
1432 | break; |
1433 | } | |
1434 | } | |
1435 | ||
1436 | if (examined >= htabslots) { | |
1437 | break; | |
1438 | } | |
1439 | ||
1440 | if (index >= htabslots) { | |
1441 | assert(index == htabslots); | |
1442 | index = 0; | |
1443 | } | |
1444 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
1445 | ||
1446 | if (index >= htabslots) { | |
1447 | assert(index == htabslots); | |
1448 | index = 0; | |
1449 | } | |
1450 | ||
1451 | spapr->htab_save_index = index; | |
1452 | ||
e68cb8b4 | 1453 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
1454 | } |
1455 | ||
e68cb8b4 AK |
1456 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
1457 | #define MAX_KVM_BUF_SIZE 2048 | |
1458 | ||
4be21d56 DG |
1459 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
1460 | { | |
28e02042 | 1461 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1462 | int fd; |
e68cb8b4 | 1463 | int rc = 0; |
4be21d56 DG |
1464 | |
1465 | /* Iteration header */ | |
1466 | qemu_put_be32(f, 0); | |
1467 | ||
e68cb8b4 AK |
1468 | if (!spapr->htab) { |
1469 | assert(kvm_enabled()); | |
1470 | ||
715c5407 DG |
1471 | fd = get_htab_fd(spapr); |
1472 | if (fd < 0) { | |
1473 | return fd; | |
01a57972 SMJ |
1474 | } |
1475 | ||
715c5407 | 1476 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
1477 | if (rc < 0) { |
1478 | return rc; | |
1479 | } | |
1480 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
1481 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
1482 | } else { | |
e68cb8b4 | 1483 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
1484 | } |
1485 | ||
1486 | /* End marker */ | |
1487 | qemu_put_be32(f, 0); | |
1488 | qemu_put_be16(f, 0); | |
1489 | qemu_put_be16(f, 0); | |
1490 | ||
e68cb8b4 | 1491 | return rc; |
4be21d56 DG |
1492 | } |
1493 | ||
1494 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
1495 | { | |
28e02042 | 1496 | sPAPRMachineState *spapr = opaque; |
715c5407 | 1497 | int fd; |
4be21d56 DG |
1498 | |
1499 | /* Iteration header */ | |
1500 | qemu_put_be32(f, 0); | |
1501 | ||
e68cb8b4 AK |
1502 | if (!spapr->htab) { |
1503 | int rc; | |
1504 | ||
1505 | assert(kvm_enabled()); | |
1506 | ||
715c5407 DG |
1507 | fd = get_htab_fd(spapr); |
1508 | if (fd < 0) { | |
1509 | return fd; | |
01a57972 SMJ |
1510 | } |
1511 | ||
715c5407 | 1512 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
1513 | if (rc < 0) { |
1514 | return rc; | |
1515 | } | |
e68cb8b4 | 1516 | } else { |
378bc217 DG |
1517 | if (spapr->htab_first_pass) { |
1518 | htab_save_first_pass(f, spapr, -1); | |
1519 | } | |
e68cb8b4 AK |
1520 | htab_save_later_pass(f, spapr, -1); |
1521 | } | |
4be21d56 DG |
1522 | |
1523 | /* End marker */ | |
1524 | qemu_put_be32(f, 0); | |
1525 | qemu_put_be16(f, 0); | |
1526 | qemu_put_be16(f, 0); | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
1532 | { | |
28e02042 | 1533 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1534 | uint32_t section_hdr; |
e68cb8b4 | 1535 | int fd = -1; |
4be21d56 DG |
1536 | |
1537 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 1538 | error_report("htab_load() bad version"); |
4be21d56 DG |
1539 | return -EINVAL; |
1540 | } | |
1541 | ||
1542 | section_hdr = qemu_get_be32(f); | |
1543 | ||
1544 | if (section_hdr) { | |
9897e462 | 1545 | Error *local_err = NULL; |
c5f54f3e DG |
1546 | |
1547 | /* First section gives the htab size */ | |
1548 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
1549 | if (local_err) { | |
1550 | error_report_err(local_err); | |
4be21d56 DG |
1551 | return -EINVAL; |
1552 | } | |
1553 | return 0; | |
1554 | } | |
1555 | ||
e68cb8b4 AK |
1556 | if (!spapr->htab) { |
1557 | assert(kvm_enabled()); | |
1558 | ||
1559 | fd = kvmppc_get_htab_fd(true); | |
1560 | if (fd < 0) { | |
98a5d100 DG |
1561 | error_report("Unable to open fd to restore KVM hash table: %s", |
1562 | strerror(errno)); | |
e68cb8b4 AK |
1563 | } |
1564 | } | |
1565 | ||
4be21d56 DG |
1566 | while (true) { |
1567 | uint32_t index; | |
1568 | uint16_t n_valid, n_invalid; | |
1569 | ||
1570 | index = qemu_get_be32(f); | |
1571 | n_valid = qemu_get_be16(f); | |
1572 | n_invalid = qemu_get_be16(f); | |
1573 | ||
1574 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
1575 | /* End of Stream */ | |
1576 | break; | |
1577 | } | |
1578 | ||
e68cb8b4 | 1579 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
1580 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
1581 | /* Bad index in stream */ | |
98a5d100 DG |
1582 | error_report( |
1583 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
1584 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
1585 | return -EINVAL; |
1586 | } | |
1587 | ||
e68cb8b4 AK |
1588 | if (spapr->htab) { |
1589 | if (n_valid) { | |
1590 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
1591 | HASH_PTE_SIZE_64 * n_valid); | |
1592 | } | |
1593 | if (n_invalid) { | |
1594 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
1595 | HASH_PTE_SIZE_64 * n_invalid); | |
1596 | } | |
1597 | } else { | |
1598 | int rc; | |
1599 | ||
1600 | assert(fd >= 0); | |
1601 | ||
1602 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
1603 | if (rc < 0) { | |
1604 | return rc; | |
1605 | } | |
4be21d56 DG |
1606 | } |
1607 | } | |
1608 | ||
e68cb8b4 AK |
1609 | if (!spapr->htab) { |
1610 | assert(fd >= 0); | |
1611 | close(fd); | |
1612 | } | |
1613 | ||
4be21d56 DG |
1614 | return 0; |
1615 | } | |
1616 | ||
c573fc03 TH |
1617 | static void htab_cleanup(void *opaque) |
1618 | { | |
1619 | sPAPRMachineState *spapr = opaque; | |
1620 | ||
1621 | close_htab_fd(spapr); | |
1622 | } | |
1623 | ||
4be21d56 DG |
1624 | static SaveVMHandlers savevm_htab_handlers = { |
1625 | .save_live_setup = htab_save_setup, | |
1626 | .save_live_iterate = htab_save_iterate, | |
a3e06c3d | 1627 | .save_live_complete_precopy = htab_save_complete, |
c573fc03 | 1628 | .cleanup = htab_cleanup, |
4be21d56 DG |
1629 | .load_state = htab_load, |
1630 | }; | |
1631 | ||
5b2128d2 AG |
1632 | static void spapr_boot_set(void *opaque, const char *boot_device, |
1633 | Error **errp) | |
1634 | { | |
1635 | MachineState *machine = MACHINE(qdev_get_machine()); | |
1636 | machine->boot_order = g_strdup(boot_device); | |
1637 | } | |
1638 | ||
224245bf DG |
1639 | /* |
1640 | * Reset routine for LMB DR devices. | |
1641 | * | |
1642 | * Unlike PCI DR devices, LMB DR devices explicitly register this reset | |
1643 | * routine. Reset for PCI DR devices will be handled by PHB reset routine | |
1644 | * when it walks all its children devices. LMB devices reset occurs | |
1645 | * as part of spapr_ppc_reset(). | |
1646 | */ | |
1647 | static void spapr_drc_reset(void *opaque) | |
1648 | { | |
1649 | sPAPRDRConnector *drc = opaque; | |
1650 | DeviceState *d = DEVICE(drc); | |
1651 | ||
1652 | if (d) { | |
1653 | device_reset(d); | |
1654 | } | |
1655 | } | |
1656 | ||
1657 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) | |
1658 | { | |
1659 | MachineState *machine = MACHINE(spapr); | |
1660 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 1661 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
1662 | int i; |
1663 | ||
1664 | for (i = 0; i < nr_lmbs; i++) { | |
1665 | sPAPRDRConnector *drc; | |
1666 | uint64_t addr; | |
1667 | ||
e8f986fc | 1668 | addr = i * lmb_size + spapr->hotplug_memory.base; |
224245bf DG |
1669 | drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, |
1670 | addr/lmb_size); | |
1671 | qemu_register_reset(spapr_drc_reset, drc); | |
1672 | } | |
1673 | } | |
1674 | ||
1675 | /* | |
1676 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
1677 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
1678 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
1679 | */ | |
7c150d6f | 1680 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
1681 | { |
1682 | int i; | |
1683 | ||
7c150d6f DG |
1684 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
1685 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
1686 | " is not aligned to %llu MiB", | |
1687 | machine->ram_size, | |
1688 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1689 | return; | |
1690 | } | |
1691 | ||
1692 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
1693 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
1694 | " is not aligned to %llu MiB", | |
1695 | machine->ram_size, | |
1696 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1697 | return; | |
224245bf DG |
1698 | } |
1699 | ||
1700 | for (i = 0; i < nb_numa_nodes; i++) { | |
1701 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
1702 | error_setg(errp, |
1703 | "Node %d memory size 0x%" PRIx64 | |
1704 | " is not aligned to %llu MiB", | |
1705 | i, numa_info[i].node_mem, | |
1706 | SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); | |
1707 | return; | |
224245bf DG |
1708 | } |
1709 | } | |
1710 | } | |
1711 | ||
9fdf0c29 | 1712 | /* pSeries LPAR / sPAPR hardware init */ |
3ef96221 | 1713 | static void ppc_spapr_init(MachineState *machine) |
9fdf0c29 | 1714 | { |
28e02042 | 1715 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
3c0c47e3 | 1716 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
224245bf | 1717 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 MA |
1718 | const char *kernel_filename = machine->kernel_filename; |
1719 | const char *kernel_cmdline = machine->kernel_cmdline; | |
1720 | const char *initrd_filename = machine->initrd_filename; | |
8c9f64df | 1721 | PCIHostState *phb; |
9fdf0c29 | 1722 | int i; |
890c2b77 AK |
1723 | MemoryRegion *sysmem = get_system_memory(); |
1724 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
658fa66b AK |
1725 | MemoryRegion *rma_region; |
1726 | void *rma = NULL; | |
a8170e5e | 1727 | hwaddr rma_alloc_size; |
b082d65a | 1728 | hwaddr node0_size = spapr_node0_size(); |
4d8d5467 BH |
1729 | uint32_t initrd_base = 0; |
1730 | long kernel_size = 0, initrd_size = 0; | |
b7d1f77a | 1731 | long load_limit, fw_size; |
16457e7f | 1732 | bool kernel_le = false; |
39ac8455 | 1733 | char *filename; |
94a94e4c BR |
1734 | int smt = kvmppc_smt_threads(); |
1735 | int spapr_cores = smp_cpus / smp_threads; | |
1736 | int spapr_max_cores = max_cpus / smp_threads; | |
1737 | ||
3c0c47e3 | 1738 | if (mc->query_hotpluggable_cpus) { |
94a94e4c BR |
1739 | if (smp_cpus % smp_threads) { |
1740 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
1741 | smp_cpus, smp_threads); | |
1742 | exit(1); | |
1743 | } | |
1744 | if (max_cpus % smp_threads) { | |
1745 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
1746 | max_cpus, smp_threads); | |
1747 | exit(1); | |
1748 | } | |
1749 | } | |
9fdf0c29 | 1750 | |
226419d6 | 1751 | msi_nonbroken = true; |
0ee2c058 | 1752 | |
d43b45e2 DG |
1753 | QLIST_INIT(&spapr->phbs); |
1754 | ||
9fdf0c29 DG |
1755 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
1756 | ||
354ac20a | 1757 | /* Allocate RMA if necessary */ |
658fa66b | 1758 | rma_alloc_size = kvmppc_alloc_rma(&rma); |
354ac20a DG |
1759 | |
1760 | if (rma_alloc_size == -1) { | |
730fce59 | 1761 | error_report("Unable to create RMA"); |
354ac20a DG |
1762 | exit(1); |
1763 | } | |
7f763a5d | 1764 | |
c4177479 | 1765 | if (rma_alloc_size && (rma_alloc_size < node0_size)) { |
7f763a5d | 1766 | spapr->rma_size = rma_alloc_size; |
354ac20a | 1767 | } else { |
c4177479 | 1768 | spapr->rma_size = node0_size; |
7f763a5d DG |
1769 | |
1770 | /* With KVM, we don't actually know whether KVM supports an | |
1771 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
1772 | * (HV KVM using VRMA), so we always assume the latter | |
1773 | * | |
1774 | * In that case, we also limit the initial allocations for RTAS | |
1775 | * etc... to 256M since we have no way to know what the VRMA size | |
1776 | * is going to be as it depends on the size of the hash table | |
1777 | * isn't determined yet. | |
1778 | */ | |
1779 | if (kvm_enabled()) { | |
1780 | spapr->vrma_adjust = 1; | |
1781 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
1782 | } | |
912acdf4 BH |
1783 | |
1784 | /* Actually we don't support unbounded RMA anymore since we | |
1785 | * added proper emulation of HV mode. The max we can get is | |
1786 | * 16G which also happens to be what we configure for PAPR | |
1787 | * mode so make sure we don't do anything bigger than that | |
1788 | */ | |
1789 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a DG |
1790 | } |
1791 | ||
c4177479 | 1792 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
1793 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
1794 | spapr->rma_size); | |
c4177479 AK |
1795 | exit(1); |
1796 | } | |
1797 | ||
b7d1f77a BH |
1798 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
1799 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 1800 | |
7b565160 | 1801 | /* Set up Interrupt Controller before we create the VCPUs */ |
27f24582 BH |
1802 | spapr->xics = xics_system_init(machine, |
1803 | DIV_ROUND_UP(max_cpus * smt, smp_threads), | |
1804 | XICS_IRQS_SPAPR, &error_fatal); | |
7b565160 | 1805 | |
224245bf | 1806 | if (smc->dr_lmb_enabled) { |
7c150d6f | 1807 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
1808 | } |
1809 | ||
9fdf0c29 | 1810 | /* init CPUs */ |
19fb2c36 BR |
1811 | if (machine->cpu_model == NULL) { |
1812 | machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; | |
9fdf0c29 | 1813 | } |
94a94e4c | 1814 | |
3c0c47e3 | 1815 | if (mc->query_hotpluggable_cpus) { |
94a94e4c BR |
1816 | char *type = spapr_get_cpu_core_type(machine->cpu_model); |
1817 | ||
4babfaf0 | 1818 | if (type == NULL) { |
caebf378 CLG |
1819 | error_report("Unable to find sPAPR CPU Core definition"); |
1820 | exit(1); | |
1821 | } | |
1822 | ||
94a94e4c | 1823 | spapr->cores = g_new0(Object *, spapr_max_cores); |
af81cf32 | 1824 | for (i = 0; i < spapr_max_cores; i++) { |
12bf2d33 | 1825 | int core_id = i * smp_threads; |
af81cf32 BR |
1826 | sPAPRDRConnector *drc = |
1827 | spapr_dr_connector_new(OBJECT(spapr), | |
12bf2d33 GK |
1828 | SPAPR_DR_CONNECTOR_TYPE_CPU, |
1829 | (core_id / smp_threads) * smt); | |
af81cf32 BR |
1830 | |
1831 | qemu_register_reset(spapr_drc_reset, drc); | |
1832 | ||
1833 | if (i < spapr_cores) { | |
caebf378 | 1834 | Object *core = object_new(type); |
af81cf32 BR |
1835 | object_property_set_int(core, smp_threads, "nr-threads", |
1836 | &error_fatal); | |
12bf2d33 | 1837 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, |
af81cf32 BR |
1838 | &error_fatal); |
1839 | object_property_set_bool(core, true, "realized", &error_fatal); | |
94a94e4c | 1840 | } |
9fdf0c29 | 1841 | } |
94a94e4c BR |
1842 | g_free(type); |
1843 | } else { | |
1844 | for (i = 0; i < smp_cpus; i++) { | |
1845 | PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model); | |
1846 | if (cpu == NULL) { | |
1847 | error_report("Unable to find PowerPC CPU definition"); | |
1848 | exit(1); | |
1849 | } | |
1850 | spapr_cpu_init(spapr, cpu, &error_fatal); | |
1851 | } | |
9fdf0c29 DG |
1852 | } |
1853 | ||
026bfd89 DG |
1854 | if (kvm_enabled()) { |
1855 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
1856 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 1857 | kvmppc_enable_set_mode_hcall(); |
026bfd89 DG |
1858 | } |
1859 | ||
9fdf0c29 | 1860 | /* allocate RAM */ |
f92f5da1 | 1861 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 1862 | machine->ram_size); |
f92f5da1 | 1863 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 1864 | |
658fa66b AK |
1865 | if (rma_alloc_size && rma) { |
1866 | rma_region = g_new(MemoryRegion, 1); | |
1867 | memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", | |
1868 | rma_alloc_size, rma); | |
1869 | vmstate_register_ram_global(rma_region); | |
1870 | memory_region_add_subregion(sysmem, 0, rma_region); | |
1871 | } | |
1872 | ||
4a1c9cf0 BR |
1873 | /* initialize hotplug memory address space */ |
1874 | if (machine->ram_size < machine->maxram_size) { | |
1875 | ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; | |
71c9a3dd BR |
1876 | /* |
1877 | * Limit the number of hotpluggable memory slots to half the number | |
1878 | * slots that KVM supports, leaving the other half for PCI and other | |
1879 | * devices. However ensure that number of slots doesn't drop below 32. | |
1880 | */ | |
1881 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
1882 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 1883 | |
71c9a3dd BR |
1884 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
1885 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
1886 | } | |
1887 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
1888 | error_report("Specified number of memory slots %" |
1889 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 1890 | machine->ram_slots, max_memslots); |
d54e4d76 | 1891 | exit(1); |
4a1c9cf0 BR |
1892 | } |
1893 | ||
1894 | spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, | |
1895 | SPAPR_HOTPLUG_MEM_ALIGN); | |
1896 | memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), | |
1897 | "hotplug-memory", hotplug_mem_size); | |
1898 | memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, | |
1899 | &spapr->hotplug_memory.mr); | |
1900 | } | |
1901 | ||
224245bf DG |
1902 | if (smc->dr_lmb_enabled) { |
1903 | spapr_create_lmb_dr_connectors(spapr); | |
1904 | } | |
1905 | ||
39ac8455 | 1906 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 1907 | if (!filename) { |
730fce59 | 1908 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
1909 | exit(1); |
1910 | } | |
b7d1f77a | 1911 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
1912 | if (spapr->rtas_size < 0) { |
1913 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
1914 | exit(1); | |
1915 | } | |
b7d1f77a BH |
1916 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
1917 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 1918 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
1919 | exit(1); |
1920 | } | |
4d8d5467 | 1921 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
1922 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
1923 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
1924 | exit(1); |
1925 | } | |
7267c094 | 1926 | g_free(filename); |
39ac8455 | 1927 | |
74d042e5 DG |
1928 | /* Set up EPOW events infrastructure */ |
1929 | spapr_events_init(spapr); | |
1930 | ||
12f42174 | 1931 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 1932 | spapr_rtc_create(spapr); |
12f42174 | 1933 | |
b5cec4c5 | 1934 | /* Set up VIO bus */ |
4040ab72 DG |
1935 | spapr->vio_bus = spapr_vio_bus_init(); |
1936 | ||
277f9acf | 1937 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 1938 | if (serial_hds[i]) { |
d601fac4 | 1939 | spapr_vty_create(spapr->vio_bus, serial_hds[i]); |
4040ab72 DG |
1940 | } |
1941 | } | |
9fdf0c29 | 1942 | |
639e8102 DG |
1943 | /* We always have at least the nvram device on VIO */ |
1944 | spapr_create_nvram(spapr); | |
1945 | ||
3384f95c | 1946 | /* Set up PCI */ |
fa28f71b AK |
1947 | spapr_pci_rtas_init(); |
1948 | ||
89dfd6e1 | 1949 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 1950 | |
277f9acf | 1951 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
1952 | NICInfo *nd = &nd_table[i]; |
1953 | ||
1954 | if (!nd->model) { | |
7267c094 | 1955 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
1956 | } |
1957 | ||
1958 | if (strcmp(nd->model, "ibmveth") == 0) { | |
d601fac4 | 1959 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 1960 | } else { |
29b358f9 | 1961 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
1962 | } |
1963 | } | |
1964 | ||
6e270446 | 1965 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 1966 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
1967 | } |
1968 | ||
f28359d8 | 1969 | /* Graphics */ |
14c6a894 | 1970 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 1971 | spapr->has_graphics = true; |
c6e76503 | 1972 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
1973 | } |
1974 | ||
4ee9ced9 | 1975 | if (machine->usb) { |
57040d45 TH |
1976 | if (smc->use_ohci_by_default) { |
1977 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
1978 | } else { | |
1979 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
1980 | } | |
c86580b8 | 1981 | |
35139a59 | 1982 | if (spapr->has_graphics) { |
c86580b8 MA |
1983 | USBBus *usb_bus = usb_bus_find(-1); |
1984 | ||
1985 | usb_create_simple(usb_bus, "usb-kbd"); | |
1986 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
1987 | } |
1988 | } | |
1989 | ||
7f763a5d | 1990 | if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { |
d54e4d76 DG |
1991 | error_report( |
1992 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
1993 | MIN_RMA_SLOF); | |
4d8d5467 BH |
1994 | exit(1); |
1995 | } | |
1996 | ||
9fdf0c29 DG |
1997 | if (kernel_filename) { |
1998 | uint64_t lowaddr = 0; | |
1999 | ||
9fdf0c29 | 2000 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
7ef295ea PC |
2001 | NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, |
2002 | 0, 0); | |
3b66da82 | 2003 | if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { |
16457e7f BH |
2004 | kernel_size = load_elf(kernel_filename, |
2005 | translate_kernel_address, NULL, | |
7ef295ea PC |
2006 | NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, |
2007 | 0, 0); | |
16457e7f BH |
2008 | kernel_le = kernel_size > 0; |
2009 | } | |
9fdf0c29 | 2010 | if (kernel_size < 0) { |
d54e4d76 DG |
2011 | error_report("error loading %s: %s", |
2012 | kernel_filename, load_elf_strerror(kernel_size)); | |
9fdf0c29 DG |
2013 | exit(1); |
2014 | } | |
2015 | ||
2016 | /* load initrd */ | |
2017 | if (initrd_filename) { | |
4d8d5467 BH |
2018 | /* Try to locate the initrd in the gap between the kernel |
2019 | * and the firmware. Add a bit of space just in case | |
2020 | */ | |
2021 | initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; | |
9fdf0c29 | 2022 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
4d8d5467 | 2023 | load_limit - initrd_base); |
9fdf0c29 | 2024 | if (initrd_size < 0) { |
d54e4d76 DG |
2025 | error_report("could not load initial ram disk '%s'", |
2026 | initrd_filename); | |
9fdf0c29 DG |
2027 | exit(1); |
2028 | } | |
2029 | } else { | |
2030 | initrd_base = 0; | |
2031 | initrd_size = 0; | |
2032 | } | |
4d8d5467 | 2033 | } |
a3467baa | 2034 | |
8e7ea787 AF |
2035 | if (bios_name == NULL) { |
2036 | bios_name = FW_FILE_NAME; | |
2037 | } | |
2038 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2039 | if (!filename) { |
68fea5a0 | 2040 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2041 | exit(1); |
2042 | } | |
4d8d5467 | 2043 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2044 | if (fw_size <= 0) { |
2045 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2046 | exit(1); |
2047 | } | |
2048 | g_free(filename); | |
4d8d5467 | 2049 | |
28e02042 DG |
2050 | /* FIXME: Should register things through the MachineState's qdev |
2051 | * interface, this is a legacy from the sPAPREnvironment structure | |
2052 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2053 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2054 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2055 | &savevm_htab_handlers, spapr); | |
2056 | ||
9fdf0c29 | 2057 | /* Prepare the device tree */ |
3bbf37f2 | 2058 | spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, |
16457e7f | 2059 | kernel_size, kernel_le, |
31fe14d1 NF |
2060 | kernel_cmdline, |
2061 | spapr->check_exception_irq); | |
a3467baa | 2062 | assert(spapr->fdt_skel != NULL); |
5b2128d2 | 2063 | |
46503c2b MR |
2064 | /* used by RTAS */ |
2065 | QTAILQ_INIT(&spapr->ccs_list); | |
2066 | qemu_register_reset(spapr_ccs_reset_hook, spapr); | |
2067 | ||
5b2128d2 | 2068 | qemu_register_boot_set(spapr_boot_set, spapr); |
9fdf0c29 DG |
2069 | } |
2070 | ||
135a129a AK |
2071 | static int spapr_kvm_type(const char *vm_type) |
2072 | { | |
2073 | if (!vm_type) { | |
2074 | return 0; | |
2075 | } | |
2076 | ||
2077 | if (!strcmp(vm_type, "HV")) { | |
2078 | return 1; | |
2079 | } | |
2080 | ||
2081 | if (!strcmp(vm_type, "PR")) { | |
2082 | return 2; | |
2083 | } | |
2084 | ||
2085 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2086 | exit(1); | |
2087 | } | |
2088 | ||
71461b0f | 2089 | /* |
627b84f4 | 2090 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2091 | * for the bootindex property handling. |
2092 | */ | |
2093 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2094 | DeviceState *dev) | |
2095 | { | |
2096 | #define CAST(type, obj, name) \ | |
2097 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2098 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2099 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
2100 | ||
2101 | if (d) { | |
2102 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2103 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2104 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2105 | ||
2106 | if (spapr) { | |
2107 | /* | |
2108 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2109 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2110 | * in the top 16 bits of the 64-bit LUN | |
2111 | */ | |
2112 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2113 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2114 | (uint64_t)id << 48); | |
2115 | } else if (virtio) { | |
2116 | /* | |
2117 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2118 | * in the top 32 bits of the 64-bit LUN | |
2119 | * Note: the quote above is from SLOF and it is wrong, | |
2120 | * the actual binding is: | |
2121 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2122 | */ | |
2123 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
2124 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2125 | (uint64_t)id << 32); | |
2126 | } else if (usb) { | |
2127 | /* | |
2128 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2129 | * in the top 32 bits of the 64-bit LUN | |
2130 | */ | |
2131 | unsigned usb_port = atoi(usb->port->path); | |
2132 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2133 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2134 | (uint64_t)id << 32); | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | if (phb) { | |
2139 | /* Replace "pci" with "pci@800000020000000" */ | |
2140 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2141 | } | |
2142 | ||
2143 | return NULL; | |
2144 | } | |
2145 | ||
23825581 EH |
2146 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2147 | { | |
28e02042 | 2148 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2149 | |
28e02042 | 2150 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2151 | } |
2152 | ||
2153 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2154 | { | |
28e02042 | 2155 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2156 | |
28e02042 DG |
2157 | g_free(spapr->kvm_type); |
2158 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2159 | } |
2160 | ||
2161 | static void spapr_machine_initfn(Object *obj) | |
2162 | { | |
715c5407 DG |
2163 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
2164 | ||
2165 | spapr->htab_fd = -1; | |
23825581 EH |
2166 | object_property_add_str(obj, "kvm-type", |
2167 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
2168 | object_property_set_description(obj, "kvm-type", |
2169 | "Specifies the KVM virtualization mode (HV, PR)", | |
2170 | NULL); | |
23825581 EH |
2171 | } |
2172 | ||
87bbdd9c DG |
2173 | static void spapr_machine_finalizefn(Object *obj) |
2174 | { | |
2175 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2176 | ||
2177 | g_free(spapr->kvm_type); | |
2178 | } | |
2179 | ||
34316482 AK |
2180 | static void ppc_cpu_do_nmi_on_cpu(void *arg) |
2181 | { | |
2182 | CPUState *cs = arg; | |
2183 | ||
2184 | cpu_synchronize_state(cs); | |
2185 | ppc_cpu_do_system_reset(cs); | |
2186 | } | |
2187 | ||
2188 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
2189 | { | |
2190 | CPUState *cs; | |
2191 | ||
2192 | CPU_FOREACH(cs) { | |
2193 | async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); | |
2194 | } | |
2195 | } | |
2196 | ||
c20d332a BR |
2197 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, |
2198 | uint32_t node, Error **errp) | |
2199 | { | |
2200 | sPAPRDRConnector *drc; | |
2201 | sPAPRDRConnectorClass *drck; | |
2202 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; | |
2203 | int i, fdt_offset, fdt_size; | |
2204 | void *fdt; | |
2205 | ||
c20d332a BR |
2206 | for (i = 0; i < nr_lmbs; i++) { |
2207 | drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
2208 | addr/SPAPR_MEMORY_BLOCK_SIZE); | |
2209 | g_assert(drc); | |
2210 | ||
2211 | fdt = create_device_tree(&fdt_size); | |
2212 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
2213 | SPAPR_MEMORY_BLOCK_SIZE); | |
2214 | ||
2215 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
2216 | drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); | |
c20d332a BR |
2217 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
2218 | } | |
5dd5238c JD |
2219 | /* send hotplug notification to the |
2220 | * guest only in case of hotplugged memory | |
2221 | */ | |
2222 | if (dev->hotplugged) { | |
2223 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); | |
2224 | } | |
c20d332a BR |
2225 | } |
2226 | ||
2227 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
2228 | uint32_t node, Error **errp) | |
2229 | { | |
2230 | Error *local_err = NULL; | |
2231 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
2232 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
2233 | PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); | |
2234 | MemoryRegion *mr = ddc->get_memory_region(dimm); | |
2235 | uint64_t align = memory_region_get_alignment(mr); | |
2236 | uint64_t size = memory_region_size(mr); | |
2237 | uint64_t addr; | |
2238 | ||
2239 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2240 | error_setg(&local_err, "Hotplugged memory size must be a multiple of " | |
2241 | "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); | |
2242 | goto out; | |
2243 | } | |
2244 | ||
d6a9b0b8 | 2245 | pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); |
c20d332a BR |
2246 | if (local_err) { |
2247 | goto out; | |
2248 | } | |
2249 | ||
2250 | addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); | |
2251 | if (local_err) { | |
2252 | pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); | |
2253 | goto out; | |
2254 | } | |
2255 | ||
2256 | spapr_add_lmbs(dev, addr, size, node, &error_abort); | |
2257 | ||
2258 | out: | |
2259 | error_propagate(errp, local_err); | |
2260 | } | |
2261 | ||
af81cf32 BR |
2262 | void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
2263 | sPAPRMachineState *spapr) | |
2264 | { | |
2265 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
2266 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
2267 | int id = ppc_get_vcpu_dt_id(cpu); | |
2268 | void *fdt; | |
2269 | int offset, fdt_size; | |
2270 | char *nodename; | |
2271 | ||
2272 | fdt = create_device_tree(&fdt_size); | |
2273 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
2274 | offset = fdt_add_subnode(fdt, 0, nodename); | |
2275 | ||
2276 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
2277 | g_free(nodename); | |
2278 | ||
2279 | *fdt_offset = offset; | |
2280 | return fdt; | |
2281 | } | |
2282 | ||
c20d332a BR |
2283 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
2284 | DeviceState *dev, Error **errp) | |
2285 | { | |
2286 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); | |
2287 | ||
2288 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
b556854b | 2289 | int node; |
c20d332a BR |
2290 | |
2291 | if (!smc->dr_lmb_enabled) { | |
2292 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
2293 | return; | |
2294 | } | |
2295 | node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); | |
2296 | if (*errp) { | |
2297 | return; | |
2298 | } | |
1a5512bb GA |
2299 | if (node < 0 || node >= MAX_NODES) { |
2300 | error_setg(errp, "Invaild node %d", node); | |
2301 | return; | |
2302 | } | |
c20d332a | 2303 | |
b556854b BR |
2304 | /* |
2305 | * Currently PowerPC kernel doesn't allow hot-adding memory to | |
2306 | * memory-less node, but instead will silently add the memory | |
2307 | * to the first node that has some memory. This causes two | |
2308 | * unexpected behaviours for the user. | |
2309 | * | |
2310 | * - Memory gets hotplugged to a different node than what the user | |
2311 | * specified. | |
2312 | * - Since pc-dimm subsystem in QEMU still thinks that memory belongs | |
2313 | * to memory-less node, a reboot will set things accordingly | |
2314 | * and the previously hotplugged memory now ends in the right node. | |
2315 | * This appears as if some memory moved from one node to another. | |
2316 | * | |
2317 | * So until kernel starts supporting memory hotplug to memory-less | |
2318 | * nodes, just prevent such attempts upfront in QEMU. | |
2319 | */ | |
2320 | if (nb_numa_nodes && !numa_info[node].node_mem) { | |
2321 | error_setg(errp, "Can't hotplug memory to memory-less node %d", | |
2322 | node); | |
2323 | return; | |
2324 | } | |
2325 | ||
c20d332a | 2326 | spapr_memory_plug(hotplug_dev, dev, node, errp); |
af81cf32 BR |
2327 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
2328 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
2329 | } |
2330 | } | |
2331 | ||
2332 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, | |
2333 | DeviceState *dev, Error **errp) | |
2334 | { | |
3c0c47e3 | 2335 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
6f4b5c3e | 2336 | |
c20d332a BR |
2337 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2338 | error_setg(errp, "Memory hot unplug not supported by sPAPR"); | |
6f4b5c3e | 2339 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3c0c47e3 | 2340 | if (!mc->query_hotpluggable_cpus) { |
6f4b5c3e BR |
2341 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
2342 | return; | |
2343 | } | |
2344 | spapr_core_unplug(hotplug_dev, dev, errp); | |
c20d332a BR |
2345 | } |
2346 | } | |
2347 | ||
94a94e4c BR |
2348 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
2349 | DeviceState *dev, Error **errp) | |
2350 | { | |
2351 | if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
2352 | spapr_core_pre_plug(hotplug_dev, dev, errp); | |
2353 | } | |
2354 | } | |
2355 | ||
c20d332a BR |
2356 | static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, |
2357 | DeviceState *dev) | |
2358 | { | |
94a94e4c BR |
2359 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
2360 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
2361 | return HOTPLUG_HANDLER(machine); |
2362 | } | |
2363 | return NULL; | |
2364 | } | |
2365 | ||
20bb648d DG |
2366 | static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) |
2367 | { | |
2368 | /* Allocate to NUMA nodes on a "socket" basis (not that concept of | |
2369 | * socket means much for the paravirtualized PAPR platform) */ | |
2370 | return cpu_index / smp_threads / smp_cores; | |
2371 | } | |
2372 | ||
2474bfd4 IM |
2373 | static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) |
2374 | { | |
2375 | int i; | |
2376 | HotpluggableCPUList *head = NULL; | |
2377 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
2378 | int spapr_max_cores = max_cpus / smp_threads; | |
2474bfd4 IM |
2379 | |
2380 | for (i = 0; i < spapr_max_cores; i++) { | |
2381 | HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); | |
2382 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); | |
2383 | CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); | |
2384 | ||
2385 | cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); | |
2386 | cpu_item->vcpus_count = smp_threads; | |
27393c33 | 2387 | cpu_props->has_core_id = true; |
12bf2d33 | 2388 | cpu_props->core_id = i * smp_threads; |
2474bfd4 IM |
2389 | /* TODO: add 'has_node/node' here to describe |
2390 | to which node core belongs */ | |
2391 | ||
2392 | cpu_item->props = cpu_props; | |
2393 | if (spapr->cores[i]) { | |
2394 | cpu_item->has_qom_path = true; | |
2395 | cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); | |
2396 | } | |
2397 | list_item->value = cpu_item; | |
2398 | list_item->next = head; | |
2399 | head = list_item; | |
2400 | } | |
2401 | return head; | |
2402 | } | |
2403 | ||
29ee3247 AK |
2404 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
2405 | { | |
2406 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 2407 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 2408 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 2409 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 2410 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
958db90c | 2411 | |
0eb9054c | 2412 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
fc9f38c3 DG |
2413 | |
2414 | /* | |
2415 | * We set up the default / latest behaviour here. The class_init | |
2416 | * functions for the specific versioned machine types can override | |
2417 | * these details for backwards compatibility | |
2418 | */ | |
958db90c MA |
2419 | mc->init = ppc_spapr_init; |
2420 | mc->reset = ppc_spapr_reset; | |
2421 | mc->block_default_type = IF_SCSI; | |
38b02bd8 | 2422 | mc->max_cpus = MAX_CPUMASK_BITS; |
958db90c | 2423 | mc->no_parallel = 1; |
5b2128d2 | 2424 | mc->default_boot_order = ""; |
a34944fe | 2425 | mc->default_ram_size = 512 * M_BYTE; |
958db90c | 2426 | mc->kvm_type = spapr_kvm_type; |
9e3f9733 | 2427 | mc->has_dynamic_sysbus = true; |
e4024630 | 2428 | mc->pci_allow_0_address = true; |
c20d332a | 2429 | mc->get_hotplug_handler = spapr_get_hotpug_handler; |
94a94e4c | 2430 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a BR |
2431 | hc->plug = spapr_machine_device_plug; |
2432 | hc->unplug = spapr_machine_device_unplug; | |
20bb648d | 2433 | mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; |
00b4fbe2 | 2434 | |
fc9f38c3 | 2435 | smc->dr_lmb_enabled = true; |
3c0c47e3 | 2436 | mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; |
71461b0f | 2437 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 2438 | nc->nmi_monitor_handler = spapr_nmi; |
29ee3247 AK |
2439 | } |
2440 | ||
2441 | static const TypeInfo spapr_machine_info = { | |
2442 | .name = TYPE_SPAPR_MACHINE, | |
2443 | .parent = TYPE_MACHINE, | |
4aee7362 | 2444 | .abstract = true, |
6ca1502e | 2445 | .instance_size = sizeof(sPAPRMachineState), |
23825581 | 2446 | .instance_init = spapr_machine_initfn, |
87bbdd9c | 2447 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 2448 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 2449 | .class_init = spapr_machine_class_init, |
71461b0f AK |
2450 | .interfaces = (InterfaceInfo[]) { |
2451 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 2452 | { TYPE_NMI }, |
c20d332a | 2453 | { TYPE_HOTPLUG_HANDLER }, |
71461b0f AK |
2454 | { } |
2455 | }, | |
29ee3247 AK |
2456 | }; |
2457 | ||
fccbc785 | 2458 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
2459 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
2460 | void *data) \ | |
2461 | { \ | |
2462 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
2463 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
2464 | if (latest) { \ |
2465 | mc->alias = "pseries"; \ | |
2466 | mc->is_default = 1; \ | |
2467 | } \ | |
5013c547 DG |
2468 | } \ |
2469 | static void spapr_machine_##suffix##_instance_init(Object *obj) \ | |
2470 | { \ | |
2471 | MachineState *machine = MACHINE(obj); \ | |
2472 | spapr_machine_##suffix##_instance_options(machine); \ | |
2473 | } \ | |
2474 | static const TypeInfo spapr_machine_##suffix##_info = { \ | |
2475 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
2476 | .parent = TYPE_SPAPR_MACHINE, \ | |
2477 | .class_init = spapr_machine_##suffix##_class_init, \ | |
2478 | .instance_init = spapr_machine_##suffix##_instance_init, \ | |
2479 | }; \ | |
2480 | static void spapr_machine_register_##suffix(void) \ | |
2481 | { \ | |
2482 | type_register(&spapr_machine_##suffix##_info); \ | |
2483 | } \ | |
0e6aac87 | 2484 | type_init(spapr_machine_register_##suffix) |
5013c547 | 2485 | |
1ea1eefc BR |
2486 | /* |
2487 | * pseries-2.7 | |
2488 | */ | |
2489 | static void spapr_machine_2_7_instance_options(MachineState *machine) | |
2490 | { | |
2491 | } | |
2492 | ||
2493 | static void spapr_machine_2_7_class_options(MachineClass *mc) | |
2494 | { | |
2495 | /* Defaults for the latest behaviour inherited from the base class */ | |
2496 | } | |
2497 | ||
2498 | DEFINE_SPAPR_MACHINE(2_7, "2.7", true); | |
2499 | ||
4b23699c DG |
2500 | /* |
2501 | * pseries-2.6 | |
2502 | */ | |
1ea1eefc | 2503 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
2504 | HW_COMPAT_2_6 \ |
2505 | { \ | |
2506 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2507 | .property = "ddw",\ | |
2508 | .value = stringify(off),\ | |
2509 | }, | |
1ea1eefc | 2510 | |
4b23699c DG |
2511 | static void spapr_machine_2_6_instance_options(MachineState *machine) |
2512 | { | |
2513 | } | |
2514 | ||
2515 | static void spapr_machine_2_6_class_options(MachineClass *mc) | |
2516 | { | |
1ea1eefc | 2517 | spapr_machine_2_7_class_options(mc); |
3c0c47e3 | 2518 | mc->query_hotpluggable_cpus = NULL; |
1ea1eefc | 2519 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
2520 | } |
2521 | ||
1ea1eefc | 2522 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 2523 | |
1c5f29bb DG |
2524 | /* |
2525 | * pseries-2.5 | |
2526 | */ | |
4b23699c | 2527 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
2528 | HW_COMPAT_2_5 \ |
2529 | { \ | |
2530 | .driver = "spapr-vlan", \ | |
2531 | .property = "use-rx-buffer-pools", \ | |
2532 | .value = "off", \ | |
2533 | }, | |
4b23699c | 2534 | |
5013c547 | 2535 | static void spapr_machine_2_5_instance_options(MachineState *machine) |
1c5f29bb | 2536 | { |
5013c547 DG |
2537 | } |
2538 | ||
2539 | static void spapr_machine_2_5_class_options(MachineClass *mc) | |
2540 | { | |
57040d45 TH |
2541 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2542 | ||
4b23699c | 2543 | spapr_machine_2_6_class_options(mc); |
57040d45 | 2544 | smc->use_ohci_by_default = true; |
4b23699c | 2545 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
2546 | } |
2547 | ||
4b23699c | 2548 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
2549 | |
2550 | /* | |
2551 | * pseries-2.4 | |
2552 | */ | |
80fd50f9 CH |
2553 | #define SPAPR_COMPAT_2_4 \ |
2554 | HW_COMPAT_2_4 | |
2555 | ||
5013c547 | 2556 | static void spapr_machine_2_4_instance_options(MachineState *machine) |
1c5f29bb | 2557 | { |
5013c547 DG |
2558 | spapr_machine_2_5_instance_options(machine); |
2559 | } | |
1c5f29bb | 2560 | |
5013c547 DG |
2561 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
2562 | { | |
fc9f38c3 DG |
2563 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2564 | ||
2565 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 2566 | smc->dr_lmb_enabled = false; |
f949b4e5 | 2567 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
2568 | } |
2569 | ||
fccbc785 | 2570 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
2571 | |
2572 | /* | |
2573 | * pseries-2.3 | |
2574 | */ | |
38ff32c6 | 2575 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
2576 | HW_COMPAT_2_3 \ |
2577 | {\ | |
2578 | .driver = "spapr-pci-host-bridge",\ | |
2579 | .property = "dynamic-reconfiguration",\ | |
2580 | .value = "off",\ | |
2581 | }, | |
38ff32c6 | 2582 | |
5013c547 | 2583 | static void spapr_machine_2_3_instance_options(MachineState *machine) |
d25228e7 | 2584 | { |
5013c547 | 2585 | spapr_machine_2_4_instance_options(machine); |
ff14e817 | 2586 | savevm_skip_section_footers(); |
13d16814 | 2587 | global_state_set_optional(); |
09b5e30d | 2588 | savevm_skip_configuration(); |
d25228e7 JW |
2589 | } |
2590 | ||
5013c547 | 2591 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 2592 | { |
fc9f38c3 | 2593 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 2594 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 2595 | } |
fccbc785 | 2596 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 2597 | |
1c5f29bb DG |
2598 | /* |
2599 | * pseries-2.2 | |
2600 | */ | |
2601 | ||
2602 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
2603 | HW_COMPAT_2_2 \ |
2604 | {\ | |
2605 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
2606 | .property = "mem_win_size",\ | |
2607 | .value = "0x20000000",\ | |
2608 | }, | |
2609 | ||
5013c547 | 2610 | static void spapr_machine_2_2_instance_options(MachineState *machine) |
1c5f29bb | 2611 | { |
5013c547 | 2612 | spapr_machine_2_3_instance_options(machine); |
cba0e779 | 2613 | machine->suppress_vmdesc = true; |
1c5f29bb DG |
2614 | } |
2615 | ||
5013c547 | 2616 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 2617 | { |
fc9f38c3 | 2618 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 2619 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
4aee7362 | 2620 | } |
fccbc785 | 2621 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 2622 | |
1c5f29bb DG |
2623 | /* |
2624 | * pseries-2.1 | |
2625 | */ | |
2626 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 2627 | HW_COMPAT_2_1 |
3dab0244 | 2628 | |
5013c547 | 2629 | static void spapr_machine_2_1_instance_options(MachineState *machine) |
1c5f29bb | 2630 | { |
5013c547 | 2631 | spapr_machine_2_2_instance_options(machine); |
1c5f29bb | 2632 | } |
d25228e7 | 2633 | |
5013c547 | 2634 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 2635 | { |
fc9f38c3 | 2636 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 2637 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 2638 | } |
fccbc785 | 2639 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 2640 | |
29ee3247 | 2641 | static void spapr_machine_register_types(void) |
9fdf0c29 | 2642 | { |
29ee3247 | 2643 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
2644 | } |
2645 | ||
29ee3247 | 2646 | type_init(spapr_machine_register_types) |