[mirror_qemu.git] / hw / ppc / spapr_cpu_core.c

/*
 * sPAPR CPU core device, acts as container of CPU thread devices.
 *
 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */
#include "hw/cpu/core.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "target-ppc/cpu.h"
#include "hw/ppc/spapr.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include "sysemu/cpus.h"
#include "target-ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target-ppc/mmu-hash64.h"
#include "sysemu/numa.h"

static void spapr_cpu_reset(void *opaque)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;

    cpu_reset(cs);

    /* All CPUs start halted.  CPU0 is unhalted from the machine level
     * reset code and the rest are explicitly started up by the guest
     * using an RTAS call */
    cs->halted = 1;

    env->spr[SPR_HIOR] = 0;

    ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
                                &error_fatal);
}

static void spapr_cpu_destroy(PowerPCCPU *cpu)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());

    xics_cpu_destroy(spapr->xics, cpu);
    qemu_unregister_reset(spapr_cpu_reset, cpu);
}

void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
{
    CPUPPCState *env = &cpu->env;
    CPUState *cs = CPU(cpu);
    int i;

    /* Set time-base frequency to 512 MHz */
    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);

    /* Enable PAPR mode in TCG or KVM */
    cpu_ppc_set_papr(cpu);

    if (cpu->max_compat) {
        Error *local_err = NULL;

        ppc_set_compat(cpu, cpu->max_compat, &local_err);
        if (local_err) {
            error_propagate(errp, local_err);
            return;
        }
    }

    /* Set NUMA node for the added CPUs  */
    for (i = 0; i < nb_numa_nodes; i++) {
        if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) {
            cs->numa_node = i;
            break;
        }
    }

    xics_cpu_setup(spapr->xics, cpu);

    qemu_register_reset(spapr_cpu_reset, cpu);
    spapr_cpu_reset(cpu);
}

/*
 * Return the sPAPR CPU core type for @model which essentially is the CPU
 * model specified with -cpu cmdline option.
 */
char *spapr_get_cpu_core_type(const char *model)
{
    char *core_type;
    gchar **model_pieces = g_strsplit(model, ",", 2);

    core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
    g_strfreev(model_pieces);

    /* Check whether it exists or whether we have to look up an alias name */
    if (!object_class_by_name(core_type)) {
        const char *realmodel;

        g_free(core_type);
        realmodel = ppc_cpu_lookup_alias(model);
        if (realmodel) {
            return spapr_get_cpu_core_type(realmodel);
        }
        return NULL;
    }

    return core_type;
}

static void spapr_core_release(DeviceState *dev, void *opaque)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    const char *typename = object_class_get_name(sc->cpu_class);
    size_t size = object_type_get_instance_size(typename);
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    CPUCore *cc = CPU_CORE(dev);
    int i;

    for (i = 0; i < cc->nr_threads; i++) {
        void *obj = sc->threads + i * size;
        DeviceState *dev = DEVICE(obj);
        CPUState *cs = CPU(dev);
        PowerPCCPU *cpu = POWERPC_CPU(cs);

        spapr_cpu_destroy(cpu);
        cpu_remove_sync(cs);
        object_unparent(obj);
    }

    spapr->cores[cc->core_id / smp_threads] = NULL;

    g_free(sc->threads);
    object_unparent(OBJECT(dev));
}

void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
                       Error **errp)
{
    CPUCore *cc = CPU_CORE(dev);
    int smt = kvmppc_smt_threads();
    int index = cc->core_id / smp_threads;
    sPAPRDRConnector *drc =
        spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
    sPAPRDRConnectorClass *drck;
    Error *local_err = NULL;

    if (index == 0) {
        error_setg(errp, "Boot CPU core may not be unplugged");
        return;
    }

    g_assert(drc);

    drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
    drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_hotplug_req_remove_by_index(drc);
}

void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
                     Error **errp)
{
    sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
    sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(dev);
    CPUState *cs = CPU(core->threads);
    sPAPRDRConnector *drc;
    sPAPRDRConnectorClass *drck;
    Error *local_err = NULL;
    void *fdt = NULL;
    int fdt_offset = 0;
    int index = cc->core_id / smp_threads;
    int smt = kvmppc_smt_threads();

    drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
    spapr->cores[index] = OBJECT(dev);

    g_assert(drc);

    /*
     * Setup CPU DT entries only for hotplugged CPUs. For boot time or
     * coldplugged CPUs DT entries are setup in spapr_finalize_fdt().
     */
    if (dev->hotplugged) {
        fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
    }

    drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
    drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
    if (local_err) {
        g_free(fdt);
        spapr->cores[index] = NULL;
        error_propagate(errp, local_err);
        return;
    }

    if (dev->hotplugged) {
        /*
         * Send hotplug notification interrupt to the guest only in case
         * of hotplugged CPUs.
         */
        spapr_hotplug_req_add_by_index(drc);
    } else {
        /*
         * Set the right DRC states for cold plugged CPU.
         */
        drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
        drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
    }
}

void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
                         Error **errp)
{
    MachineState *machine = MACHINE(OBJECT(hotplug_dev));
    MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
    sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
    int spapr_max_cores = max_cpus / smp_threads;
    int index;
    Error *local_err = NULL;
    CPUCore *cc = CPU_CORE(dev);
    char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
    const char *type = object_get_typename(OBJECT(dev));

    if (!mc->query_hotpluggable_cpus) {
        error_setg(&local_err, "CPU hotplug not supported for this machine");
        goto out;
    }

    if (strcmp(base_core_type, type)) {
        error_setg(&local_err, "CPU core type should be %s", base_core_type);
        goto out;
    }

    if (cc->nr_threads != smp_threads) {
        error_setg(&local_err, "threads must be %d", smp_threads);
        goto out;
    }

    if (cc->core_id % smp_threads) {
        error_setg(&local_err, "invalid core id %d", cc->core_id);
        goto out;
    }

    index = cc->core_id / smp_threads;
    if (index < 0 || index >= spapr_max_cores) {
        error_setg(&local_err, "core id %d out of range", cc->core_id);
        goto out;
    }

    if (spapr->cores[index]) {
        error_setg(&local_err, "core %d already populated", cc->core_id);
        goto out;
    }

out:
    g_free(base_core_type);
    error_propagate(errp, local_err);
}

static void spapr_cpu_core_realize_child(Object *child, Error **errp)
{
    Error *local_err = NULL;
    sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
    CPUState *cs = CPU(child);
    PowerPCCPU *cpu = POWERPC_CPU(cs);

    object_property_set_bool(child, true, "realized", &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    spapr_cpu_init(spapr, cpu, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }
}

static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(OBJECT(dev));
    const char *typename = object_class_get_name(sc->cpu_class);
    size_t size = object_type_get_instance_size(typename);
    Error *local_err = NULL;
    void *obj;
    int i, j;

    sc->threads = g_malloc0(size * cc->nr_threads);
    for (i = 0; i < cc->nr_threads; i++) {
        char id[32];
        CPUState *cs;

        obj = sc->threads + i * size;

        object_initialize(obj, size, typename);
        cs = CPU(obj);
        cs->cpu_index = cc->core_id + i;
        snprintf(id, sizeof(id), "thread[%d]", i);
        object_property_add_child(OBJECT(sc), id, obj, &local_err);
        if (local_err) {
            goto err;
        }
        object_unref(obj);
    }

    for (j = 0; j < cc->nr_threads; j++) {
        obj = sc->threads + j * size;

        spapr_cpu_core_realize_child(obj, &local_err);
        if (local_err) {
            goto err;
        }
    }
    return;

err:
    while (--i >= 0) {
        obj = sc->threads + i * size;
        object_unparent(obj);
    }
    g_free(sc->threads);
    error_propagate(errp, local_err);
}

static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    dc->realize = spapr_cpu_core_realize;
}

/*
 * instance_init routines from different flavours of sPAPR CPU cores.
 */
#define SPAPR_CPU_CORE_INITFN(_type, _fname) \
static void glue(glue(spapr_cpu_core_, _fname), _initfn(Object *obj)) \
{ \
    sPAPRCPUCore *core = SPAPR_CPU_CORE(obj); \
    char *name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, stringify(_type)); \
    ObjectClass *oc = object_class_by_name(name); \
    g_assert(oc); \
    g_free((void *)name); \
    core->cpu_class = oc; \
}

SPAPR_CPU_CORE_INITFN(970mp_v1.0, 970MP_v10);
SPAPR_CPU_CORE_INITFN(970mp_v1.1, 970MP_v11);
SPAPR_CPU_CORE_INITFN(970_v2.2, 970);
SPAPR_CPU_CORE_INITFN(POWER5+_v2.1, POWER5plus);
SPAPR_CPU_CORE_INITFN(POWER7_v2.3, POWER7);
SPAPR_CPU_CORE_INITFN(POWER7+_v2.1, POWER7plus);
SPAPR_CPU_CORE_INITFN(POWER8_v2.0, POWER8);
SPAPR_CPU_CORE_INITFN(POWER8E_v2.1, POWER8E);
SPAPR_CPU_CORE_INITFN(POWER8NVL_v1.0, POWER8NVL);

typedef struct SPAPRCoreInfo {
    const char *name;
    void (*initfn)(Object *obj);
} SPAPRCoreInfo;

static const SPAPRCoreInfo spapr_cores[] = {
    /* 970 */
    { .name = "970_v2.2", .initfn = spapr_cpu_core_970_initfn },

    /* 970MP variants */
    { .name = "970MP_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
    { .name = "970mp_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
    { .name = "970MP_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
    { .name = "970mp_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },

    /* POWER5+ */
    { .name = "POWER5+_v2.1", .initfn = spapr_cpu_core_POWER5plus_initfn },

    /* POWER7 */
    { .name = "POWER7_v2.3", .initfn = spapr_cpu_core_POWER7_initfn },

    /* POWER7+ */
    { .name = "POWER7+_v2.1", .initfn = spapr_cpu_core_POWER7plus_initfn },

    /* POWER8 */
    { .name = "POWER8_v2.0", .initfn = spapr_cpu_core_POWER8_initfn },

    /* POWER8E */
    { .name = "POWER8E_v2.1", .initfn = spapr_cpu_core_POWER8E_initfn },

    /* POWER8NVL */
    { .name = "POWER8NVL_v1.0", .initfn = spapr_cpu_core_POWER8NVL_initfn },

    { .name = NULL }
};

static void spapr_cpu_core_register(const SPAPRCoreInfo *info)
{
    TypeInfo type_info = {
        .parent = TYPE_SPAPR_CPU_CORE,
        .instance_size = sizeof(sPAPRCPUCore),
        .instance_init = info->initfn,
    };

    type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, info->name);
    type_register(&type_info);
    g_free((void *)type_info.name);
}

static const TypeInfo spapr_cpu_core_type_info = {
    .name = TYPE_SPAPR_CPU_CORE,
    .parent = TYPE_CPU_CORE,
    .abstract = true,
    .instance_size = sizeof(sPAPRCPUCore),
    .class_init = spapr_cpu_core_class_init,
};

static void spapr_cpu_core_register_types(void)
{
    const SPAPRCoreInfo *info = spapr_cores;

    type_register_static(&spapr_cpu_core_type_info);
    while (info->name) {
        spapr_cpu_core_register(info);
        info++;
    }
}

type_init(spapr_cpu_core_register_types)
Commit	Line	Data
3b542549 BR	1	/*
	2	* sPAPR CPU core device, acts as container of CPU thread devices.
	3	*
	4	* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
	9	#include "hw/cpu/core.h"
	10	#include "hw/ppc/spapr_cpu_core.h"
	11	#include "target-ppc/cpu.h"
	12	#include "hw/ppc/spapr.h"
	13	#include "hw/boards.h"
	14	#include "qapi/error.h"
a9c94277	15	#include "sysemu/cpus.h"
3b542549	16	#include "target-ppc/kvm_ppc.h"
afd10a0f BR	17	#include "hw/ppc/ppc.h"
afd10a0f BR	18	#include "target-ppc/mmu-hash64.h"
a9c94277	19	#include "sysemu/numa.h"
afd10a0f BR	20
	21	static void spapr_cpu_reset(void *opaque)
	22	{
	23	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	24	PowerPCCPU *cpu = opaque;
	25	CPUState *cs = CPU(cpu);
	26	CPUPPCState *env = &cpu->env;
	27
	28	cpu_reset(cs);
	29
	30	/* All CPUs start halted. CPU0 is unhalted from the machine level
	31	* reset code and the rest are explicitly started up by the guest
	32	* using an RTAS call */
	33	cs->halted = 1;
	34
	35	env->spr[SPR_HIOR] = 0;
	36
	37	ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
	38	&error_fatal);
	39	}
	40
6f4b5c3e BR	41	static void spapr_cpu_destroy(PowerPCCPU *cpu)
	42	{
	43	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	44
27f24582	45	xics_cpu_destroy(spapr->xics, cpu);
6f4b5c3e BR	46	qemu_unregister_reset(spapr_cpu_reset, cpu);
	47	}
	48
afd10a0f BR	49	void spapr_cpu_init(sPAPRMachineState spapr, PowerPCCPU cpu, Error **errp)
	50	{
	51	CPUPPCState *env = &cpu->env;
af81cf32 BR	52	CPUState *cs = CPU(cpu);
af81cf32 BR	53	int i;
afd10a0f BR	54
	55	/* Set time-base frequency to 512 MHz */
	56	cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
	57
	58	/* Enable PAPR mode in TCG or KVM */
	59	cpu_ppc_set_papr(cpu);
	60
	61	if (cpu->max_compat) {
	62	Error *local_err = NULL;
	63
	64	ppc_set_compat(cpu, cpu->max_compat, &local_err);
	65	if (local_err) {
	66	error_propagate(errp, local_err);
	67	return;
	68	}
	69	}
	70
af81cf32 BR	71	/* Set NUMA node for the added CPUs */
	72	for (i = 0; i < nb_numa_nodes; i++) {
	73	if (test_bit(cs->cpu_index, numa_info[i].node_cpu)) {
	74	cs->numa_node = i;
	75	break;
	76	}
	77	}
	78
27f24582	79	xics_cpu_setup(spapr->xics, cpu);
afd10a0f BR	80
afd10a0f BR	81	qemu_register_reset(spapr_cpu_reset, cpu);
af81cf32	82	spapr_cpu_reset(cpu);
afd10a0f	83	}
3b542549	84
94a94e4c BR	85	/*
	86	* Return the sPAPR CPU core type for @model which essentially is the CPU
	87	* model specified with -cpu cmdline option.
	88	*/
	89	char spapr_get_cpu_core_type(const char model)
	90	{
	91	char *core_type;
	92	gchar **model_pieces = g_strsplit(model, ",", 2);
	93
	94	core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
	95	g_strfreev(model_pieces);
4babfaf0 TH	96
	97	/* Check whether it exists or whether we have to look up an alias name */
	98	if (!object_class_by_name(core_type)) {
	99	const char *realmodel;
	100
	101	g_free(core_type);
	102	realmodel = ppc_cpu_lookup_alias(model);
	103	if (realmodel) {
	104	return spapr_get_cpu_core_type(realmodel);
	105	}
	106	return NULL;
	107	}
	108
94a94e4c BR	109	return core_type;
	110	}
	111
6f4b5c3e BR	112	static void spapr_core_release(DeviceState dev, void opaque)
	113	{
	114	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
	115	const char *typename = object_class_get_name(sc->cpu_class);
	116	size_t size = object_type_get_instance_size(typename);
	117	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
6f4b5c3e	118	CPUCore *cc = CPU_CORE(dev);
6f4b5c3e BR	119	int i;
	120
	121	for (i = 0; i < cc->nr_threads; i++) {
	122	void obj = sc->threads + i size;
	123	DeviceState *dev = DEVICE(obj);
	124	CPUState *cs = CPU(dev);
	125	PowerPCCPU *cpu = POWERPC_CPU(cs);
	126
	127	spapr_cpu_destroy(cpu);
	128	cpu_remove_sync(cs);
	129	object_unparent(obj);
	130	}
	131
12bf2d33	132	spapr->cores[cc->core_id / smp_threads] = NULL;
6f4b5c3e	133
8a1eb71b	134	g_free(sc->threads);
6f4b5c3e BR	135	object_unparent(OBJECT(dev));
	136	}
	137
	138	void spapr_core_unplug(HotplugHandler hotplug_dev, DeviceState dev,
	139	Error **errp)
	140	{
44d691f7	141	CPUCore *cc = CPU_CORE(dev);
12bf2d33 GK	142	int smt = kvmppc_smt_threads();
12bf2d33 GK	143	int index = cc->core_id / smp_threads;
6f4b5c3e	144	sPAPRDRConnector *drc =
12bf2d33	145	spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
6f4b5c3e BR	146	sPAPRDRConnectorClass *drck;
	147	Error *local_err = NULL;
	148
62be8b04 BR	149	if (index == 0) {
	150	error_setg(errp, "Boot CPU core may not be unplugged");
	151	return;
	152	}
	153
6f4b5c3e BR	154	g_assert(drc);
	155
	156	drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
	157	drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
	158	if (local_err) {
	159	error_propagate(errp, local_err);
	160	return;
	161	}
	162
	163	spapr_hotplug_req_remove_by_index(drc);
	164	}
	165
af81cf32 BR	166	void spapr_core_plug(HotplugHandler hotplug_dev, DeviceState dev,
	167	Error **errp)
	168	{
af81cf32 BR	169	sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
	170	sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
	171	CPUCore *cc = CPU_CORE(dev);
	172	CPUState *cs = CPU(core->threads);
	173	sPAPRDRConnector *drc;
	174	sPAPRDRConnectorClass *drck;
	175	Error *local_err = NULL;
	176	void *fdt = NULL;
	177	int fdt_offset = 0;
12bf2d33	178	int index = cc->core_id / smp_threads;
af81cf32 BR	179	int smt = kvmppc_smt_threads();
af81cf32 BR	180
12bf2d33	181	drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
af81cf32 BR	182	spapr->cores[index] = OBJECT(dev);
af81cf32 BR	183
af81cf32 BR	184	g_assert(drc);
	185
	186	/*
	187	* Setup CPU DT entries only for hotplugged CPUs. For boot time or
	188	* coldplugged CPUs DT entries are setup in spapr_finalize_fdt().
	189	*/
	190	if (dev->hotplugged) {
	191	fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
	192	}
	193
	194	drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
	195	drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
	196	if (local_err) {
	197	g_free(fdt);
	198	spapr->cores[index] = NULL;
	199	error_propagate(errp, local_err);
	200	return;
	201	}
	202
	203	if (dev->hotplugged) {
	204	/*
	205	* Send hotplug notification interrupt to the guest only in case
	206	* of hotplugged CPUs.
	207	*/
	208	spapr_hotplug_req_add_by_index(drc);
	209	} else {
	210	/*
	211	* Set the right DRC states for cold plugged CPU.
	212	*/
	213	drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
	214	drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
	215	}
	216	}
	217
94a94e4c BR	218	void spapr_core_pre_plug(HotplugHandler hotplug_dev, DeviceState dev,
	219	Error **errp)
	220	{
	221	MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3c0c47e3	222	MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
94a94e4c BR	223	sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
94a94e4c BR	224	int spapr_max_cores = max_cpus / smp_threads;
7cdd7613	225	int index;
94a94e4c BR	226	Error *local_err = NULL;
	227	CPUCore *cc = CPU_CORE(dev);
	228	char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
	229	const char *type = object_get_typename(OBJECT(dev));
	230
3c0c47e3	231	if (!mc->query_hotpluggable_cpus) {
c8721d35	232	error_setg(&local_err, "CPU hotplug not supported for this machine");
94a94e4c BR	233	goto out;
	234	}
	235
c8721d35 BR	236	if (strcmp(base_core_type, type)) {
c8721d35 BR	237	error_setg(&local_err, "CPU core type should be %s", base_core_type);
af81cf32 BR	238	goto out;
	239	}
	240
94a94e4c BR	241	if (cc->nr_threads != smp_threads) {
	242	error_setg(&local_err, "threads must be %d", smp_threads);
	243	goto out;
	244	}
	245
12bf2d33	246	if (cc->core_id % smp_threads) {
df3c286c	247	error_setg(&local_err, "invalid core id %d", cc->core_id);
94a94e4c BR	248	goto out;
	249	}
	250
12bf2d33	251	index = cc->core_id / smp_threads;
94a94e4c BR	252	if (index < 0 \|\| index >= spapr_max_cores) {
	253	error_setg(&local_err, "core id %d out of range", cc->core_id);
	254	goto out;
	255	}
	256
	257	if (spapr->cores[index]) {
	258	error_setg(&local_err, "core %d already populated", cc->core_id);
	259	goto out;
	260	}
	261
	262	out:
	263	g_free(base_core_type);
	264	error_propagate(errp, local_err);
	265	}
	266
7093645a	267	static void spapr_cpu_core_realize_child(Object child, Error *errp)
3b542549	268	{
7093645a	269	Error *local_err = NULL;
3b542549 BR	270	sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
	271	CPUState *cs = CPU(child);
	272	PowerPCCPU *cpu = POWERPC_CPU(cs);
	273
f11235b9 GK	274	object_property_set_bool(child, true, "realized", &local_err);
	275	if (local_err) {
	276	error_propagate(errp, local_err);
7093645a	277	return;
3b542549 BR	278	}
3b542549 BR	279
f11235b9 GK	280	spapr_cpu_init(spapr, cpu, &local_err);
	281	if (local_err) {
	282	error_propagate(errp, local_err);
7093645a	283	return;
3b542549	284	}
3b542549 BR	285	}
	286
	287	static void spapr_cpu_core_realize(DeviceState dev, Error *errp)
	288	{
	289	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
	290	CPUCore *cc = CPU_CORE(OBJECT(dev));
	291	const char *typename = object_class_get_name(sc->cpu_class);
	292	size_t size = object_type_get_instance_size(typename);
	293	Error *local_err = NULL;
7093645a BR	294	void *obj;
7093645a BR	295	int i, j;
3b542549 BR	296
	297	sc->threads = g_malloc0(size * cc->nr_threads);
	298	for (i = 0; i < cc->nr_threads; i++) {
	299	char id[32];
b63578bd IM	300	CPUState *cs;
b63578bd IM	301
7093645a	302	obj = sc->threads + i * size;
3b542549 BR	303
3b542549 BR	304	object_initialize(obj, size, typename);
b63578bd IM	305	cs = CPU(obj);
b63578bd IM	306	cs->cpu_index = cc->core_id + i;
3b542549 BR	307	snprintf(id, sizeof(id), "thread[%d]", i);
	308	object_property_add_child(OBJECT(sc), id, obj, &local_err);
	309	if (local_err) {
	310	goto err;
	311	}
8e758dee	312	object_unref(obj);
3b542549	313	}
7093645a BR	314
	315	for (j = 0; j < cc->nr_threads; j++) {
	316	obj = sc->threads + j * size;
	317
	318	spapr_cpu_core_realize_child(obj, &local_err);
	319	if (local_err) {
	320	goto err;
	321	}
3b542549	322	}
7093645a	323	return;
3b542549 BR	324
3b542549 BR	325	err:
dde35bc9	326	while (--i >= 0) {
3b542549 BR	327	obj = sc->threads + i * size;
3b542549 BR	328	object_unparent(obj);
3b542549 BR	329	}
	330	g_free(sc->threads);
	331	error_propagate(errp, local_err);
	332	}
	333
	334	static void spapr_cpu_core_class_init(ObjectClass oc, void data)
	335	{
	336	DeviceClass *dc = DEVICE_CLASS(oc);
	337	dc->realize = spapr_cpu_core_realize;
	338	}
	339
	340	/*
	341	* instance_init routines from different flavours of sPAPR CPU cores.
3b542549 BR	342	*/
	343	#define SPAPR_CPU_CORE_INITFN(_type, _fname) \
	344	static void glue(glue(spapr_cpu_core_, _fname), _initfn(Object *obj)) \
	345	{ \
	346	sPAPRCPUCore *core = SPAPR_CPU_CORE(obj); \
	347	char *name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, stringify(_type)); \
	348	ObjectClass *oc = object_class_by_name(name); \
	349	g_assert(oc); \
	350	g_free((void *)name); \
	351	core->cpu_class = oc; \
	352	}
	353
470f2157 BR	354	SPAPR_CPU_CORE_INITFN(970mp_v1.0, 970MP_v10);
470f2157 BR	355	SPAPR_CPU_CORE_INITFN(970mp_v1.1, 970MP_v11);
ff461b8d BR	356	SPAPR_CPU_CORE_INITFN(970_v2.2, 970);
ff461b8d BR	357	SPAPR_CPU_CORE_INITFN(POWER5+_v2.1, POWER5plus);
3b542549 BR	358	SPAPR_CPU_CORE_INITFN(POWER7_v2.3, POWER7);
	359	SPAPR_CPU_CORE_INITFN(POWER7+_v2.1, POWER7plus);
	360	SPAPR_CPU_CORE_INITFN(POWER8_v2.0, POWER8);
	361	SPAPR_CPU_CORE_INITFN(POWER8E_v2.1, POWER8E);
470f2157	362	SPAPR_CPU_CORE_INITFN(POWER8NVL_v1.0, POWER8NVL);
3b542549 BR	363
	364	typedef struct SPAPRCoreInfo {
	365	const char *name;
	366	void (initfn)(Object obj);
	367	} SPAPRCoreInfo;
	368
	369	static const SPAPRCoreInfo spapr_cores[] = {
4babfaf0	370	/* 970 */
470f2157	371	{ .name = "970_v2.2", .initfn = spapr_cpu_core_970_initfn },
ff461b8d	372
4babfaf0	373	/* 970MP variants */
470f2157 BR	374	{ .name = "970MP_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
	375	{ .name = "970mp_v1.0", .initfn = spapr_cpu_core_970MP_v10_initfn },
	376	{ .name = "970MP_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
	377	{ .name = "970mp_v1.1", .initfn = spapr_cpu_core_970MP_v11_initfn },
470f2157	378
4babfaf0	379	/* POWER5+ */
470f2157	380	{ .name = "POWER5+_v2.1", .initfn = spapr_cpu_core_POWER5plus_initfn },
ff461b8d	381
4babfaf0	382	/* POWER7 */
3b542549	383	{ .name = "POWER7_v2.3", .initfn = spapr_cpu_core_POWER7_initfn },
3b542549	384
4babfaf0	385	/* POWER7+ */
3b542549	386	{ .name = "POWER7+_v2.1", .initfn = spapr_cpu_core_POWER7plus_initfn },
3b542549	387
4babfaf0	388	/* POWER8 */
3b542549	389	{ .name = "POWER8_v2.0", .initfn = spapr_cpu_core_POWER8_initfn },
3b542549	390
4babfaf0	391	/* POWER8E */
3b542549	392	{ .name = "POWER8E_v2.1", .initfn = spapr_cpu_core_POWER8E_initfn },
3b542549	393
4babfaf0	394	/* POWER8NVL */
470f2157	395	{ .name = "POWER8NVL_v1.0", .initfn = spapr_cpu_core_POWER8NVL_initfn },
470f2157	396
3b542549 BR	397	{ .name = NULL }
	398	};
	399
	400	static void spapr_cpu_core_register(const SPAPRCoreInfo *info)
	401	{
	402	TypeInfo type_info = {
	403	.parent = TYPE_SPAPR_CPU_CORE,
	404	.instance_size = sizeof(sPAPRCPUCore),
	405	.instance_init = info->initfn,
	406	};
	407
	408	type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, info->name);
	409	type_register(&type_info);
	410	g_free((void *)type_info.name);
	411	}
	412
	413	static const TypeInfo spapr_cpu_core_type_info = {
	414	.name = TYPE_SPAPR_CPU_CORE,
	415	.parent = TYPE_CPU_CORE,
	416	.abstract = true,
	417	.instance_size = sizeof(sPAPRCPUCore),
	418	.class_init = spapr_cpu_core_class_init,
	419	};
	420
	421	static void spapr_cpu_core_register_types(void)
	422	{
	423	const SPAPRCoreInfo *info = spapr_cores;
	424
	425	type_register_static(&spapr_cpu_core_type_info);
	426	while (info->name) {
	427	spapr_cpu_core_register(info);
	428	info++;
	429	}
	430	}
	431
	432	type_init(spapr_cpu_core_register_types)