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Commit | Line | Data |
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0d75590d | 1 | #include "qemu/osdep.h" |
da34e65c | 2 | #include "qapi/error.h" |
9c17d615 | 3 | #include "sysemu/sysemu.h" |
03dd024f | 4 | #include "qemu/log.h" |
9fdf0c29 | 5 | #include "cpu.h" |
63c91552 | 6 | #include "exec/exec-all.h" |
ed120055 | 7 | #include "helper_regs.h" |
0d09e41a | 8 | #include "hw/ppc/spapr.h" |
d5aea6f3 | 9 | #include "mmu-hash64.h" |
3794d548 AK |
10 | #include "cpu-models.h" |
11 | #include "trace.h" | |
77ac58dd | 12 | #include "sysemu/kvm.h" |
3794d548 | 13 | #include "kvm_ppc.h" |
f43e3525 | 14 | |
a46622fd | 15 | struct SPRSyncState { |
a46622fd AK |
16 | int spr; |
17 | target_ulong value; | |
18 | target_ulong mask; | |
19 | }; | |
20 | ||
e0eeb4a2 | 21 | static void do_spr_sync(CPUState *cs, void *arg) |
a46622fd AK |
22 | { |
23 | struct SPRSyncState *s = arg; | |
e0eeb4a2 | 24 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
a46622fd AK |
25 | CPUPPCState *env = &cpu->env; |
26 | ||
e0eeb4a2 | 27 | cpu_synchronize_state(cs); |
a46622fd AK |
28 | env->spr[s->spr] &= ~s->mask; |
29 | env->spr[s->spr] |= s->value; | |
30 | } | |
31 | ||
32 | static void set_spr(CPUState *cs, int spr, target_ulong value, | |
33 | target_ulong mask) | |
34 | { | |
35 | struct SPRSyncState s = { | |
a46622fd AK |
36 | .spr = spr, |
37 | .value = value, | |
38 | .mask = mask | |
39 | }; | |
40 | run_on_cpu(cs, do_spr_sync, &s); | |
41 | } | |
42 | ||
af08a58f TH |
43 | static bool has_spr(PowerPCCPU *cpu, int spr) |
44 | { | |
45 | /* We can test whether the SPR is defined by checking for a valid name */ | |
46 | return cpu->env.spr_cb[spr].name != NULL; | |
47 | } | |
48 | ||
f3c75d42 AK |
49 | static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index) |
50 | { | |
51 | /* | |
52 | * hash value/pteg group index is normalized by htab_mask | |
53 | */ | |
54 | if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) { | |
55 | return false; | |
56 | } | |
57 | return true; | |
58 | } | |
59 | ||
ecbc25fa DG |
60 | static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) |
61 | { | |
62 | MachineState *machine = MACHINE(spapr); | |
63 | MemoryHotplugState *hpms = &spapr->hotplug_memory; | |
64 | ||
65 | if (addr < machine->ram_size) { | |
66 | return true; | |
67 | } | |
68 | if ((addr >= hpms->base) | |
69 | && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { | |
70 | return true; | |
71 | } | |
72 | ||
73 | return false; | |
74 | } | |
75 | ||
28e02042 | 76 | static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
f43e3525 DG |
77 | target_ulong opcode, target_ulong *args) |
78 | { | |
b13ce26d | 79 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
80 | target_ulong flags = args[0]; |
81 | target_ulong pte_index = args[1]; | |
82 | target_ulong pteh = args[2]; | |
83 | target_ulong ptel = args[3]; | |
1f0252e6 | 84 | unsigned apshift; |
f73a2575 | 85 | target_ulong raddr; |
7c43bca0 | 86 | target_ulong index; |
7c43bca0 | 87 | uint64_t token; |
f43e3525 | 88 | |
1f0252e6 | 89 | apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); |
1114e712 DG |
90 | if (!apshift) { |
91 | /* Bad page size encoding */ | |
92 | return H_PARAMETER; | |
f43e3525 DG |
93 | } |
94 | ||
1114e712 | 95 | raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); |
f43e3525 | 96 | |
ecbc25fa | 97 | if (is_ram_address(spapr, raddr)) { |
f73a2575 | 98 | /* Regular RAM - should have WIMG=0010 */ |
d5aea6f3 | 99 | if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { |
f73a2575 DG |
100 | return H_PARAMETER; |
101 | } | |
102 | } else { | |
c1175907 | 103 | target_ulong wimg_flags; |
f73a2575 DG |
104 | /* Looks like an IO address */ |
105 | /* FIXME: What WIMG combinations could be sensible for IO? | |
106 | * For now we allow WIMG=010x, but are there others? */ | |
107 | /* FIXME: Should we check against registered IO addresses? */ | |
c1175907 AK |
108 | wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); |
109 | ||
110 | if (wimg_flags != HPTE64_R_I && | |
111 | wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { | |
f73a2575 DG |
112 | return H_PARAMETER; |
113 | } | |
f43e3525 | 114 | } |
f73a2575 | 115 | |
f43e3525 DG |
116 | pteh &= ~0x60ULL; |
117 | ||
f3c75d42 | 118 | if (!valid_pte_index(env, pte_index)) { |
f43e3525 DG |
119 | return H_PARAMETER; |
120 | } | |
7c43bca0 AK |
121 | |
122 | index = 0; | |
f43e3525 DG |
123 | if (likely((flags & H_EXACT) == 0)) { |
124 | pte_index &= ~7ULL; | |
7c43bca0 | 125 | token = ppc_hash64_start_access(cpu, pte_index); |
7aaf4957 | 126 | for (; index < 8; index++) { |
7ef23068 | 127 | if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) { |
f43e3525 DG |
128 | break; |
129 | } | |
7aaf4957 | 130 | } |
c18ad9a5 | 131 | ppc_hash64_stop_access(cpu, token); |
7aaf4957 AK |
132 | if (index == 8) { |
133 | return H_PTEG_FULL; | |
134 | } | |
f43e3525 | 135 | } else { |
7c43bca0 | 136 | token = ppc_hash64_start_access(cpu, pte_index); |
7ef23068 | 137 | if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) { |
c18ad9a5 | 138 | ppc_hash64_stop_access(cpu, token); |
f43e3525 DG |
139 | return H_PTEG_FULL; |
140 | } | |
c18ad9a5 | 141 | ppc_hash64_stop_access(cpu, token); |
f43e3525 | 142 | } |
7c43bca0 | 143 | |
7ef23068 | 144 | ppc_hash64_store_hpte(cpu, pte_index + index, |
3f94170b | 145 | pteh | HPTE64_V_HPTE_DIRTY, ptel); |
f43e3525 | 146 | |
7c43bca0 | 147 | args[0] = pte_index + index; |
f43e3525 DG |
148 | return H_SUCCESS; |
149 | } | |
150 | ||
a3801402 | 151 | typedef enum { |
a3d0abae DG |
152 | REMOVE_SUCCESS = 0, |
153 | REMOVE_NOT_FOUND = 1, | |
154 | REMOVE_PARM = 2, | |
155 | REMOVE_HW = 3, | |
a3801402 | 156 | } RemoveResult; |
a3d0abae | 157 | |
7ef23068 | 158 | static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, |
a3d0abae DG |
159 | target_ulong avpn, |
160 | target_ulong flags, | |
161 | target_ulong *vp, target_ulong *rp) | |
f43e3525 | 162 | { |
7ef23068 | 163 | CPUPPCState *env = &cpu->env; |
7c43bca0 | 164 | uint64_t token; |
61a36c9b | 165 | target_ulong v, r; |
f43e3525 | 166 | |
f3c75d42 | 167 | if (!valid_pte_index(env, ptex)) { |
a3d0abae | 168 | return REMOVE_PARM; |
f43e3525 DG |
169 | } |
170 | ||
7ef23068 DG |
171 | token = ppc_hash64_start_access(cpu, ptex); |
172 | v = ppc_hash64_load_hpte0(cpu, token, 0); | |
173 | r = ppc_hash64_load_hpte1(cpu, token, 0); | |
c18ad9a5 | 174 | ppc_hash64_stop_access(cpu, token); |
f43e3525 | 175 | |
d5aea6f3 | 176 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 DG |
177 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || |
178 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
a3d0abae | 179 | return REMOVE_NOT_FOUND; |
f43e3525 | 180 | } |
35f9304d | 181 | *vp = v; |
a3d0abae | 182 | *rp = r; |
7ef23068 | 183 | ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); |
61a36c9b | 184 | ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); |
a3d0abae DG |
185 | return REMOVE_SUCCESS; |
186 | } | |
187 | ||
28e02042 | 188 | static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a3d0abae DG |
189 | target_ulong opcode, target_ulong *args) |
190 | { | |
cd0c6f47 | 191 | CPUPPCState *env = &cpu->env; |
a3d0abae DG |
192 | target_ulong flags = args[0]; |
193 | target_ulong pte_index = args[1]; | |
194 | target_ulong avpn = args[2]; | |
a3801402 | 195 | RemoveResult ret; |
a3d0abae | 196 | |
7ef23068 | 197 | ret = remove_hpte(cpu, pte_index, avpn, flags, |
a3d0abae DG |
198 | &args[0], &args[1]); |
199 | ||
200 | switch (ret) { | |
201 | case REMOVE_SUCCESS: | |
e3cffe6f | 202 | check_tlb_flush(env, true); |
a3d0abae DG |
203 | return H_SUCCESS; |
204 | ||
205 | case REMOVE_NOT_FOUND: | |
206 | return H_NOT_FOUND; | |
207 | ||
208 | case REMOVE_PARM: | |
209 | return H_PARAMETER; | |
210 | ||
211 | case REMOVE_HW: | |
212 | return H_HARDWARE; | |
213 | } | |
214 | ||
9a39970d | 215 | g_assert_not_reached(); |
a3d0abae DG |
216 | } |
217 | ||
218 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL | |
219 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL | |
220 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL | |
221 | #define H_BULK_REMOVE_END 0xc000000000000000ULL | |
222 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL | |
223 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL | |
224 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL | |
225 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL | |
226 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL | |
227 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL | |
228 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL | |
229 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL | |
230 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL | |
231 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL | |
232 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL | |
233 | ||
234 | #define H_BULK_REMOVE_MAX_BATCH 4 | |
235 | ||
28e02042 | 236 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a3d0abae DG |
237 | target_ulong opcode, target_ulong *args) |
238 | { | |
cd0c6f47 | 239 | CPUPPCState *env = &cpu->env; |
a3d0abae | 240 | int i; |
cd0c6f47 | 241 | target_ulong rc = H_SUCCESS; |
a3d0abae DG |
242 | |
243 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { | |
244 | target_ulong *tsh = &args[i*2]; | |
245 | target_ulong tsl = args[i*2 + 1]; | |
246 | target_ulong v, r, ret; | |
247 | ||
248 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { | |
249 | break; | |
250 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { | |
251 | return H_PARAMETER; | |
252 | } | |
253 | ||
254 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; | |
255 | *tsh |= H_BULK_REMOVE_RESPONSE; | |
256 | ||
257 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { | |
258 | *tsh |= H_BULK_REMOVE_PARM; | |
259 | return H_PARAMETER; | |
260 | } | |
261 | ||
7ef23068 | 262 | ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, |
a3d0abae DG |
263 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, |
264 | &v, &r); | |
265 | ||
266 | *tsh |= ret << 60; | |
267 | ||
268 | switch (ret) { | |
269 | case REMOVE_SUCCESS: | |
d5aea6f3 | 270 | *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; |
a3d0abae DG |
271 | break; |
272 | ||
273 | case REMOVE_PARM: | |
cd0c6f47 BH |
274 | rc = H_PARAMETER; |
275 | goto exit; | |
a3d0abae DG |
276 | |
277 | case REMOVE_HW: | |
cd0c6f47 BH |
278 | rc = H_HARDWARE; |
279 | goto exit; | |
a3d0abae DG |
280 | } |
281 | } | |
cd0c6f47 | 282 | exit: |
e3cffe6f | 283 | check_tlb_flush(env, true); |
a3d0abae | 284 | |
cd0c6f47 | 285 | return rc; |
f43e3525 DG |
286 | } |
287 | ||
28e02042 | 288 | static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
f43e3525 DG |
289 | target_ulong opcode, target_ulong *args) |
290 | { | |
b13ce26d | 291 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
292 | target_ulong flags = args[0]; |
293 | target_ulong pte_index = args[1]; | |
294 | target_ulong avpn = args[2]; | |
7c43bca0 | 295 | uint64_t token; |
61a36c9b | 296 | target_ulong v, r; |
f43e3525 | 297 | |
f3c75d42 | 298 | if (!valid_pte_index(env, pte_index)) { |
f43e3525 DG |
299 | return H_PARAMETER; |
300 | } | |
301 | ||
7c43bca0 | 302 | token = ppc_hash64_start_access(cpu, pte_index); |
7ef23068 DG |
303 | v = ppc_hash64_load_hpte0(cpu, token, 0); |
304 | r = ppc_hash64_load_hpte1(cpu, token, 0); | |
c18ad9a5 | 305 | ppc_hash64_stop_access(cpu, token); |
f43e3525 | 306 | |
d5aea6f3 | 307 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 | 308 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { |
f43e3525 DG |
309 | return H_NOT_FOUND; |
310 | } | |
311 | ||
d5aea6f3 DG |
312 | r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
313 | HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); | |
314 | r |= (flags << 55) & HPTE64_R_PP0; | |
315 | r |= (flags << 48) & HPTE64_R_KEY_HI; | |
316 | r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); | |
7ef23068 | 317 | ppc_hash64_store_hpte(cpu, pte_index, |
3f94170b | 318 | (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); |
61a36c9b | 319 | ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r); |
d76ab5e1 ND |
320 | /* Flush the tlb */ |
321 | check_tlb_flush(env, true); | |
f43e3525 | 322 | /* Don't need a memory barrier, due to qemu's global lock */ |
7ef23068 | 323 | ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r); |
f43e3525 DG |
324 | return H_SUCCESS; |
325 | } | |
326 | ||
28e02042 | 327 | static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
6bbd5dde EC |
328 | target_ulong opcode, target_ulong *args) |
329 | { | |
330 | CPUPPCState *env = &cpu->env; | |
331 | target_ulong flags = args[0]; | |
332 | target_ulong pte_index = args[1]; | |
333 | uint8_t *hpte; | |
334 | int i, ridx, n_entries = 1; | |
335 | ||
f3c75d42 | 336 | if (!valid_pte_index(env, pte_index)) { |
6bbd5dde EC |
337 | return H_PARAMETER; |
338 | } | |
339 | ||
340 | if (flags & H_READ_4) { | |
341 | /* Clear the two low order bits */ | |
342 | pte_index &= ~(3ULL); | |
343 | n_entries = 4; | |
344 | } | |
345 | ||
346 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
347 | ||
348 | for (i = 0, ridx = 0; i < n_entries; i++) { | |
349 | args[ridx++] = ldq_p(hpte); | |
350 | args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
351 | hpte += HASH_PTE_SIZE_64; | |
352 | } | |
353 | ||
354 | return H_SUCCESS; | |
355 | } | |
356 | ||
423576f7 TH |
357 | static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
358 | target_ulong opcode, target_ulong *args) | |
359 | { | |
360 | cpu_synchronize_state(CPU(cpu)); | |
361 | cpu->env.spr[SPR_SPRG0] = args[0]; | |
362 | ||
363 | return H_SUCCESS; | |
364 | } | |
365 | ||
28e02042 | 366 | static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
367 | target_ulong opcode, target_ulong *args) |
368 | { | |
af08a58f TH |
369 | if (!has_spr(cpu, SPR_DABR)) { |
370 | return H_HARDWARE; /* DABR register not available */ | |
371 | } | |
372 | cpu_synchronize_state(CPU(cpu)); | |
373 | ||
374 | if (has_spr(cpu, SPR_DABRX)) { | |
375 | cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ | |
376 | } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ | |
377 | return H_RESERVED_DABR; | |
378 | } | |
379 | ||
380 | cpu->env.spr[SPR_DABR] = args[0]; | |
381 | return H_SUCCESS; | |
821303f5 DG |
382 | } |
383 | ||
e49ff266 TH |
384 | static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
385 | target_ulong opcode, target_ulong *args) | |
386 | { | |
387 | target_ulong dabrx = args[1]; | |
388 | ||
389 | if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { | |
390 | return H_HARDWARE; | |
391 | } | |
392 | ||
393 | if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 | |
394 | || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { | |
395 | return H_PARAMETER; | |
396 | } | |
397 | ||
398 | cpu_synchronize_state(CPU(cpu)); | |
399 | cpu->env.spr[SPR_DABRX] = dabrx; | |
400 | cpu->env.spr[SPR_DABR] = args[0]; | |
401 | ||
402 | return H_SUCCESS; | |
403 | } | |
404 | ||
3240dd9a TH |
405 | static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
406 | target_ulong opcode, target_ulong *args) | |
407 | { | |
408 | target_ulong flags = args[0]; | |
409 | hwaddr dst = args[1]; | |
410 | hwaddr src = args[2]; | |
411 | hwaddr len = TARGET_PAGE_SIZE; | |
412 | uint8_t *pdst, *psrc; | |
413 | target_long ret = H_SUCCESS; | |
414 | ||
415 | if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE | |
416 | | H_COPY_PAGE | H_ZERO_PAGE)) { | |
417 | qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", | |
418 | flags); | |
419 | return H_PARAMETER; | |
420 | } | |
421 | ||
422 | /* Map-in destination */ | |
423 | if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { | |
424 | return H_PARAMETER; | |
425 | } | |
426 | pdst = cpu_physical_memory_map(dst, &len, 1); | |
427 | if (!pdst || len != TARGET_PAGE_SIZE) { | |
428 | return H_PARAMETER; | |
429 | } | |
430 | ||
431 | if (flags & H_COPY_PAGE) { | |
432 | /* Map-in source, copy to destination, and unmap source again */ | |
433 | if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { | |
434 | ret = H_PARAMETER; | |
435 | goto unmap_out; | |
436 | } | |
437 | psrc = cpu_physical_memory_map(src, &len, 0); | |
438 | if (!psrc || len != TARGET_PAGE_SIZE) { | |
439 | ret = H_PARAMETER; | |
440 | goto unmap_out; | |
441 | } | |
442 | memcpy(pdst, psrc, len); | |
443 | cpu_physical_memory_unmap(psrc, len, 0, len); | |
444 | } else if (flags & H_ZERO_PAGE) { | |
445 | memset(pdst, 0, len); /* Just clear the destination page */ | |
446 | } | |
447 | ||
448 | if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { | |
449 | kvmppc_dcbst_range(cpu, pdst, len); | |
450 | } | |
451 | if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { | |
452 | if (kvm_enabled()) { | |
453 | kvmppc_icbi_range(cpu, pdst, len); | |
454 | } else { | |
455 | tb_flush(CPU(cpu)); | |
456 | } | |
457 | } | |
458 | ||
459 | unmap_out: | |
460 | cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); | |
461 | return ret; | |
462 | } | |
463 | ||
ed120055 DG |
464 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
465 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
466 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
467 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
468 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
469 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
470 | ||
471 | #define VPA_MIN_SIZE 640 | |
472 | #define VPA_SIZE_OFFSET 0x4 | |
473 | #define VPA_SHARED_PROC_OFFSET 0x9 | |
474 | #define VPA_SHARED_PROC_VAL 0x2 | |
475 | ||
e2684c0b | 476 | static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 477 | { |
33276f1b | 478 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
479 | uint16_t size; |
480 | uint8_t tmp; | |
481 | ||
482 | if (vpa == 0) { | |
483 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
484 | return H_HARDWARE; | |
485 | } | |
486 | ||
487 | if (vpa % env->dcache_line_size) { | |
488 | return H_PARAMETER; | |
489 | } | |
490 | /* FIXME: bounds check the address */ | |
491 | ||
41701aa4 | 492 | size = lduw_be_phys(cs->as, vpa + 0x4); |
ed120055 DG |
493 | |
494 | if (size < VPA_MIN_SIZE) { | |
495 | return H_PARAMETER; | |
496 | } | |
497 | ||
498 | /* VPA is not allowed to cross a page boundary */ | |
499 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
500 | return H_PARAMETER; | |
501 | } | |
502 | ||
1bfb37d1 | 503 | env->vpa_addr = vpa; |
ed120055 | 504 | |
2c17449b | 505 | tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
ed120055 | 506 | tmp |= VPA_SHARED_PROC_VAL; |
db3be60d | 507 | stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
ed120055 DG |
508 | |
509 | return H_SUCCESS; | |
510 | } | |
511 | ||
e2684c0b | 512 | static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 513 | { |
1bfb37d1 | 514 | if (env->slb_shadow_addr) { |
ed120055 DG |
515 | return H_RESOURCE; |
516 | } | |
517 | ||
1bfb37d1 | 518 | if (env->dtl_addr) { |
ed120055 DG |
519 | return H_RESOURCE; |
520 | } | |
521 | ||
1bfb37d1 | 522 | env->vpa_addr = 0; |
ed120055 DG |
523 | return H_SUCCESS; |
524 | } | |
525 | ||
e2684c0b | 526 | static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 527 | { |
33276f1b | 528 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
529 | uint32_t size; |
530 | ||
531 | if (addr == 0) { | |
532 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
533 | return H_HARDWARE; | |
534 | } | |
535 | ||
fdfba1a2 | 536 | size = ldl_be_phys(cs->as, addr + 0x4); |
ed120055 DG |
537 | if (size < 0x8) { |
538 | return H_PARAMETER; | |
539 | } | |
540 | ||
541 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
542 | return H_PARAMETER; | |
543 | } | |
544 | ||
1bfb37d1 | 545 | if (!env->vpa_addr) { |
ed120055 DG |
546 | return H_RESOURCE; |
547 | } | |
548 | ||
1bfb37d1 DG |
549 | env->slb_shadow_addr = addr; |
550 | env->slb_shadow_size = size; | |
ed120055 DG |
551 | |
552 | return H_SUCCESS; | |
553 | } | |
554 | ||
e2684c0b | 555 | static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 556 | { |
1bfb37d1 DG |
557 | env->slb_shadow_addr = 0; |
558 | env->slb_shadow_size = 0; | |
ed120055 DG |
559 | return H_SUCCESS; |
560 | } | |
561 | ||
e2684c0b | 562 | static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 563 | { |
33276f1b | 564 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
ed120055 DG |
565 | uint32_t size; |
566 | ||
567 | if (addr == 0) { | |
568 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
569 | return H_HARDWARE; | |
570 | } | |
571 | ||
fdfba1a2 | 572 | size = ldl_be_phys(cs->as, addr + 0x4); |
ed120055 DG |
573 | |
574 | if (size < 48) { | |
575 | return H_PARAMETER; | |
576 | } | |
577 | ||
1bfb37d1 | 578 | if (!env->vpa_addr) { |
ed120055 DG |
579 | return H_RESOURCE; |
580 | } | |
581 | ||
1bfb37d1 | 582 | env->dtl_addr = addr; |
ed120055 DG |
583 | env->dtl_size = size; |
584 | ||
585 | return H_SUCCESS; | |
586 | } | |
587 | ||
73f7821b | 588 | static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 589 | { |
1bfb37d1 | 590 | env->dtl_addr = 0; |
ed120055 DG |
591 | env->dtl_size = 0; |
592 | ||
593 | return H_SUCCESS; | |
594 | } | |
595 | ||
28e02042 | 596 | static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ed120055 DG |
597 | target_ulong opcode, target_ulong *args) |
598 | { | |
599 | target_ulong flags = args[0]; | |
600 | target_ulong procno = args[1]; | |
601 | target_ulong vpa = args[2]; | |
602 | target_ulong ret = H_PARAMETER; | |
e2684c0b | 603 | CPUPPCState *tenv; |
0f20ba62 | 604 | PowerPCCPU *tcpu; |
ed120055 | 605 | |
0f20ba62 | 606 | tcpu = ppc_get_vcpu_by_dt_id(procno); |
5353d03d | 607 | if (!tcpu) { |
ed120055 DG |
608 | return H_PARAMETER; |
609 | } | |
0f20ba62 | 610 | tenv = &tcpu->env; |
ed120055 DG |
611 | |
612 | switch (flags) { | |
613 | case FLAGS_REGISTER_VPA: | |
614 | ret = register_vpa(tenv, vpa); | |
615 | break; | |
616 | ||
617 | case FLAGS_DEREGISTER_VPA: | |
618 | ret = deregister_vpa(tenv, vpa); | |
619 | break; | |
620 | ||
621 | case FLAGS_REGISTER_SLBSHADOW: | |
622 | ret = register_slb_shadow(tenv, vpa); | |
623 | break; | |
624 | ||
625 | case FLAGS_DEREGISTER_SLBSHADOW: | |
626 | ret = deregister_slb_shadow(tenv, vpa); | |
627 | break; | |
628 | ||
629 | case FLAGS_REGISTER_DTL: | |
630 | ret = register_dtl(tenv, vpa); | |
631 | break; | |
632 | ||
633 | case FLAGS_DEREGISTER_DTL: | |
634 | ret = deregister_dtl(tenv, vpa); | |
635 | break; | |
636 | } | |
637 | ||
638 | return ret; | |
639 | } | |
640 | ||
28e02042 | 641 | static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ed120055 DG |
642 | target_ulong opcode, target_ulong *args) |
643 | { | |
b13ce26d | 644 | CPUPPCState *env = &cpu->env; |
fcd7d003 | 645 | CPUState *cs = CPU(cpu); |
b13ce26d | 646 | |
ed120055 DG |
647 | env->msr |= (1ULL << MSR_EE); |
648 | hreg_compute_hflags(env); | |
fcd7d003 | 649 | if (!cpu_has_work(cs)) { |
259186a7 | 650 | cs->halted = 1; |
27103424 | 651 | cs->exception_index = EXCP_HLT; |
fcd7d003 | 652 | cs->exit_request = 1; |
ed120055 DG |
653 | } |
654 | return H_SUCCESS; | |
655 | } | |
656 | ||
28e02042 | 657 | static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
39ac8455 DG |
658 | target_ulong opcode, target_ulong *args) |
659 | { | |
660 | target_ulong rtas_r3 = args[0]; | |
4fe822e0 AK |
661 | uint32_t token = rtas_ld(rtas_r3, 0); |
662 | uint32_t nargs = rtas_ld(rtas_r3, 1); | |
663 | uint32_t nret = rtas_ld(rtas_r3, 2); | |
39ac8455 | 664 | |
210b580b | 665 | return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, |
39ac8455 DG |
666 | nret, rtas_r3 + 12 + 4*nargs); |
667 | } | |
668 | ||
28e02042 | 669 | static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
670 | target_ulong opcode, target_ulong *args) |
671 | { | |
fdfba1a2 | 672 | CPUState *cs = CPU(cpu); |
827200a2 DG |
673 | target_ulong size = args[0]; |
674 | target_ulong addr = args[1]; | |
675 | ||
676 | switch (size) { | |
677 | case 1: | |
2c17449b | 678 | args[0] = ldub_phys(cs->as, addr); |
827200a2 DG |
679 | return H_SUCCESS; |
680 | case 2: | |
41701aa4 | 681 | args[0] = lduw_phys(cs->as, addr); |
827200a2 DG |
682 | return H_SUCCESS; |
683 | case 4: | |
fdfba1a2 | 684 | args[0] = ldl_phys(cs->as, addr); |
827200a2 DG |
685 | return H_SUCCESS; |
686 | case 8: | |
2c17449b | 687 | args[0] = ldq_phys(cs->as, addr); |
827200a2 DG |
688 | return H_SUCCESS; |
689 | } | |
690 | return H_PARAMETER; | |
691 | } | |
692 | ||
28e02042 | 693 | static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
694 | target_ulong opcode, target_ulong *args) |
695 | { | |
f606604f EI |
696 | CPUState *cs = CPU(cpu); |
697 | ||
827200a2 DG |
698 | target_ulong size = args[0]; |
699 | target_ulong addr = args[1]; | |
700 | target_ulong val = args[2]; | |
701 | ||
702 | switch (size) { | |
703 | case 1: | |
db3be60d | 704 | stb_phys(cs->as, addr, val); |
827200a2 DG |
705 | return H_SUCCESS; |
706 | case 2: | |
5ce5944d | 707 | stw_phys(cs->as, addr, val); |
827200a2 DG |
708 | return H_SUCCESS; |
709 | case 4: | |
ab1da857 | 710 | stl_phys(cs->as, addr, val); |
827200a2 DG |
711 | return H_SUCCESS; |
712 | case 8: | |
f606604f | 713 | stq_phys(cs->as, addr, val); |
827200a2 DG |
714 | return H_SUCCESS; |
715 | } | |
716 | return H_PARAMETER; | |
717 | } | |
718 | ||
28e02042 | 719 | static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c73e3771 BH |
720 | target_ulong opcode, target_ulong *args) |
721 | { | |
fdfba1a2 EI |
722 | CPUState *cs = CPU(cpu); |
723 | ||
c73e3771 BH |
724 | target_ulong dst = args[0]; /* Destination address */ |
725 | target_ulong src = args[1]; /* Source address */ | |
726 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ | |
727 | target_ulong count = args[3]; /* Element count */ | |
728 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ | |
729 | uint64_t tmp; | |
730 | unsigned int mask = (1 << esize) - 1; | |
731 | int step = 1 << esize; | |
732 | ||
733 | if (count > 0x80000000) { | |
734 | return H_PARAMETER; | |
735 | } | |
736 | ||
737 | if ((dst & mask) || (src & mask) || (op > 1)) { | |
738 | return H_PARAMETER; | |
739 | } | |
740 | ||
741 | if (dst >= src && dst < (src + (count << esize))) { | |
742 | dst = dst + ((count - 1) << esize); | |
743 | src = src + ((count - 1) << esize); | |
744 | step = -step; | |
745 | } | |
746 | ||
747 | while (count--) { | |
748 | switch (esize) { | |
749 | case 0: | |
2c17449b | 750 | tmp = ldub_phys(cs->as, src); |
c73e3771 BH |
751 | break; |
752 | case 1: | |
41701aa4 | 753 | tmp = lduw_phys(cs->as, src); |
c73e3771 BH |
754 | break; |
755 | case 2: | |
fdfba1a2 | 756 | tmp = ldl_phys(cs->as, src); |
c73e3771 BH |
757 | break; |
758 | case 3: | |
2c17449b | 759 | tmp = ldq_phys(cs->as, src); |
c73e3771 BH |
760 | break; |
761 | default: | |
762 | return H_PARAMETER; | |
763 | } | |
764 | if (op == 1) { | |
765 | tmp = ~tmp; | |
766 | } | |
767 | switch (esize) { | |
768 | case 0: | |
db3be60d | 769 | stb_phys(cs->as, dst, tmp); |
c73e3771 BH |
770 | break; |
771 | case 1: | |
5ce5944d | 772 | stw_phys(cs->as, dst, tmp); |
c73e3771 BH |
773 | break; |
774 | case 2: | |
ab1da857 | 775 | stl_phys(cs->as, dst, tmp); |
c73e3771 BH |
776 | break; |
777 | case 3: | |
f606604f | 778 | stq_phys(cs->as, dst, tmp); |
c73e3771 BH |
779 | break; |
780 | } | |
781 | dst = dst + step; | |
782 | src = src + step; | |
783 | } | |
784 | ||
785 | return H_SUCCESS; | |
786 | } | |
787 | ||
28e02042 | 788 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
789 | target_ulong opcode, target_ulong *args) |
790 | { | |
791 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
792 | return H_SUCCESS; | |
793 | } | |
794 | ||
28e02042 | 795 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
827200a2 DG |
796 | target_ulong opcode, target_ulong *args) |
797 | { | |
798 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
799 | return H_SUCCESS; | |
800 | } | |
801 | ||
7d0cd464 PM |
802 | static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, |
803 | target_ulong mflags, | |
804 | target_ulong value1, | |
805 | target_ulong value2) | |
42561bf2 AB |
806 | { |
807 | CPUState *cs; | |
42561bf2 | 808 | |
c4015bbd AK |
809 | if (value1) { |
810 | return H_P3; | |
811 | } | |
812 | if (value2) { | |
813 | return H_P4; | |
814 | } | |
815 | ||
816 | switch (mflags) { | |
817 | case H_SET_MODE_ENDIAN_BIG: | |
818 | CPU_FOREACH(cs) { | |
819 | set_spr(cs, SPR_LPCR, 0, LPCR_ILE); | |
42561bf2 | 820 | } |
eefaccc0 | 821 | spapr_pci_switch_vga(true); |
c4015bbd AK |
822 | return H_SUCCESS; |
823 | ||
824 | case H_SET_MODE_ENDIAN_LITTLE: | |
825 | CPU_FOREACH(cs) { | |
826 | set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); | |
42561bf2 | 827 | } |
eefaccc0 | 828 | spapr_pci_switch_vga(false); |
c4015bbd AK |
829 | return H_SUCCESS; |
830 | } | |
42561bf2 | 831 | |
c4015bbd AK |
832 | return H_UNSUPPORTED_FLAG; |
833 | } | |
42561bf2 | 834 | |
7d0cd464 PM |
835 | static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, |
836 | target_ulong mflags, | |
837 | target_ulong value1, | |
838 | target_ulong value2) | |
d5ac4f54 AK |
839 | { |
840 | CPUState *cs; | |
841 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
d5ac4f54 AK |
842 | |
843 | if (!(pcc->insns_flags2 & PPC2_ISA207S)) { | |
844 | return H_P2; | |
845 | } | |
846 | if (value1) { | |
847 | return H_P3; | |
848 | } | |
849 | if (value2) { | |
850 | return H_P4; | |
851 | } | |
852 | ||
5c94b2a5 | 853 | if (mflags == AIL_RESERVED) { |
d5ac4f54 AK |
854 | return H_UNSUPPORTED_FLAG; |
855 | } | |
856 | ||
857 | CPU_FOREACH(cs) { | |
d5ac4f54 | 858 | set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); |
d5ac4f54 AK |
859 | } |
860 | ||
861 | return H_SUCCESS; | |
862 | } | |
863 | ||
28e02042 | 864 | static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c4015bbd AK |
865 | target_ulong opcode, target_ulong *args) |
866 | { | |
867 | target_ulong resource = args[1]; | |
868 | target_ulong ret = H_P2; | |
869 | ||
870 | switch (resource) { | |
871 | case H_SET_MODE_RESOURCE_LE: | |
7d0cd464 | 872 | ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); |
c4015bbd | 873 | break; |
d5ac4f54 | 874 | case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: |
7d0cd464 PM |
875 | ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], |
876 | args[2], args[3]); | |
d5ac4f54 | 877 | break; |
42561bf2 AB |
878 | } |
879 | ||
42561bf2 AB |
880 | return ret; |
881 | } | |
882 | ||
03d196b7 BR |
883 | /* |
884 | * Return the offset to the requested option vector @vector in the | |
885 | * option vector table @table. | |
886 | */ | |
887 | static target_ulong cas_get_option_vector(int vector, target_ulong table) | |
888 | { | |
889 | int i; | |
890 | char nr_vectors, nr_entries; | |
891 | ||
892 | if (!table) { | |
893 | return 0; | |
894 | } | |
895 | ||
896 | nr_vectors = (ldl_phys(&address_space_memory, table) >> 24) + 1; | |
897 | if (!vector || vector > nr_vectors) { | |
898 | return 0; | |
899 | } | |
900 | table++; /* skip nr option vectors */ | |
901 | ||
902 | for (i = 0; i < vector - 1; i++) { | |
903 | nr_entries = ldl_phys(&address_space_memory, table) >> 24; | |
904 | table += nr_entries + 2; | |
905 | } | |
906 | return table; | |
907 | } | |
908 | ||
3794d548 | 909 | typedef struct { |
3794d548 | 910 | uint32_t cpu_version; |
f9ab1e87 | 911 | Error *err; |
3794d548 AK |
912 | } SetCompatState; |
913 | ||
e0eeb4a2 | 914 | static void do_set_compat(CPUState *cs, void *arg) |
3794d548 | 915 | { |
e0eeb4a2 | 916 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
3794d548 AK |
917 | SetCompatState *s = arg; |
918 | ||
e0eeb4a2 AB |
919 | cpu_synchronize_state(cs); |
920 | ppc_set_compat(cpu, s->cpu_version, &s->err); | |
3794d548 AK |
921 | } |
922 | ||
923 | #define get_compat_level(cpuver) ( \ | |
924 | ((cpuver) == CPU_POWERPC_LOGICAL_2_05) ? 2050 : \ | |
925 | ((cpuver) == CPU_POWERPC_LOGICAL_2_06) ? 2060 : \ | |
926 | ((cpuver) == CPU_POWERPC_LOGICAL_2_06_PLUS) ? 2061 : \ | |
927 | ((cpuver) == CPU_POWERPC_LOGICAL_2_07) ? 2070 : 0) | |
928 | ||
7386ae63 TH |
929 | static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr, |
930 | unsigned max_lvl, unsigned *compat_lvl, | |
931 | unsigned *cpu_version) | |
932 | { | |
933 | unsigned lvl = get_compat_level(pvr); | |
b30ff227 | 934 | bool is205, is206, is207; |
7386ae63 TH |
935 | |
936 | if (!lvl) { | |
937 | return; | |
938 | } | |
939 | ||
940 | /* If it is a logical PVR, try to determine the highest level */ | |
8cd2ce7a | 941 | is205 = (pcc->pcr_supported & PCR_COMPAT_2_05) && |
7386ae63 | 942 | (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05)); |
8cd2ce7a | 943 | is206 = (pcc->pcr_supported & PCR_COMPAT_2_06) && |
7386ae63 TH |
944 | ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) || |
945 | (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS))); | |
b30ff227 TH |
946 | is207 = (pcc->pcr_supported & PCR_COMPAT_2_07) && |
947 | (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_07)); | |
7386ae63 | 948 | |
b30ff227 | 949 | if (is205 || is206 || is207) { |
7386ae63 TH |
950 | if (!max_lvl) { |
951 | /* User did not set the level, choose the highest */ | |
952 | if (*compat_lvl <= lvl) { | |
953 | *compat_lvl = lvl; | |
954 | *cpu_version = pvr; | |
955 | } | |
956 | } else if (max_lvl >= lvl) { | |
957 | /* User chose the level, don't set higher than this */ | |
958 | *compat_lvl = lvl; | |
959 | *cpu_version = pvr; | |
960 | } | |
961 | } | |
962 | } | |
963 | ||
03d196b7 BR |
964 | #define OV5_DRCONF_MEMORY 0x20 |
965 | ||
2a6593cb | 966 | static target_ulong h_client_architecture_support(PowerPCCPU *cpu_, |
28e02042 | 967 | sPAPRMachineState *spapr, |
2a6593cb AK |
968 | target_ulong opcode, |
969 | target_ulong *args) | |
970 | { | |
27ac3e06 DG |
971 | target_ulong list = ppc64_phys_to_real(args[0]); |
972 | target_ulong ov_table, ov5; | |
7386ae63 | 973 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu_); |
3794d548 | 974 | CPUState *cs; |
03d196b7 | 975 | bool cpu_match = false, cpu_update = true, memory_update = false; |
3794d548 AK |
976 | unsigned old_cpu_version = cpu_->cpu_version; |
977 | unsigned compat_lvl = 0, cpu_version = 0; | |
978 | unsigned max_lvl = get_compat_level(cpu_->max_compat); | |
979 | int counter; | |
03d196b7 | 980 | char ov5_byte2; |
3794d548 AK |
981 | |
982 | /* Parse PVR list */ | |
983 | for (counter = 0; counter < 512; ++counter) { | |
984 | uint32_t pvr, pvr_mask; | |
985 | ||
27ac3e06 | 986 | pvr_mask = ldl_be_phys(&address_space_memory, list); |
3794d548 | 987 | list += 4; |
27ac3e06 | 988 | pvr = ldl_be_phys(&address_space_memory, list); |
3794d548 AK |
989 | list += 4; |
990 | ||
991 | trace_spapr_cas_pvr_try(pvr); | |
992 | if (!max_lvl && | |
993 | ((cpu_->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask))) { | |
994 | cpu_match = true; | |
995 | cpu_version = 0; | |
996 | } else if (pvr == cpu_->cpu_version) { | |
997 | cpu_match = true; | |
998 | cpu_version = cpu_->cpu_version; | |
999 | } else if (!cpu_match) { | |
7386ae63 | 1000 | cas_handle_compat_cpu(pcc, pvr, max_lvl, &compat_lvl, &cpu_version); |
3794d548 AK |
1001 | } |
1002 | /* Terminator record */ | |
1003 | if (~pvr_mask & pvr) { | |
1004 | break; | |
1005 | } | |
1006 | } | |
1007 | ||
3794d548 AK |
1008 | /* Parsing finished */ |
1009 | trace_spapr_cas_pvr(cpu_->cpu_version, cpu_match, | |
7386ae63 | 1010 | cpu_version, pcc->pcr_mask); |
3794d548 AK |
1011 | |
1012 | /* Update CPUs */ | |
1013 | if (old_cpu_version != cpu_version) { | |
1014 | CPU_FOREACH(cs) { | |
1015 | SetCompatState s = { | |
3794d548 | 1016 | .cpu_version = cpu_version, |
f9ab1e87 | 1017 | .err = NULL, |
3794d548 AK |
1018 | }; |
1019 | ||
1020 | run_on_cpu(cs, do_set_compat, &s); | |
1021 | ||
f9ab1e87 DG |
1022 | if (s.err) { |
1023 | error_report_err(s.err); | |
3794d548 AK |
1024 | return H_HARDWARE; |
1025 | } | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | if (!cpu_version) { | |
03d196b7 | 1030 | cpu_update = false; |
3794d548 | 1031 | } |
2a6593cb | 1032 | |
03d196b7 BR |
1033 | /* For the future use: here @ov_table points to the first option vector */ |
1034 | ov_table = list; | |
1035 | ||
27ac3e06 DG |
1036 | ov5 = cas_get_option_vector(5, ov_table); |
1037 | if (!ov5) { | |
2a6593cb AK |
1038 | return H_SUCCESS; |
1039 | } | |
1040 | ||
03d196b7 | 1041 | /* @list now points to OV 5 */ |
27ac3e06 | 1042 | ov5_byte2 = ldub_phys(&address_space_memory, ov5 + 2); |
03d196b7 BR |
1043 | if (ov5_byte2 & OV5_DRCONF_MEMORY) { |
1044 | memory_update = true; | |
1045 | } | |
1046 | ||
1047 | if (spapr_h_cas_compose_response(spapr, args[1], args[2], | |
1048 | cpu_update, memory_update)) { | |
2a6593cb AK |
1049 | qemu_system_reset_request(); |
1050 | } | |
1051 | ||
1052 | return H_SUCCESS; | |
1053 | } | |
1054 | ||
7d7ba3fe DG |
1055 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
1056 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; | |
9fdf0c29 DG |
1057 | |
1058 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
1059 | { | |
39ac8455 DG |
1060 | spapr_hcall_fn *slot; |
1061 | ||
1062 | if (opcode <= MAX_HCALL_OPCODE) { | |
1063 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 1064 | |
39ac8455 DG |
1065 | slot = &papr_hypercall_table[opcode / 4]; |
1066 | } else { | |
1067 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 1068 | |
39ac8455 DG |
1069 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
1070 | } | |
9fdf0c29 | 1071 | |
c89d5299 | 1072 | assert(!(*slot)); |
39ac8455 | 1073 | *slot = fn; |
9fdf0c29 DG |
1074 | } |
1075 | ||
aa100fa4 | 1076 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
1077 | target_ulong *args) |
1078 | { | |
28e02042 DG |
1079 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); |
1080 | ||
9fdf0c29 DG |
1081 | if ((opcode <= MAX_HCALL_OPCODE) |
1082 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
1083 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
1084 | ||
1085 | if (fn) { | |
b13ce26d | 1086 | return fn(cpu, spapr, opcode, args); |
39ac8455 DG |
1087 | } |
1088 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
1089 | (opcode <= KVMPPC_HCALL_MAX)) { | |
1090 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
1091 | |
1092 | if (fn) { | |
b13ce26d | 1093 | return fn(cpu, spapr, opcode, args); |
9fdf0c29 DG |
1094 | } |
1095 | } | |
1096 | ||
aaf87c66 TH |
1097 | qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", |
1098 | opcode); | |
9fdf0c29 DG |
1099 | return H_FUNCTION; |
1100 | } | |
f43e3525 | 1101 | |
83f7d43a | 1102 | static void hypercall_register_types(void) |
f43e3525 DG |
1103 | { |
1104 | /* hcall-pft */ | |
1105 | spapr_register_hypercall(H_ENTER, h_enter); | |
1106 | spapr_register_hypercall(H_REMOVE, h_remove); | |
1107 | spapr_register_hypercall(H_PROTECT, h_protect); | |
6bbd5dde | 1108 | spapr_register_hypercall(H_READ, h_read); |
39ac8455 | 1109 | |
a3d0abae DG |
1110 | /* hcall-bulk */ |
1111 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); | |
1112 | ||
ed120055 DG |
1113 | /* hcall-splpar */ |
1114 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
1115 | spapr_register_hypercall(H_CEDE, h_cede); | |
1116 | ||
423576f7 TH |
1117 | /* processor register resource access h-calls */ |
1118 | spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); | |
af08a58f | 1119 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
e49ff266 | 1120 | spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); |
3240dd9a | 1121 | spapr_register_hypercall(H_PAGE_INIT, h_page_init); |
423576f7 TH |
1122 | spapr_register_hypercall(H_SET_MODE, h_set_mode); |
1123 | ||
827200a2 DG |
1124 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
1125 | * here between the "CI" and the "CACHE" variants, they will use whatever | |
1126 | * mapping attributes qemu is using. When using KVM, the kernel will | |
1127 | * enforce the attributes more strongly | |
1128 | */ | |
1129 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); | |
1130 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); | |
1131 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); | |
1132 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); | |
1133 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); | |
1134 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); | |
c73e3771 | 1135 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
827200a2 | 1136 | |
39ac8455 DG |
1137 | /* qemu/KVM-PPC specific hcalls */ |
1138 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
42561bf2 | 1139 | |
2a6593cb AK |
1140 | /* ibm,client-architecture-support support */ |
1141 | spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); | |
f43e3525 | 1142 | } |
83f7d43a AF |
1143 | |
1144 | type_init(hypercall_register_types) |