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Commit | Line | Data |
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39ac8455 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Hypercall based emulated RTAS | |
5 | * | |
6 | * Copyright (c) 2010-2011 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
39ac8455 | 28 | #include "cpu.h" |
03dd024f | 29 | #include "qemu/log.h" |
ce9863b7 | 30 | #include "qemu/error-report.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
dccfcd0e | 32 | #include "sysemu/char.h" |
39ac8455 | 33 | #include "hw/qdev.h" |
9c17d615 | 34 | #include "sysemu/device_tree.h" |
db4ef288 | 35 | #include "sysemu/cpus.h" |
77ac58dd | 36 | #include "sysemu/kvm.h" |
39ac8455 | 37 | |
0d09e41a PB |
38 | #include "hw/ppc/spapr.h" |
39 | #include "hw/ppc/spapr_vio.h" | |
eeddd59f | 40 | #include "hw/ppc/spapr_rtas.h" |
af81cf32 | 41 | #include "hw/ppc/ppc.h" |
e010ad8f | 42 | #include "qapi-event.h" |
e3943228 | 43 | #include "hw/boards.h" |
39ac8455 DG |
44 | |
45 | #include <libfdt.h> | |
8c8639df | 46 | #include "hw/ppc/spapr_drc.h" |
f348b6d1 | 47 | #include "qemu/cutils.h" |
8c8639df MD |
48 | |
49 | /* #define DEBUG_SPAPR */ | |
50 | ||
51 | #ifdef DEBUG_SPAPR | |
52 | #define DPRINTF(fmt, ...) \ | |
53 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
54 | #else | |
55 | #define DPRINTF(fmt, ...) \ | |
56 | do { } while (0) | |
57 | #endif | |
58 | ||
28e02042 | 59 | static sPAPRConfigureConnectorState *spapr_ccs_find(sPAPRMachineState *spapr, |
46503c2b MR |
60 | uint32_t drc_index) |
61 | { | |
62 | sPAPRConfigureConnectorState *ccs = NULL; | |
63 | ||
64 | QTAILQ_FOREACH(ccs, &spapr->ccs_list, next) { | |
65 | if (ccs->drc_index == drc_index) { | |
66 | break; | |
67 | } | |
68 | } | |
69 | ||
70 | return ccs; | |
71 | } | |
72 | ||
28e02042 | 73 | static void spapr_ccs_add(sPAPRMachineState *spapr, |
46503c2b MR |
74 | sPAPRConfigureConnectorState *ccs) |
75 | { | |
76 | g_assert(!spapr_ccs_find(spapr, ccs->drc_index)); | |
77 | QTAILQ_INSERT_HEAD(&spapr->ccs_list, ccs, next); | |
78 | } | |
79 | ||
28e02042 | 80 | static void spapr_ccs_remove(sPAPRMachineState *spapr, |
46503c2b MR |
81 | sPAPRConfigureConnectorState *ccs) |
82 | { | |
83 | QTAILQ_REMOVE(&spapr->ccs_list, ccs, next); | |
84 | g_free(ccs); | |
85 | } | |
86 | ||
87 | void spapr_ccs_reset_hook(void *opaque) | |
88 | { | |
28e02042 | 89 | sPAPRMachineState *spapr = opaque; |
46503c2b MR |
90 | sPAPRConfigureConnectorState *ccs, *ccs_tmp; |
91 | ||
92 | QTAILQ_FOREACH_SAFE(ccs, &spapr->ccs_list, next, ccs_tmp) { | |
93 | spapr_ccs_remove(spapr, ccs); | |
94 | } | |
95 | } | |
39ac8455 | 96 | |
28e02042 | 97 | static void rtas_display_character(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
98 | uint32_t token, uint32_t nargs, |
99 | target_ulong args, | |
100 | uint32_t nret, target_ulong rets) | |
101 | { | |
102 | uint8_t c = rtas_ld(args, 0); | |
5f2e2ba2 | 103 | VIOsPAPRDevice *sdev = vty_lookup(spapr, 0); |
821303f5 DG |
104 | |
105 | if (!sdev) { | |
a64d325d | 106 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
821303f5 DG |
107 | } else { |
108 | vty_putchars(sdev, &c, sizeof(c)); | |
a64d325d | 109 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
821303f5 DG |
110 | } |
111 | } | |
112 | ||
28e02042 | 113 | static void rtas_power_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
821303f5 DG |
114 | uint32_t token, uint32_t nargs, target_ulong args, |
115 | uint32_t nret, target_ulong rets) | |
116 | { | |
117 | if (nargs != 2 || nret != 1) { | |
a64d325d | 118 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
821303f5 DG |
119 | return; |
120 | } | |
121 | qemu_system_shutdown_request(); | |
8a9c1b77 | 122 | cpu_stop_current(); |
a64d325d | 123 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
821303f5 DG |
124 | } |
125 | ||
28e02042 | 126 | static void rtas_system_reboot(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
c821a43c DG |
127 | uint32_t token, uint32_t nargs, |
128 | target_ulong args, | |
129 | uint32_t nret, target_ulong rets) | |
130 | { | |
131 | if (nargs != 0 || nret != 1) { | |
a64d325d | 132 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
c821a43c DG |
133 | return; |
134 | } | |
135 | qemu_system_reset_request(); | |
a64d325d | 136 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
c821a43c DG |
137 | } |
138 | ||
210b580b | 139 | static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_, |
28e02042 | 140 | sPAPRMachineState *spapr, |
a9f8ad8f DG |
141 | uint32_t token, uint32_t nargs, |
142 | target_ulong args, | |
143 | uint32_t nret, target_ulong rets) | |
144 | { | |
145 | target_ulong id; | |
0f20ba62 | 146 | PowerPCCPU *cpu; |
a9f8ad8f DG |
147 | |
148 | if (nargs != 1 || nret != 2) { | |
a64d325d | 149 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
150 | return; |
151 | } | |
152 | ||
153 | id = rtas_ld(args, 0); | |
0f20ba62 | 154 | cpu = ppc_get_vcpu_by_dt_id(id); |
05318a85 | 155 | if (cpu != NULL) { |
0f20ba62 | 156 | if (CPU(cpu)->halted) { |
a9f8ad8f DG |
157 | rtas_st(rets, 1, 0); |
158 | } else { | |
159 | rtas_st(rets, 1, 2); | |
160 | } | |
161 | ||
a64d325d | 162 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
a9f8ad8f DG |
163 | return; |
164 | } | |
165 | ||
166 | /* Didn't find a matching cpu */ | |
a64d325d | 167 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
168 | } |
169 | ||
af81cf32 BR |
170 | /* |
171 | * Set the timebase offset of the CPU to that of first CPU. | |
172 | * This helps hotplugged CPU to have the correct timebase offset. | |
173 | */ | |
174 | static void spapr_cpu_update_tb_offset(PowerPCCPU *cpu) | |
175 | { | |
176 | PowerPCCPU *fcpu = POWERPC_CPU(first_cpu); | |
177 | ||
178 | cpu->env.tb_env->tb_offset = fcpu->env.tb_env->tb_offset; | |
179 | } | |
180 | ||
181 | static void spapr_cpu_set_endianness(PowerPCCPU *cpu) | |
182 | { | |
183 | PowerPCCPU *fcpu = POWERPC_CPU(first_cpu); | |
184 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(fcpu); | |
185 | ||
186 | if (!pcc->interrupts_big_endian(fcpu)) { | |
187 | cpu->env.spr[SPR_LPCR] |= LPCR_ILE; | |
188 | } | |
189 | } | |
190 | ||
28e02042 | 191 | static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr, |
a9f8ad8f DG |
192 | uint32_t token, uint32_t nargs, |
193 | target_ulong args, | |
194 | uint32_t nret, target_ulong rets) | |
195 | { | |
196 | target_ulong id, start, r3; | |
0f20ba62 | 197 | PowerPCCPU *cpu; |
a9f8ad8f DG |
198 | |
199 | if (nargs != 3 || nret != 1) { | |
a64d325d | 200 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
201 | return; |
202 | } | |
203 | ||
204 | id = rtas_ld(args, 0); | |
205 | start = rtas_ld(args, 1); | |
206 | r3 = rtas_ld(args, 2); | |
207 | ||
0f20ba62 AK |
208 | cpu = ppc_get_vcpu_by_dt_id(id); |
209 | if (cpu != NULL) { | |
210 | CPUState *cs = CPU(cpu); | |
c67e216b | 211 | CPUPPCState *env = &cpu->env; |
a9f8ad8f | 212 | |
c67e216b | 213 | if (!cs->halted) { |
a64d325d | 214 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
a9f8ad8f DG |
215 | return; |
216 | } | |
217 | ||
048706d9 DG |
218 | /* This will make sure qemu state is up to date with kvm, and |
219 | * mark it dirty so our changes get flushed back before the | |
220 | * new cpu enters */ | |
dd1750d7 | 221 | kvm_cpu_synchronize_state(cs); |
048706d9 | 222 | |
a9f8ad8f DG |
223 | env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); |
224 | env->nip = start; | |
225 | env->gpr[3] = r3; | |
c67e216b | 226 | cs->halted = 0; |
af81cf32 BR |
227 | spapr_cpu_set_endianness(cpu); |
228 | spapr_cpu_update_tb_offset(cpu); | |
a9f8ad8f | 229 | |
c67e216b | 230 | qemu_cpu_kick(cs); |
a9f8ad8f | 231 | |
a64d325d | 232 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
a9f8ad8f DG |
233 | return; |
234 | } | |
235 | ||
236 | /* Didn't find a matching cpu */ | |
a64d325d | 237 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
a9f8ad8f DG |
238 | } |
239 | ||
28e02042 | 240 | static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
59760f2d AK |
241 | uint32_t token, uint32_t nargs, |
242 | target_ulong args, | |
243 | uint32_t nret, target_ulong rets) | |
244 | { | |
245 | CPUState *cs = CPU(cpu); | |
246 | CPUPPCState *env = &cpu->env; | |
247 | ||
248 | cs->halted = 1; | |
9102deda | 249 | qemu_cpu_kick(cs); |
59760f2d AK |
250 | /* |
251 | * While stopping a CPU, the guest calls H_CPPR which | |
252 | * effectively disables interrupts on XICS level. | |
253 | * However decrementer interrupts in TCG can still | |
254 | * wake the CPU up so here we disable interrupts in MSR | |
255 | * as well. | |
256 | * As rtas_start_cpu() resets the whole MSR anyway, there is | |
257 | * no need to bother with specific bits, we just clear it. | |
258 | */ | |
259 | env->msr = 0; | |
260 | } | |
261 | ||
c920f7b4 DG |
262 | static inline int sysparm_st(target_ulong addr, target_ulong len, |
263 | const void *val, uint16_t vallen) | |
264 | { | |
265 | hwaddr phys = ppc64_phys_to_real(addr); | |
266 | ||
267 | if (len < 2) { | |
268 | return RTAS_OUT_SYSPARM_PARAM_ERROR; | |
269 | } | |
270 | stw_be_phys(&address_space_memory, phys, vallen); | |
271 | cpu_physical_memory_write(phys + 2, val, MIN(len - 2, vallen)); | |
272 | return RTAS_OUT_SUCCESS; | |
273 | } | |
274 | ||
3ada6b11 | 275 | static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu, |
28e02042 | 276 | sPAPRMachineState *spapr, |
3ada6b11 AK |
277 | uint32_t token, uint32_t nargs, |
278 | target_ulong args, | |
279 | uint32_t nret, target_ulong rets) | |
280 | { | |
281 | target_ulong parameter = rtas_ld(args, 0); | |
282 | target_ulong buffer = rtas_ld(args, 1); | |
283 | target_ulong length = rtas_ld(args, 2); | |
c920f7b4 | 284 | target_ulong ret; |
3ada6b11 AK |
285 | |
286 | switch (parameter) { | |
3b50d897 | 287 | case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: { |
e3943228 SB |
288 | char *param_val = g_strdup_printf("MaxEntCap=%d," |
289 | "DesMem=%llu," | |
290 | "DesProcs=%d," | |
291 | "MaxPlatProcs=%d", | |
292 | max_cpus, | |
293 | current_machine->ram_size / M_BYTE, | |
294 | smp_cpus, | |
295 | max_cpus); | |
c920f7b4 | 296 | ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1); |
3b50d897 S |
297 | g_free(param_val); |
298 | break; | |
299 | } | |
3052d951 S |
300 | case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: { |
301 | uint8_t param_val = DIAGNOSTICS_RUN_MODE_DISABLED; | |
302 | ||
c920f7b4 | 303 | ret = sysparm_st(buffer, length, ¶m_val, sizeof(param_val)); |
3ada6b11 AK |
304 | break; |
305 | } | |
b907d7b0 | 306 | case RTAS_SYSPARM_UUID: |
c920f7b4 | 307 | ret = sysparm_st(buffer, length, qemu_uuid, (qemu_uuid_set ? 16 : 0)); |
b907d7b0 | 308 | break; |
3052d951 S |
309 | default: |
310 | ret = RTAS_OUT_NOT_SUPPORTED; | |
311 | } | |
3ada6b11 AK |
312 | |
313 | rtas_st(rets, 0, ret); | |
314 | } | |
315 | ||
316 | static void rtas_ibm_set_system_parameter(PowerPCCPU *cpu, | |
28e02042 | 317 | sPAPRMachineState *spapr, |
3ada6b11 AK |
318 | uint32_t token, uint32_t nargs, |
319 | target_ulong args, | |
320 | uint32_t nret, target_ulong rets) | |
321 | { | |
322 | target_ulong parameter = rtas_ld(args, 0); | |
323 | target_ulong ret = RTAS_OUT_NOT_SUPPORTED; | |
324 | ||
325 | switch (parameter) { | |
3b50d897 | 326 | case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: |
3052d951 | 327 | case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: |
b907d7b0 | 328 | case RTAS_SYSPARM_UUID: |
3ada6b11 AK |
329 | ret = RTAS_OUT_NOT_AUTHORIZED; |
330 | break; | |
331 | } | |
332 | ||
333 | rtas_st(rets, 0, ret); | |
334 | } | |
335 | ||
2e14072f | 336 | static void rtas_ibm_os_term(PowerPCCPU *cpu, |
28e02042 | 337 | sPAPRMachineState *spapr, |
2e14072f ND |
338 | uint32_t token, uint32_t nargs, |
339 | target_ulong args, | |
340 | uint32_t nret, target_ulong rets) | |
341 | { | |
342 | target_ulong ret = 0; | |
343 | ||
344 | qapi_event_send_guest_panicked(GUEST_PANIC_ACTION_PAUSE, &error_abort); | |
345 | ||
346 | rtas_st(rets, 0, ret); | |
347 | } | |
348 | ||
28e02042 | 349 | static void rtas_set_power_level(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
094d2058 NF |
350 | uint32_t token, uint32_t nargs, |
351 | target_ulong args, uint32_t nret, | |
352 | target_ulong rets) | |
353 | { | |
354 | int32_t power_domain; | |
355 | ||
356 | if (nargs != 2 || nret != 2) { | |
357 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
358 | return; | |
359 | } | |
360 | ||
361 | /* we currently only use a single, "live insert" powerdomain for | |
362 | * hotplugged/dlpar'd resources, so the power is always live/full (100) | |
363 | */ | |
364 | power_domain = rtas_ld(args, 0); | |
365 | if (power_domain != -1) { | |
366 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
367 | return; | |
368 | } | |
369 | ||
370 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
371 | rtas_st(rets, 1, 100); | |
372 | } | |
373 | ||
28e02042 | 374 | static void rtas_get_power_level(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
094d2058 NF |
375 | uint32_t token, uint32_t nargs, |
376 | target_ulong args, uint32_t nret, | |
377 | target_ulong rets) | |
378 | { | |
379 | int32_t power_domain; | |
380 | ||
381 | if (nargs != 1 || nret != 2) { | |
382 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
383 | return; | |
384 | } | |
385 | ||
386 | /* we currently only use a single, "live insert" powerdomain for | |
387 | * hotplugged/dlpar'd resources, so the power is always live/full (100) | |
388 | */ | |
389 | power_domain = rtas_ld(args, 0); | |
390 | if (power_domain != -1) { | |
391 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
392 | return; | |
393 | } | |
394 | ||
395 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
396 | rtas_st(rets, 1, 100); | |
397 | } | |
398 | ||
8c8639df MD |
399 | static bool sensor_type_is_dr(uint32_t sensor_type) |
400 | { | |
401 | switch (sensor_type) { | |
402 | case RTAS_SENSOR_TYPE_ISOLATION_STATE: | |
403 | case RTAS_SENSOR_TYPE_DR: | |
404 | case RTAS_SENSOR_TYPE_ALLOCATION_STATE: | |
405 | return true; | |
406 | } | |
407 | ||
408 | return false; | |
409 | } | |
410 | ||
28e02042 | 411 | static void rtas_set_indicator(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
8c8639df MD |
412 | uint32_t token, uint32_t nargs, |
413 | target_ulong args, uint32_t nret, | |
414 | target_ulong rets) | |
415 | { | |
416 | uint32_t sensor_type; | |
417 | uint32_t sensor_index; | |
418 | uint32_t sensor_state; | |
0cb688d2 | 419 | uint32_t ret = RTAS_OUT_SUCCESS; |
8c8639df MD |
420 | sPAPRDRConnector *drc; |
421 | sPAPRDRConnectorClass *drck; | |
422 | ||
423 | if (nargs != 3 || nret != 1) { | |
0cb688d2 MR |
424 | ret = RTAS_OUT_PARAM_ERROR; |
425 | goto out; | |
8c8639df MD |
426 | } |
427 | ||
428 | sensor_type = rtas_ld(args, 0); | |
429 | sensor_index = rtas_ld(args, 1); | |
430 | sensor_state = rtas_ld(args, 2); | |
431 | ||
432 | if (!sensor_type_is_dr(sensor_type)) { | |
433 | goto out_unimplemented; | |
434 | } | |
435 | ||
436 | /* if this is a DR sensor we can assume sensor_index == drc_index */ | |
437 | drc = spapr_dr_connector_by_index(sensor_index); | |
438 | if (!drc) { | |
439 | DPRINTF("rtas_set_indicator: invalid sensor/DRC index: %xh\n", | |
440 | sensor_index); | |
0cb688d2 MR |
441 | ret = RTAS_OUT_PARAM_ERROR; |
442 | goto out; | |
8c8639df MD |
443 | } |
444 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
445 | ||
446 | switch (sensor_type) { | |
447 | case RTAS_SENSOR_TYPE_ISOLATION_STATE: | |
46503c2b MR |
448 | /* if the guest is configuring a device attached to this |
449 | * DRC, we should reset the configuration state at this | |
450 | * point since it may no longer be reliable (guest released | |
451 | * device and needs to start over, or unplug occurred so | |
452 | * the FDT is no longer valid) | |
453 | */ | |
454 | if (sensor_state == SPAPR_DR_ISOLATION_STATE_ISOLATED) { | |
455 | sPAPRConfigureConnectorState *ccs = spapr_ccs_find(spapr, | |
456 | sensor_index); | |
457 | if (ccs) { | |
458 | spapr_ccs_remove(spapr, ccs); | |
459 | } | |
460 | } | |
0cb688d2 | 461 | ret = drck->set_isolation_state(drc, sensor_state); |
8c8639df MD |
462 | break; |
463 | case RTAS_SENSOR_TYPE_DR: | |
0cb688d2 | 464 | ret = drck->set_indicator_state(drc, sensor_state); |
8c8639df MD |
465 | break; |
466 | case RTAS_SENSOR_TYPE_ALLOCATION_STATE: | |
0cb688d2 | 467 | ret = drck->set_allocation_state(drc, sensor_state); |
8c8639df MD |
468 | break; |
469 | default: | |
470 | goto out_unimplemented; | |
471 | } | |
472 | ||
0cb688d2 MR |
473 | out: |
474 | rtas_st(rets, 0, ret); | |
8c8639df MD |
475 | return; |
476 | ||
477 | out_unimplemented: | |
478 | /* currently only DR-related sensors are implemented */ | |
479 | DPRINTF("rtas_set_indicator: sensor/indicator not implemented: %d\n", | |
480 | sensor_type); | |
481 | rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); | |
482 | } | |
483 | ||
28e02042 | 484 | static void rtas_get_sensor_state(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
886445a6 MD |
485 | uint32_t token, uint32_t nargs, |
486 | target_ulong args, uint32_t nret, | |
487 | target_ulong rets) | |
488 | { | |
489 | uint32_t sensor_type; | |
490 | uint32_t sensor_index; | |
0cb688d2 | 491 | uint32_t sensor_state = 0; |
886445a6 MD |
492 | sPAPRDRConnector *drc; |
493 | sPAPRDRConnectorClass *drck; | |
0cb688d2 | 494 | uint32_t ret = RTAS_OUT_SUCCESS; |
886445a6 MD |
495 | |
496 | if (nargs != 2 || nret != 2) { | |
0cb688d2 MR |
497 | ret = RTAS_OUT_PARAM_ERROR; |
498 | goto out; | |
886445a6 MD |
499 | } |
500 | ||
501 | sensor_type = rtas_ld(args, 0); | |
502 | sensor_index = rtas_ld(args, 1); | |
503 | ||
504 | if (sensor_type != RTAS_SENSOR_TYPE_ENTITY_SENSE) { | |
505 | /* currently only DR-related sensors are implemented */ | |
506 | DPRINTF("rtas_get_sensor_state: sensor/indicator not implemented: %d\n", | |
507 | sensor_type); | |
0cb688d2 MR |
508 | ret = RTAS_OUT_NOT_SUPPORTED; |
509 | goto out; | |
886445a6 MD |
510 | } |
511 | ||
512 | drc = spapr_dr_connector_by_index(sensor_index); | |
513 | if (!drc) { | |
514 | DPRINTF("rtas_get_sensor_state: invalid sensor/DRC index: %xh\n", | |
515 | sensor_index); | |
0cb688d2 MR |
516 | ret = RTAS_OUT_PARAM_ERROR; |
517 | goto out; | |
886445a6 MD |
518 | } |
519 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
0cb688d2 | 520 | ret = drck->entity_sense(drc, &sensor_state); |
886445a6 | 521 | |
0cb688d2 MR |
522 | out: |
523 | rtas_st(rets, 0, ret); | |
524 | rtas_st(rets, 1, sensor_state); | |
886445a6 MD |
525 | } |
526 | ||
46503c2b MR |
527 | /* configure-connector work area offsets, int32_t units for field |
528 | * indexes, bytes for field offset/len values. | |
529 | * | |
530 | * as documented by PAPR+ v2.7, 13.5.3.5 | |
531 | */ | |
532 | #define CC_IDX_NODE_NAME_OFFSET 2 | |
533 | #define CC_IDX_PROP_NAME_OFFSET 2 | |
534 | #define CC_IDX_PROP_LEN 3 | |
535 | #define CC_IDX_PROP_DATA_OFFSET 4 | |
536 | #define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4) | |
537 | #define CC_WA_LEN 4096 | |
538 | ||
f201987b DG |
539 | static void configure_connector_st(target_ulong addr, target_ulong offset, |
540 | const void *buf, size_t len) | |
541 | { | |
542 | cpu_physical_memory_write(ppc64_phys_to_real(addr + offset), | |
543 | buf, MIN(len, CC_WA_LEN - offset)); | |
544 | } | |
545 | ||
46503c2b | 546 | static void rtas_ibm_configure_connector(PowerPCCPU *cpu, |
28e02042 | 547 | sPAPRMachineState *spapr, |
46503c2b MR |
548 | uint32_t token, uint32_t nargs, |
549 | target_ulong args, uint32_t nret, | |
550 | target_ulong rets) | |
551 | { | |
552 | uint64_t wa_addr; | |
553 | uint64_t wa_offset; | |
554 | uint32_t drc_index; | |
555 | sPAPRDRConnector *drc; | |
556 | sPAPRDRConnectorClass *drck; | |
557 | sPAPRConfigureConnectorState *ccs; | |
558 | sPAPRDRCCResponse resp = SPAPR_DR_CC_RESPONSE_CONTINUE; | |
559 | int rc; | |
560 | const void *fdt; | |
561 | ||
562 | if (nargs != 2 || nret != 1) { | |
563 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
564 | return; | |
565 | } | |
566 | ||
567 | wa_addr = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 0); | |
568 | ||
569 | drc_index = rtas_ld(wa_addr, 0); | |
570 | drc = spapr_dr_connector_by_index(drc_index); | |
571 | if (!drc) { | |
572 | DPRINTF("rtas_ibm_configure_connector: invalid DRC index: %xh\n", | |
573 | drc_index); | |
574 | rc = RTAS_OUT_PARAM_ERROR; | |
575 | goto out; | |
576 | } | |
577 | ||
578 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
579 | fdt = drck->get_fdt(drc, NULL); | |
e6fc9568 BR |
580 | if (!fdt) { |
581 | DPRINTF("rtas_ibm_configure_connector: Missing FDT for DRC index: %xh\n", | |
582 | drc_index); | |
583 | rc = SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE; | |
584 | goto out; | |
585 | } | |
46503c2b MR |
586 | |
587 | ccs = spapr_ccs_find(spapr, drc_index); | |
588 | if (!ccs) { | |
589 | ccs = g_new0(sPAPRConfigureConnectorState, 1); | |
590 | (void)drck->get_fdt(drc, &ccs->fdt_offset); | |
591 | ccs->drc_index = drc_index; | |
592 | spapr_ccs_add(spapr, ccs); | |
593 | } | |
594 | ||
595 | do { | |
596 | uint32_t tag; | |
597 | const char *name; | |
598 | const struct fdt_property *prop; | |
599 | int fdt_offset_next, prop_len; | |
600 | ||
601 | tag = fdt_next_tag(fdt, ccs->fdt_offset, &fdt_offset_next); | |
602 | ||
603 | switch (tag) { | |
604 | case FDT_BEGIN_NODE: | |
605 | ccs->fdt_depth++; | |
606 | name = fdt_get_name(fdt, ccs->fdt_offset, NULL); | |
607 | ||
608 | /* provide the name of the next OF node */ | |
609 | wa_offset = CC_VAL_DATA_OFFSET; | |
610 | rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset); | |
f201987b | 611 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); |
46503c2b MR |
612 | resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD; |
613 | break; | |
614 | case FDT_END_NODE: | |
615 | ccs->fdt_depth--; | |
616 | if (ccs->fdt_depth == 0) { | |
617 | /* done sending the device tree, don't need to track | |
618 | * the state anymore | |
619 | */ | |
620 | drck->set_configured(drc); | |
621 | spapr_ccs_remove(spapr, ccs); | |
622 | ccs = NULL; | |
623 | resp = SPAPR_DR_CC_RESPONSE_SUCCESS; | |
624 | } else { | |
625 | resp = SPAPR_DR_CC_RESPONSE_PREV_PARENT; | |
626 | } | |
627 | break; | |
628 | case FDT_PROP: | |
629 | prop = fdt_get_property_by_offset(fdt, ccs->fdt_offset, | |
630 | &prop_len); | |
631 | name = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); | |
632 | ||
633 | /* provide the name of the next OF property */ | |
634 | wa_offset = CC_VAL_DATA_OFFSET; | |
635 | rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset); | |
f201987b | 636 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); |
46503c2b MR |
637 | |
638 | /* provide the length and value of the OF property. data gets | |
639 | * placed immediately after NULL terminator of the OF property's | |
640 | * name string | |
641 | */ | |
642 | wa_offset += strlen(name) + 1, | |
643 | rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len); | |
644 | rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset); | |
f201987b | 645 | configure_connector_st(wa_addr, wa_offset, prop->data, prop_len); |
46503c2b MR |
646 | resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY; |
647 | break; | |
648 | case FDT_END: | |
649 | resp = SPAPR_DR_CC_RESPONSE_ERROR; | |
650 | default: | |
651 | /* keep seeking for an actionable tag */ | |
652 | break; | |
653 | } | |
654 | if (ccs) { | |
655 | ccs->fdt_offset = fdt_offset_next; | |
656 | } | |
657 | } while (resp == SPAPR_DR_CC_RESPONSE_CONTINUE); | |
658 | ||
659 | rc = resp; | |
660 | out: | |
661 | rtas_st(rets, 0, rc); | |
662 | } | |
663 | ||
39ac8455 DG |
664 | static struct rtas_call { |
665 | const char *name; | |
666 | spapr_rtas_fn fn; | |
3a3b8502 | 667 | } rtas_table[RTAS_TOKEN_MAX - RTAS_TOKEN_BASE]; |
39ac8455 | 668 | |
28e02042 | 669 | target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
39ac8455 DG |
670 | uint32_t token, uint32_t nargs, target_ulong args, |
671 | uint32_t nret, target_ulong rets) | |
672 | { | |
3a3b8502 AK |
673 | if ((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX)) { |
674 | struct rtas_call *call = rtas_table + (token - RTAS_TOKEN_BASE); | |
39ac8455 DG |
675 | |
676 | if (call->fn) { | |
210b580b | 677 | call->fn(cpu, spapr, token, nargs, args, nret, rets); |
39ac8455 DG |
678 | return H_SUCCESS; |
679 | } | |
680 | } | |
681 | ||
821303f5 DG |
682 | /* HACK: Some Linux early debug code uses RTAS display-character, |
683 | * but assumes the token value is 0xa (which it is on some real | |
684 | * machines) without looking it up in the device tree. This | |
685 | * special case makes this work */ | |
686 | if (token == 0xa) { | |
210b580b | 687 | rtas_display_character(cpu, spapr, 0xa, nargs, args, nret, rets); |
821303f5 DG |
688 | return H_SUCCESS; |
689 | } | |
690 | ||
39ac8455 | 691 | hcall_dprintf("Unknown RTAS token 0x%x\n", token); |
a64d325d | 692 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
39ac8455 DG |
693 | return H_PARAMETER; |
694 | } | |
695 | ||
eeddd59f LV |
696 | uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uint64_t args, |
697 | uint32_t nret, uint64_t rets) | |
698 | { | |
699 | int token; | |
700 | ||
701 | for (token = 0; token < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; token++) { | |
702 | if (strcmp(cmd, rtas_table[token].name) == 0) { | |
703 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
704 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); | |
705 | ||
706 | rtas_table[token].fn(cpu, spapr, token + RTAS_TOKEN_BASE, | |
707 | nargs, args, nret, rets); | |
708 | return H_SUCCESS; | |
709 | } | |
710 | } | |
711 | return H_PARAMETER; | |
712 | } | |
713 | ||
3a3b8502 | 714 | void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn) |
39ac8455 | 715 | { |
adf9ac50 | 716 | assert((token >= RTAS_TOKEN_BASE) && (token < RTAS_TOKEN_MAX)); |
c89d5299 | 717 | |
3a3b8502 | 718 | token -= RTAS_TOKEN_BASE; |
adf9ac50 DG |
719 | |
720 | assert(!rtas_table[token].name); | |
39ac8455 | 721 | |
3a3b8502 AK |
722 | rtas_table[token].name = name; |
723 | rtas_table[token].fn = fn; | |
39ac8455 DG |
724 | } |
725 | ||
a8170e5e AK |
726 | int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, |
727 | hwaddr rtas_size) | |
39ac8455 DG |
728 | { |
729 | int ret; | |
730 | int i; | |
db4ef288 BR |
731 | uint32_t lrdr_capacity[5]; |
732 | MachineState *machine = MACHINE(qdev_get_machine()); | |
a110655a BR |
733 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
734 | uint64_t max_hotplug_addr = spapr->hotplug_memory.base + | |
735 | memory_region_size(&spapr->hotplug_memory.mr); | |
39ac8455 DG |
736 | |
737 | ret = fdt_add_mem_rsv(fdt, rtas_addr, rtas_size); | |
738 | if (ret < 0) { | |
ce9863b7 | 739 | error_report("Couldn't add RTAS reserve entry: %s", |
39ac8455 DG |
740 | fdt_strerror(ret)); |
741 | return ret; | |
742 | } | |
743 | ||
5a4348d1 PC |
744 | ret = qemu_fdt_setprop_cell(fdt, "/rtas", "linux,rtas-base", |
745 | rtas_addr); | |
39ac8455 | 746 | if (ret < 0) { |
ce9863b7 | 747 | error_report("Couldn't add linux,rtas-base property: %s", |
39ac8455 DG |
748 | fdt_strerror(ret)); |
749 | return ret; | |
750 | } | |
751 | ||
5a4348d1 PC |
752 | ret = qemu_fdt_setprop_cell(fdt, "/rtas", "linux,rtas-entry", |
753 | rtas_addr); | |
39ac8455 | 754 | if (ret < 0) { |
ce9863b7 | 755 | error_report("Couldn't add linux,rtas-entry property: %s", |
39ac8455 DG |
756 | fdt_strerror(ret)); |
757 | return ret; | |
758 | } | |
759 | ||
5a4348d1 PC |
760 | ret = qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", |
761 | rtas_size); | |
39ac8455 | 762 | if (ret < 0) { |
ce9863b7 | 763 | error_report("Couldn't add rtas-size property: %s", |
39ac8455 DG |
764 | fdt_strerror(ret)); |
765 | return ret; | |
766 | } | |
767 | ||
3a3b8502 | 768 | for (i = 0; i < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; i++) { |
39ac8455 DG |
769 | struct rtas_call *call = &rtas_table[i]; |
770 | ||
d36b66f7 | 771 | if (!call->name) { |
39ac8455 DG |
772 | continue; |
773 | } | |
774 | ||
5a4348d1 | 775 | ret = qemu_fdt_setprop_cell(fdt, "/rtas", call->name, |
3a3b8502 | 776 | i + RTAS_TOKEN_BASE); |
39ac8455 | 777 | if (ret < 0) { |
ce9863b7 | 778 | error_report("Couldn't add rtas token for %s: %s", |
39ac8455 DG |
779 | call->name, fdt_strerror(ret)); |
780 | return ret; | |
781 | } | |
782 | ||
783 | } | |
db4ef288 | 784 | |
a110655a BR |
785 | lrdr_capacity[0] = cpu_to_be32(max_hotplug_addr >> 32); |
786 | lrdr_capacity[1] = cpu_to_be32(max_hotplug_addr & 0xffffffff); | |
db4ef288 BR |
787 | lrdr_capacity[2] = 0; |
788 | lrdr_capacity[3] = cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE); | |
789 | lrdr_capacity[4] = cpu_to_be32(max_cpus/smp_threads); | |
790 | ret = qemu_fdt_setprop(fdt, "/rtas", "ibm,lrdr-capacity", lrdr_capacity, | |
791 | sizeof(lrdr_capacity)); | |
792 | if (ret < 0) { | |
ce9863b7 | 793 | error_report("Couldn't add ibm,lrdr-capacity rtas property"); |
db4ef288 BR |
794 | return ret; |
795 | } | |
796 | ||
39ac8455 DG |
797 | return 0; |
798 | } | |
821303f5 | 799 | |
83f7d43a | 800 | static void core_rtas_register_types(void) |
821303f5 | 801 | { |
3a3b8502 AK |
802 | spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", |
803 | rtas_display_character); | |
3a3b8502 AK |
804 | spapr_rtas_register(RTAS_POWER_OFF, "power-off", rtas_power_off); |
805 | spapr_rtas_register(RTAS_SYSTEM_REBOOT, "system-reboot", | |
806 | rtas_system_reboot); | |
807 | spapr_rtas_register(RTAS_QUERY_CPU_STOPPED_STATE, "query-cpu-stopped-state", | |
a9f8ad8f | 808 | rtas_query_cpu_stopped_state); |
3a3b8502 AK |
809 | spapr_rtas_register(RTAS_START_CPU, "start-cpu", rtas_start_cpu); |
810 | spapr_rtas_register(RTAS_STOP_SELF, "stop-self", rtas_stop_self); | |
811 | spapr_rtas_register(RTAS_IBM_GET_SYSTEM_PARAMETER, | |
812 | "ibm,get-system-parameter", | |
3ada6b11 | 813 | rtas_ibm_get_system_parameter); |
3a3b8502 AK |
814 | spapr_rtas_register(RTAS_IBM_SET_SYSTEM_PARAMETER, |
815 | "ibm,set-system-parameter", | |
3ada6b11 | 816 | rtas_ibm_set_system_parameter); |
2e14072f ND |
817 | spapr_rtas_register(RTAS_IBM_OS_TERM, "ibm,os-term", |
818 | rtas_ibm_os_term); | |
094d2058 NF |
819 | spapr_rtas_register(RTAS_SET_POWER_LEVEL, "set-power-level", |
820 | rtas_set_power_level); | |
821 | spapr_rtas_register(RTAS_GET_POWER_LEVEL, "get-power-level", | |
822 | rtas_get_power_level); | |
8c8639df MD |
823 | spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator", |
824 | rtas_set_indicator); | |
886445a6 MD |
825 | spapr_rtas_register(RTAS_GET_SENSOR_STATE, "get-sensor-state", |
826 | rtas_get_sensor_state); | |
46503c2b MR |
827 | spapr_rtas_register(RTAS_IBM_CONFIGURE_CONNECTOR, "ibm,configure-connector", |
828 | rtas_ibm_configure_connector); | |
821303f5 | 829 | } |
83f7d43a AF |
830 | |
831 | type_init(core_rtas_register_types) |