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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
9a64fbe4 | 23 | */ |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "nvram.h" | |
26 | #include "pc.h" | |
27 | #include "fdc.h" | |
28 | #include "net.h" | |
29 | #include "sysemu.h" | |
30 | #include "isa.h" | |
31 | #include "pci.h" | |
18e08a55 MT |
32 | #include "prep_pci.h" |
33 | #include "usb-ohci.h" | |
87ecb68b PB |
34 | #include "ppc.h" |
35 | #include "boards.h" | |
3b3fb322 | 36 | #include "qemu-log.h" |
ec82026c | 37 | #include "ide.h" |
ca20cf32 | 38 | #include "loader.h" |
9fddaa0c | 39 | |
9a64fbe4 | 40 | //#define HARD_DEBUG_PPC_IO |
a541f297 | 41 | //#define DEBUG_PPC_IO |
9a64fbe4 | 42 | |
fe33cc71 JM |
43 | /* SMP is not enabled, for now */ |
44 | #define MAX_CPUS 1 | |
45 | ||
e4bcb14c TS |
46 | #define MAX_IDE_BUS 2 |
47 | ||
bba831e8 | 48 | #define BIOS_SIZE (1024 * 1024) |
b6b8bd18 FB |
49 | #define BIOS_FILENAME "ppc_rom.bin" |
50 | #define KERNEL_LOAD_ADDR 0x01000000 | |
51 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 52 | |
9a64fbe4 FB |
53 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
54 | #define DEBUG_PPC_IO | |
55 | #endif | |
56 | ||
57 | #if defined (HARD_DEBUG_PPC_IO) | |
001faf32 | 58 | #define PPC_IO_DPRINTF(fmt, ...) \ |
9a64fbe4 | 59 | do { \ |
8fec2b8c | 60 | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ |
001faf32 | 61 | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 | 62 | } else { \ |
001faf32 | 63 | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 FB |
64 | } \ |
65 | } while (0) | |
66 | #elif defined (DEBUG_PPC_IO) | |
0bf9e31a BS |
67 | #define PPC_IO_DPRINTF(fmt, ...) \ |
68 | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) | |
9a64fbe4 | 69 | #else |
001faf32 | 70 | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
9a64fbe4 FB |
71 | #endif |
72 | ||
64201201 | 73 | /* Constants for devices init */ |
a541f297 FB |
74 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
75 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
76 | static const int ide_irq[2] = { 13, 13 }; | |
77 | ||
78 | #define NE2000_NB_MAX 6 | |
79 | ||
80 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
81 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 82 | |
64201201 FB |
83 | //static PITState *pit; |
84 | ||
85 | /* ISA IO ports bridge */ | |
9a64fbe4 FB |
86 | #define PPC_IO_BASE 0x80000000 |
87 | ||
b1d8e52e | 88 | #if 0 |
64201201 | 89 | /* Speaker port 0x61 */ |
b1d8e52e BS |
90 | static int speaker_data_on; |
91 | static int dummy_refresh_clock; | |
92 | #endif | |
64201201 | 93 | |
36081602 | 94 | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 95 | { |
a541f297 | 96 | #if 0 |
64201201 FB |
97 | speaker_data_on = (val >> 1) & 1; |
98 | pit_set_gate(pit, 2, val & 1); | |
a541f297 | 99 | #endif |
9a64fbe4 FB |
100 | } |
101 | ||
47103572 | 102 | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
9a64fbe4 | 103 | { |
a541f297 | 104 | #if 0 |
64201201 FB |
105 | int out; |
106 | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); | |
107 | dummy_refresh_clock ^= 1; | |
108 | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | | |
47103572 | 109 | (dummy_refresh_clock << 4); |
a541f297 | 110 | #endif |
64201201 | 111 | return 0; |
9a64fbe4 FB |
112 | } |
113 | ||
64201201 FB |
114 | /* PCI intack register */ |
115 | /* Read-only register (?) */ | |
47103572 | 116 | static void _PPC_intack_write (void *opaque, |
c227f099 | 117 | target_phys_addr_t addr, uint32_t value) |
64201201 | 118 | { |
90e189ec BS |
119 | #if 0 |
120 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, | |
121 | value); | |
122 | #endif | |
64201201 FB |
123 | } |
124 | ||
c227f099 | 125 | static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) |
64201201 FB |
126 | { |
127 | uint32_t retval = 0; | |
128 | ||
4dd8c138 | 129 | if ((addr & 0xf) == 0) |
3de388f6 | 130 | retval = pic_intack_read(isa_pic); |
90e189ec BS |
131 | #if 0 |
132 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, | |
133 | retval); | |
134 | #endif | |
64201201 FB |
135 | |
136 | return retval; | |
137 | } | |
138 | ||
c227f099 | 139 | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
140 | { |
141 | return _PPC_intack_read(addr); | |
142 | } | |
143 | ||
c227f099 | 144 | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 145 | { |
f658b4db | 146 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
147 | return bswap16(_PPC_intack_read(addr)); |
148 | #else | |
149 | return _PPC_intack_read(addr); | |
f658b4db | 150 | #endif |
9a64fbe4 FB |
151 | } |
152 | ||
c227f099 | 153 | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 154 | { |
f658b4db | 155 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
156 | return bswap32(_PPC_intack_read(addr)); |
157 | #else | |
158 | return _PPC_intack_read(addr); | |
f658b4db | 159 | #endif |
9a64fbe4 FB |
160 | } |
161 | ||
d60efc6b | 162 | static CPUWriteMemoryFunc * const PPC_intack_write[] = { |
64201201 FB |
163 | &_PPC_intack_write, |
164 | &_PPC_intack_write, | |
165 | &_PPC_intack_write, | |
166 | }; | |
167 | ||
d60efc6b | 168 | static CPUReadMemoryFunc * const PPC_intack_read[] = { |
64201201 FB |
169 | &PPC_intack_readb, |
170 | &PPC_intack_readw, | |
171 | &PPC_intack_readl, | |
172 | }; | |
173 | ||
174 | /* PowerPC control and status registers */ | |
175 | #if 0 // Not used | |
176 | static struct { | |
177 | /* IDs */ | |
178 | uint32_t veni_devi; | |
179 | uint32_t revi; | |
180 | /* Control and status */ | |
181 | uint32_t gcsr; | |
182 | uint32_t xcfr; | |
183 | uint32_t ct32; | |
184 | uint32_t mcsr; | |
185 | /* General purpose registers */ | |
186 | uint32_t gprg[6]; | |
187 | /* Exceptions */ | |
188 | uint32_t feen; | |
189 | uint32_t fest; | |
190 | uint32_t fema; | |
191 | uint32_t fecl; | |
192 | uint32_t eeen; | |
193 | uint32_t eest; | |
194 | uint32_t eecl; | |
195 | uint32_t eeint; | |
196 | uint32_t eemck0; | |
197 | uint32_t eemck1; | |
198 | /* Error diagnostic */ | |
199 | } XCSR; | |
64201201 | 200 | |
36081602 | 201 | static void PPC_XCSR_writeb (void *opaque, |
c227f099 | 202 | target_phys_addr_t addr, uint32_t value) |
64201201 | 203 | { |
90e189ec BS |
204 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
205 | value); | |
64201201 FB |
206 | } |
207 | ||
36081602 | 208 | static void PPC_XCSR_writew (void *opaque, |
c227f099 | 209 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 210 | { |
f658b4db | 211 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 212 | value = bswap16(value); |
f658b4db | 213 | #endif |
90e189ec BS |
214 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
215 | value); | |
9a64fbe4 FB |
216 | } |
217 | ||
36081602 | 218 | static void PPC_XCSR_writel (void *opaque, |
c227f099 | 219 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 220 | { |
f658b4db | 221 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 222 | value = bswap32(value); |
f658b4db | 223 | #endif |
90e189ec BS |
224 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
225 | value); | |
9a64fbe4 FB |
226 | } |
227 | ||
c227f099 | 228 | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
229 | { |
230 | uint32_t retval = 0; | |
9a64fbe4 | 231 | |
90e189ec BS |
232 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
233 | retval); | |
9a64fbe4 | 234 | |
64201201 FB |
235 | return retval; |
236 | } | |
237 | ||
c227f099 | 238 | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 239 | { |
64201201 FB |
240 | uint32_t retval = 0; |
241 | ||
90e189ec BS |
242 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
243 | retval); | |
64201201 FB |
244 | #ifdef TARGET_WORDS_BIGENDIAN |
245 | retval = bswap16(retval); | |
246 | #endif | |
247 | ||
248 | return retval; | |
9a64fbe4 FB |
249 | } |
250 | ||
c227f099 | 251 | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 FB |
252 | { |
253 | uint32_t retval = 0; | |
254 | ||
90e189ec BS |
255 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
256 | retval); | |
64201201 FB |
257 | #ifdef TARGET_WORDS_BIGENDIAN |
258 | retval = bswap32(retval); | |
259 | #endif | |
9a64fbe4 FB |
260 | |
261 | return retval; | |
262 | } | |
263 | ||
d60efc6b | 264 | static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { |
64201201 FB |
265 | &PPC_XCSR_writeb, |
266 | &PPC_XCSR_writew, | |
267 | &PPC_XCSR_writel, | |
9a64fbe4 FB |
268 | }; |
269 | ||
d60efc6b | 270 | static CPUReadMemoryFunc * const PPC_XCSR_read[] = { |
64201201 FB |
271 | &PPC_XCSR_readb, |
272 | &PPC_XCSR_readw, | |
273 | &PPC_XCSR_readl, | |
9a64fbe4 | 274 | }; |
b6b8bd18 | 275 | #endif |
9a64fbe4 | 276 | |
64201201 | 277 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
c227f099 | 278 | typedef struct sysctrl_t { |
c4781a51 | 279 | qemu_irq reset_irq; |
c227f099 | 280 | m48t59_t *nvram; |
64201201 FB |
281 | uint8_t state; |
282 | uint8_t syscontrol; | |
283 | uint8_t fake_io[2]; | |
da9b266b | 284 | int contiguous_map; |
fb3444b8 | 285 | int endian; |
c227f099 | 286 | } sysctrl_t; |
9a64fbe4 | 287 | |
64201201 FB |
288 | enum { |
289 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 290 | }; |
9a64fbe4 | 291 | |
c227f099 | 292 | static sysctrl_t *sysctrl; |
9a64fbe4 | 293 | |
a541f297 | 294 | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 295 | { |
c227f099 | 296 | sysctrl_t *sysctrl = opaque; |
64201201 | 297 | |
aae9366a JM |
298 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
299 | val); | |
64201201 | 300 | sysctrl->fake_io[addr - 0x0398] = val; |
9a64fbe4 FB |
301 | } |
302 | ||
a541f297 | 303 | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
9a64fbe4 | 304 | { |
c227f099 | 305 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 | 306 | |
aae9366a | 307 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
64201201 FB |
308 | sysctrl->fake_io[addr - 0x0398]); |
309 | return sysctrl->fake_io[addr - 0x0398]; | |
310 | } | |
9a64fbe4 | 311 | |
a541f297 | 312 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 313 | { |
c227f099 | 314 | sysctrl_t *sysctrl = opaque; |
64201201 | 315 | |
aae9366a JM |
316 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
317 | addr - PPC_IO_BASE, val); | |
9a64fbe4 FB |
318 | switch (addr) { |
319 | case 0x0092: | |
320 | /* Special port 92 */ | |
321 | /* Check soft reset asked */ | |
64201201 | 322 | if (val & 0x01) { |
c4781a51 JM |
323 | qemu_irq_raise(sysctrl->reset_irq); |
324 | } else { | |
325 | qemu_irq_lower(sysctrl->reset_irq); | |
9a64fbe4 FB |
326 | } |
327 | /* Check LE mode */ | |
64201201 | 328 | if (val & 0x02) { |
fb3444b8 FB |
329 | sysctrl->endian = 1; |
330 | } else { | |
331 | sysctrl->endian = 0; | |
9a64fbe4 FB |
332 | } |
333 | break; | |
64201201 FB |
334 | case 0x0800: |
335 | /* Motorola CPU configuration register : read-only */ | |
336 | break; | |
337 | case 0x0802: | |
338 | /* Motorola base module feature register : read-only */ | |
339 | break; | |
340 | case 0x0803: | |
341 | /* Motorola base module status register : read-only */ | |
342 | break; | |
9a64fbe4 | 343 | case 0x0808: |
64201201 FB |
344 | /* Hardfile light register */ |
345 | if (val & 1) | |
346 | sysctrl->state |= STATE_HARDFILE; | |
347 | else | |
348 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
349 | break; |
350 | case 0x0810: | |
351 | /* Password protect 1 register */ | |
64201201 FB |
352 | if (sysctrl->nvram != NULL) |
353 | m48t59_toggle_lock(sysctrl->nvram, 1); | |
9a64fbe4 FB |
354 | break; |
355 | case 0x0812: | |
356 | /* Password protect 2 register */ | |
64201201 FB |
357 | if (sysctrl->nvram != NULL) |
358 | m48t59_toggle_lock(sysctrl->nvram, 2); | |
9a64fbe4 FB |
359 | break; |
360 | case 0x0814: | |
64201201 | 361 | /* L2 invalidate register */ |
c68ea704 | 362 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
363 | break; |
364 | case 0x081C: | |
365 | /* system control register */ | |
64201201 | 366 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
367 | break; |
368 | case 0x0850: | |
369 | /* I/O map type register */ | |
da9b266b | 370 | sysctrl->contiguous_map = val & 0x01; |
9a64fbe4 FB |
371 | break; |
372 | default: | |
aae9366a JM |
373 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
374 | " => %02" PRIx32"\n", addr, val); | |
9a64fbe4 FB |
375 | break; |
376 | } | |
377 | } | |
378 | ||
a541f297 | 379 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 380 | { |
c227f099 | 381 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
382 | uint32_t retval = 0xFF; |
383 | ||
384 | switch (addr) { | |
385 | case 0x0092: | |
386 | /* Special port 92 */ | |
64201201 FB |
387 | retval = 0x00; |
388 | break; | |
389 | case 0x0800: | |
390 | /* Motorola CPU configuration register */ | |
391 | retval = 0xEF; /* MPC750 */ | |
392 | break; | |
393 | case 0x0802: | |
394 | /* Motorola Base module feature register */ | |
395 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
396 | break; | |
397 | case 0x0803: | |
398 | /* Motorola base module status register */ | |
399 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
400 | break; |
401 | case 0x080C: | |
402 | /* Equipment present register: | |
403 | * no L2 cache | |
404 | * no upgrade processor | |
405 | * no cards in PCI slots | |
406 | * SCSI fuse is bad | |
407 | */ | |
64201201 FB |
408 | retval = 0x3C; |
409 | break; | |
410 | case 0x0810: | |
411 | /* Motorola base module extended feature register */ | |
412 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 413 | break; |
da9b266b FB |
414 | case 0x0814: |
415 | /* L2 invalidate: don't care */ | |
416 | break; | |
9a64fbe4 FB |
417 | case 0x0818: |
418 | /* Keylock */ | |
419 | retval = 0x00; | |
420 | break; | |
421 | case 0x081C: | |
422 | /* system control register | |
423 | * 7 - 6 / 1 - 0: L2 cache enable | |
424 | */ | |
64201201 | 425 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
426 | break; |
427 | case 0x0823: | |
428 | /* */ | |
429 | retval = 0x03; /* no L2 cache */ | |
430 | break; | |
431 | case 0x0850: | |
432 | /* I/O map type register */ | |
da9b266b | 433 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
434 | break; |
435 | default: | |
aae9366a | 436 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
9a64fbe4 FB |
437 | break; |
438 | } | |
aae9366a JM |
439 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
440 | addr - PPC_IO_BASE, retval); | |
9a64fbe4 FB |
441 | |
442 | return retval; | |
443 | } | |
444 | ||
c227f099 AL |
445 | static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
446 | target_phys_addr_t addr) | |
da9b266b FB |
447 | { |
448 | if (sysctrl->contiguous_map == 0) { | |
449 | /* 64 KB contiguous space for IOs */ | |
450 | addr &= 0xFFFF; | |
451 | } else { | |
452 | /* 8 MB non-contiguous space for IOs */ | |
453 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
454 | } | |
455 | ||
456 | return addr; | |
457 | } | |
458 | ||
c227f099 | 459 | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
460 | uint32_t value) |
461 | { | |
c227f099 | 462 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
463 | |
464 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 465 | cpu_outb(addr, value); |
da9b266b FB |
466 | } |
467 | ||
c227f099 | 468 | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
da9b266b | 469 | { |
c227f099 | 470 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
471 | uint32_t ret; |
472 | ||
473 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 474 | ret = cpu_inb(addr); |
da9b266b FB |
475 | |
476 | return ret; | |
477 | } | |
478 | ||
c227f099 | 479 | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
480 | uint32_t value) |
481 | { | |
c227f099 | 482 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
483 | |
484 | addr = prep_IO_address(sysctrl, addr); | |
485 | #ifdef TARGET_WORDS_BIGENDIAN | |
486 | value = bswap16(value); | |
487 | #endif | |
90e189ec | 488 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 489 | cpu_outw(addr, value); |
da9b266b FB |
490 | } |
491 | ||
c227f099 | 492 | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
da9b266b | 493 | { |
c227f099 | 494 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
495 | uint32_t ret; |
496 | ||
497 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 498 | ret = cpu_inw(addr); |
da9b266b FB |
499 | #ifdef TARGET_WORDS_BIGENDIAN |
500 | ret = bswap16(ret); | |
501 | #endif | |
90e189ec | 502 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
503 | |
504 | return ret; | |
505 | } | |
506 | ||
c227f099 | 507 | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
508 | uint32_t value) |
509 | { | |
c227f099 | 510 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
511 | |
512 | addr = prep_IO_address(sysctrl, addr); | |
513 | #ifdef TARGET_WORDS_BIGENDIAN | |
514 | value = bswap32(value); | |
515 | #endif | |
90e189ec | 516 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 517 | cpu_outl(addr, value); |
da9b266b FB |
518 | } |
519 | ||
c227f099 | 520 | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
da9b266b | 521 | { |
c227f099 | 522 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
523 | uint32_t ret; |
524 | ||
525 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 526 | ret = cpu_inl(addr); |
da9b266b FB |
527 | #ifdef TARGET_WORDS_BIGENDIAN |
528 | ret = bswap32(ret); | |
529 | #endif | |
90e189ec | 530 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
531 | |
532 | return ret; | |
533 | } | |
534 | ||
d60efc6b | 535 | static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { |
da9b266b FB |
536 | &PPC_prep_io_writeb, |
537 | &PPC_prep_io_writew, | |
538 | &PPC_prep_io_writel, | |
539 | }; | |
540 | ||
d60efc6b | 541 | static CPUReadMemoryFunc * const PPC_prep_io_read[] = { |
da9b266b FB |
542 | &PPC_prep_io_readb, |
543 | &PPC_prep_io_readw, | |
544 | &PPC_prep_io_readl, | |
545 | }; | |
546 | ||
64201201 | 547 | #define NVRAM_SIZE 0x2000 |
a541f297 | 548 | |
26aa7d72 | 549 | /* PowerPC PREP hardware initialisation */ |
c227f099 | 550 | static void ppc_prep_init (ram_addr_t ram_size, |
3023f332 | 551 | const char *boot_device, |
b881c2c6 | 552 | const char *kernel_filename, |
94fc95cd JM |
553 | const char *kernel_cmdline, |
554 | const char *initrd_filename, | |
555 | const char *cpu_model) | |
a541f297 | 556 | { |
0d913fdb | 557 | CPUState *env = NULL, *envs[MAX_CPUS]; |
5cea8590 | 558 | char *filename; |
c227f099 AL |
559 | nvram_t nvram; |
560 | m48t59_t *m48t59; | |
a541f297 | 561 | int PPC_io_memory; |
4157a662 | 562 | int linux_boot, i, nb_nics1, bios_size; |
c227f099 | 563 | ram_addr_t ram_offset, bios_offset; |
64201201 | 564 | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
46e50e9d | 565 | PCIBus *pci_bus; |
d537cf6c | 566 | qemu_irq *i8259; |
28c5af54 | 567 | int ppc_boot_device; |
f455e98c | 568 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 569 | DriveInfo *fd[MAX_FD]; |
64201201 | 570 | |
c227f099 | 571 | sysctrl = qemu_mallocz(sizeof(sysctrl_t)); |
a541f297 FB |
572 | |
573 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 574 | |
c68ea704 | 575 | /* init CPUs */ |
94fc95cd | 576 | if (cpu_model == NULL) |
b37fc148 | 577 | cpu_model = "602"; |
fe33cc71 | 578 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
579 | env = cpu_init(cpu_model); |
580 | if (!env) { | |
581 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
582 | exit(1); | |
583 | } | |
4018bae9 JM |
584 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
585 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
586 | cpu_ppc_tb_init(env, 7812500UL); | |
587 | } else { | |
588 | /* Set time-base frequency to 100 Mhz */ | |
589 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
590 | } | |
d84bda46 | 591 | qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
fe33cc71 JM |
592 | envs[i] = env; |
593 | } | |
a541f297 FB |
594 | |
595 | /* allocate RAM */ | |
cf9c147c BS |
596 | ram_offset = qemu_ram_alloc(ram_size); |
597 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
598 | ||
64201201 | 599 | /* allocate and load BIOS */ |
cf9c147c | 600 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
1192dad8 JM |
601 | if (bios_name == NULL) |
602 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
603 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
604 | if (filename) { | |
605 | bios_size = get_image_size(filename); | |
606 | } else { | |
607 | bios_size = -1; | |
608 | } | |
dcac9679 | 609 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
c227f099 | 610 | target_phys_addr_t bios_addr; |
dcac9679 PB |
611 | bios_size = (bios_size + 0xfff) & ~0xfff; |
612 | bios_addr = (uint32_t)(-bios_size); | |
613 | cpu_register_physical_memory(bios_addr, bios_size, | |
614 | bios_offset | IO_MEM_ROM); | |
5cea8590 | 615 | bios_size = load_image_targphys(filename, bios_addr, bios_size); |
dcac9679 | 616 | } |
4157a662 | 617 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 PB |
618 | hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); |
619 | } | |
620 | if (filename) { | |
621 | qemu_free(filename); | |
64201201 | 622 | } |
4c823cff | 623 | if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
2ac71179 | 624 | hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); |
4c823cff | 625 | } |
26aa7d72 | 626 | |
a541f297 | 627 | if (linux_boot) { |
64201201 | 628 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 629 | /* now we can load the kernel */ |
dcac9679 PB |
630 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
631 | ram_size - kernel_base); | |
64201201 | 632 | if (kernel_size < 0) { |
2ac71179 | 633 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
a541f297 FB |
634 | exit(1); |
635 | } | |
636 | /* load initrd */ | |
a541f297 | 637 | if (initrd_filename) { |
64201201 | 638 | initrd_base = INITRD_LOAD_ADDR; |
dcac9679 PB |
639 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
640 | ram_size - initrd_base); | |
a541f297 | 641 | if (initrd_size < 0) { |
2ac71179 | 642 | hw_error("qemu: could not load initial ram disk '%s'\n", |
4a057712 | 643 | initrd_filename); |
a541f297 | 644 | } |
64201201 FB |
645 | } else { |
646 | initrd_base = 0; | |
647 | initrd_size = 0; | |
a541f297 | 648 | } |
6ac0e82d | 649 | ppc_boot_device = 'm'; |
a541f297 | 650 | } else { |
64201201 FB |
651 | kernel_base = 0; |
652 | kernel_size = 0; | |
653 | initrd_base = 0; | |
654 | initrd_size = 0; | |
28c5af54 JM |
655 | ppc_boot_device = '\0'; |
656 | /* For now, OHW cannot boot from the network. */ | |
0d913fdb JM |
657 | for (i = 0; boot_device[i] != '\0'; i++) { |
658 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { | |
659 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 660 | break; |
0d913fdb | 661 | } |
28c5af54 JM |
662 | } |
663 | if (ppc_boot_device == '\0') { | |
664 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
665 | exit(1); | |
666 | } | |
a541f297 FB |
667 | } |
668 | ||
64201201 | 669 | isa_mem_base = 0xc0000000; |
dd37a5e4 | 670 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
2ac71179 | 671 | hw_error("Only 6xx bus is supported on PREP machine\n"); |
dd37a5e4 | 672 | } |
24be5ae3 | 673 | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
d537cf6c | 674 | pci_bus = pci_prep_init(i8259); |
b37fc148 GH |
675 | /* Hmm, prep has no pci-isa bridge ??? */ |
676 | isa_bus_new(NULL); | |
677 | isa_bus_irqs(i8259); | |
da9b266b FB |
678 | // pci_bus = i440fx_init(); |
679 | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ | |
1eed09cb | 680 | PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, |
da9b266b FB |
681 | PPC_prep_io_write, sysctrl); |
682 | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); | |
64201201 | 683 | |
a541f297 | 684 | /* init basic PC hardware */ |
fbe1b595 | 685 | pci_vga_init(pci_bus, 0, 0); |
64201201 | 686 | // openpic = openpic_init(0x00000000, 0xF0000000, 1); |
d537cf6c | 687 | // pit = pit_init(0x40, i8259[0]); |
32e0c826 | 688 | rtc_init(2000); |
a541f297 | 689 | |
ac0be998 GH |
690 | if (serial_hds[0]) |
691 | serial_isa_init(0, serial_hds[0]); | |
a541f297 FB |
692 | nb_nics1 = nb_nics; |
693 | if (nb_nics1 > NE2000_NB_MAX) | |
694 | nb_nics1 = NE2000_NB_MAX; | |
695 | for(i = 0; i < nb_nics1; i++) { | |
5652ef78 | 696 | if (nd_table[i].model == NULL) { |
9203f520 | 697 | nd_table[i].model = qemu_strdup("ne2k_isa"); |
5652ef78 AJ |
698 | } |
699 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { | |
9453c5bc | 700 | isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
a41b2ff2 | 701 | } else { |
07caea31 | 702 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
a41b2ff2 | 703 | } |
a541f297 | 704 | } |
a541f297 | 705 | |
e4bcb14c TS |
706 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
707 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
708 | exit(1); | |
709 | } | |
710 | ||
711 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 712 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c TS |
713 | } |
714 | ||
715 | for(i = 0; i < MAX_IDE_BUS; i++) { | |
dea21e97 | 716 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
717 | hd[2 * i], |
718 | hd[2 * i + 1]); | |
a541f297 | 719 | } |
11d23c35 | 720 | isa_create_simple("i8042"); |
b6b8bd18 | 721 | DMA_init(1); |
a541f297 FB |
722 | // SB16_init(); |
723 | ||
e4bcb14c | 724 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 725 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 726 | } |
86c86157 | 727 | fdctrl_init_isa(fd); |
a541f297 | 728 | |
64201201 FB |
729 | /* Register speaker port */ |
730 | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); | |
731 | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); | |
a541f297 | 732 | /* Register fake IO ports for PREP */ |
c4781a51 | 733 | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
64201201 FB |
734 | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
735 | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); | |
a541f297 | 736 | /* System control ports */ |
64201201 FB |
737 | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
738 | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); | |
739 | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); | |
740 | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); | |
741 | /* PCI intack location */ | |
1eed09cb | 742 | PPC_io_memory = cpu_register_io_memory(PPC_intack_read, |
a4193c8a | 743 | PPC_intack_write, NULL); |
a541f297 | 744 | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
64201201 | 745 | /* PowerPC control and status register group */ |
b6b8bd18 | 746 | #if 0 |
1eed09cb | 747 | PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, |
36081602 | 748 | NULL); |
64201201 | 749 | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
b6b8bd18 | 750 | #endif |
a541f297 | 751 | |
0d92ed30 | 752 | if (usb_enabled) { |
5b19d9a2 | 753 | usb_ohci_init_pci(pci_bus, -1); |
0d92ed30 PB |
754 | } |
755 | ||
3cbee15b JM |
756 | m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
757 | if (m48t59 == NULL) | |
64201201 | 758 | return; |
3cbee15b | 759 | sysctrl->nvram = m48t59; |
64201201 FB |
760 | |
761 | /* Initialise NVRAM */ | |
3cbee15b JM |
762 | nvram.opaque = m48t59; |
763 | nvram.read_fn = &m48t59_read; | |
764 | nvram.write_fn = &m48t59_write; | |
6ac0e82d | 765 | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, |
64201201 | 766 | kernel_base, kernel_size, |
b6b8bd18 | 767 | kernel_cmdline, |
64201201 FB |
768 | initrd_base, initrd_size, |
769 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
770 | 0, |
771 | graphic_width, graphic_height, graphic_depth); | |
c0e564d5 FB |
772 | |
773 | /* Special port to get debug messages from Open-Firmware */ | |
774 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); | |
a541f297 | 775 | } |
c0e564d5 | 776 | |
f80f9ec9 | 777 | static QEMUMachine prep_machine = { |
4b32e168 AL |
778 | .name = "prep", |
779 | .desc = "PowerPC PREP platform", | |
780 | .init = ppc_prep_init, | |
3d878caa | 781 | .max_cpus = MAX_CPUS, |
c0e564d5 | 782 | }; |
f80f9ec9 AL |
783 | |
784 | static void prep_machine_init(void) | |
785 | { | |
786 | qemu_register_machine(&prep_machine); | |
787 | } | |
788 | ||
789 | machine_init(prep_machine_init); |