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a19cbfb3 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann | |
5 | * maintained by Gerd Hoffmann <kraxel@redhat.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
a19cbfb3 GH |
21 | #include "qemu-common.h" |
22 | #include "qemu-timer.h" | |
23 | #include "qemu-queue.h" | |
24 | #include "monitor.h" | |
25 | #include "sysemu.h" | |
26 | ||
27 | #include "qxl.h" | |
28 | ||
29 | #undef SPICE_RING_PROD_ITEM | |
30 | #define SPICE_RING_PROD_ITEM(r, ret) { \ | |
31 | typeof(r) start = r; \ | |
32 | typeof(r) end = r + 1; \ | |
33 | uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ | |
34 | typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ | |
35 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
36 | abort(); \ | |
37 | } \ | |
38 | ret = &m_item->el; \ | |
39 | } | |
40 | ||
41 | #undef SPICE_RING_CONS_ITEM | |
42 | #define SPICE_RING_CONS_ITEM(r, ret) { \ | |
43 | typeof(r) start = r; \ | |
44 | typeof(r) end = r + 1; \ | |
45 | uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ | |
46 | typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ | |
47 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
48 | abort(); \ | |
49 | } \ | |
50 | ret = &m_item->el; \ | |
51 | } | |
52 | ||
53 | #undef ALIGN | |
54 | #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) | |
55 | ||
56 | #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" | |
57 | ||
58 | #define QXL_MODE(_x, _y, _b, _o) \ | |
59 | { .x_res = _x, \ | |
60 | .y_res = _y, \ | |
61 | .bits = _b, \ | |
62 | .stride = (_x) * (_b) / 8, \ | |
63 | .x_mili = PIXEL_SIZE * (_x), \ | |
64 | .y_mili = PIXEL_SIZE * (_y), \ | |
65 | .orientation = _o, \ | |
66 | } | |
67 | ||
68 | #define QXL_MODE_16_32(x_res, y_res, orientation) \ | |
69 | QXL_MODE(x_res, y_res, 16, orientation), \ | |
70 | QXL_MODE(x_res, y_res, 32, orientation) | |
71 | ||
72 | #define QXL_MODE_EX(x_res, y_res) \ | |
73 | QXL_MODE_16_32(x_res, y_res, 0), \ | |
74 | QXL_MODE_16_32(y_res, x_res, 1), \ | |
75 | QXL_MODE_16_32(x_res, y_res, 2), \ | |
76 | QXL_MODE_16_32(y_res, x_res, 3) | |
77 | ||
78 | static QXLMode qxl_modes[] = { | |
79 | QXL_MODE_EX(640, 480), | |
80 | QXL_MODE_EX(800, 480), | |
81 | QXL_MODE_EX(800, 600), | |
82 | QXL_MODE_EX(832, 624), | |
83 | QXL_MODE_EX(960, 640), | |
84 | QXL_MODE_EX(1024, 600), | |
85 | QXL_MODE_EX(1024, 768), | |
86 | QXL_MODE_EX(1152, 864), | |
87 | QXL_MODE_EX(1152, 870), | |
88 | QXL_MODE_EX(1280, 720), | |
89 | QXL_MODE_EX(1280, 760), | |
90 | QXL_MODE_EX(1280, 768), | |
91 | QXL_MODE_EX(1280, 800), | |
92 | QXL_MODE_EX(1280, 960), | |
93 | QXL_MODE_EX(1280, 1024), | |
94 | QXL_MODE_EX(1360, 768), | |
95 | QXL_MODE_EX(1366, 768), | |
96 | QXL_MODE_EX(1400, 1050), | |
97 | QXL_MODE_EX(1440, 900), | |
98 | QXL_MODE_EX(1600, 900), | |
99 | QXL_MODE_EX(1600, 1200), | |
100 | QXL_MODE_EX(1680, 1050), | |
101 | QXL_MODE_EX(1920, 1080), | |
102 | #if VGA_RAM_SIZE >= (16 * 1024 * 1024) | |
103 | /* these modes need more than 8 MB video memory */ | |
104 | QXL_MODE_EX(1920, 1200), | |
105 | QXL_MODE_EX(1920, 1440), | |
106 | QXL_MODE_EX(2048, 1536), | |
107 | QXL_MODE_EX(2560, 1440), | |
108 | QXL_MODE_EX(2560, 1600), | |
109 | #endif | |
110 | #if VGA_RAM_SIZE >= (32 * 1024 * 1024) | |
111 | /* these modes need more than 16 MB video memory */ | |
112 | QXL_MODE_EX(2560, 2048), | |
113 | QXL_MODE_EX(2800, 2100), | |
114 | QXL_MODE_EX(3200, 2400), | |
115 | #endif | |
116 | }; | |
117 | ||
118 | static PCIQXLDevice *qxl0; | |
119 | ||
120 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events); | |
5ff4e36c | 121 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
a19cbfb3 GH |
122 | static void qxl_reset_memslots(PCIQXLDevice *d); |
123 | static void qxl_reset_surfaces(PCIQXLDevice *d); | |
124 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl); | |
125 | ||
7635392c | 126 | void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
2bce0400 | 127 | { |
2bce0400 | 128 | qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
2bce0400 | 129 | if (qxl->guestdebug) { |
7635392c AL |
130 | va_list ap; |
131 | va_start(ap, msg); | |
132 | fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); | |
133 | vfprintf(stderr, msg, ap); | |
134 | fprintf(stderr, "\n"); | |
135 | va_end(ap); | |
2bce0400 GH |
136 | } |
137 | } | |
138 | ||
aee32bf3 GH |
139 | |
140 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, | |
141 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
142 | uint32_t num_dirty_rects, | |
5ff4e36c | 143 | uint32_t clear_dirty_region, |
2e1a98c9 | 144 | qxl_async_io async, struct QXLCookie *cookie) |
aee32bf3 | 145 | { |
5ff4e36c AL |
146 | if (async == QXL_SYNC) { |
147 | qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, | |
148 | dirty_rects, num_dirty_rects, clear_dirty_region); | |
149 | } else { | |
2e1a98c9 | 150 | assert(cookie != NULL); |
5ff4e36c | 151 | spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
2e1a98c9 | 152 | clear_dirty_region, (uint64_t)cookie); |
5ff4e36c | 153 | } |
aee32bf3 GH |
154 | } |
155 | ||
5ff4e36c AL |
156 | static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
157 | uint32_t id) | |
aee32bf3 | 158 | { |
14898cf6 | 159 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
160 | qxl->guest_surfaces.cmds[id] = 0; |
161 | qxl->guest_surfaces.count--; | |
162 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
163 | } |
164 | ||
5ff4e36c AL |
165 | static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
166 | qxl_async_io async) | |
167 | { | |
2e1a98c9 AL |
168 | QXLCookie *cookie; |
169 | ||
5ff4e36c | 170 | if (async) { |
2e1a98c9 AL |
171 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
172 | QXL_IO_DESTROY_SURFACE_ASYNC); | |
173 | cookie->u.surface_id = id; | |
174 | spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uint64_t)cookie); | |
5ff4e36c AL |
175 | } else { |
176 | qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); | |
177 | qxl_spice_destroy_surface_wait_complete(qxl, id); | |
178 | } | |
179 | } | |
180 | ||
3e16b9c5 AL |
181 | static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
182 | { | |
2e1a98c9 AL |
183 | spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
184 | (uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
185 | QXL_IO_FLUSH_SURFACES_ASYNC)); | |
3e16b9c5 | 186 | } |
3e16b9c5 | 187 | |
aee32bf3 GH |
188 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
189 | uint32_t count) | |
190 | { | |
191 | qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); | |
192 | } | |
193 | ||
194 | void qxl_spice_oom(PCIQXLDevice *qxl) | |
195 | { | |
196 | qxl->ssd.worker->oom(qxl->ssd.worker); | |
197 | } | |
198 | ||
199 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl) | |
200 | { | |
201 | qxl->ssd.worker->reset_memslots(qxl->ssd.worker); | |
202 | } | |
203 | ||
5ff4e36c | 204 | static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
aee32bf3 | 205 | { |
14898cf6 | 206 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
207 | memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds)); |
208 | qxl->guest_surfaces.count = 0; | |
209 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
210 | } |
211 | ||
5ff4e36c AL |
212 | static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
213 | { | |
214 | if (async) { | |
2e1a98c9 AL |
215 | spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
216 | (uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
217 | QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); | |
5ff4e36c AL |
218 | } else { |
219 | qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); | |
220 | qxl_spice_destroy_surfaces_complete(qxl); | |
221 | } | |
222 | } | |
223 | ||
aee32bf3 GH |
224 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) |
225 | { | |
226 | qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); | |
227 | } | |
228 | ||
229 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl) | |
230 | { | |
231 | qxl->ssd.worker->reset_cursor(qxl->ssd.worker); | |
30f6da66 YH |
232 | qemu_mutex_lock(&qxl->track_lock); |
233 | qxl->guest_cursor = 0; | |
234 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
235 | } |
236 | ||
237 | ||
a19cbfb3 GH |
238 | static inline uint32_t msb_mask(uint32_t val) |
239 | { | |
240 | uint32_t mask; | |
241 | ||
242 | do { | |
243 | mask = ~(val - 1) & val; | |
244 | val &= ~mask; | |
245 | } while (mask < val); | |
246 | ||
247 | return mask; | |
248 | } | |
249 | ||
250 | static ram_addr_t qxl_rom_size(void) | |
251 | { | |
252 | uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); | |
253 | rom_size = MAX(rom_size, TARGET_PAGE_SIZE); | |
254 | rom_size = msb_mask(rom_size * 2 - 1); | |
255 | return rom_size; | |
256 | } | |
257 | ||
258 | static void init_qxl_rom(PCIQXLDevice *d) | |
259 | { | |
b1950430 | 260 | QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
a19cbfb3 GH |
261 | QXLModes *modes = (QXLModes *)(rom + 1); |
262 | uint32_t ram_header_size; | |
263 | uint32_t surface0_area_size; | |
264 | uint32_t num_pages; | |
265 | uint32_t fb, maxfb = 0; | |
266 | int i; | |
267 | ||
268 | memset(rom, 0, d->rom_size); | |
269 | ||
270 | rom->magic = cpu_to_le32(QXL_ROM_MAGIC); | |
271 | rom->id = cpu_to_le32(d->id); | |
272 | rom->log_level = cpu_to_le32(d->guestdebug); | |
273 | rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); | |
274 | ||
275 | rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; | |
276 | rom->slot_id_bits = MEMSLOT_SLOT_BITS; | |
277 | rom->slots_start = 1; | |
278 | rom->slots_end = NUM_MEMSLOTS - 1; | |
279 | rom->n_surfaces = cpu_to_le32(NUM_SURFACES); | |
280 | ||
281 | modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes)); | |
282 | for (i = 0; i < modes->n_modes; i++) { | |
283 | fb = qxl_modes[i].y_res * qxl_modes[i].stride; | |
284 | if (maxfb < fb) { | |
285 | maxfb = fb; | |
286 | } | |
287 | modes->modes[i].id = cpu_to_le32(i); | |
288 | modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res); | |
289 | modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res); | |
290 | modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits); | |
291 | modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride); | |
292 | modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili); | |
293 | modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili); | |
294 | modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation); | |
295 | } | |
296 | if (maxfb < VGA_RAM_SIZE && d->id == 0) | |
297 | maxfb = VGA_RAM_SIZE; | |
298 | ||
299 | ram_header_size = ALIGN(sizeof(QXLRam), 4096); | |
300 | surface0_area_size = ALIGN(maxfb, 4096); | |
301 | num_pages = d->vga.vram_size; | |
302 | num_pages -= ram_header_size; | |
303 | num_pages -= surface0_area_size; | |
304 | num_pages = num_pages / TARGET_PAGE_SIZE; | |
305 | ||
306 | rom->draw_area_offset = cpu_to_le32(0); | |
307 | rom->surface0_area_size = cpu_to_le32(surface0_area_size); | |
308 | rom->pages_offset = cpu_to_le32(surface0_area_size); | |
309 | rom->num_pages = cpu_to_le32(num_pages); | |
310 | rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); | |
311 | ||
312 | d->shadow_rom = *rom; | |
313 | d->rom = rom; | |
314 | d->modes = modes; | |
315 | } | |
316 | ||
317 | static void init_qxl_ram(PCIQXLDevice *d) | |
318 | { | |
319 | uint8_t *buf; | |
320 | uint64_t *item; | |
321 | ||
322 | buf = d->vga.vram_ptr; | |
323 | d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); | |
324 | d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); | |
325 | d->ram->int_pending = cpu_to_le32(0); | |
326 | d->ram->int_mask = cpu_to_le32(0); | |
9f0f352d | 327 | d->ram->update_surface = 0; |
a19cbfb3 GH |
328 | SPICE_RING_INIT(&d->ram->cmd_ring); |
329 | SPICE_RING_INIT(&d->ram->cursor_ring); | |
330 | SPICE_RING_INIT(&d->ram->release_ring); | |
331 | SPICE_RING_PROD_ITEM(&d->ram->release_ring, item); | |
332 | *item = 0; | |
333 | qxl_ring_set_dirty(d); | |
334 | } | |
335 | ||
336 | /* can be called from spice server thread context */ | |
b1950430 | 337 | static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
a19cbfb3 | 338 | { |
fd4aa979 | 339 | memory_region_set_dirty(mr, addr, end - addr); |
a19cbfb3 GH |
340 | } |
341 | ||
342 | static void qxl_rom_set_dirty(PCIQXLDevice *qxl) | |
343 | { | |
b1950430 | 344 | qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); |
a19cbfb3 GH |
345 | } |
346 | ||
347 | /* called from spice server thread context only */ | |
348 | static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) | |
349 | { | |
a19cbfb3 GH |
350 | void *base = qxl->vga.vram_ptr; |
351 | intptr_t offset; | |
352 | ||
353 | offset = ptr - base; | |
354 | offset &= ~(TARGET_PAGE_SIZE-1); | |
355 | assert(offset < qxl->vga.vram_size); | |
b1950430 | 356 | qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
a19cbfb3 GH |
357 | } |
358 | ||
359 | /* can be called from spice server thread context */ | |
360 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl) | |
361 | { | |
b1950430 AK |
362 | ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
363 | ram_addr_t end = qxl->vga.vram_size; | |
364 | qxl_set_dirty(&qxl->vga.vram, addr, end); | |
a19cbfb3 GH |
365 | } |
366 | ||
367 | /* | |
368 | * keep track of some command state, for savevm/loadvm. | |
369 | * called from spice server thread context only | |
370 | */ | |
371 | static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) | |
372 | { | |
373 | switch (le32_to_cpu(ext->cmd.type)) { | |
374 | case QXL_CMD_SURFACE: | |
375 | { | |
376 | QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
377 | uint32_t id = le32_to_cpu(cmd->surface_id); | |
378 | PANIC_ON(id >= NUM_SURFACES); | |
14898cf6 | 379 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 GH |
380 | if (cmd->type == QXL_SURFACE_CMD_CREATE) { |
381 | qxl->guest_surfaces.cmds[id] = ext->cmd.data; | |
382 | qxl->guest_surfaces.count++; | |
383 | if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) | |
384 | qxl->guest_surfaces.max = qxl->guest_surfaces.count; | |
385 | } | |
386 | if (cmd->type == QXL_SURFACE_CMD_DESTROY) { | |
387 | qxl->guest_surfaces.cmds[id] = 0; | |
388 | qxl->guest_surfaces.count--; | |
389 | } | |
14898cf6 | 390 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
391 | break; |
392 | } | |
393 | case QXL_CMD_CURSOR: | |
394 | { | |
395 | QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
396 | if (cmd->type == QXL_CURSOR_SET) { | |
30f6da66 | 397 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 | 398 | qxl->guest_cursor = ext->cmd.data; |
30f6da66 | 399 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
400 | } |
401 | break; | |
402 | } | |
403 | } | |
404 | } | |
405 | ||
406 | /* spice display interface callbacks */ | |
407 | ||
408 | static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) | |
409 | { | |
410 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
411 | ||
412 | dprint(qxl, 1, "%s:\n", __FUNCTION__); | |
413 | qxl->ssd.worker = qxl_worker; | |
414 | } | |
415 | ||
416 | static void interface_set_compression_level(QXLInstance *sin, int level) | |
417 | { | |
418 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
419 | ||
420 | dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level); | |
421 | qxl->shadow_rom.compression_level = cpu_to_le32(level); | |
422 | qxl->rom->compression_level = cpu_to_le32(level); | |
423 | qxl_rom_set_dirty(qxl); | |
424 | } | |
425 | ||
426 | static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) | |
427 | { | |
428 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
429 | ||
430 | qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); | |
431 | qxl->rom->mm_clock = cpu_to_le32(mm_time); | |
432 | qxl_rom_set_dirty(qxl); | |
433 | } | |
434 | ||
435 | static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) | |
436 | { | |
437 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
438 | ||
439 | dprint(qxl, 1, "%s:\n", __FUNCTION__); | |
440 | info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; | |
441 | info->memslot_id_bits = MEMSLOT_SLOT_BITS; | |
442 | info->num_memslots = NUM_MEMSLOTS; | |
443 | info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; | |
444 | info->internal_groupslot_id = 0; | |
445 | info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; | |
446 | info->n_surfaces = NUM_SURFACES; | |
447 | } | |
448 | ||
5b77870c AL |
449 | static const char *qxl_mode_to_string(int mode) |
450 | { | |
451 | switch (mode) { | |
452 | case QXL_MODE_COMPAT: | |
453 | return "compat"; | |
454 | case QXL_MODE_NATIVE: | |
455 | return "native"; | |
456 | case QXL_MODE_UNDEFINED: | |
457 | return "undefined"; | |
458 | case QXL_MODE_VGA: | |
459 | return "vga"; | |
460 | } | |
461 | return "INVALID"; | |
462 | } | |
463 | ||
8b92e298 AL |
464 | static const char *io_port_to_string(uint32_t io_port) |
465 | { | |
466 | if (io_port >= QXL_IO_RANGE_SIZE) { | |
467 | return "out of range"; | |
468 | } | |
469 | static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { | |
470 | [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", | |
471 | [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", | |
472 | [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", | |
473 | [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", | |
474 | [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", | |
475 | [QXL_IO_RESET] = "QXL_IO_RESET", | |
476 | [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", | |
477 | [QXL_IO_LOG] = "QXL_IO_LOG", | |
478 | [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", | |
479 | [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", | |
480 | [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", | |
481 | [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", | |
482 | [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", | |
483 | [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", | |
484 | [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", | |
485 | [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", | |
8b92e298 AL |
486 | [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", |
487 | [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", | |
488 | [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", | |
489 | [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", | |
490 | [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", | |
491 | [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] | |
492 | = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", | |
493 | [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", | |
494 | [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", | |
8b92e298 AL |
495 | }; |
496 | return io_port_to_string[io_port]; | |
497 | } | |
498 | ||
a19cbfb3 GH |
499 | /* called from spice server thread context only */ |
500 | static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
501 | { | |
502 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
503 | SimpleSpiceUpdate *update; | |
504 | QXLCommandRing *ring; | |
505 | QXLCommand *cmd; | |
e0c64d08 | 506 | int notify, ret; |
a19cbfb3 GH |
507 | |
508 | switch (qxl->mode) { | |
509 | case QXL_MODE_VGA: | |
510 | dprint(qxl, 2, "%s: vga\n", __FUNCTION__); | |
e0c64d08 GH |
511 | ret = false; |
512 | qemu_mutex_lock(&qxl->ssd.lock); | |
513 | if (qxl->ssd.update != NULL) { | |
514 | update = qxl->ssd.update; | |
515 | qxl->ssd.update = NULL; | |
516 | *ext = update->ext; | |
517 | ret = true; | |
a19cbfb3 | 518 | } |
e0c64d08 | 519 | qemu_mutex_unlock(&qxl->ssd.lock); |
212496c9 | 520 | if (ret) { |
5b77870c | 521 | dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
212496c9 AL |
522 | qxl_log_command(qxl, "vga", ext); |
523 | } | |
e0c64d08 | 524 | return ret; |
a19cbfb3 GH |
525 | case QXL_MODE_COMPAT: |
526 | case QXL_MODE_NATIVE: | |
527 | case QXL_MODE_UNDEFINED: | |
5b77870c | 528 | dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
529 | ring = &qxl->ram->cmd_ring; |
530 | if (SPICE_RING_IS_EMPTY(ring)) { | |
531 | return false; | |
532 | } | |
5b77870c | 533 | dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
534 | SPICE_RING_CONS_ITEM(ring, cmd); |
535 | ext->cmd = *cmd; | |
536 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
537 | ext->flags = qxl->cmdflags; | |
538 | SPICE_RING_POP(ring, notify); | |
539 | qxl_ring_set_dirty(qxl); | |
540 | if (notify) { | |
541 | qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); | |
542 | } | |
543 | qxl->guest_primary.commands++; | |
544 | qxl_track_command(qxl, ext); | |
545 | qxl_log_command(qxl, "cmd", ext); | |
546 | return true; | |
547 | default: | |
548 | return false; | |
549 | } | |
550 | } | |
551 | ||
552 | /* called from spice server thread context only */ | |
553 | static int interface_req_cmd_notification(QXLInstance *sin) | |
554 | { | |
555 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
556 | int wait = 1; | |
557 | ||
558 | switch (qxl->mode) { | |
559 | case QXL_MODE_COMPAT: | |
560 | case QXL_MODE_NATIVE: | |
561 | case QXL_MODE_UNDEFINED: | |
562 | SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); | |
563 | qxl_ring_set_dirty(qxl); | |
564 | break; | |
565 | default: | |
566 | /* nothing */ | |
567 | break; | |
568 | } | |
569 | return wait; | |
570 | } | |
571 | ||
572 | /* called from spice server thread context only */ | |
573 | static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) | |
574 | { | |
575 | QXLReleaseRing *ring = &d->ram->release_ring; | |
576 | uint64_t *item; | |
577 | int notify; | |
578 | ||
579 | #define QXL_FREE_BUNCH_SIZE 32 | |
580 | ||
581 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
582 | /* ring full -- can't push */ | |
583 | return; | |
584 | } | |
585 | if (!flush && d->oom_running) { | |
586 | /* collect everything from oom handler before pushing */ | |
587 | return; | |
588 | } | |
589 | if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { | |
590 | /* collect a bit more before pushing */ | |
591 | return; | |
592 | } | |
593 | ||
594 | SPICE_RING_PUSH(ring, notify); | |
595 | dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n", | |
596 | d->num_free_res, notify ? "yes" : "no", | |
597 | ring->prod - ring->cons, ring->num_items, | |
598 | ring->prod, ring->cons); | |
599 | if (notify) { | |
600 | qxl_send_events(d, QXL_INTERRUPT_DISPLAY); | |
601 | } | |
602 | SPICE_RING_PROD_ITEM(ring, item); | |
603 | *item = 0; | |
604 | d->num_free_res = 0; | |
605 | d->last_release = NULL; | |
606 | qxl_ring_set_dirty(d); | |
607 | } | |
608 | ||
609 | /* called from spice server thread context only */ | |
610 | static void interface_release_resource(QXLInstance *sin, | |
611 | struct QXLReleaseInfoExt ext) | |
612 | { | |
613 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
614 | QXLReleaseRing *ring; | |
615 | uint64_t *item, id; | |
616 | ||
617 | if (ext.group_id == MEMSLOT_GROUP_HOST) { | |
618 | /* host group -> vga mode update request */ | |
f4a8a424 | 619 | qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); |
a19cbfb3 GH |
620 | return; |
621 | } | |
622 | ||
623 | /* | |
624 | * ext->info points into guest-visible memory | |
625 | * pci bar 0, $command.release_info | |
626 | */ | |
627 | ring = &qxl->ram->release_ring; | |
628 | SPICE_RING_PROD_ITEM(ring, item); | |
629 | if (*item == 0) { | |
630 | /* stick head into the ring */ | |
631 | id = ext.info->id; | |
632 | ext.info->next = 0; | |
633 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
634 | *item = id; | |
635 | qxl_ring_set_dirty(qxl); | |
636 | } else { | |
637 | /* append item to the list */ | |
638 | qxl->last_release->next = ext.info->id; | |
639 | qxl_ram_set_dirty(qxl, &qxl->last_release->next); | |
640 | ext.info->next = 0; | |
641 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
642 | } | |
643 | qxl->last_release = ext.info; | |
644 | qxl->num_free_res++; | |
645 | dprint(qxl, 3, "%4d\r", qxl->num_free_res); | |
646 | qxl_push_free_res(qxl, 0); | |
647 | } | |
648 | ||
649 | /* called from spice server thread context only */ | |
650 | static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
651 | { | |
652 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
653 | QXLCursorRing *ring; | |
654 | QXLCommand *cmd; | |
655 | int notify; | |
656 | ||
657 | switch (qxl->mode) { | |
658 | case QXL_MODE_COMPAT: | |
659 | case QXL_MODE_NATIVE: | |
660 | case QXL_MODE_UNDEFINED: | |
661 | ring = &qxl->ram->cursor_ring; | |
662 | if (SPICE_RING_IS_EMPTY(ring)) { | |
663 | return false; | |
664 | } | |
665 | SPICE_RING_CONS_ITEM(ring, cmd); | |
666 | ext->cmd = *cmd; | |
667 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
668 | ext->flags = qxl->cmdflags; | |
669 | SPICE_RING_POP(ring, notify); | |
670 | qxl_ring_set_dirty(qxl); | |
671 | if (notify) { | |
672 | qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); | |
673 | } | |
674 | qxl->guest_primary.commands++; | |
675 | qxl_track_command(qxl, ext); | |
676 | qxl_log_command(qxl, "csr", ext); | |
677 | if (qxl->id == 0) { | |
678 | qxl_render_cursor(qxl, ext); | |
679 | } | |
680 | return true; | |
681 | default: | |
682 | return false; | |
683 | } | |
684 | } | |
685 | ||
686 | /* called from spice server thread context only */ | |
687 | static int interface_req_cursor_notification(QXLInstance *sin) | |
688 | { | |
689 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
690 | int wait = 1; | |
691 | ||
692 | switch (qxl->mode) { | |
693 | case QXL_MODE_COMPAT: | |
694 | case QXL_MODE_NATIVE: | |
695 | case QXL_MODE_UNDEFINED: | |
696 | SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); | |
697 | qxl_ring_set_dirty(qxl); | |
698 | break; | |
699 | default: | |
700 | /* nothing */ | |
701 | break; | |
702 | } | |
703 | return wait; | |
704 | } | |
705 | ||
706 | /* called from spice server thread context */ | |
707 | static void interface_notify_update(QXLInstance *sin, uint32_t update_id) | |
708 | { | |
709 | fprintf(stderr, "%s: abort()\n", __FUNCTION__); | |
710 | abort(); | |
711 | } | |
712 | ||
713 | /* called from spice server thread context only */ | |
714 | static int interface_flush_resources(QXLInstance *sin) | |
715 | { | |
716 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
717 | int ret; | |
718 | ||
719 | dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res); | |
720 | ret = qxl->num_free_res; | |
721 | if (ret) { | |
722 | qxl_push_free_res(qxl, 1); | |
723 | } | |
724 | return ret; | |
725 | } | |
726 | ||
5ff4e36c AL |
727 | static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
728 | ||
5ff4e36c | 729 | /* called from spice server thread context only */ |
2e1a98c9 | 730 | static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
5ff4e36c | 731 | { |
5ff4e36c AL |
732 | uint32_t current_async; |
733 | ||
734 | qemu_mutex_lock(&qxl->async_lock); | |
735 | current_async = qxl->current_async; | |
736 | qxl->current_async = QXL_UNDEFINED_IO; | |
737 | qemu_mutex_unlock(&qxl->async_lock); | |
738 | ||
2e1a98c9 AL |
739 | dprint(qxl, 2, "async_complete: %d (%p) done\n", current_async, cookie); |
740 | if (!cookie) { | |
741 | fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); | |
742 | return; | |
743 | } | |
744 | if (cookie && current_async != cookie->io) { | |
745 | fprintf(stderr, | |
746 | "qxl: %s: error: current_async = %d != %ld = cookie->io\n", | |
747 | __func__, current_async, cookie->io); | |
748 | } | |
5ff4e36c | 749 | switch (current_async) { |
81fb6f15 AL |
750 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
751 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
752 | case QXL_IO_UPDATE_AREA_ASYNC: | |
753 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
754 | break; | |
5ff4e36c AL |
755 | case QXL_IO_CREATE_PRIMARY_ASYNC: |
756 | qxl_create_guest_primary_complete(qxl); | |
757 | break; | |
758 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
759 | qxl_spice_destroy_surfaces_complete(qxl); | |
760 | break; | |
761 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
2e1a98c9 | 762 | qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
5ff4e36c | 763 | break; |
81fb6f15 AL |
764 | default: |
765 | fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, | |
766 | current_async); | |
5ff4e36c AL |
767 | } |
768 | qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); | |
769 | } | |
770 | ||
81fb6f15 AL |
771 | /* called from spice server thread context only */ |
772 | static void interface_update_area_complete(QXLInstance *sin, | |
773 | uint32_t surface_id, | |
774 | QXLRect *dirty, uint32_t num_updated_rects) | |
775 | { | |
776 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
777 | int i; | |
778 | int qxl_i; | |
779 | ||
780 | qemu_mutex_lock(&qxl->ssd.lock); | |
781 | if (surface_id != 0 || !qxl->render_update_cookie_num) { | |
782 | qemu_mutex_unlock(&qxl->ssd.lock); | |
783 | return; | |
784 | } | |
785 | if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { | |
786 | /* | |
787 | * overflow - treat this as a full update. Not expected to be common. | |
788 | */ | |
789 | dprint(qxl, 1, "%s: overflow of dirty rects\n", __func__); | |
790 | qxl->guest_primary.resized = 1; | |
791 | } | |
792 | if (qxl->guest_primary.resized) { | |
793 | /* | |
794 | * Don't bother copying or scheduling the bh since we will flip | |
795 | * the whole area anyway on completion of the update_area async call | |
796 | */ | |
797 | qemu_mutex_unlock(&qxl->ssd.lock); | |
798 | return; | |
799 | } | |
800 | qxl_i = qxl->num_dirty_rects; | |
801 | for (i = 0; i < num_updated_rects; i++) { | |
802 | qxl->dirty[qxl_i++] = dirty[i]; | |
803 | } | |
804 | qxl->num_dirty_rects += num_updated_rects; | |
805 | dprint(qxl, 1, "%s: scheduling update_area_bh, #dirty %d\n", | |
806 | __func__, qxl->num_dirty_rects); | |
807 | qemu_bh_schedule(qxl->update_area_bh); | |
808 | qemu_mutex_unlock(&qxl->ssd.lock); | |
809 | } | |
810 | ||
2e1a98c9 AL |
811 | /* called from spice server thread context only */ |
812 | static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) | |
813 | { | |
814 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
815 | QXLCookie *cookie = (QXLCookie *)cookie_token; | |
816 | ||
817 | switch (cookie->type) { | |
818 | case QXL_COOKIE_TYPE_IO: | |
819 | interface_async_complete_io(qxl, cookie); | |
81fb6f15 AL |
820 | g_free(cookie); |
821 | break; | |
822 | case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: | |
823 | qxl_render_update_area_done(qxl, cookie); | |
2e1a98c9 AL |
824 | break; |
825 | default: | |
826 | fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", | |
827 | __func__, cookie->type); | |
81fb6f15 | 828 | g_free(cookie); |
2e1a98c9 | 829 | } |
2e1a98c9 AL |
830 | } |
831 | ||
a19cbfb3 GH |
832 | static const QXLInterface qxl_interface = { |
833 | .base.type = SPICE_INTERFACE_QXL, | |
834 | .base.description = "qxl gpu", | |
835 | .base.major_version = SPICE_INTERFACE_QXL_MAJOR, | |
836 | .base.minor_version = SPICE_INTERFACE_QXL_MINOR, | |
837 | ||
838 | .attache_worker = interface_attach_worker, | |
839 | .set_compression_level = interface_set_compression_level, | |
840 | .set_mm_time = interface_set_mm_time, | |
841 | .get_init_info = interface_get_init_info, | |
842 | ||
843 | /* the callbacks below are called from spice server thread context */ | |
844 | .get_command = interface_get_command, | |
845 | .req_cmd_notification = interface_req_cmd_notification, | |
846 | .release_resource = interface_release_resource, | |
847 | .get_cursor_command = interface_get_cursor_command, | |
848 | .req_cursor_notification = interface_req_cursor_notification, | |
849 | .notify_update = interface_notify_update, | |
850 | .flush_resources = interface_flush_resources, | |
5ff4e36c | 851 | .async_complete = interface_async_complete, |
81fb6f15 | 852 | .update_area_complete = interface_update_area_complete, |
a19cbfb3 GH |
853 | }; |
854 | ||
855 | static void qxl_enter_vga_mode(PCIQXLDevice *d) | |
856 | { | |
857 | if (d->mode == QXL_MODE_VGA) { | |
858 | return; | |
859 | } | |
860 | dprint(d, 1, "%s\n", __FUNCTION__); | |
861 | qemu_spice_create_host_primary(&d->ssd); | |
862 | d->mode = QXL_MODE_VGA; | |
863 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
864 | } | |
865 | ||
866 | static void qxl_exit_vga_mode(PCIQXLDevice *d) | |
867 | { | |
868 | if (d->mode != QXL_MODE_VGA) { | |
869 | return; | |
870 | } | |
871 | dprint(d, 1, "%s\n", __FUNCTION__); | |
5ff4e36c | 872 | qxl_destroy_primary(d, QXL_SYNC); |
a19cbfb3 GH |
873 | } |
874 | ||
40010aea | 875 | static void qxl_update_irq(PCIQXLDevice *d) |
a19cbfb3 GH |
876 | { |
877 | uint32_t pending = le32_to_cpu(d->ram->int_pending); | |
878 | uint32_t mask = le32_to_cpu(d->ram->int_mask); | |
879 | int level = !!(pending & mask); | |
880 | qemu_set_irq(d->pci.irq[0], level); | |
881 | qxl_ring_set_dirty(d); | |
882 | } | |
883 | ||
a19cbfb3 GH |
884 | static void qxl_check_state(PCIQXLDevice *d) |
885 | { | |
886 | QXLRam *ram = d->ram; | |
887 | ||
be48e995 YH |
888 | assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
889 | assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
a19cbfb3 GH |
890 | } |
891 | ||
892 | static void qxl_reset_state(PCIQXLDevice *d) | |
893 | { | |
a19cbfb3 GH |
894 | QXLRom *rom = d->rom; |
895 | ||
be48e995 | 896 | qxl_check_state(d); |
a19cbfb3 GH |
897 | d->shadow_rom.update_id = cpu_to_le32(0); |
898 | *rom = d->shadow_rom; | |
899 | qxl_rom_set_dirty(d); | |
900 | init_qxl_ram(d); | |
901 | d->num_free_res = 0; | |
902 | d->last_release = NULL; | |
903 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
904 | } | |
905 | ||
906 | static void qxl_soft_reset(PCIQXLDevice *d) | |
907 | { | |
908 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
909 | qxl_check_state(d); | |
910 | ||
911 | if (d->id == 0) { | |
912 | qxl_enter_vga_mode(d); | |
913 | } else { | |
914 | d->mode = QXL_MODE_UNDEFINED; | |
915 | } | |
916 | } | |
917 | ||
918 | static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) | |
919 | { | |
920 | dprint(d, 1, "%s: start%s\n", __FUNCTION__, | |
921 | loadvm ? " (loadvm)" : ""); | |
922 | ||
aee32bf3 GH |
923 | qxl_spice_reset_cursor(d); |
924 | qxl_spice_reset_image_cache(d); | |
a19cbfb3 GH |
925 | qxl_reset_surfaces(d); |
926 | qxl_reset_memslots(d); | |
927 | ||
928 | /* pre loadvm reset must not touch QXLRam. This lives in | |
929 | * device memory, is migrated together with RAM and thus | |
930 | * already loaded at this point */ | |
931 | if (!loadvm) { | |
932 | qxl_reset_state(d); | |
933 | } | |
934 | qemu_spice_create_host_memslot(&d->ssd); | |
935 | qxl_soft_reset(d); | |
936 | ||
937 | dprint(d, 1, "%s: done\n", __FUNCTION__); | |
938 | } | |
939 | ||
940 | static void qxl_reset_handler(DeviceState *dev) | |
941 | { | |
942 | PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); | |
943 | qxl_hard_reset(d, 0); | |
944 | } | |
945 | ||
946 | static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
947 | { | |
948 | VGACommonState *vga = opaque; | |
949 | PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); | |
950 | ||
951 | if (qxl->mode != QXL_MODE_VGA) { | |
952 | dprint(qxl, 1, "%s\n", __FUNCTION__); | |
5ff4e36c | 953 | qxl_destroy_primary(qxl, QXL_SYNC); |
a19cbfb3 GH |
954 | qxl_soft_reset(qxl); |
955 | } | |
956 | vga_ioport_write(opaque, addr, val); | |
957 | } | |
958 | ||
f67ab77a GH |
959 | static const MemoryRegionPortio qxl_vga_portio_list[] = { |
960 | { 0x04, 2, 1, .read = vga_ioport_read, | |
961 | .write = qxl_vga_ioport_write }, /* 3b4 */ | |
962 | { 0x0a, 1, 1, .read = vga_ioport_read, | |
963 | .write = qxl_vga_ioport_write }, /* 3ba */ | |
964 | { 0x10, 16, 1, .read = vga_ioport_read, | |
965 | .write = qxl_vga_ioport_write }, /* 3c0 */ | |
966 | { 0x24, 2, 1, .read = vga_ioport_read, | |
967 | .write = qxl_vga_ioport_write }, /* 3d4 */ | |
968 | { 0x2a, 1, 1, .read = vga_ioport_read, | |
969 | .write = qxl_vga_ioport_write }, /* 3da */ | |
970 | PORTIO_END_OF_LIST(), | |
971 | }; | |
972 | ||
5ff4e36c AL |
973 | static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
974 | qxl_async_io async) | |
a19cbfb3 GH |
975 | { |
976 | static const int regions[] = { | |
977 | QXL_RAM_RANGE_INDEX, | |
978 | QXL_VRAM_RANGE_INDEX, | |
979 | }; | |
980 | uint64_t guest_start; | |
981 | uint64_t guest_end; | |
982 | int pci_region; | |
983 | pcibus_t pci_start; | |
984 | pcibus_t pci_end; | |
985 | intptr_t virt_start; | |
986 | QXLDevMemSlot memslot; | |
987 | int i; | |
988 | ||
989 | guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); | |
990 | guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); | |
991 | ||
992 | dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n", | |
993 | __FUNCTION__, slot_id, | |
994 | guest_start, guest_end); | |
995 | ||
996 | PANIC_ON(slot_id >= NUM_MEMSLOTS); | |
997 | PANIC_ON(guest_start > guest_end); | |
998 | ||
999 | for (i = 0; i < ARRAY_SIZE(regions); i++) { | |
1000 | pci_region = regions[i]; | |
1001 | pci_start = d->pci.io_regions[pci_region].addr; | |
1002 | pci_end = pci_start + d->pci.io_regions[pci_region].size; | |
1003 | /* mapped? */ | |
1004 | if (pci_start == -1) { | |
1005 | continue; | |
1006 | } | |
1007 | /* start address in range ? */ | |
1008 | if (guest_start < pci_start || guest_start > pci_end) { | |
1009 | continue; | |
1010 | } | |
1011 | /* end address in range ? */ | |
1012 | if (guest_end > pci_end) { | |
1013 | continue; | |
1014 | } | |
1015 | /* passed */ | |
1016 | break; | |
1017 | } | |
1018 | PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */ | |
1019 | ||
1020 | switch (pci_region) { | |
1021 | case QXL_RAM_RANGE_INDEX: | |
b1950430 | 1022 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
a19cbfb3 GH |
1023 | break; |
1024 | case QXL_VRAM_RANGE_INDEX: | |
b1950430 | 1025 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
a19cbfb3 GH |
1026 | break; |
1027 | default: | |
1028 | /* should not happen */ | |
1029 | abort(); | |
1030 | } | |
1031 | ||
1032 | memslot.slot_id = slot_id; | |
1033 | memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ | |
1034 | memslot.virt_start = virt_start + (guest_start - pci_start); | |
1035 | memslot.virt_end = virt_start + (guest_end - pci_start); | |
1036 | memslot.addr_delta = memslot.virt_start - delta; | |
1037 | memslot.generation = d->rom->slot_generation = 0; | |
1038 | qxl_rom_set_dirty(d); | |
1039 | ||
a680f7e7 | 1040 | dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n", |
a19cbfb3 GH |
1041 | __FUNCTION__, memslot.slot_id, |
1042 | memslot.virt_start, memslot.virt_end); | |
1043 | ||
5ff4e36c | 1044 | qemu_spice_add_memslot(&d->ssd, &memslot, async); |
a19cbfb3 GH |
1045 | d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; |
1046 | d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; | |
1047 | d->guest_slots[slot_id].delta = delta; | |
1048 | d->guest_slots[slot_id].active = 1; | |
1049 | } | |
1050 | ||
1051 | static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) | |
1052 | { | |
1053 | dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id); | |
5c59d118 | 1054 | qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
a19cbfb3 GH |
1055 | d->guest_slots[slot_id].active = 0; |
1056 | } | |
1057 | ||
1058 | static void qxl_reset_memslots(PCIQXLDevice *d) | |
1059 | { | |
1060 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
aee32bf3 | 1061 | qxl_spice_reset_memslots(d); |
a19cbfb3 GH |
1062 | memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
1063 | } | |
1064 | ||
1065 | static void qxl_reset_surfaces(PCIQXLDevice *d) | |
1066 | { | |
1067 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
1068 | d->mode = QXL_MODE_UNDEFINED; | |
5ff4e36c | 1069 | qxl_spice_destroy_surfaces(d, QXL_SYNC); |
a19cbfb3 GH |
1070 | } |
1071 | ||
e25139b3 | 1072 | /* can be also called from spice server thread context */ |
a19cbfb3 GH |
1073 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
1074 | { | |
1075 | uint64_t phys = le64_to_cpu(pqxl); | |
1076 | uint32_t slot = (phys >> (64 - 8)) & 0xff; | |
1077 | uint64_t offset = phys & 0xffffffffffff; | |
1078 | ||
1079 | switch (group_id) { | |
1080 | case MEMSLOT_GROUP_HOST: | |
f4a8a424 | 1081 | return (void *)(intptr_t)offset; |
a19cbfb3 | 1082 | case MEMSLOT_GROUP_GUEST: |
6b7332eb | 1083 | PANIC_ON(slot >= NUM_MEMSLOTS); |
a19cbfb3 GH |
1084 | PANIC_ON(!qxl->guest_slots[slot].active); |
1085 | PANIC_ON(offset < qxl->guest_slots[slot].delta); | |
1086 | offset -= qxl->guest_slots[slot].delta; | |
1087 | PANIC_ON(offset > qxl->guest_slots[slot].size) | |
1088 | return qxl->guest_slots[slot].ptr + offset; | |
1089 | default: | |
1090 | PANIC_ON(1); | |
1091 | } | |
1092 | } | |
1093 | ||
5ff4e36c AL |
1094 | static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
1095 | { | |
1096 | /* for local rendering */ | |
1097 | qxl_render_resize(qxl); | |
1098 | } | |
1099 | ||
1100 | static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, | |
1101 | qxl_async_io async) | |
a19cbfb3 GH |
1102 | { |
1103 | QXLDevSurfaceCreate surface; | |
1104 | QXLSurfaceCreate *sc = &qxl->guest_primary.surface; | |
1105 | ||
1106 | assert(qxl->mode != QXL_MODE_NATIVE); | |
1107 | qxl_exit_vga_mode(qxl); | |
1108 | ||
1109 | dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__, | |
1110 | le32_to_cpu(sc->width), le32_to_cpu(sc->height)); | |
1111 | ||
1112 | surface.format = le32_to_cpu(sc->format); | |
1113 | surface.height = le32_to_cpu(sc->height); | |
1114 | surface.mem = le64_to_cpu(sc->mem); | |
1115 | surface.position = le32_to_cpu(sc->position); | |
1116 | surface.stride = le32_to_cpu(sc->stride); | |
1117 | surface.width = le32_to_cpu(sc->width); | |
1118 | surface.type = le32_to_cpu(sc->type); | |
1119 | surface.flags = le32_to_cpu(sc->flags); | |
1120 | ||
1121 | surface.mouse_mode = true; | |
1122 | surface.group_id = MEMSLOT_GROUP_GUEST; | |
1123 | if (loadvm) { | |
1124 | surface.flags |= QXL_SURF_FLAG_KEEP_DATA; | |
1125 | } | |
1126 | ||
1127 | qxl->mode = QXL_MODE_NATIVE; | |
1128 | qxl->cmdflags = 0; | |
5ff4e36c | 1129 | qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); |
a19cbfb3 | 1130 | |
5ff4e36c AL |
1131 | if (async == QXL_SYNC) { |
1132 | qxl_create_guest_primary_complete(qxl); | |
1133 | } | |
a19cbfb3 GH |
1134 | } |
1135 | ||
5ff4e36c AL |
1136 | /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or |
1137 | * done (in QXL_SYNC case), 0 otherwise. */ | |
1138 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) | |
a19cbfb3 GH |
1139 | { |
1140 | if (d->mode == QXL_MODE_UNDEFINED) { | |
5ff4e36c | 1141 | return 0; |
a19cbfb3 | 1142 | } |
a19cbfb3 | 1143 | dprint(d, 1, "%s\n", __FUNCTION__); |
a19cbfb3 | 1144 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1145 | qemu_spice_destroy_primary_surface(&d->ssd, 0, async); |
30f6da66 | 1146 | qxl_spice_reset_cursor(d); |
5ff4e36c | 1147 | return 1; |
a19cbfb3 GH |
1148 | } |
1149 | ||
1150 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) | |
1151 | { | |
1152 | pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1153 | pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; | |
1154 | QXLMode *mode = d->modes->modes + modenr; | |
1155 | uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1156 | QXLMemSlot slot = { | |
1157 | .mem_start = start, | |
1158 | .mem_end = end | |
1159 | }; | |
1160 | QXLSurfaceCreate surface = { | |
1161 | .width = mode->x_res, | |
1162 | .height = mode->y_res, | |
1163 | .stride = -mode->x_res * 4, | |
1164 | .format = SPICE_SURFACE_FMT_32_xRGB, | |
1165 | .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, | |
1166 | .mouse_mode = true, | |
1167 | .mem = devmem + d->shadow_rom.draw_area_offset, | |
1168 | }; | |
1169 | ||
a680f7e7 PM |
1170 | dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n", |
1171 | __func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem); | |
a19cbfb3 GH |
1172 | if (!loadvm) { |
1173 | qxl_hard_reset(d, 0); | |
1174 | } | |
1175 | ||
1176 | d->guest_slots[0].slot = slot; | |
5ff4e36c | 1177 | qxl_add_memslot(d, 0, devmem, QXL_SYNC); |
a19cbfb3 GH |
1178 | |
1179 | d->guest_primary.surface = surface; | |
5ff4e36c | 1180 | qxl_create_guest_primary(d, 0, QXL_SYNC); |
a19cbfb3 GH |
1181 | |
1182 | d->mode = QXL_MODE_COMPAT; | |
1183 | d->cmdflags = QXL_COMMAND_FLAG_COMPAT; | |
1184 | #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */ | |
1185 | if (mode->bits == 16) { | |
1186 | d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; | |
1187 | } | |
1188 | #endif | |
1189 | d->shadow_rom.mode = cpu_to_le32(modenr); | |
1190 | d->rom->mode = cpu_to_le32(modenr); | |
1191 | qxl_rom_set_dirty(d); | |
1192 | } | |
1193 | ||
b1950430 AK |
1194 | static void ioport_write(void *opaque, target_phys_addr_t addr, |
1195 | uint64_t val, unsigned size) | |
a19cbfb3 GH |
1196 | { |
1197 | PCIQXLDevice *d = opaque; | |
b1950430 | 1198 | uint32_t io_port = addr; |
5ff4e36c | 1199 | qxl_async_io async = QXL_SYNC; |
5ff4e36c | 1200 | uint32_t orig_io_port = io_port; |
a19cbfb3 GH |
1201 | |
1202 | switch (io_port) { | |
1203 | case QXL_IO_RESET: | |
1204 | case QXL_IO_SET_MODE: | |
1205 | case QXL_IO_MEMSLOT_ADD: | |
1206 | case QXL_IO_MEMSLOT_DEL: | |
1207 | case QXL_IO_CREATE_PRIMARY: | |
81144d1a | 1208 | case QXL_IO_UPDATE_IRQ: |
a3d14054 | 1209 | case QXL_IO_LOG: |
5ff4e36c AL |
1210 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
1211 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
a19cbfb3 GH |
1212 | break; |
1213 | default: | |
e21a298a | 1214 | if (d->mode != QXL_MODE_VGA) { |
a19cbfb3 | 1215 | break; |
e21a298a | 1216 | } |
8b92e298 AL |
1217 | dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n", |
1218 | __func__, io_port, io_port_to_string(io_port)); | |
5ff4e36c AL |
1219 | /* be nice to buggy guest drivers */ |
1220 | if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && | |
1221 | io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) { | |
1222 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1223 | } | |
a19cbfb3 GH |
1224 | return; |
1225 | } | |
1226 | ||
5ff4e36c AL |
1227 | /* we change the io_port to avoid ifdeffery in the main switch */ |
1228 | orig_io_port = io_port; | |
1229 | switch (io_port) { | |
1230 | case QXL_IO_UPDATE_AREA_ASYNC: | |
1231 | io_port = QXL_IO_UPDATE_AREA; | |
1232 | goto async_common; | |
1233 | case QXL_IO_MEMSLOT_ADD_ASYNC: | |
1234 | io_port = QXL_IO_MEMSLOT_ADD; | |
1235 | goto async_common; | |
1236 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
1237 | io_port = QXL_IO_CREATE_PRIMARY; | |
1238 | goto async_common; | |
1239 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
1240 | io_port = QXL_IO_DESTROY_PRIMARY; | |
1241 | goto async_common; | |
1242 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
1243 | io_port = QXL_IO_DESTROY_SURFACE_WAIT; | |
1244 | goto async_common; | |
1245 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
1246 | io_port = QXL_IO_DESTROY_ALL_SURFACES; | |
3e16b9c5 AL |
1247 | goto async_common; |
1248 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
5ff4e36c AL |
1249 | async_common: |
1250 | async = QXL_ASYNC; | |
1251 | qemu_mutex_lock(&d->async_lock); | |
1252 | if (d->current_async != QXL_UNDEFINED_IO) { | |
1253 | qxl_guest_bug(d, "%d async started before last (%d) complete", | |
1254 | io_port, d->current_async); | |
1255 | qemu_mutex_unlock(&d->async_lock); | |
1256 | return; | |
1257 | } | |
1258 | d->current_async = orig_io_port; | |
1259 | qemu_mutex_unlock(&d->async_lock); | |
c5f3dabb | 1260 | dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val); |
5ff4e36c AL |
1261 | break; |
1262 | default: | |
1263 | break; | |
1264 | } | |
5ff4e36c | 1265 | |
a19cbfb3 GH |
1266 | switch (io_port) { |
1267 | case QXL_IO_UPDATE_AREA: | |
1268 | { | |
81fb6f15 | 1269 | QXLCookie *cookie = NULL; |
a19cbfb3 | 1270 | QXLRect update = d->ram->update_area; |
81fb6f15 AL |
1271 | |
1272 | if (async == QXL_ASYNC) { | |
1273 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
1274 | QXL_IO_UPDATE_AREA_ASYNC); | |
1275 | cookie->u.area = update; | |
1276 | } | |
aee32bf3 | 1277 | qxl_spice_update_area(d, d->ram->update_surface, |
81fb6f15 AL |
1278 | cookie ? &cookie->u.area : &update, |
1279 | NULL, 0, 0, async, cookie); | |
a19cbfb3 GH |
1280 | break; |
1281 | } | |
1282 | case QXL_IO_NOTIFY_CMD: | |
5c59d118 | 1283 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1284 | break; |
1285 | case QXL_IO_NOTIFY_CURSOR: | |
5c59d118 | 1286 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1287 | break; |
1288 | case QXL_IO_UPDATE_IRQ: | |
40010aea | 1289 | qxl_update_irq(d); |
a19cbfb3 GH |
1290 | break; |
1291 | case QXL_IO_NOTIFY_OOM: | |
a19cbfb3 GH |
1292 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { |
1293 | break; | |
1294 | } | |
1295 | d->oom_running = 1; | |
aee32bf3 | 1296 | qxl_spice_oom(d); |
a19cbfb3 GH |
1297 | d->oom_running = 0; |
1298 | break; | |
1299 | case QXL_IO_SET_MODE: | |
b1950430 | 1300 | dprint(d, 1, "QXL_SET_MODE %d\n", (int)val); |
a19cbfb3 GH |
1301 | qxl_set_mode(d, val, 0); |
1302 | break; | |
1303 | case QXL_IO_LOG: | |
1304 | if (d->guestdebug) { | |
a680f7e7 | 1305 | fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
6ebebb55 | 1306 | qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
a19cbfb3 GH |
1307 | } |
1308 | break; | |
1309 | case QXL_IO_RESET: | |
1310 | dprint(d, 1, "QXL_IO_RESET\n"); | |
1311 | qxl_hard_reset(d, 0); | |
1312 | break; | |
1313 | case QXL_IO_MEMSLOT_ADD: | |
2bce0400 GH |
1314 | if (val >= NUM_MEMSLOTS) { |
1315 | qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); | |
1316 | break; | |
1317 | } | |
1318 | if (d->guest_slots[val].active) { | |
1319 | qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active"); | |
1320 | break; | |
1321 | } | |
a19cbfb3 | 1322 | d->guest_slots[val].slot = d->ram->mem_slot; |
5ff4e36c | 1323 | qxl_add_memslot(d, val, 0, async); |
a19cbfb3 GH |
1324 | break; |
1325 | case QXL_IO_MEMSLOT_DEL: | |
2bce0400 GH |
1326 | if (val >= NUM_MEMSLOTS) { |
1327 | qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); | |
1328 | break; | |
1329 | } | |
a19cbfb3 GH |
1330 | qxl_del_memslot(d, val); |
1331 | break; | |
1332 | case QXL_IO_CREATE_PRIMARY: | |
2bce0400 | 1333 | if (val != 0) { |
5ff4e36c AL |
1334 | qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", |
1335 | async); | |
1336 | goto cancel_async; | |
2bce0400 | 1337 | } |
5ff4e36c | 1338 | dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async); |
a19cbfb3 | 1339 | d->guest_primary.surface = d->ram->create_surface; |
5ff4e36c | 1340 | qxl_create_guest_primary(d, 0, async); |
a19cbfb3 GH |
1341 | break; |
1342 | case QXL_IO_DESTROY_PRIMARY: | |
2bce0400 | 1343 | if (val != 0) { |
5ff4e36c AL |
1344 | qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", |
1345 | async); | |
1346 | goto cancel_async; | |
1347 | } | |
1348 | dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async, | |
1349 | qxl_mode_to_string(d->mode)); | |
1350 | if (!qxl_destroy_primary(d, async)) { | |
1351 | dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n", | |
1352 | qxl_mode_to_string(d->mode)); | |
1353 | goto cancel_async; | |
2bce0400 | 1354 | } |
a19cbfb3 GH |
1355 | break; |
1356 | case QXL_IO_DESTROY_SURFACE_WAIT: | |
5ff4e36c AL |
1357 | if (val >= NUM_SURFACES) { |
1358 | qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" | |
1359 | "%d >= NUM_SURFACES", async, val); | |
1360 | goto cancel_async; | |
1361 | } | |
1362 | qxl_spice_destroy_surface_wait(d, val, async); | |
a19cbfb3 | 1363 | break; |
3e16b9c5 AL |
1364 | case QXL_IO_FLUSH_RELEASE: { |
1365 | QXLReleaseRing *ring = &d->ram->release_ring; | |
1366 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
1367 | fprintf(stderr, | |
1368 | "ERROR: no flush, full release ring [p%d,%dc]\n", | |
1369 | ring->prod, ring->cons); | |
1370 | } | |
1371 | qxl_push_free_res(d, 1 /* flush */); | |
1372 | dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n", | |
1373 | qxl_mode_to_string(d->mode), d->guest_surfaces.count, | |
1374 | d->num_free_res, d->last_release); | |
1375 | break; | |
1376 | } | |
1377 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
c5f3dabb AL |
1378 | dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC" |
1379 | " (%"PRId64") (%s, s#=%d, res#=%d)\n", | |
3e16b9c5 AL |
1380 | val, qxl_mode_to_string(d->mode), d->guest_surfaces.count, |
1381 | d->num_free_res); | |
1382 | qxl_spice_flush_surfaces_async(d); | |
1383 | break; | |
a19cbfb3 | 1384 | case QXL_IO_DESTROY_ALL_SURFACES: |
5ff4e36c AL |
1385 | d->mode = QXL_MODE_UNDEFINED; |
1386 | qxl_spice_destroy_surfaces(d, async); | |
a19cbfb3 GH |
1387 | break; |
1388 | default: | |
1389 | fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port); | |
1390 | abort(); | |
1391 | } | |
5ff4e36c AL |
1392 | return; |
1393 | cancel_async: | |
5ff4e36c AL |
1394 | if (async) { |
1395 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1396 | qemu_mutex_lock(&d->async_lock); | |
1397 | d->current_async = QXL_UNDEFINED_IO; | |
1398 | qemu_mutex_unlock(&d->async_lock); | |
1399 | } | |
a19cbfb3 GH |
1400 | } |
1401 | ||
b1950430 AK |
1402 | static uint64_t ioport_read(void *opaque, target_phys_addr_t addr, |
1403 | unsigned size) | |
a19cbfb3 GH |
1404 | { |
1405 | PCIQXLDevice *d = opaque; | |
1406 | ||
1407 | dprint(d, 1, "%s: unexpected\n", __FUNCTION__); | |
1408 | return 0xff; | |
1409 | } | |
1410 | ||
b1950430 AK |
1411 | static const MemoryRegionOps qxl_io_ops = { |
1412 | .read = ioport_read, | |
1413 | .write = ioport_write, | |
1414 | .valid = { | |
1415 | .min_access_size = 1, | |
1416 | .max_access_size = 1, | |
1417 | }, | |
1418 | }; | |
a19cbfb3 GH |
1419 | |
1420 | static void pipe_read(void *opaque) | |
1421 | { | |
1422 | PCIQXLDevice *d = opaque; | |
1423 | char dummy; | |
1424 | int len; | |
1425 | ||
1426 | do { | |
1427 | len = read(d->pipe[0], &dummy, sizeof(dummy)); | |
1428 | } while (len == sizeof(dummy)); | |
40010aea | 1429 | qxl_update_irq(d); |
a19cbfb3 GH |
1430 | } |
1431 | ||
a19cbfb3 GH |
1432 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1433 | { | |
1434 | uint32_t old_pending; | |
1435 | uint32_t le_events = cpu_to_le32(events); | |
1436 | ||
1437 | assert(d->ssd.running); | |
1438 | old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); | |
1439 | if ((old_pending & le_events) == le_events) { | |
1440 | return; | |
1441 | } | |
691f5c7b | 1442 | if (qemu_thread_is_self(&d->main)) { |
40010aea | 1443 | qxl_update_irq(d); |
a19cbfb3 GH |
1444 | } else { |
1445 | if (write(d->pipe[1], d, 1) != 1) { | |
1446 | dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__); | |
1447 | } | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | static void init_pipe_signaling(PCIQXLDevice *d) | |
1452 | { | |
1453 | if (pipe(d->pipe) < 0) { | |
1454 | dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__); | |
1455 | return; | |
1456 | } | |
a19cbfb3 | 1457 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); |
a19cbfb3 GH |
1458 | fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); |
1459 | fcntl(d->pipe[0], F_SETOWN, getpid()); | |
1460 | ||
691f5c7b | 1461 | qemu_thread_get_self(&d->main); |
a19cbfb3 GH |
1462 | qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); |
1463 | } | |
1464 | ||
1465 | /* graphics console */ | |
1466 | ||
1467 | static void qxl_hw_update(void *opaque) | |
1468 | { | |
1469 | PCIQXLDevice *qxl = opaque; | |
1470 | VGACommonState *vga = &qxl->vga; | |
1471 | ||
1472 | switch (qxl->mode) { | |
1473 | case QXL_MODE_VGA: | |
1474 | vga->update(vga); | |
1475 | break; | |
1476 | case QXL_MODE_COMPAT: | |
1477 | case QXL_MODE_NATIVE: | |
1478 | qxl_render_update(qxl); | |
1479 | break; | |
1480 | default: | |
1481 | break; | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | static void qxl_hw_invalidate(void *opaque) | |
1486 | { | |
1487 | PCIQXLDevice *qxl = opaque; | |
1488 | VGACommonState *vga = &qxl->vga; | |
1489 | ||
1490 | vga->invalidate(vga); | |
1491 | } | |
1492 | ||
45efb161 | 1493 | static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch) |
a19cbfb3 GH |
1494 | { |
1495 | PCIQXLDevice *qxl = opaque; | |
1496 | VGACommonState *vga = &qxl->vga; | |
1497 | ||
1498 | switch (qxl->mode) { | |
1499 | case QXL_MODE_COMPAT: | |
1500 | case QXL_MODE_NATIVE: | |
1501 | qxl_render_update(qxl); | |
1502 | ppm_save(filename, qxl->ssd.ds->surface); | |
1503 | break; | |
1504 | case QXL_MODE_VGA: | |
45efb161 | 1505 | vga->screen_dump(vga, filename, cswitch); |
a19cbfb3 GH |
1506 | break; |
1507 | default: | |
1508 | break; | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) | |
1513 | { | |
1514 | PCIQXLDevice *qxl = opaque; | |
1515 | VGACommonState *vga = &qxl->vga; | |
1516 | ||
1517 | if (qxl->mode == QXL_MODE_VGA) { | |
1518 | vga->text_update(vga, chardata); | |
1519 | return; | |
1520 | } | |
1521 | } | |
1522 | ||
e25139b3 YH |
1523 | static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
1524 | { | |
1525 | intptr_t vram_start; | |
1526 | int i; | |
1527 | ||
2aa9e85c | 1528 | if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { |
e25139b3 YH |
1529 | return; |
1530 | } | |
1531 | ||
1532 | /* dirty the primary surface */ | |
1533 | qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, | |
1534 | qxl->shadow_rom.surface0_area_size); | |
1535 | ||
1536 | vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); | |
1537 | ||
1538 | /* dirty the off-screen surfaces */ | |
1539 | for (i = 0; i < NUM_SURFACES; i++) { | |
1540 | QXLSurfaceCmd *cmd; | |
1541 | intptr_t surface_offset; | |
1542 | int surface_size; | |
1543 | ||
1544 | if (qxl->guest_surfaces.cmds[i] == 0) { | |
1545 | continue; | |
1546 | } | |
1547 | ||
1548 | cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], | |
1549 | MEMSLOT_GROUP_GUEST); | |
1550 | assert(cmd->type == QXL_SURFACE_CMD_CREATE); | |
1551 | surface_offset = (intptr_t)qxl_phys2virt(qxl, | |
1552 | cmd->u.surface_create.data, | |
1553 | MEMSLOT_GROUP_GUEST); | |
1554 | surface_offset -= vram_start; | |
1555 | surface_size = cmd->u.surface_create.height * | |
1556 | abs(cmd->u.surface_create.stride); | |
1557 | dprint(qxl, 3, "%s: dirty surface %d, offset %d, size %d\n", __func__, | |
1558 | i, (int)surface_offset, surface_size); | |
1559 | qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); | |
1560 | } | |
1561 | } | |
1562 | ||
1dfb4dd9 LC |
1563 | static void qxl_vm_change_state_handler(void *opaque, int running, |
1564 | RunState state) | |
a19cbfb3 GH |
1565 | { |
1566 | PCIQXLDevice *qxl = opaque; | |
1dfb4dd9 | 1567 | qemu_spice_vm_change_state_handler(&qxl->ssd, running, state); |
a19cbfb3 | 1568 | |
efbf2950 YH |
1569 | if (running) { |
1570 | /* | |
1571 | * if qxl_send_events was called from spice server context before | |
40010aea | 1572 | * migration ended, qxl_update_irq for these events might not have been |
efbf2950 YH |
1573 | * called |
1574 | */ | |
40010aea | 1575 | qxl_update_irq(qxl); |
e25139b3 YH |
1576 | } else { |
1577 | /* make sure surfaces are saved before migration */ | |
1578 | qxl_dirty_surfaces(qxl); | |
a19cbfb3 GH |
1579 | } |
1580 | } | |
1581 | ||
1582 | /* display change listener */ | |
1583 | ||
1584 | static void display_update(struct DisplayState *ds, int x, int y, int w, int h) | |
1585 | { | |
1586 | if (qxl0->mode == QXL_MODE_VGA) { | |
1587 | qemu_spice_display_update(&qxl0->ssd, x, y, w, h); | |
1588 | } | |
1589 | } | |
1590 | ||
1591 | static void display_resize(struct DisplayState *ds) | |
1592 | { | |
1593 | if (qxl0->mode == QXL_MODE_VGA) { | |
1594 | qemu_spice_display_resize(&qxl0->ssd); | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | static void display_refresh(struct DisplayState *ds) | |
1599 | { | |
1600 | if (qxl0->mode == QXL_MODE_VGA) { | |
1601 | qemu_spice_display_refresh(&qxl0->ssd); | |
bb5a8cd5 AL |
1602 | } else { |
1603 | qemu_mutex_lock(&qxl0->ssd.lock); | |
1604 | qemu_spice_cursor_refresh_unlocked(&qxl0->ssd); | |
1605 | qemu_mutex_unlock(&qxl0->ssd.lock); | |
a19cbfb3 GH |
1606 | } |
1607 | } | |
1608 | ||
1609 | static DisplayChangeListener display_listener = { | |
1610 | .dpy_update = display_update, | |
1611 | .dpy_resize = display_resize, | |
1612 | .dpy_refresh = display_refresh, | |
1613 | }; | |
1614 | ||
a974192c GH |
1615 | static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb) |
1616 | { | |
1617 | /* vga ram (bar 0) */ | |
017438ee GH |
1618 | if (qxl->ram_size_mb != -1) { |
1619 | qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; | |
1620 | } | |
a974192c GH |
1621 | if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) { |
1622 | qxl->vga.vram_size = ram_min_mb * 1024 * 1024; | |
1623 | } | |
1624 | ||
1625 | /* vram (surfaces, bar 1) */ | |
017438ee GH |
1626 | if (qxl->vram_size_mb != -1) { |
1627 | qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; | |
1628 | } | |
a974192c GH |
1629 | if (qxl->vram_size < 4096) { |
1630 | qxl->vram_size = 4096; | |
1631 | } | |
1632 | if (qxl->revision == 1) { | |
1633 | qxl->vram_size = 4096; | |
1634 | } | |
1635 | ||
1636 | qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); | |
1637 | qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); | |
1638 | } | |
1639 | ||
a19cbfb3 GH |
1640 | static int qxl_init_common(PCIQXLDevice *qxl) |
1641 | { | |
1642 | uint8_t* config = qxl->pci.config; | |
a19cbfb3 GH |
1643 | uint32_t pci_device_rev; |
1644 | uint32_t io_size; | |
1645 | ||
1646 | qxl->mode = QXL_MODE_UNDEFINED; | |
1647 | qxl->generation = 1; | |
1648 | qxl->num_memslots = NUM_MEMSLOTS; | |
1649 | qxl->num_surfaces = NUM_SURFACES; | |
14898cf6 | 1650 | qemu_mutex_init(&qxl->track_lock); |
5ff4e36c AL |
1651 | qemu_mutex_init(&qxl->async_lock); |
1652 | qxl->current_async = QXL_UNDEFINED_IO; | |
a19cbfb3 GH |
1653 | |
1654 | switch (qxl->revision) { | |
1655 | case 1: /* spice 0.4 -- qxl-1 */ | |
a19cbfb3 GH |
1656 | pci_device_rev = QXL_REVISION_STABLE_V04; |
1657 | break; | |
1658 | case 2: /* spice 0.6 -- qxl-2 */ | |
a19cbfb3 GH |
1659 | pci_device_rev = QXL_REVISION_STABLE_V06; |
1660 | break; | |
9197a7c8 | 1661 | case 3: /* qxl-3 */ |
9197a7c8 GH |
1662 | default: |
1663 | pci_device_rev = QXL_DEFAULT_REVISION; | |
1664 | break; | |
a19cbfb3 GH |
1665 | } |
1666 | ||
a19cbfb3 GH |
1667 | pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1668 | pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); | |
1669 | ||
1670 | qxl->rom_size = qxl_rom_size(); | |
c5705a77 AK |
1671 | memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); |
1672 | vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); | |
a19cbfb3 GH |
1673 | init_qxl_rom(qxl); |
1674 | init_qxl_ram(qxl); | |
1675 | ||
c5705a77 AK |
1676 | memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); |
1677 | vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); | |
a19cbfb3 GH |
1678 | |
1679 | io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); | |
1680 | if (qxl->revision == 1) { | |
1681 | io_size = 8; | |
1682 | } | |
1683 | ||
b1950430 AK |
1684 | memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
1685 | "qxl-ioports", io_size); | |
1686 | if (qxl->id == 0) { | |
1687 | vga_dirty_log_start(&qxl->vga); | |
1688 | } | |
1689 | ||
1690 | ||
e824b2cc AK |
1691 | pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
1692 | PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); | |
a19cbfb3 | 1693 | |
e824b2cc AK |
1694 | pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
1695 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); | |
a19cbfb3 | 1696 | |
e824b2cc AK |
1697 | pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
1698 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); | |
a19cbfb3 | 1699 | |
e824b2cc AK |
1700 | pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
1701 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar); | |
a19cbfb3 GH |
1702 | |
1703 | qxl->ssd.qxl.base.sif = &qxl_interface.base; | |
1704 | qxl->ssd.qxl.id = qxl->id; | |
1705 | qemu_spice_add_interface(&qxl->ssd.qxl.base); | |
1706 | qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); | |
1707 | ||
1708 | init_pipe_signaling(qxl); | |
1709 | qxl_reset_state(qxl); | |
1710 | ||
81fb6f15 AL |
1711 | qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
1712 | ||
a19cbfb3 GH |
1713 | return 0; |
1714 | } | |
1715 | ||
1716 | static int qxl_init_primary(PCIDevice *dev) | |
1717 | { | |
1718 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
1719 | VGACommonState *vga = &qxl->vga; | |
f67ab77a | 1720 | PortioList *qxl_vga_port_list = g_new(PortioList, 1); |
a19cbfb3 GH |
1721 | |
1722 | qxl->id = 0; | |
a974192c GH |
1723 | qxl_init_ramsize(qxl, 32); |
1724 | vga_common_init(vga, qxl->vga.vram_size); | |
0a039dc7 | 1725 | vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); |
f67ab77a GH |
1726 | portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); |
1727 | portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); | |
a19cbfb3 GH |
1728 | |
1729 | vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, | |
1730 | qxl_hw_screen_dump, qxl_hw_text_update, qxl); | |
a963f876 | 1731 | qemu_spice_display_init_common(&qxl->ssd, vga->ds); |
a19cbfb3 GH |
1732 | |
1733 | qxl0 = qxl; | |
1734 | register_displaychangelistener(vga->ds, &display_listener); | |
1735 | ||
a19cbfb3 GH |
1736 | return qxl_init_common(qxl); |
1737 | } | |
1738 | ||
1739 | static int qxl_init_secondary(PCIDevice *dev) | |
1740 | { | |
1741 | static int device_id = 1; | |
1742 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
a19cbfb3 GH |
1743 | |
1744 | qxl->id = device_id++; | |
a974192c | 1745 | qxl_init_ramsize(qxl, 16); |
c5705a77 AK |
1746 | memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); |
1747 | vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); | |
b1950430 | 1748 | qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
a19cbfb3 | 1749 | |
a19cbfb3 GH |
1750 | return qxl_init_common(qxl); |
1751 | } | |
1752 | ||
1753 | static void qxl_pre_save(void *opaque) | |
1754 | { | |
1755 | PCIQXLDevice* d = opaque; | |
1756 | uint8_t *ram_start = d->vga.vram_ptr; | |
1757 | ||
1758 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
1759 | if (d->last_release == NULL) { | |
1760 | d->last_release_offset = 0; | |
1761 | } else { | |
1762 | d->last_release_offset = (uint8_t *)d->last_release - ram_start; | |
1763 | } | |
1764 | assert(d->last_release_offset < d->vga.vram_size); | |
1765 | } | |
1766 | ||
1767 | static int qxl_pre_load(void *opaque) | |
1768 | { | |
1769 | PCIQXLDevice* d = opaque; | |
1770 | ||
1771 | dprint(d, 1, "%s: start\n", __FUNCTION__); | |
1772 | qxl_hard_reset(d, 1); | |
1773 | qxl_exit_vga_mode(d); | |
1774 | dprint(d, 1, "%s: done\n", __FUNCTION__); | |
1775 | return 0; | |
1776 | } | |
1777 | ||
54825d2e AL |
1778 | static void qxl_create_memslots(PCIQXLDevice *d) |
1779 | { | |
1780 | int i; | |
1781 | ||
1782 | for (i = 0; i < NUM_MEMSLOTS; i++) { | |
1783 | if (!d->guest_slots[i].active) { | |
1784 | continue; | |
1785 | } | |
1786 | dprint(d, 1, "%s: restoring guest slot %d\n", __func__, i); | |
1787 | qxl_add_memslot(d, i, 0, QXL_SYNC); | |
1788 | } | |
1789 | } | |
1790 | ||
a19cbfb3 GH |
1791 | static int qxl_post_load(void *opaque, int version) |
1792 | { | |
1793 | PCIQXLDevice* d = opaque; | |
1794 | uint8_t *ram_start = d->vga.vram_ptr; | |
1795 | QXLCommandExt *cmds; | |
54825d2e | 1796 | int in, out, newmode; |
a19cbfb3 GH |
1797 | |
1798 | dprint(d, 1, "%s: start\n", __FUNCTION__); | |
1799 | ||
1800 | assert(d->last_release_offset < d->vga.vram_size); | |
1801 | if (d->last_release_offset == 0) { | |
1802 | d->last_release = NULL; | |
1803 | } else { | |
1804 | d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); | |
1805 | } | |
1806 | ||
1807 | d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); | |
1808 | ||
5b77870c AL |
1809 | dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__, |
1810 | qxl_mode_to_string(d->mode)); | |
a19cbfb3 GH |
1811 | newmode = d->mode; |
1812 | d->mode = QXL_MODE_UNDEFINED; | |
54825d2e | 1813 | |
a19cbfb3 GH |
1814 | switch (newmode) { |
1815 | case QXL_MODE_UNDEFINED: | |
1816 | break; | |
1817 | case QXL_MODE_VGA: | |
54825d2e | 1818 | qxl_create_memslots(d); |
a19cbfb3 GH |
1819 | qxl_enter_vga_mode(d); |
1820 | break; | |
1821 | case QXL_MODE_NATIVE: | |
54825d2e | 1822 | qxl_create_memslots(d); |
5ff4e36c | 1823 | qxl_create_guest_primary(d, 1, QXL_SYNC); |
a19cbfb3 GH |
1824 | |
1825 | /* replay surface-create and cursor-set commands */ | |
7267c094 | 1826 | cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1)); |
a19cbfb3 GH |
1827 | for (in = 0, out = 0; in < NUM_SURFACES; in++) { |
1828 | if (d->guest_surfaces.cmds[in] == 0) { | |
1829 | continue; | |
1830 | } | |
1831 | cmds[out].cmd.data = d->guest_surfaces.cmds[in]; | |
1832 | cmds[out].cmd.type = QXL_CMD_SURFACE; | |
1833 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
1834 | out++; | |
1835 | } | |
30f6da66 YH |
1836 | if (d->guest_cursor) { |
1837 | cmds[out].cmd.data = d->guest_cursor; | |
1838 | cmds[out].cmd.type = QXL_CMD_CURSOR; | |
1839 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
1840 | out++; | |
1841 | } | |
aee32bf3 | 1842 | qxl_spice_loadvm_commands(d, cmds, out); |
7267c094 | 1843 | g_free(cmds); |
a19cbfb3 GH |
1844 | |
1845 | break; | |
1846 | case QXL_MODE_COMPAT: | |
54825d2e AL |
1847 | /* note: no need to call qxl_create_memslots, qxl_set_mode |
1848 | * creates the mem slot. */ | |
a19cbfb3 GH |
1849 | qxl_set_mode(d, d->shadow_rom.mode, 1); |
1850 | break; | |
1851 | } | |
1852 | dprint(d, 1, "%s: done\n", __FUNCTION__); | |
1853 | ||
a19cbfb3 GH |
1854 | return 0; |
1855 | } | |
1856 | ||
b67737a6 | 1857 | #define QXL_SAVE_VERSION 21 |
a19cbfb3 GH |
1858 | |
1859 | static VMStateDescription qxl_memslot = { | |
1860 | .name = "qxl-memslot", | |
1861 | .version_id = QXL_SAVE_VERSION, | |
1862 | .minimum_version_id = QXL_SAVE_VERSION, | |
1863 | .fields = (VMStateField[]) { | |
1864 | VMSTATE_UINT64(slot.mem_start, struct guest_slots), | |
1865 | VMSTATE_UINT64(slot.mem_end, struct guest_slots), | |
1866 | VMSTATE_UINT32(active, struct guest_slots), | |
1867 | VMSTATE_END_OF_LIST() | |
1868 | } | |
1869 | }; | |
1870 | ||
1871 | static VMStateDescription qxl_surface = { | |
1872 | .name = "qxl-surface", | |
1873 | .version_id = QXL_SAVE_VERSION, | |
1874 | .minimum_version_id = QXL_SAVE_VERSION, | |
1875 | .fields = (VMStateField[]) { | |
1876 | VMSTATE_UINT32(width, QXLSurfaceCreate), | |
1877 | VMSTATE_UINT32(height, QXLSurfaceCreate), | |
1878 | VMSTATE_INT32(stride, QXLSurfaceCreate), | |
1879 | VMSTATE_UINT32(format, QXLSurfaceCreate), | |
1880 | VMSTATE_UINT32(position, QXLSurfaceCreate), | |
1881 | VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), | |
1882 | VMSTATE_UINT32(flags, QXLSurfaceCreate), | |
1883 | VMSTATE_UINT32(type, QXLSurfaceCreate), | |
1884 | VMSTATE_UINT64(mem, QXLSurfaceCreate), | |
1885 | VMSTATE_END_OF_LIST() | |
1886 | } | |
1887 | }; | |
1888 | ||
a19cbfb3 GH |
1889 | static VMStateDescription qxl_vmstate = { |
1890 | .name = "qxl", | |
1891 | .version_id = QXL_SAVE_VERSION, | |
1892 | .minimum_version_id = QXL_SAVE_VERSION, | |
1893 | .pre_save = qxl_pre_save, | |
1894 | .pre_load = qxl_pre_load, | |
1895 | .post_load = qxl_post_load, | |
1896 | .fields = (VMStateField []) { | |
1897 | VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), | |
1898 | VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), | |
1899 | VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), | |
1900 | VMSTATE_UINT32(num_free_res, PCIQXLDevice), | |
1901 | VMSTATE_UINT32(last_release_offset, PCIQXLDevice), | |
1902 | VMSTATE_UINT32(mode, PCIQXLDevice), | |
1903 | VMSTATE_UINT32(ssd.unique, PCIQXLDevice), | |
b67737a6 GH |
1904 | VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
1905 | VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, | |
1906 | qxl_memslot, struct guest_slots), | |
1907 | VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, | |
1908 | qxl_surface, QXLSurfaceCreate), | |
1909 | VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice), | |
1910 | VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0, | |
1911 | vmstate_info_uint64, uint64_t), | |
1912 | VMSTATE_UINT64(guest_cursor, PCIQXLDevice), | |
a19cbfb3 GH |
1913 | VMSTATE_END_OF_LIST() |
1914 | }, | |
a19cbfb3 GH |
1915 | }; |
1916 | ||
78e60ba5 GH |
1917 | static Property qxl_properties[] = { |
1918 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, | |
1919 | 64 * 1024 * 1024), | |
1920 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, | |
1921 | 64 * 1024 * 1024), | |
1922 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, | |
1923 | QXL_DEFAULT_REVISION), | |
1924 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
1925 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
1926 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
017438ee GH |
1927 | DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
1928 | DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram_size_mb, -1), | |
78e60ba5 GH |
1929 | DEFINE_PROP_END_OF_LIST(), |
1930 | }; | |
1931 | ||
40021f08 AL |
1932 | static void qxl_primary_class_init(ObjectClass *klass, void *data) |
1933 | { | |
39bffca2 | 1934 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1935 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1936 | ||
1937 | k->no_hotplug = 1; | |
1938 | k->init = qxl_init_primary; | |
1939 | k->romfile = "vgabios-qxl.bin"; | |
1940 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
1941 | k->device_id = QXL_DEVICE_ID_STABLE; | |
1942 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
39bffca2 AL |
1943 | dc->desc = "Spice QXL GPU (primary, vga compatible)"; |
1944 | dc->reset = qxl_reset_handler; | |
1945 | dc->vmsd = &qxl_vmstate; | |
1946 | dc->props = qxl_properties; | |
40021f08 AL |
1947 | } |
1948 | ||
39bffca2 AL |
1949 | static TypeInfo qxl_primary_info = { |
1950 | .name = "qxl-vga", | |
1951 | .parent = TYPE_PCI_DEVICE, | |
1952 | .instance_size = sizeof(PCIQXLDevice), | |
1953 | .class_init = qxl_primary_class_init, | |
a19cbfb3 GH |
1954 | }; |
1955 | ||
40021f08 AL |
1956 | static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
1957 | { | |
39bffca2 | 1958 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1959 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1960 | ||
1961 | k->init = qxl_init_secondary; | |
1962 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
1963 | k->device_id = QXL_DEVICE_ID_STABLE; | |
1964 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
39bffca2 AL |
1965 | dc->desc = "Spice QXL GPU (secondary)"; |
1966 | dc->reset = qxl_reset_handler; | |
1967 | dc->vmsd = &qxl_vmstate; | |
1968 | dc->props = qxl_properties; | |
40021f08 AL |
1969 | } |
1970 | ||
39bffca2 AL |
1971 | static TypeInfo qxl_secondary_info = { |
1972 | .name = "qxl", | |
1973 | .parent = TYPE_PCI_DEVICE, | |
1974 | .instance_size = sizeof(PCIQXLDevice), | |
1975 | .class_init = qxl_secondary_class_init, | |
a19cbfb3 GH |
1976 | }; |
1977 | ||
83f7d43a | 1978 | static void qxl_register_types(void) |
a19cbfb3 | 1979 | { |
39bffca2 AL |
1980 | type_register_static(&qxl_primary_info); |
1981 | type_register_static(&qxl_secondary_info); | |
a19cbfb3 GH |
1982 | } |
1983 | ||
83f7d43a | 1984 | type_init(qxl_register_types) |