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bb72692c MC |
1 | /* |
2 | * QEMU model of the UART on the SiFive E300 and U500 series SOCs. | |
3 | * | |
4 | * Copyright (c) 2016 Stefan O'Rear | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qapi/error.h" | |
21 | #include "hw/sysbus.h" | |
22 | #include "chardev/char.h" | |
23 | #include "chardev/char-fe.h" | |
24 | #include "target/riscv/cpu.h" | |
25 | #include "hw/riscv/sifive_uart.h" | |
26 | ||
27 | /* | |
28 | * Not yet implemented: | |
29 | * | |
30 | * Transmit FIFO using "qemu/fifo8.h" | |
bb72692c MC |
31 | */ |
32 | ||
40061ac0 NG |
33 | /* Returns the state of the IP (interrupt pending) register */ |
34 | static uint64_t uart_ip(SiFiveUARTState *s) | |
35 | { | |
36 | uint64_t ret = 0; | |
37 | ||
38 | uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); | |
39 | uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl); | |
40 | ||
41 | if (txcnt != 0) { | |
42 | ret |= SIFIVE_UART_IP_TXWM; | |
43 | } | |
44 | if (s->rx_fifo_len > rxcnt) { | |
45 | ret |= SIFIVE_UART_IP_RXWM; | |
46 | } | |
47 | ||
48 | return ret; | |
49 | } | |
50 | ||
bb72692c MC |
51 | static void update_irq(SiFiveUARTState *s) |
52 | { | |
53 | int cond = 0; | |
54 | if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { | |
55 | cond = 1; | |
56 | } | |
57 | if (cond) { | |
58 | qemu_irq_raise(s->irq); | |
59 | } else { | |
60 | qemu_irq_lower(s->irq); | |
61 | } | |
62 | } | |
63 | ||
64 | static uint64_t | |
65 | uart_read(void *opaque, hwaddr addr, unsigned int size) | |
66 | { | |
67 | SiFiveUARTState *s = opaque; | |
68 | unsigned char r; | |
69 | switch (addr) { | |
70 | case SIFIVE_UART_RXFIFO: | |
71 | if (s->rx_fifo_len) { | |
72 | r = s->rx_fifo[0]; | |
73 | memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); | |
74 | s->rx_fifo_len--; | |
75 | qemu_chr_fe_accept_input(&s->chr); | |
76 | update_irq(s); | |
77 | return r; | |
78 | } | |
79 | return 0x80000000; | |
80 | ||
81 | case SIFIVE_UART_TXFIFO: | |
82 | return 0; /* Should check tx fifo */ | |
83 | case SIFIVE_UART_IE: | |
84 | return s->ie; | |
85 | case SIFIVE_UART_IP: | |
40061ac0 | 86 | return uart_ip(s); |
bb72692c MC |
87 | case SIFIVE_UART_TXCTRL: |
88 | return s->txctrl; | |
89 | case SIFIVE_UART_RXCTRL: | |
90 | return s->rxctrl; | |
91 | case SIFIVE_UART_DIV: | |
92 | return s->div; | |
93 | } | |
94 | ||
95 | hw_error("%s: bad read: addr=0x%x\n", | |
96 | __func__, (int)addr); | |
97 | return 0; | |
98 | } | |
99 | ||
100 | static void | |
101 | uart_write(void *opaque, hwaddr addr, | |
102 | uint64_t val64, unsigned int size) | |
103 | { | |
104 | SiFiveUARTState *s = opaque; | |
105 | uint32_t value = val64; | |
106 | unsigned char ch = value; | |
107 | ||
108 | switch (addr) { | |
109 | case SIFIVE_UART_TXFIFO: | |
110 | qemu_chr_fe_write(&s->chr, &ch, 1); | |
111 | return; | |
112 | case SIFIVE_UART_IE: | |
113 | s->ie = val64; | |
114 | update_irq(s); | |
115 | return; | |
116 | case SIFIVE_UART_TXCTRL: | |
117 | s->txctrl = val64; | |
118 | return; | |
119 | case SIFIVE_UART_RXCTRL: | |
120 | s->rxctrl = val64; | |
121 | return; | |
122 | case SIFIVE_UART_DIV: | |
123 | s->div = val64; | |
124 | return; | |
125 | } | |
126 | hw_error("%s: bad write: addr=0x%x v=0x%x\n", | |
127 | __func__, (int)addr, (int)value); | |
128 | } | |
129 | ||
130 | static const MemoryRegionOps uart_ops = { | |
131 | .read = uart_read, | |
132 | .write = uart_write, | |
133 | .endianness = DEVICE_NATIVE_ENDIAN, | |
134 | .valid = { | |
135 | .min_access_size = 4, | |
136 | .max_access_size = 4 | |
137 | } | |
138 | }; | |
139 | ||
140 | static void uart_rx(void *opaque, const uint8_t *buf, int size) | |
141 | { | |
142 | SiFiveUARTState *s = opaque; | |
143 | ||
144 | /* Got a byte. */ | |
145 | if (s->rx_fifo_len >= sizeof(s->rx_fifo)) { | |
146 | printf("WARNING: UART dropped char.\n"); | |
147 | return; | |
148 | } | |
149 | s->rx_fifo[s->rx_fifo_len++] = *buf; | |
150 | ||
151 | update_irq(s); | |
152 | } | |
153 | ||
154 | static int uart_can_rx(void *opaque) | |
155 | { | |
156 | SiFiveUARTState *s = opaque; | |
157 | ||
158 | return s->rx_fifo_len < sizeof(s->rx_fifo); | |
159 | } | |
160 | ||
161 | static void uart_event(void *opaque, int event) | |
162 | { | |
163 | } | |
164 | ||
165 | static int uart_be_change(void *opaque) | |
166 | { | |
167 | SiFiveUARTState *s = opaque; | |
168 | ||
169 | qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, | |
170 | uart_be_change, s, NULL, true); | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | /* | |
176 | * Create UART device. | |
177 | */ | |
178 | SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, | |
179 | Chardev *chr, qemu_irq irq) | |
180 | { | |
181 | SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); | |
182 | s->irq = irq; | |
183 | qemu_chr_fe_init(&s->chr, chr, &error_abort); | |
184 | qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, | |
185 | uart_be_change, s, NULL, true); | |
186 | memory_region_init_io(&s->mmio, NULL, &uart_ops, s, | |
187 | TYPE_SIFIVE_UART, SIFIVE_UART_MAX); | |
188 | memory_region_add_subregion(address_space, base, &s->mmio); | |
189 | return s; | |
190 | } |