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04331d0b MC |
1 | /* |
2 | * QEMU RISC-V VirtIO Board | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * RISC-V machine with 16550a UART and VirtIO MMIO | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2 or later, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
4bf46af7 | 22 | #include "qemu/units.h" |
04331d0b MC |
23 | #include "qemu/error-report.h" |
24 | #include "qapi/error.h" | |
04331d0b MC |
25 | #include "hw/boards.h" |
26 | #include "hw/loader.h" | |
27 | #include "hw/sysbus.h" | |
71eb522c | 28 | #include "hw/qdev-properties.h" |
04331d0b MC |
29 | #include "hw/char/serial.h" |
30 | #include "target/riscv/cpu.h" | |
04331d0b | 31 | #include "hw/riscv/riscv_hart.h" |
04331d0b | 32 | #include "hw/riscv/virt.h" |
0ac24d56 | 33 | #include "hw/riscv/boot.h" |
18df0b46 | 34 | #include "hw/riscv/numa.h" |
cc63a182 | 35 | #include "hw/intc/riscv_aclint.h" |
e6faee65 | 36 | #include "hw/intc/riscv_aplic.h" |
28d8c281 | 37 | #include "hw/intc/riscv_imsic.h" |
84fcf3c1 | 38 | #include "hw/intc/sifive_plic.h" |
a4b84608 | 39 | #include "hw/misc/sifive_test.h" |
1832b7cb | 40 | #include "hw/platform-bus.h" |
04331d0b | 41 | #include "chardev/char.h" |
04331d0b | 42 | #include "sysemu/device_tree.h" |
46517dd4 | 43 | #include "sysemu/sysemu.h" |
ad40be27 | 44 | #include "sysemu/kvm.h" |
6d56e396 AF |
45 | #include "hw/pci/pci.h" |
46 | #include "hw/pci-host/gpex.h" | |
c346749e | 47 | #include "hw/display/ramfb.h" |
04331d0b | 48 | |
0631aaae AP |
49 | /* |
50 | * The virt machine physical address space used by some of the devices | |
51 | * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, | |
52 | * number of CPUs, and number of IMSIC guest files. | |
53 | * | |
54 | * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, | |
55 | * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization | |
56 | * of virt machine physical address space. | |
57 | */ | |
58 | ||
28d8c281 AP |
59 | #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) |
60 | #if VIRT_IMSIC_GROUP_MAX_SIZE < \ | |
61 | IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) | |
62 | #error "Can't accomodate single IMSIC group in address space" | |
63 | #endif | |
64 | ||
65 | #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ | |
66 | VIRT_IMSIC_GROUP_MAX_SIZE) | |
67 | #if 0x4000000 < VIRT_IMSIC_MAX_SIZE | |
68 | #error "Can't accomodate all IMSIC groups in address space" | |
69 | #endif | |
70 | ||
73261285 | 71 | static const MemMapEntry virt_memmap[] = { |
1832b7cb AF |
72 | [VIRT_DEBUG] = { 0x0, 0x100 }, |
73 | [VIRT_MROM] = { 0x1000, 0xf000 }, | |
74 | [VIRT_TEST] = { 0x100000, 0x1000 }, | |
75 | [VIRT_RTC] = { 0x101000, 0x1000 }, | |
76 | [VIRT_CLINT] = { 0x2000000, 0x10000 }, | |
77 | [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, | |
78 | [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, | |
79 | [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, | |
80 | [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, | |
81 | [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, | |
82 | [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, | |
83 | [VIRT_UART0] = { 0x10000000, 0x100 }, | |
84 | [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, | |
85 | [VIRT_FW_CFG] = { 0x10100000, 0x18 }, | |
86 | [VIRT_FLASH] = { 0x20000000, 0x4000000 }, | |
87 | [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, | |
88 | [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, | |
89 | [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, | |
90 | [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, | |
91 | [VIRT_DRAM] = { 0x80000000, 0x0 }, | |
04331d0b MC |
92 | }; |
93 | ||
19800265 BM |
94 | /* PCIe high mmio is fixed for RV32 */ |
95 | #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL | |
96 | #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) | |
97 | ||
98 | /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ | |
99 | #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) | |
100 | ||
101 | static MemMapEntry virt_high_pcie_memmap; | |
102 | ||
71eb522c AF |
103 | #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) |
104 | ||
105 | static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, | |
106 | const char *name, | |
107 | const char *alias_prop_name) | |
108 | { | |
109 | /* | |
110 | * Create a single flash device. We use the same parameters as | |
111 | * the flash devices on the ARM virt board. | |
112 | */ | |
df707969 | 113 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
71eb522c AF |
114 | |
115 | qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); | |
116 | qdev_prop_set_uint8(dev, "width", 4); | |
117 | qdev_prop_set_uint8(dev, "device-width", 2); | |
118 | qdev_prop_set_bit(dev, "big-endian", false); | |
119 | qdev_prop_set_uint16(dev, "id0", 0x89); | |
120 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
121 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
122 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
123 | qdev_prop_set_string(dev, "name", name); | |
124 | ||
d2623129 | 125 | object_property_add_child(OBJECT(s), name, OBJECT(dev)); |
71eb522c | 126 | object_property_add_alias(OBJECT(s), alias_prop_name, |
d2623129 | 127 | OBJECT(dev), "drive"); |
71eb522c AF |
128 | |
129 | return PFLASH_CFI01(dev); | |
130 | } | |
131 | ||
132 | static void virt_flash_create(RISCVVirtState *s) | |
133 | { | |
134 | s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); | |
135 | s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); | |
136 | } | |
137 | ||
138 | static void virt_flash_map1(PFlashCFI01 *flash, | |
139 | hwaddr base, hwaddr size, | |
140 | MemoryRegion *sysmem) | |
141 | { | |
142 | DeviceState *dev = DEVICE(flash); | |
143 | ||
4cdd0a77 | 144 | assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); |
71eb522c AF |
145 | assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); |
146 | qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); | |
3c6ef471 | 147 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
71eb522c AF |
148 | |
149 | memory_region_add_subregion(sysmem, base, | |
150 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), | |
151 | 0)); | |
152 | } | |
153 | ||
154 | static void virt_flash_map(RISCVVirtState *s, | |
155 | MemoryRegion *sysmem) | |
156 | { | |
157 | hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; | |
158 | hwaddr flashbase = virt_memmap[VIRT_FLASH].base; | |
159 | ||
160 | virt_flash_map1(s->flash[0], flashbase, flashsize, | |
161 | sysmem); | |
162 | virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, | |
163 | sysmem); | |
164 | } | |
165 | ||
e6faee65 AP |
166 | static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, |
167 | uint32_t irqchip_phandle) | |
6d56e396 AF |
168 | { |
169 | int pin, dev; | |
e6faee65 AP |
170 | uint32_t irq_map_stride = 0; |
171 | uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * | |
172 | FDT_MAX_INT_MAP_WIDTH] = {}; | |
6d56e396 AF |
173 | uint32_t *irq_map = full_irq_map; |
174 | ||
175 | /* This code creates a standard swizzle of interrupts such that | |
176 | * each device's first interrupt is based on it's PCI_SLOT number. | |
177 | * (See pci_swizzle_map_irq_fn()) | |
178 | * | |
179 | * We only need one entry per interrupt in the table (not one per | |
180 | * possible slot) seeing the interrupt-map-mask will allow the table | |
181 | * to wrap to any number of devices. | |
182 | */ | |
183 | for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { | |
184 | int devfn = dev * 0x8; | |
185 | ||
186 | for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { | |
187 | int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); | |
188 | int i = 0; | |
189 | ||
e6faee65 | 190 | /* Fill PCI address cells */ |
6d56e396 | 191 | irq_map[i] = cpu_to_be32(devfn << 8); |
6d56e396 | 192 | i += FDT_PCI_ADDR_CELLS; |
6d56e396 | 193 | |
e6faee65 AP |
194 | /* Fill PCI Interrupt cells */ |
195 | irq_map[i] = cpu_to_be32(pin + 1); | |
6d56e396 | 196 | i += FDT_PCI_INT_CELLS; |
6d56e396 | 197 | |
e6faee65 AP |
198 | /* Fill interrupt controller phandle and cells */ |
199 | irq_map[i++] = cpu_to_be32(irqchip_phandle); | |
200 | irq_map[i++] = cpu_to_be32(irq_nr); | |
201 | if (s->aia_type != VIRT_AIA_TYPE_NONE) { | |
202 | irq_map[i++] = cpu_to_be32(0x4); | |
203 | } | |
6d56e396 | 204 | |
e6faee65 AP |
205 | if (!irq_map_stride) { |
206 | irq_map_stride = i; | |
207 | } | |
208 | irq_map += irq_map_stride; | |
6d56e396 AF |
209 | } |
210 | } | |
211 | ||
e6faee65 AP |
212 | qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, |
213 | GPEX_NUM_IRQS * GPEX_NUM_IRQS * | |
214 | irq_map_stride * sizeof(uint32_t)); | |
6d56e396 AF |
215 | |
216 | qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", | |
217 | 0x1800, 0, 0, 0x7); | |
218 | } | |
219 | ||
0ffc1a95 AP |
220 | static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, |
221 | char *clust_name, uint32_t *phandle, | |
222 | bool is_32_bit, uint32_t *intc_phandles) | |
04331d0b | 223 | { |
0ffc1a95 AP |
224 | int cpu; |
225 | uint32_t cpu_phandle; | |
18df0b46 | 226 | MachineState *mc = MACHINE(s); |
0ffc1a95 AP |
227 | char *name, *cpu_name, *core_name, *intc_name; |
228 | ||
229 | for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { | |
230 | cpu_phandle = (*phandle)++; | |
231 | ||
232 | cpu_name = g_strdup_printf("/cpus/cpu@%d", | |
233 | s->soc[socket].hartid_base + cpu); | |
234 | qemu_fdt_add_subnode(mc->fdt, cpu_name); | |
d6db2c0f NC |
235 | if (riscv_feature(&s->soc[socket].harts[cpu].env, |
236 | RISCV_FEATURE_MMU)) { | |
237 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", | |
238 | (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); | |
239 | } else { | |
240 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", | |
241 | "riscv,none"); | |
242 | } | |
0ffc1a95 AP |
243 | name = riscv_isa_string(&s->soc[socket].harts[cpu]); |
244 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); | |
245 | g_free(name); | |
246 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); | |
247 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); | |
248 | qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", | |
249 | s->soc[socket].hartid_base + cpu); | |
250 | qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); | |
251 | riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); | |
252 | qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); | |
253 | ||
254 | intc_phandles[cpu] = (*phandle)++; | |
255 | ||
256 | intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); | |
257 | qemu_fdt_add_subnode(mc->fdt, intc_name); | |
258 | qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", | |
259 | intc_phandles[cpu]); | |
d207863c AP |
260 | if (riscv_feature(&s->soc[socket].harts[cpu].env, |
261 | RISCV_FEATURE_AIA)) { | |
262 | static const char * const compat[2] = { | |
263 | "riscv,cpu-intc-aia", "riscv,cpu-intc" | |
264 | }; | |
265 | qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", | |
266 | (char **)&compat, ARRAY_SIZE(compat)); | |
267 | } else { | |
268 | qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", | |
269 | "riscv,cpu-intc"); | |
270 | } | |
0ffc1a95 AP |
271 | qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); |
272 | qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); | |
273 | ||
274 | core_name = g_strdup_printf("%s/core%d", clust_name, cpu); | |
275 | qemu_fdt_add_subnode(mc->fdt, core_name); | |
276 | qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); | |
277 | ||
278 | g_free(core_name); | |
279 | g_free(intc_name); | |
280 | g_free(cpu_name); | |
281 | } | |
282 | } | |
283 | ||
284 | static void create_fdt_socket_memory(RISCVVirtState *s, | |
285 | const MemMapEntry *memmap, int socket) | |
286 | { | |
287 | char *mem_name; | |
18df0b46 | 288 | uint64_t addr, size; |
0ffc1a95 AP |
289 | MachineState *mc = MACHINE(s); |
290 | ||
291 | addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); | |
292 | size = riscv_socket_mem_size(mc, socket); | |
293 | mem_name = g_strdup_printf("/memory@%lx", (long)addr); | |
294 | qemu_fdt_add_subnode(mc->fdt, mem_name); | |
295 | qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", | |
296 | addr >> 32, addr, size >> 32, size); | |
297 | qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); | |
298 | riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); | |
299 | g_free(mem_name); | |
300 | } | |
301 | ||
302 | static void create_fdt_socket_clint(RISCVVirtState *s, | |
303 | const MemMapEntry *memmap, int socket, | |
304 | uint32_t *intc_phandles) | |
305 | { | |
306 | int cpu; | |
307 | char *clint_name; | |
308 | uint32_t *clint_cells; | |
309 | unsigned long clint_addr; | |
310 | MachineState *mc = MACHINE(s); | |
7cfbb17f BM |
311 | static const char * const clint_compat[2] = { |
312 | "sifive,clint0", "riscv,clint0" | |
313 | }; | |
0ffc1a95 AP |
314 | |
315 | clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); | |
316 | ||
317 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | |
318 | clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
319 | clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
320 | clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); | |
321 | clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
322 | } | |
323 | ||
324 | clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); | |
325 | clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); | |
326 | qemu_fdt_add_subnode(mc->fdt, clint_name); | |
327 | qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", | |
328 | (char **)&clint_compat, | |
329 | ARRAY_SIZE(clint_compat)); | |
330 | qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", | |
331 | 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); | |
332 | qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", | |
333 | clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | |
334 | riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); | |
335 | g_free(clint_name); | |
336 | ||
337 | g_free(clint_cells); | |
338 | } | |
339 | ||
954886ea AP |
340 | static void create_fdt_socket_aclint(RISCVVirtState *s, |
341 | const MemMapEntry *memmap, int socket, | |
342 | uint32_t *intc_phandles) | |
343 | { | |
344 | int cpu; | |
345 | char *name; | |
28d8c281 | 346 | unsigned long addr, size; |
954886ea AP |
347 | uint32_t aclint_cells_size; |
348 | uint32_t *aclint_mswi_cells; | |
349 | uint32_t *aclint_sswi_cells; | |
350 | uint32_t *aclint_mtimer_cells; | |
351 | MachineState *mc = MACHINE(s); | |
352 | ||
353 | aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | |
354 | aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | |
355 | aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | |
356 | ||
357 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | |
358 | aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
359 | aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
360 | aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
361 | aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); | |
362 | aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
363 | aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); | |
364 | } | |
365 | aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; | |
366 | ||
28d8c281 AP |
367 | if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { |
368 | addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); | |
369 | name = g_strdup_printf("/soc/mswi@%lx", addr); | |
370 | qemu_fdt_add_subnode(mc->fdt, name); | |
371 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", | |
372 | "riscv,aclint-mswi"); | |
373 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", | |
374 | 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); | |
375 | qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", | |
376 | aclint_mswi_cells, aclint_cells_size); | |
377 | qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); | |
378 | qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); | |
379 | riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); | |
380 | g_free(name); | |
381 | } | |
954886ea | 382 | |
28d8c281 AP |
383 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
384 | addr = memmap[VIRT_CLINT].base + | |
385 | (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); | |
386 | size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; | |
387 | } else { | |
388 | addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + | |
389 | (memmap[VIRT_CLINT].size * socket); | |
390 | size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; | |
391 | } | |
954886ea AP |
392 | name = g_strdup_printf("/soc/mtimer@%lx", addr); |
393 | qemu_fdt_add_subnode(mc->fdt, name); | |
394 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", | |
395 | "riscv,aclint-mtimer"); | |
396 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", | |
397 | 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, | |
28d8c281 | 398 | 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, |
954886ea AP |
399 | 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, |
400 | 0x0, RISCV_ACLINT_DEFAULT_MTIME); | |
401 | qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", | |
402 | aclint_mtimer_cells, aclint_cells_size); | |
403 | riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); | |
404 | g_free(name); | |
405 | ||
28d8c281 AP |
406 | if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { |
407 | addr = memmap[VIRT_ACLINT_SSWI].base + | |
408 | (memmap[VIRT_ACLINT_SSWI].size * socket); | |
409 | name = g_strdup_printf("/soc/sswi@%lx", addr); | |
410 | qemu_fdt_add_subnode(mc->fdt, name); | |
411 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", | |
412 | "riscv,aclint-sswi"); | |
413 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", | |
414 | 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); | |
415 | qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", | |
416 | aclint_sswi_cells, aclint_cells_size); | |
417 | qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); | |
418 | qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); | |
419 | riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); | |
420 | g_free(name); | |
421 | } | |
954886ea AP |
422 | |
423 | g_free(aclint_mswi_cells); | |
424 | g_free(aclint_mtimer_cells); | |
425 | g_free(aclint_sswi_cells); | |
426 | } | |
427 | ||
0ffc1a95 AP |
428 | static void create_fdt_socket_plic(RISCVVirtState *s, |
429 | const MemMapEntry *memmap, int socket, | |
430 | uint32_t *phandle, uint32_t *intc_phandles, | |
431 | uint32_t *plic_phandles) | |
432 | { | |
433 | int cpu; | |
434 | char *plic_name; | |
435 | uint32_t *plic_cells; | |
436 | unsigned long plic_addr; | |
437 | MachineState *mc = MACHINE(s); | |
60bb5407 BM |
438 | static const char * const plic_compat[2] = { |
439 | "sifive,plic-1.0.0", "riscv,plic0" | |
440 | }; | |
04331d0b | 441 | |
ad40be27 YJ |
442 | if (kvm_enabled()) { |
443 | plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | |
444 | } else { | |
445 | plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); | |
446 | } | |
0ffc1a95 AP |
447 | |
448 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | |
ad40be27 YJ |
449 | if (kvm_enabled()) { |
450 | plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
451 | plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); | |
452 | } else { | |
453 | plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
454 | plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); | |
455 | plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); | |
456 | plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); | |
457 | } | |
04331d0b MC |
458 | } |
459 | ||
0ffc1a95 AP |
460 | plic_phandles[socket] = (*phandle)++; |
461 | plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); | |
462 | plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); | |
463 | qemu_fdt_add_subnode(mc->fdt, plic_name); | |
0ffc1a95 AP |
464 | qemu_fdt_setprop_cell(mc->fdt, plic_name, |
465 | "#interrupt-cells", FDT_PLIC_INT_CELLS); | |
466 | qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", | |
467 | (char **)&plic_compat, | |
468 | ARRAY_SIZE(plic_compat)); | |
469 | qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); | |
470 | qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", | |
471 | plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | |
472 | qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", | |
473 | 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); | |
474 | qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); | |
475 | riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); | |
476 | qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", | |
477 | plic_phandles[socket]); | |
478 | g_free(plic_name); | |
479 | ||
480 | g_free(plic_cells); | |
481 | } | |
04331d0b | 482 | |
28d8c281 AP |
483 | static uint32_t imsic_num_bits(uint32_t count) |
484 | { | |
485 | uint32_t ret = 0; | |
486 | ||
487 | while (BIT(ret) < count) { | |
488 | ret++; | |
489 | } | |
490 | ||
491 | return ret; | |
492 | } | |
493 | ||
494 | static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, | |
495 | uint32_t *phandle, uint32_t *intc_phandles, | |
496 | uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) | |
497 | { | |
498 | int cpu, socket; | |
499 | char *imsic_name; | |
500 | MachineState *mc = MACHINE(s); | |
501 | uint32_t imsic_max_hart_per_socket, imsic_guest_bits; | |
502 | uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; | |
503 | ||
504 | *msi_m_phandle = (*phandle)++; | |
505 | *msi_s_phandle = (*phandle)++; | |
506 | imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); | |
507 | imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); | |
508 | ||
509 | /* M-level IMSIC node */ | |
510 | for (cpu = 0; cpu < mc->smp.cpus; cpu++) { | |
511 | imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
512 | imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); | |
513 | } | |
514 | imsic_max_hart_per_socket = 0; | |
515 | for (socket = 0; socket < riscv_socket_count(mc); socket++) { | |
516 | imsic_addr = memmap[VIRT_IMSIC_M].base + | |
517 | socket * VIRT_IMSIC_GROUP_MAX_SIZE; | |
518 | imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; | |
519 | imsic_regs[socket * 4 + 0] = 0; | |
520 | imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); | |
521 | imsic_regs[socket * 4 + 2] = 0; | |
522 | imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); | |
523 | if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { | |
524 | imsic_max_hart_per_socket = s->soc[socket].num_harts; | |
525 | } | |
526 | } | |
527 | imsic_name = g_strdup_printf("/soc/imsics@%lx", | |
528 | (unsigned long)memmap[VIRT_IMSIC_M].base); | |
529 | qemu_fdt_add_subnode(mc->fdt, imsic_name); | |
530 | qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", | |
531 | "riscv,imsics"); | |
532 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", | |
533 | FDT_IMSIC_INT_CELLS); | |
534 | qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", | |
535 | NULL, 0); | |
536 | qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", | |
537 | NULL, 0); | |
538 | qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", | |
539 | imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); | |
540 | qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, | |
541 | riscv_socket_count(mc) * sizeof(uint32_t) * 4); | |
542 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", | |
543 | VIRT_IRQCHIP_NUM_MSIS); | |
544 | qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", | |
545 | VIRT_IRQCHIP_IPI_MSI); | |
546 | if (riscv_socket_count(mc) > 1) { | |
547 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", | |
548 | imsic_num_bits(imsic_max_hart_per_socket)); | |
549 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", | |
550 | imsic_num_bits(riscv_socket_count(mc))); | |
551 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", | |
552 | IMSIC_MMIO_GROUP_MIN_SHIFT); | |
553 | } | |
554 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); | |
555 | g_free(imsic_name); | |
556 | ||
557 | /* S-level IMSIC node */ | |
558 | for (cpu = 0; cpu < mc->smp.cpus; cpu++) { | |
559 | imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
560 | imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); | |
561 | } | |
562 | imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); | |
563 | imsic_max_hart_per_socket = 0; | |
564 | for (socket = 0; socket < riscv_socket_count(mc); socket++) { | |
565 | imsic_addr = memmap[VIRT_IMSIC_S].base + | |
566 | socket * VIRT_IMSIC_GROUP_MAX_SIZE; | |
567 | imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * | |
568 | s->soc[socket].num_harts; | |
569 | imsic_regs[socket * 4 + 0] = 0; | |
570 | imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); | |
571 | imsic_regs[socket * 4 + 2] = 0; | |
572 | imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); | |
573 | if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { | |
574 | imsic_max_hart_per_socket = s->soc[socket].num_harts; | |
575 | } | |
576 | } | |
577 | imsic_name = g_strdup_printf("/soc/imsics@%lx", | |
578 | (unsigned long)memmap[VIRT_IMSIC_S].base); | |
579 | qemu_fdt_add_subnode(mc->fdt, imsic_name); | |
580 | qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", | |
581 | "riscv,imsics"); | |
582 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", | |
583 | FDT_IMSIC_INT_CELLS); | |
584 | qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", | |
585 | NULL, 0); | |
586 | qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", | |
587 | NULL, 0); | |
588 | qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", | |
589 | imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); | |
590 | qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, | |
591 | riscv_socket_count(mc) * sizeof(uint32_t) * 4); | |
592 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", | |
593 | VIRT_IRQCHIP_NUM_MSIS); | |
594 | qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", | |
595 | VIRT_IRQCHIP_IPI_MSI); | |
596 | if (imsic_guest_bits) { | |
597 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", | |
598 | imsic_guest_bits); | |
599 | } | |
600 | if (riscv_socket_count(mc) > 1) { | |
601 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", | |
602 | imsic_num_bits(imsic_max_hart_per_socket)); | |
603 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", | |
604 | imsic_num_bits(riscv_socket_count(mc))); | |
605 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", | |
606 | IMSIC_MMIO_GROUP_MIN_SHIFT); | |
607 | } | |
608 | qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); | |
609 | g_free(imsic_name); | |
610 | ||
611 | g_free(imsic_regs); | |
612 | g_free(imsic_cells); | |
613 | } | |
614 | ||
615 | static void create_fdt_socket_aplic(RISCVVirtState *s, | |
616 | const MemMapEntry *memmap, int socket, | |
617 | uint32_t msi_m_phandle, | |
618 | uint32_t msi_s_phandle, | |
619 | uint32_t *phandle, | |
620 | uint32_t *intc_phandles, | |
621 | uint32_t *aplic_phandles) | |
e6faee65 AP |
622 | { |
623 | int cpu; | |
624 | char *aplic_name; | |
625 | uint32_t *aplic_cells; | |
626 | unsigned long aplic_addr; | |
627 | MachineState *mc = MACHINE(s); | |
628 | uint32_t aplic_m_phandle, aplic_s_phandle; | |
629 | ||
630 | aplic_m_phandle = (*phandle)++; | |
631 | aplic_s_phandle = (*phandle)++; | |
632 | aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | |
633 | ||
634 | /* M-level APLIC node */ | |
635 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | |
636 | aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
637 | aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); | |
638 | } | |
639 | aplic_addr = memmap[VIRT_APLIC_M].base + | |
640 | (memmap[VIRT_APLIC_M].size * socket); | |
641 | aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); | |
642 | qemu_fdt_add_subnode(mc->fdt, aplic_name); | |
643 | qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); | |
644 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, | |
645 | "#interrupt-cells", FDT_APLIC_INT_CELLS); | |
646 | qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); | |
28d8c281 AP |
647 | if (s->aia_type == VIRT_AIA_TYPE_APLIC) { |
648 | qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", | |
649 | aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); | |
650 | } else { | |
651 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", | |
652 | msi_m_phandle); | |
653 | } | |
e6faee65 AP |
654 | qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", |
655 | 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); | |
656 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", | |
657 | VIRT_IRQCHIP_NUM_SOURCES); | |
658 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", | |
659 | aplic_s_phandle); | |
660 | qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", | |
661 | aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); | |
662 | riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); | |
663 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); | |
664 | g_free(aplic_name); | |
665 | ||
666 | /* S-level APLIC node */ | |
667 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | |
668 | aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | |
669 | aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); | |
670 | } | |
671 | aplic_addr = memmap[VIRT_APLIC_S].base + | |
672 | (memmap[VIRT_APLIC_S].size * socket); | |
673 | aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); | |
674 | qemu_fdt_add_subnode(mc->fdt, aplic_name); | |
675 | qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); | |
676 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, | |
677 | "#interrupt-cells", FDT_APLIC_INT_CELLS); | |
678 | qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); | |
28d8c281 AP |
679 | if (s->aia_type == VIRT_AIA_TYPE_APLIC) { |
680 | qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", | |
681 | aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); | |
682 | } else { | |
683 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", | |
684 | msi_s_phandle); | |
685 | } | |
e6faee65 AP |
686 | qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", |
687 | 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); | |
688 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", | |
689 | VIRT_IRQCHIP_NUM_SOURCES); | |
690 | riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); | |
691 | qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); | |
692 | g_free(aplic_name); | |
693 | ||
694 | g_free(aplic_cells); | |
695 | aplic_phandles[socket] = aplic_s_phandle; | |
696 | } | |
697 | ||
0ffc1a95 AP |
698 | static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, |
699 | bool is_32_bit, uint32_t *phandle, | |
700 | uint32_t *irq_mmio_phandle, | |
701 | uint32_t *irq_pcie_phandle, | |
28d8c281 AP |
702 | uint32_t *irq_virtio_phandle, |
703 | uint32_t *msi_pcie_phandle) | |
0ffc1a95 | 704 | { |
0ffc1a95 | 705 | char *clust_name; |
28d8c281 | 706 | int socket, phandle_pos; |
0ffc1a95 | 707 | MachineState *mc = MACHINE(s); |
28d8c281 AP |
708 | uint32_t msi_m_phandle = 0, msi_s_phandle = 0; |
709 | uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; | |
04331d0b | 710 | |
0ffc1a95 AP |
711 | qemu_fdt_add_subnode(mc->fdt, "/cpus"); |
712 | qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", | |
b8fb878a | 713 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); |
0ffc1a95 AP |
714 | qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); |
715 | qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); | |
716 | qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); | |
18df0b46 | 717 | |
28d8c281 AP |
718 | intc_phandles = g_new0(uint32_t, mc->smp.cpus); |
719 | ||
720 | phandle_pos = mc->smp.cpus; | |
18df0b46 | 721 | for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { |
28d8c281 AP |
722 | phandle_pos -= s->soc[socket].num_harts; |
723 | ||
18df0b46 | 724 | clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); |
0ffc1a95 AP |
725 | qemu_fdt_add_subnode(mc->fdt, clust_name); |
726 | ||
0ffc1a95 | 727 | create_fdt_socket_cpus(s, socket, clust_name, phandle, |
28d8c281 | 728 | is_32_bit, &intc_phandles[phandle_pos]); |
04331d0b | 729 | |
0ffc1a95 AP |
730 | create_fdt_socket_memory(s, memmap, socket); |
731 | ||
28d8c281 AP |
732 | g_free(clust_name); |
733 | ||
ad40be27 YJ |
734 | if (!kvm_enabled()) { |
735 | if (s->have_aclint) { | |
28d8c281 AP |
736 | create_fdt_socket_aclint(s, memmap, socket, |
737 | &intc_phandles[phandle_pos]); | |
ad40be27 | 738 | } else { |
28d8c281 AP |
739 | create_fdt_socket_clint(s, memmap, socket, |
740 | &intc_phandles[phandle_pos]); | |
ad40be27 | 741 | } |
954886ea | 742 | } |
28d8c281 AP |
743 | } |
744 | ||
745 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { | |
746 | create_fdt_imsic(s, memmap, phandle, intc_phandles, | |
747 | &msi_m_phandle, &msi_s_phandle); | |
748 | *msi_pcie_phandle = msi_s_phandle; | |
749 | } | |
750 | ||
751 | phandle_pos = mc->smp.cpus; | |
752 | for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { | |
753 | phandle_pos -= s->soc[socket].num_harts; | |
0ffc1a95 | 754 | |
e6faee65 AP |
755 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
756 | create_fdt_socket_plic(s, memmap, socket, phandle, | |
28d8c281 | 757 | &intc_phandles[phandle_pos], xplic_phandles); |
e6faee65 | 758 | } else { |
28d8c281 AP |
759 | create_fdt_socket_aplic(s, memmap, socket, |
760 | msi_m_phandle, msi_s_phandle, phandle, | |
761 | &intc_phandles[phandle_pos], xplic_phandles); | |
e6faee65 | 762 | } |
28a4df97 AP |
763 | } |
764 | ||
28d8c281 AP |
765 | g_free(intc_phandles); |
766 | ||
18df0b46 AP |
767 | for (socket = 0; socket < riscv_socket_count(mc); socket++) { |
768 | if (socket == 0) { | |
0ffc1a95 AP |
769 | *irq_mmio_phandle = xplic_phandles[socket]; |
770 | *irq_virtio_phandle = xplic_phandles[socket]; | |
771 | *irq_pcie_phandle = xplic_phandles[socket]; | |
18df0b46 AP |
772 | } |
773 | if (socket == 1) { | |
0ffc1a95 AP |
774 | *irq_virtio_phandle = xplic_phandles[socket]; |
775 | *irq_pcie_phandle = xplic_phandles[socket]; | |
18df0b46 AP |
776 | } |
777 | if (socket == 2) { | |
0ffc1a95 | 778 | *irq_pcie_phandle = xplic_phandles[socket]; |
18df0b46 | 779 | } |
04331d0b | 780 | } |
18df0b46 | 781 | |
0ffc1a95 AP |
782 | riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); |
783 | } | |
784 | ||
785 | static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, | |
786 | uint32_t irq_virtio_phandle) | |
787 | { | |
788 | int i; | |
789 | char *name; | |
790 | MachineState *mc = MACHINE(s); | |
04331d0b MC |
791 | |
792 | for (i = 0; i < VIRTIO_COUNT; i++) { | |
18df0b46 | 793 | name = g_strdup_printf("/soc/virtio_mmio@%lx", |
04331d0b | 794 | (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); |
0ffc1a95 AP |
795 | qemu_fdt_add_subnode(mc->fdt, name); |
796 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); | |
797 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", | |
04331d0b MC |
798 | 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, |
799 | 0x0, memmap[VIRT_VIRTIO].size); | |
0ffc1a95 AP |
800 | qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", |
801 | irq_virtio_phandle); | |
e6faee65 AP |
802 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
803 | qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", | |
804 | VIRTIO_IRQ + i); | |
805 | } else { | |
806 | qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", | |
807 | VIRTIO_IRQ + i, 0x4); | |
808 | } | |
18df0b46 | 809 | g_free(name); |
04331d0b | 810 | } |
0ffc1a95 AP |
811 | } |
812 | ||
813 | static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, | |
28d8c281 AP |
814 | uint32_t irq_pcie_phandle, |
815 | uint32_t msi_pcie_phandle) | |
0ffc1a95 AP |
816 | { |
817 | char *name; | |
818 | MachineState *mc = MACHINE(s); | |
04331d0b | 819 | |
18df0b46 | 820 | name = g_strdup_printf("/soc/pci@%lx", |
6d56e396 | 821 | (long) memmap[VIRT_PCIE_ECAM].base); |
0ffc1a95 AP |
822 | qemu_fdt_add_subnode(mc->fdt, name); |
823 | qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", | |
824 | FDT_PCI_ADDR_CELLS); | |
825 | qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", | |
826 | FDT_PCI_INT_CELLS); | |
827 | qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); | |
828 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", | |
829 | "pci-host-ecam-generic"); | |
830 | qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); | |
831 | qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); | |
832 | qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, | |
18df0b46 | 833 | memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); |
0ffc1a95 | 834 | qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); |
28d8c281 AP |
835 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
836 | qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); | |
837 | } | |
0ffc1a95 | 838 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, |
18df0b46 | 839 | memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); |
0ffc1a95 | 840 | qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", |
6d56e396 AF |
841 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
842 | 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, | |
843 | 1, FDT_PCI_RANGE_MMIO, | |
844 | 2, memmap[VIRT_PCIE_MMIO].base, | |
19800265 BM |
845 | 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, |
846 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
847 | 2, virt_high_pcie_memmap.base, | |
848 | 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); | |
849 | ||
e6faee65 | 850 | create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); |
18df0b46 | 851 | g_free(name); |
0ffc1a95 | 852 | } |
6d56e396 | 853 | |
0ffc1a95 AP |
854 | static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, |
855 | uint32_t *phandle) | |
856 | { | |
857 | char *name; | |
858 | uint32_t test_phandle; | |
859 | MachineState *mc = MACHINE(s); | |
860 | ||
861 | test_phandle = (*phandle)++; | |
18df0b46 | 862 | name = g_strdup_printf("/soc/test@%lx", |
04331d0b | 863 | (long)memmap[VIRT_TEST].base); |
0ffc1a95 | 864 | qemu_fdt_add_subnode(mc->fdt, name); |
9c0fb20c | 865 | { |
2cc04550 BM |
866 | static const char * const compat[3] = { |
867 | "sifive,test1", "sifive,test0", "syscon" | |
868 | }; | |
0ffc1a95 AP |
869 | qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", |
870 | (char **)&compat, ARRAY_SIZE(compat)); | |
9c0fb20c | 871 | } |
0ffc1a95 AP |
872 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", |
873 | 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); | |
874 | qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); | |
875 | test_phandle = qemu_fdt_get_phandle(mc->fdt, name); | |
18df0b46 AP |
876 | g_free(name); |
877 | ||
878 | name = g_strdup_printf("/soc/reboot"); | |
0ffc1a95 AP |
879 | qemu_fdt_add_subnode(mc->fdt, name); |
880 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); | |
881 | qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); | |
882 | qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); | |
883 | qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); | |
18df0b46 AP |
884 | g_free(name); |
885 | ||
886 | name = g_strdup_printf("/soc/poweroff"); | |
0ffc1a95 AP |
887 | qemu_fdt_add_subnode(mc->fdt, name); |
888 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); | |
889 | qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); | |
890 | qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); | |
891 | qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); | |
18df0b46 | 892 | g_free(name); |
0ffc1a95 AP |
893 | } |
894 | ||
895 | static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, | |
896 | uint32_t irq_mmio_phandle) | |
897 | { | |
898 | char *name; | |
899 | MachineState *mc = MACHINE(s); | |
18df0b46 AP |
900 | |
901 | name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); | |
0ffc1a95 AP |
902 | qemu_fdt_add_subnode(mc->fdt, name); |
903 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); | |
904 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", | |
04331d0b MC |
905 | 0x0, memmap[VIRT_UART0].base, |
906 | 0x0, memmap[VIRT_UART0].size); | |
0ffc1a95 AP |
907 | qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); |
908 | qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); | |
e6faee65 AP |
909 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
910 | qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); | |
911 | } else { | |
912 | qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); | |
913 | } | |
04331d0b | 914 | |
0ffc1a95 AP |
915 | qemu_fdt_add_subnode(mc->fdt, "/chosen"); |
916 | qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); | |
18df0b46 | 917 | g_free(name); |
0ffc1a95 AP |
918 | } |
919 | ||
920 | static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, | |
921 | uint32_t irq_mmio_phandle) | |
922 | { | |
923 | char *name; | |
924 | MachineState *mc = MACHINE(s); | |
18df0b46 AP |
925 | |
926 | name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); | |
0ffc1a95 AP |
927 | qemu_fdt_add_subnode(mc->fdt, name); |
928 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", | |
929 | "google,goldfish-rtc"); | |
930 | qemu_fdt_setprop_cells(mc->fdt, name, "reg", | |
931 | 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); | |
932 | qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", | |
933 | irq_mmio_phandle); | |
e6faee65 AP |
934 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
935 | qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); | |
936 | } else { | |
937 | qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); | |
938 | } | |
18df0b46 | 939 | g_free(name); |
0ffc1a95 AP |
940 | } |
941 | ||
942 | static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) | |
943 | { | |
944 | char *name; | |
945 | MachineState *mc = MACHINE(s); | |
946 | hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; | |
947 | hwaddr flashbase = virt_memmap[VIRT_FLASH].base; | |
18df0b46 | 948 | |
58bde469 | 949 | name = g_strdup_printf("/flash@%" PRIx64, flashbase); |
c65d7080 AB |
950 | qemu_fdt_add_subnode(mc->fdt, name); |
951 | qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); | |
952 | qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", | |
71eb522c AF |
953 | 2, flashbase, 2, flashsize, |
954 | 2, flashbase + flashsize, 2, flashsize); | |
c65d7080 | 955 | qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); |
18df0b46 | 956 | g_free(name); |
0ffc1a95 AP |
957 | } |
958 | ||
959 | static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, | |
960 | uint64_t mem_size, const char *cmdline, bool is_32_bit) | |
961 | { | |
962 | MachineState *mc = MACHINE(s); | |
28d8c281 | 963 | uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; |
0ffc1a95 AP |
964 | uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; |
965 | ||
966 | if (mc->dtb) { | |
967 | mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); | |
968 | if (!mc->fdt) { | |
969 | error_report("load_device_tree() failed"); | |
970 | exit(1); | |
971 | } | |
972 | goto update_bootargs; | |
973 | } else { | |
974 | mc->fdt = create_device_tree(&s->fdt_size); | |
975 | if (!mc->fdt) { | |
976 | error_report("create_device_tree() failed"); | |
977 | exit(1); | |
978 | } | |
979 | } | |
980 | ||
981 | qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); | |
982 | qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); | |
983 | qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); | |
984 | qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); | |
985 | ||
986 | qemu_fdt_add_subnode(mc->fdt, "/soc"); | |
987 | qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); | |
988 | qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); | |
989 | qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); | |
990 | qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); | |
991 | ||
992 | create_fdt_sockets(s, memmap, is_32_bit, &phandle, | |
28d8c281 AP |
993 | &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, |
994 | &msi_pcie_phandle); | |
0ffc1a95 AP |
995 | |
996 | create_fdt_virtio(s, memmap, irq_virtio_phandle); | |
997 | ||
28d8c281 | 998 | create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); |
0ffc1a95 AP |
999 | |
1000 | create_fdt_reset(s, memmap, &phandle); | |
1001 | ||
1002 | create_fdt_uart(s, memmap, irq_mmio_phandle); | |
1003 | ||
1004 | create_fdt_rtc(s, memmap, irq_mmio_phandle); | |
1005 | ||
1006 | create_fdt_flash(s, memmap); | |
4e1e3003 AP |
1007 | |
1008 | update_bootargs: | |
58303fc0 | 1009 | if (cmdline && *cmdline) { |
0ffc1a95 | 1010 | qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); |
4e1e3003 | 1011 | } |
04331d0b MC |
1012 | } |
1013 | ||
6d56e396 AF |
1014 | static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, |
1015 | hwaddr ecam_base, hwaddr ecam_size, | |
1016 | hwaddr mmio_base, hwaddr mmio_size, | |
19800265 BM |
1017 | hwaddr high_mmio_base, |
1018 | hwaddr high_mmio_size, | |
6d56e396 | 1019 | hwaddr pio_base, |
e6faee65 | 1020 | DeviceState *irqchip) |
6d56e396 AF |
1021 | { |
1022 | DeviceState *dev; | |
1023 | MemoryRegion *ecam_alias, *ecam_reg; | |
19800265 | 1024 | MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; |
6d56e396 AF |
1025 | qemu_irq irq; |
1026 | int i; | |
1027 | ||
3e80f690 | 1028 | dev = qdev_new(TYPE_GPEX_HOST); |
6d56e396 | 1029 | |
3c6ef471 | 1030 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
6d56e396 AF |
1031 | |
1032 | ecam_alias = g_new0(MemoryRegion, 1); | |
1033 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
1034 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
1035 | ecam_reg, 0, ecam_size); | |
1036 | memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); | |
1037 | ||
1038 | mmio_alias = g_new0(MemoryRegion, 1); | |
1039 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
1040 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
1041 | mmio_reg, mmio_base, mmio_size); | |
1042 | memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); | |
1043 | ||
19800265 BM |
1044 | /* Map high MMIO space */ |
1045 | high_mmio_alias = g_new0(MemoryRegion, 1); | |
1046 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
1047 | mmio_reg, high_mmio_base, high_mmio_size); | |
1048 | memory_region_add_subregion(get_system_memory(), high_mmio_base, | |
1049 | high_mmio_alias); | |
1050 | ||
6d56e396 AF |
1051 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); |
1052 | ||
1053 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
e6faee65 | 1054 | irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); |
6d56e396 AF |
1055 | |
1056 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); | |
1057 | gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); | |
1058 | } | |
1059 | ||
1060 | return dev; | |
1061 | } | |
1062 | ||
0489348d AC |
1063 | static FWCfgState *create_fw_cfg(const MachineState *mc) |
1064 | { | |
1065 | hwaddr base = virt_memmap[VIRT_FW_CFG].base; | |
1066 | hwaddr size = virt_memmap[VIRT_FW_CFG].size; | |
1067 | FWCfgState *fw_cfg; | |
1068 | char *nodename; | |
1069 | ||
1070 | fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, | |
1071 | &address_space_memory); | |
1072 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); | |
1073 | ||
1074 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
1075 | qemu_fdt_add_subnode(mc->fdt, nodename); | |
1076 | qemu_fdt_setprop_string(mc->fdt, nodename, | |
1077 | "compatible", "qemu,fw-cfg-mmio"); | |
1078 | qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", | |
1079 | 2, base, 2, size); | |
1080 | qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); | |
1081 | g_free(nodename); | |
1082 | return fw_cfg; | |
1083 | } | |
1084 | ||
e6faee65 AP |
1085 | static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, |
1086 | int base_hartid, int hart_count) | |
1087 | { | |
1088 | DeviceState *ret; | |
1089 | char *plic_hart_config; | |
1090 | ||
1091 | /* Per-socket PLIC hart topology configuration string */ | |
1092 | plic_hart_config = riscv_plic_hart_config_string(hart_count); | |
1093 | ||
1094 | /* Per-socket PLIC */ | |
1095 | ret = sifive_plic_create( | |
1096 | memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, | |
1097 | plic_hart_config, hart_count, base_hartid, | |
1098 | VIRT_IRQCHIP_NUM_SOURCES, | |
1099 | ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), | |
1100 | VIRT_PLIC_PRIORITY_BASE, | |
1101 | VIRT_PLIC_PENDING_BASE, | |
1102 | VIRT_PLIC_ENABLE_BASE, | |
1103 | VIRT_PLIC_ENABLE_STRIDE, | |
1104 | VIRT_PLIC_CONTEXT_BASE, | |
1105 | VIRT_PLIC_CONTEXT_STRIDE, | |
1106 | memmap[VIRT_PLIC].size); | |
1107 | ||
1108 | g_free(plic_hart_config); | |
1109 | ||
1110 | return ret; | |
1111 | } | |
1112 | ||
28d8c281 | 1113 | static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, |
e6faee65 AP |
1114 | const MemMapEntry *memmap, int socket, |
1115 | int base_hartid, int hart_count) | |
1116 | { | |
28d8c281 AP |
1117 | int i; |
1118 | hwaddr addr; | |
1119 | uint32_t guest_bits; | |
e6faee65 | 1120 | DeviceState *aplic_m; |
28d8c281 AP |
1121 | bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; |
1122 | ||
1123 | if (msimode) { | |
1124 | /* Per-socket M-level IMSICs */ | |
1125 | addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; | |
1126 | for (i = 0; i < hart_count; i++) { | |
1127 | riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), | |
1128 | base_hartid + i, true, 1, | |
1129 | VIRT_IRQCHIP_NUM_MSIS); | |
1130 | } | |
1131 | ||
1132 | /* Per-socket S-level IMSICs */ | |
1133 | guest_bits = imsic_num_bits(aia_guests + 1); | |
1134 | addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; | |
1135 | for (i = 0; i < hart_count; i++) { | |
1136 | riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), | |
1137 | base_hartid + i, false, 1 + aia_guests, | |
1138 | VIRT_IRQCHIP_NUM_MSIS); | |
1139 | } | |
1140 | } | |
e6faee65 AP |
1141 | |
1142 | /* Per-socket M-level APLIC */ | |
1143 | aplic_m = riscv_aplic_create( | |
1144 | memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, | |
1145 | memmap[VIRT_APLIC_M].size, | |
28d8c281 AP |
1146 | (msimode) ? 0 : base_hartid, |
1147 | (msimode) ? 0 : hart_count, | |
e6faee65 AP |
1148 | VIRT_IRQCHIP_NUM_SOURCES, |
1149 | VIRT_IRQCHIP_NUM_PRIO_BITS, | |
28d8c281 | 1150 | msimode, true, NULL); |
e6faee65 AP |
1151 | |
1152 | if (aplic_m) { | |
1153 | /* Per-socket S-level APLIC */ | |
1154 | riscv_aplic_create( | |
1155 | memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, | |
1156 | memmap[VIRT_APLIC_S].size, | |
28d8c281 AP |
1157 | (msimode) ? 0 : base_hartid, |
1158 | (msimode) ? 0 : hart_count, | |
e6faee65 AP |
1159 | VIRT_IRQCHIP_NUM_SOURCES, |
1160 | VIRT_IRQCHIP_NUM_PRIO_BITS, | |
28d8c281 | 1161 | msimode, false, aplic_m); |
e6faee65 AP |
1162 | } |
1163 | ||
1164 | return aplic_m; | |
1165 | } | |
1166 | ||
1832b7cb AF |
1167 | static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) |
1168 | { | |
1169 | DeviceState *dev; | |
1170 | SysBusDevice *sysbus; | |
1171 | const MemMapEntry *memmap = virt_memmap; | |
1172 | int i; | |
1173 | MemoryRegion *sysmem = get_system_memory(); | |
1174 | ||
1175 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); | |
1176 | dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); | |
1177 | qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); | |
1178 | qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); | |
1179 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | |
1180 | s->platform_bus_dev = dev; | |
1181 | ||
1182 | sysbus = SYS_BUS_DEVICE(dev); | |
1183 | for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { | |
1184 | int irq = VIRT_PLATFORM_BUS_IRQ + i; | |
1185 | sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); | |
1186 | } | |
1187 | ||
1188 | memory_region_add_subregion(sysmem, | |
1189 | memmap[VIRT_PLATFORM_BUS].base, | |
1190 | sysbus_mmio_get_region(sysbus, 0)); | |
1191 | } | |
1192 | ||
1c20d3ff AF |
1193 | static void virt_machine_done(Notifier *notifier, void *data) |
1194 | { | |
1195 | RISCVVirtState *s = container_of(notifier, RISCVVirtState, | |
1196 | machine_done); | |
1197 | const MemMapEntry *memmap = virt_memmap; | |
1198 | MachineState *machine = MACHINE(s); | |
1199 | target_ulong start_addr = memmap[VIRT_DRAM].base; | |
1200 | target_ulong firmware_end_addr, kernel_start_addr; | |
1201 | uint32_t fdt_load_addr; | |
1202 | uint64_t kernel_entry; | |
1203 | ||
1204 | /* | |
1205 | * Only direct boot kernel is currently supported for KVM VM, | |
1206 | * so the "-bios" parameter is not supported when KVM is enabled. | |
1207 | */ | |
1208 | if (kvm_enabled()) { | |
1209 | if (machine->firmware) { | |
1210 | if (strcmp(machine->firmware, "none")) { | |
1211 | error_report("Machine mode firmware is not supported in " | |
1212 | "combination with KVM."); | |
1213 | exit(1); | |
1214 | } | |
1215 | } else { | |
1216 | machine->firmware = g_strdup("none"); | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | if (riscv_is_32bit(&s->soc[0])) { | |
1221 | firmware_end_addr = riscv_find_and_load_firmware(machine, | |
1222 | RISCV32_BIOS_BIN, start_addr, NULL); | |
1223 | } else { | |
1224 | firmware_end_addr = riscv_find_and_load_firmware(machine, | |
1225 | RISCV64_BIOS_BIN, start_addr, NULL); | |
1226 | } | |
1227 | ||
1228 | if (machine->kernel_filename) { | |
1229 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], | |
1230 | firmware_end_addr); | |
1231 | ||
1232 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | |
1233 | kernel_start_addr, NULL); | |
1234 | ||
1235 | if (machine->initrd_filename) { | |
1236 | hwaddr start; | |
1237 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
1238 | machine->ram_size, kernel_entry, | |
1239 | &start); | |
1240 | qemu_fdt_setprop_cell(machine->fdt, "/chosen", | |
1241 | "linux,initrd-start", start); | |
1242 | qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", | |
1243 | end); | |
1244 | } | |
1245 | } else { | |
1246 | /* | |
1247 | * If dynamic firmware is used, it doesn't know where is the next mode | |
1248 | * if kernel argument is not set. | |
1249 | */ | |
1250 | kernel_entry = 0; | |
1251 | } | |
1252 | ||
1253 | if (drive_get(IF_PFLASH, 0, 0)) { | |
1254 | /* | |
1255 | * Pflash was supplied, let's overwrite the address we jump to after | |
1256 | * reset to the base of the flash. | |
1257 | */ | |
1258 | start_addr = virt_memmap[VIRT_FLASH].base; | |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device | |
1263 | * tree cannot be altered and we get FDT_ERR_NOSPACE. | |
1264 | */ | |
1265 | s->fw_cfg = create_fw_cfg(machine); | |
1266 | rom_set_fw(s->fw_cfg); | |
1267 | ||
1268 | /* Compute the fdt load address in dram */ | |
1269 | fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, | |
1270 | machine->ram_size, machine->fdt); | |
1271 | /* load the reset vector */ | |
1272 | riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, | |
1273 | virt_memmap[VIRT_MROM].base, | |
1274 | virt_memmap[VIRT_MROM].size, kernel_entry, | |
1275 | fdt_load_addr, machine->fdt); | |
1276 | ||
1277 | /* | |
1278 | * Only direct boot kernel is currently supported for KVM VM, | |
1279 | * So here setup kernel start address and fdt address. | |
1280 | * TODO:Support firmware loading and integrate to TCG start | |
1281 | */ | |
1282 | if (kvm_enabled()) { | |
1283 | riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); | |
1284 | } | |
1285 | } | |
1286 | ||
b2a3a071 | 1287 | static void virt_machine_init(MachineState *machine) |
04331d0b | 1288 | { |
73261285 | 1289 | const MemMapEntry *memmap = virt_memmap; |
cdfc19e4 | 1290 | RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); |
04331d0b | 1291 | MemoryRegion *system_memory = get_system_memory(); |
5aec3247 | 1292 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); |
e6faee65 | 1293 | char *soc_name; |
e6faee65 | 1294 | DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; |
33fcedfa | 1295 | int i, base_hartid, hart_count; |
04331d0b | 1296 | |
18df0b46 AP |
1297 | /* Check socket count limit */ |
1298 | if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { | |
1299 | error_report("number of sockets/nodes should be less than %d", | |
1300 | VIRT_SOCKETS_MAX); | |
1301 | exit(1); | |
1302 | } | |
1303 | ||
1304 | /* Initialize sockets */ | |
e6faee65 | 1305 | mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; |
18df0b46 AP |
1306 | for (i = 0; i < riscv_socket_count(machine); i++) { |
1307 | if (!riscv_socket_check_hartids(machine, i)) { | |
1308 | error_report("discontinuous hartids in socket%d", i); | |
1309 | exit(1); | |
1310 | } | |
1311 | ||
1312 | base_hartid = riscv_socket_first_hartid(machine, i); | |
1313 | if (base_hartid < 0) { | |
1314 | error_report("can't find hartid base for socket%d", i); | |
1315 | exit(1); | |
1316 | } | |
1317 | ||
1318 | hart_count = riscv_socket_hart_count(machine, i); | |
1319 | if (hart_count < 0) { | |
1320 | error_report("can't find hart count for socket%d", i); | |
1321 | exit(1); | |
1322 | } | |
1323 | ||
1324 | soc_name = g_strdup_printf("soc%d", i); | |
1325 | object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], | |
1326 | TYPE_RISCV_HART_ARRAY); | |
1327 | g_free(soc_name); | |
1328 | object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", | |
1329 | machine->cpu_type, &error_abort); | |
1330 | object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", | |
1331 | base_hartid, &error_abort); | |
1332 | object_property_set_int(OBJECT(&s->soc[i]), "num-harts", | |
1333 | hart_count, &error_abort); | |
1334 | sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); | |
1335 | ||
ad40be27 | 1336 | if (!kvm_enabled()) { |
ad40be27 | 1337 | if (s->have_aclint) { |
28d8c281 AP |
1338 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
1339 | /* Per-socket ACLINT MTIMER */ | |
1340 | riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + | |
1341 | i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, | |
1342 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, | |
1343 | base_hartid, hart_count, | |
1344 | RISCV_ACLINT_DEFAULT_MTIMECMP, | |
1345 | RISCV_ACLINT_DEFAULT_MTIME, | |
1346 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); | |
1347 | } else { | |
1348 | /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ | |
1349 | riscv_aclint_swi_create(memmap[VIRT_CLINT].base + | |
1350 | i * memmap[VIRT_CLINT].size, | |
1351 | base_hartid, hart_count, false); | |
1352 | riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + | |
1353 | i * memmap[VIRT_CLINT].size + | |
1354 | RISCV_ACLINT_SWI_SIZE, | |
1355 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, | |
1356 | base_hartid, hart_count, | |
1357 | RISCV_ACLINT_DEFAULT_MTIMECMP, | |
1358 | RISCV_ACLINT_DEFAULT_MTIME, | |
1359 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); | |
1360 | riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + | |
1361 | i * memmap[VIRT_ACLINT_SSWI].size, | |
1362 | base_hartid, hart_count, true); | |
1363 | } | |
1364 | } else { | |
1365 | /* Per-socket SiFive CLINT */ | |
ad40be27 | 1366 | riscv_aclint_swi_create( |
28d8c281 AP |
1367 | memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, |
1368 | base_hartid, hart_count, false); | |
1369 | riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + | |
1370 | i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, | |
1371 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, | |
1372 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, | |
1373 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); | |
ad40be27 | 1374 | } |
954886ea AP |
1375 | } |
1376 | ||
e6faee65 AP |
1377 | /* Per-socket interrupt controller */ |
1378 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { | |
1379 | s->irqchip[i] = virt_create_plic(memmap, i, | |
1380 | base_hartid, hart_count); | |
1381 | } else { | |
28d8c281 AP |
1382 | s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, |
1383 | memmap, i, base_hartid, | |
1384 | hart_count); | |
e6faee65 | 1385 | } |
18df0b46 | 1386 | |
e6faee65 | 1387 | /* Try to use different IRQCHIP instance based device type */ |
18df0b46 | 1388 | if (i == 0) { |
e6faee65 AP |
1389 | mmio_irqchip = s->irqchip[i]; |
1390 | virtio_irqchip = s->irqchip[i]; | |
1391 | pcie_irqchip = s->irqchip[i]; | |
18df0b46 AP |
1392 | } |
1393 | if (i == 1) { | |
e6faee65 AP |
1394 | virtio_irqchip = s->irqchip[i]; |
1395 | pcie_irqchip = s->irqchip[i]; | |
18df0b46 AP |
1396 | } |
1397 | if (i == 2) { | |
e6faee65 | 1398 | pcie_irqchip = s->irqchip[i]; |
18df0b46 AP |
1399 | } |
1400 | } | |
04331d0b | 1401 | |
cfeb8a17 BM |
1402 | if (riscv_is_32bit(&s->soc[0])) { |
1403 | #if HOST_LONG_BITS == 64 | |
1404 | /* limit RAM size in a 32-bit system */ | |
1405 | if (machine->ram_size > 10 * GiB) { | |
1406 | machine->ram_size = 10 * GiB; | |
1407 | error_report("Limiting RAM size to 10 GiB"); | |
1408 | } | |
1409 | #endif | |
19800265 BM |
1410 | virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; |
1411 | virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; | |
1412 | } else { | |
1413 | virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; | |
1414 | virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; | |
1415 | virt_high_pcie_memmap.base = | |
1416 | ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); | |
cfeb8a17 BM |
1417 | } |
1418 | ||
04331d0b | 1419 | /* register system main memory (actual RAM) */ |
04331d0b | 1420 | memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, |
03fd0c5f | 1421 | machine->ram); |
04331d0b | 1422 | |
04331d0b | 1423 | /* boot rom */ |
5aec3247 MC |
1424 | memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", |
1425 | memmap[VIRT_MROM].size, &error_fatal); | |
1426 | memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, | |
1427 | mask_rom); | |
04331d0b | 1428 | |
18df0b46 | 1429 | /* SiFive Test MMIO device */ |
04331d0b MC |
1430 | sifive_test_create(memmap[VIRT_TEST].base); |
1431 | ||
18df0b46 | 1432 | /* VirtIO MMIO devices */ |
04331d0b MC |
1433 | for (i = 0; i < VIRTIO_COUNT; i++) { |
1434 | sysbus_create_simple("virtio-mmio", | |
1435 | memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, | |
e6faee65 | 1436 | qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); |
04331d0b MC |
1437 | } |
1438 | ||
6d56e396 | 1439 | gpex_pcie_init(system_memory, |
2fa3c7b6 BM |
1440 | memmap[VIRT_PCIE_ECAM].base, |
1441 | memmap[VIRT_PCIE_ECAM].size, | |
1442 | memmap[VIRT_PCIE_MMIO].base, | |
1443 | memmap[VIRT_PCIE_MMIO].size, | |
19800265 BM |
1444 | virt_high_pcie_memmap.base, |
1445 | virt_high_pcie_memmap.size, | |
2fa3c7b6 | 1446 | memmap[VIRT_PCIE_PIO].base, |
e6faee65 | 1447 | DEVICE(pcie_irqchip)); |
6d56e396 | 1448 | |
1832b7cb AF |
1449 | create_platform_bus(s, DEVICE(mmio_irqchip)); |
1450 | ||
04331d0b | 1451 | serial_mm_init(system_memory, memmap[VIRT_UART0].base, |
e6faee65 | 1452 | 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, |
9bca0edb | 1453 | serial_hd(0), DEVICE_LITTLE_ENDIAN); |
b6aa6ced | 1454 | |
67b5ef30 | 1455 | sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, |
e6faee65 | 1456 | qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); |
67b5ef30 | 1457 | |
71eb522c AF |
1458 | virt_flash_create(s); |
1459 | ||
1460 | for (i = 0; i < ARRAY_SIZE(s->flash); i++) { | |
1461 | /* Map legacy -drive if=pflash to machine properties */ | |
1462 | pflash_cfi01_legacy_drive(s->flash[i], | |
1463 | drive_get(IF_PFLASH, 0, i)); | |
1464 | } | |
1465 | virt_flash_map(s, system_memory); | |
1c20d3ff AF |
1466 | |
1467 | /* create device tree */ | |
1468 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | |
1469 | riscv_is_32bit(&s->soc[0])); | |
1470 | ||
1471 | s->machine_done.notify = virt_machine_done; | |
1472 | qemu_add_machine_init_done_notifier(&s->machine_done); | |
04331d0b MC |
1473 | } |
1474 | ||
b2a3a071 | 1475 | static void virt_machine_instance_init(Object *obj) |
04331d0b | 1476 | { |
cdfc19e4 AF |
1477 | } |
1478 | ||
28d8c281 AP |
1479 | static char *virt_get_aia_guests(Object *obj, Error **errp) |
1480 | { | |
1481 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); | |
1482 | char val[32]; | |
1483 | ||
1484 | sprintf(val, "%d", s->aia_guests); | |
1485 | return g_strdup(val); | |
1486 | } | |
1487 | ||
1488 | static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) | |
1489 | { | |
1490 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); | |
1491 | ||
1492 | s->aia_guests = atoi(val); | |
1493 | if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { | |
1494 | error_setg(errp, "Invalid number of AIA IMSIC guests"); | |
1495 | error_append_hint(errp, "Valid values be between 0 and %d.\n", | |
1496 | VIRT_IRQCHIP_MAX_GUESTS); | |
1497 | } | |
1498 | } | |
1499 | ||
e6faee65 AP |
1500 | static char *virt_get_aia(Object *obj, Error **errp) |
1501 | { | |
1502 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); | |
1503 | const char *val; | |
1504 | ||
1505 | switch (s->aia_type) { | |
1506 | case VIRT_AIA_TYPE_APLIC: | |
1507 | val = "aplic"; | |
1508 | break; | |
28d8c281 AP |
1509 | case VIRT_AIA_TYPE_APLIC_IMSIC: |
1510 | val = "aplic-imsic"; | |
1511 | break; | |
e6faee65 AP |
1512 | default: |
1513 | val = "none"; | |
1514 | break; | |
1515 | }; | |
1516 | ||
1517 | return g_strdup(val); | |
1518 | } | |
1519 | ||
1520 | static void virt_set_aia(Object *obj, const char *val, Error **errp) | |
1521 | { | |
1522 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); | |
1523 | ||
1524 | if (!strcmp(val, "none")) { | |
1525 | s->aia_type = VIRT_AIA_TYPE_NONE; | |
1526 | } else if (!strcmp(val, "aplic")) { | |
1527 | s->aia_type = VIRT_AIA_TYPE_APLIC; | |
28d8c281 AP |
1528 | } else if (!strcmp(val, "aplic-imsic")) { |
1529 | s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; | |
e6faee65 AP |
1530 | } else { |
1531 | error_setg(errp, "Invalid AIA interrupt controller type"); | |
28d8c281 AP |
1532 | error_append_hint(errp, "Valid values are none, aplic, and " |
1533 | "aplic-imsic.\n"); | |
e6faee65 AP |
1534 | } |
1535 | } | |
1536 | ||
954886ea AP |
1537 | static bool virt_get_aclint(Object *obj, Error **errp) |
1538 | { | |
1539 | MachineState *ms = MACHINE(obj); | |
1540 | RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); | |
1541 | ||
1542 | return s->have_aclint; | |
1543 | } | |
1544 | ||
1545 | static void virt_set_aclint(Object *obj, bool value, Error **errp) | |
1546 | { | |
1547 | MachineState *ms = MACHINE(obj); | |
1548 | RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); | |
1549 | ||
1550 | s->have_aclint = value; | |
1551 | } | |
1552 | ||
b2a3a071 | 1553 | static void virt_machine_class_init(ObjectClass *oc, void *data) |
cdfc19e4 | 1554 | { |
28d8c281 | 1555 | char str[128]; |
cdfc19e4 AF |
1556 | MachineClass *mc = MACHINE_CLASS(oc); |
1557 | ||
1558 | mc->desc = "RISC-V VirtIO board"; | |
b2a3a071 | 1559 | mc->init = virt_machine_init; |
18df0b46 | 1560 | mc->max_cpus = VIRT_CPUS_MAX; |
09fe1712 | 1561 | mc->default_cpu_type = TYPE_RISCV_CPU_BASE; |
acead54c | 1562 | mc->pci_allow_0_address = true; |
18df0b46 AP |
1563 | mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; |
1564 | mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; | |
1565 | mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; | |
1566 | mc->numa_mem_supported = true; | |
03fd0c5f | 1567 | mc->default_ram_id = "riscv_virt_board.ram"; |
c346749e AC |
1568 | |
1569 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); | |
954886ea AP |
1570 | |
1571 | object_class_property_add_bool(oc, "aclint", virt_get_aclint, | |
1572 | virt_set_aclint); | |
1573 | object_class_property_set_description(oc, "aclint", | |
1574 | "Set on/off to enable/disable " | |
1575 | "emulating ACLINT devices"); | |
e6faee65 AP |
1576 | |
1577 | object_class_property_add_str(oc, "aia", virt_get_aia, | |
1578 | virt_set_aia); | |
1579 | object_class_property_set_description(oc, "aia", | |
1580 | "Set type of AIA interrupt " | |
1581 | "conttoller. Valid values are " | |
28d8c281 AP |
1582 | "none, aplic, and aplic-imsic."); |
1583 | ||
1584 | object_class_property_add_str(oc, "aia-guests", | |
1585 | virt_get_aia_guests, | |
1586 | virt_set_aia_guests); | |
1587 | sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " | |
1588 | "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); | |
1589 | object_class_property_set_description(oc, "aia-guests", str); | |
04331d0b MC |
1590 | } |
1591 | ||
b2a3a071 | 1592 | static const TypeInfo virt_machine_typeinfo = { |
cdfc19e4 AF |
1593 | .name = MACHINE_TYPE_NAME("virt"), |
1594 | .parent = TYPE_MACHINE, | |
b2a3a071 BM |
1595 | .class_init = virt_machine_class_init, |
1596 | .instance_init = virt_machine_instance_init, | |
cdfc19e4 AF |
1597 | .instance_size = sizeof(RISCVVirtState), |
1598 | }; | |
1599 | ||
b2a3a071 | 1600 | static void virt_machine_init_register_types(void) |
cdfc19e4 | 1601 | { |
b2a3a071 | 1602 | type_register_static(&virt_machine_typeinfo); |
cdfc19e4 AF |
1603 | } |
1604 | ||
b2a3a071 | 1605 | type_init(virt_machine_init_register_types) |