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rtl8139: support byte read to TxStatus registers
[mirror_qemu.git] / hw / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
3ada003a 56#include "dma.h"
87ecb68b
PB		 57#include "qemu-timer.h"
58#include "net.h"
254111ec 59#include "loader.h"
1ca4d09a 60#include "sysemu.h"
bf6b87a8 61#include "iov.h"
a41b2ff2 62
a41b2ff2
PB		 63/* debug RTL8139 card */
64//#define DEBUG_RTL8139 1
65
6cadb320
FB		 66#define PCI_FREQUENCY 33000000L
67
a41b2ff2
PB		 68#define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71/* arg % size for size which is a power of 2 */
72#define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
18dabfd1
BP		 75#define ETHER_ADDR_LEN 6
76#define ETHER_TYPE_LEN 2
77#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78#define ETH_P_IP 0x0800 /* Internet Protocol packet */
79#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80#define ETH_MTU 1500
81
82#define VLAN_TCI_LEN 2
83#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
6cadb320 85#if defined (DEBUG_RTL8139)
7cdeb319
BP		 86# define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 88#else
c6a0487b 89static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 90{
91 return 0;
92}
6cadb320
FB		 93#endif
94
a41b2ff2
PB		 95/* Symbolic offsets to registers. */
96enum RTL8139_registers {
97 MAC0 = 0, /* Ethernet hardware address. */
98 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 99 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
100 /* Dump Tally Conter control register(64bit). C+ mode only */
101 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 102 RxBuf = 0x30,
103 ChipCmd = 0x37,
104 RxBufPtr = 0x38,
105 RxBufAddr = 0x3A,
106 IntrMask = 0x3C,
107 IntrStatus = 0x3E,
108 TxConfig = 0x40,
109 RxConfig = 0x44,
110 Timer = 0x48, /* A general-purpose counter. */
111 RxMissed = 0x4C, /* 24 bits valid, write clears. */
112 Cfg9346 = 0x50,
113 Config0 = 0x51,
114 Config1 = 0x52,
115 FlashReg = 0x54,
116 MediaStatus = 0x58,
117 Config3 = 0x59,
118 Config4 = 0x5A, /* absent on RTL-8139A */
119 HltClk = 0x5B,
120 MultiIntr = 0x5C,
121 PCIRevisionID = 0x5E,
122 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
123 BasicModeCtrl = 0x62,
124 BasicModeStatus = 0x64,
125 NWayAdvert = 0x66,
126 NWayLPAR = 0x68,
127 NWayExpansion = 0x6A,
128 /* Undocumented registers, but required for proper operation. */
129 FIFOTMS = 0x70, /* FIFO Control and test. */
130 CSCR = 0x74, /* Chip Status and Configuration Register. */
131 PARA78 = 0x78,
132 PARA7c = 0x7c, /* Magic transceiver parameter register. */
133 Config5 = 0xD8, /* absent on RTL-8139A */
134 /* C+ mode */
135 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
136 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
137 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
138 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
139 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
140 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
141 TxThresh = 0xEC, /* Early Tx threshold */
142};
143
144enum ClearBitMasks {
145 MultiIntrClear = 0xF000,
146 ChipCmdClear = 0xE2,
147 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148};
149
150enum ChipCmdBits {
151 CmdReset = 0x10,
152 CmdRxEnb = 0x08,
153 CmdTxEnb = 0x04,
154 RxBufEmpty = 0x01,
155};
156
157/* C+ mode */
158enum CplusCmdBits {
6cadb320
FB		 159 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
160 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
161 CPlusRxEnb = 0x0002,
162 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 163};
164
165/* Interrupt register bits, using my own meaningful names. */
166enum IntrStatusBits {
167 PCIErr = 0x8000,
168 PCSTimeout = 0x4000,
169 RxFIFOOver = 0x40,
170 RxUnderrun = 0x20,
171 RxOverflow = 0x10,
172 TxErr = 0x08,
173 TxOK = 0x04,
174 RxErr = 0x02,
175 RxOK = 0x01,
176
177 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
178};
179
180enum TxStatusBits {
181 TxHostOwns = 0x2000,
182 TxUnderrun = 0x4000,
183 TxStatOK = 0x8000,
184 TxOutOfWindow = 0x20000000,
185 TxAborted = 0x40000000,
186 TxCarrierLost = 0x80000000,
187};
188enum RxStatusBits {
189 RxMulticast = 0x8000,
190 RxPhysical = 0x4000,
191 RxBroadcast = 0x2000,
192 RxBadSymbol = 0x0020,
193 RxRunt = 0x0010,
194 RxTooLong = 0x0008,
195 RxCRCErr = 0x0004,
196 RxBadAlign = 0x0002,
197 RxStatusOK = 0x0001,
198};
199
200/* Bits in RxConfig. */
201enum rx_mode_bits {
202 AcceptErr = 0x20,
203 AcceptRunt = 0x10,
204 AcceptBroadcast = 0x08,
205 AcceptMulticast = 0x04,
206 AcceptMyPhys = 0x02,
207 AcceptAllPhys = 0x01,
208};
209
210/* Bits in TxConfig. */
211enum tx_config_bits {
212
213 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
214 TxIFGShift = 24,
215 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
216 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
217 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
218 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
219
220 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
221 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
222 TxClearAbt = (1 << 0), /* Clear abort (WO) */
223 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
224 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
225
226 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
227};
228
229
230/* Transmit Status of All Descriptors (TSAD) Register */
231enum TSAD_bits {
232 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
233 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
234 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
235 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
236 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
237 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
238 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
239 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
240 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
241 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
242 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
243 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
244 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
245 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
246 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
247 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
248};
249
250
251/* Bits in Config1 */
252enum Config1Bits {
253 Cfg1_PM_Enable = 0x01,
254 Cfg1_VPD_Enable = 0x02,
255 Cfg1_PIO = 0x04,
256 Cfg1_MMIO = 0x08,
257 LWAKE = 0x10, /* not on 8139, 8139A */
258 Cfg1_Driver_Load = 0x20,
259 Cfg1_LED0 = 0x40,
260 Cfg1_LED1 = 0x80,
261 SLEEP = (1 << 1), /* only on 8139, 8139A */
262 PWRDN = (1 << 0), /* only on 8139, 8139A */
263};
264
265/* Bits in Config3 */
266enum Config3Bits {
267 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
268 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
269 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
270 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
271 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
272 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
273 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
274 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
275};
276
277/* Bits in Config4 */
278enum Config4Bits {
279 LWPTN = (1 << 2), /* not on 8139, 8139A */
280};
281
282/* Bits in Config5 */
283enum Config5Bits {
284 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
285 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
286 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
287 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
288 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
289 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
290 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
291};
292
293enum RxConfigBits {
294 /* rx fifo threshold */
295 RxCfgFIFOShift = 13,
296 RxCfgFIFONone = (7 << RxCfgFIFOShift),
297
298 /* Max DMA burst */
299 RxCfgDMAShift = 8,
300 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
301
302 /* rx ring buffer length */
303 RxCfgRcv8K = 0,
304 RxCfgRcv16K = (1 << 11),
305 RxCfgRcv32K = (1 << 12),
306 RxCfgRcv64K = (1 << 11) | (1 << 12),
307
308 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
309 RxNoWrap = (1 << 7),
310};
311
312/* Twister tuning parameters from RealTek.
313 Completely undocumented, but required to tune bad links on some boards. */
314/*
315enum CSCRBits {
316 CSCR_LinkOKBit = 0x0400,
317 CSCR_LinkChangeBit = 0x0800,
318 CSCR_LinkStatusBits = 0x0f000,
319 CSCR_LinkDownOffCmd = 0x003c0,
320 CSCR_LinkDownCmd = 0x0f3c0,
321*/
322enum CSCRBits {
5fafdf24 323 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 324 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
325 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
326 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 327 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 328 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
329 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
330 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
331 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
332};
333
334enum Cfg9346Bits {
335 Cfg9346_Lock = 0x00,
336 Cfg9346_Unlock = 0xC0,
337};
338
339typedef enum {
340 CH_8139 = 0,
341 CH_8139_K,
342 CH_8139A,
343 CH_8139A_G,
344 CH_8139B,
345 CH_8130,
346 CH_8139C,
347 CH_8100,
348 CH_8100B_8139D,
349 CH_8101,
c227f099 350} chip_t;
a41b2ff2
PB		 351
352enum chip_flags {
353 HasHltClk = (1 << 0),
354 HasLWake = (1 << 1),
355};
356
357#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
358 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
359#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
360
6cadb320
FB		 361#define RTL8139_PCI_REVID_8139 0x10
362#define RTL8139_PCI_REVID_8139CPLUS 0x20
363
364#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
365
a41b2ff2
PB		 366/* Size is 64 * 16bit words */
367#define EEPROM_9346_ADDR_BITS 6
368#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
369#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
370
371enum Chip9346Operation
372{
373 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
374 Chip9346_op_read = 0x80, /* 10 AAAAAA */
375 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
376 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
377 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
378 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
379 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
380};
381
382enum Chip9346Mode
383{
384 Chip9346_none = 0,
385 Chip9346_enter_command_mode,
386 Chip9346_read_command,
387 Chip9346_data_read, /* from output register */
388 Chip9346_data_write, /* to input register, then to contents at specified address */
389 Chip9346_data_write_all, /* to input register, then filling contents */
390};
391
392typedef struct EEprom9346
393{
394 uint16_t contents[EEPROM_9346_SIZE];
395 int mode;
396 uint32_t tick;
397 uint8_t address;
398 uint16_t input;
399 uint16_t output;
400
401 uint8_t eecs;
402 uint8_t eesk;
403 uint8_t eedi;
404 uint8_t eedo;
405} EEprom9346;
406
6cadb320
FB		 407typedef struct RTL8139TallyCounters
408{
409 /* Tally counters */
410 uint64_t TxOk;
411 uint64_t RxOk;
412 uint64_t TxERR;
413 uint32_t RxERR;
414 uint16_t MissPkt;
415 uint16_t FAE;
416 uint32_t Tx1Col;
417 uint32_t TxMCol;
418 uint64_t RxOkPhy;
419 uint64_t RxOkBrd;
420 uint32_t RxOkMul;
421 uint16_t TxAbt;
422 uint16_t TxUndrn;
423} RTL8139TallyCounters;
424
425/* Clears all tally counters */
426static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
427
a41b2ff2 428typedef struct RTL8139State {
efd6dd45 429 PCIDevice dev;
a41b2ff2
PB		 430 uint8_t phys[8]; /* mac address */
431 uint8_t mult[8]; /* multicast mask array */
432
6cadb320 433 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 434 uint32_t TxAddr[4]; /* TxAddr0 */
435 uint32_t RxBuf; /* Receive buffer */
436 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
437 uint32_t RxBufPtr;
438 uint32_t RxBufAddr;
439
440 uint16_t IntrStatus;
441 uint16_t IntrMask;
442
443 uint32_t TxConfig;
444 uint32_t RxConfig;
445 uint32_t RxMissed;
446
447 uint16_t CSCR;
448
449 uint8_t Cfg9346;
450 uint8_t Config0;
451 uint8_t Config1;
452 uint8_t Config3;
453 uint8_t Config4;
454 uint8_t Config5;
455
456 uint8_t clock_enabled;
457 uint8_t bChipCmdState;
458
459 uint16_t MultiIntr;
460
461 uint16_t BasicModeCtrl;
462 uint16_t BasicModeStatus;
463 uint16_t NWayAdvert;
464 uint16_t NWayLPAR;
465 uint16_t NWayExpansion;
466
467 uint16_t CpCmd;
468 uint8_t TxThresh;
469
1673ad51 470 NICState *nic;
254111ec 471 NICConf conf;
a41b2ff2
PB		 472
473 /* C ring mode */
474 uint32_t currTxDesc;
475
476 /* C+ mode */
2c3891ab
AL		 477 uint32_t cplus_enabled;
478
a41b2ff2
PB		 479 uint32_t currCPlusRxDesc;
480 uint32_t currCPlusTxDesc;
481
482 uint32_t RxRingAddrLO;
483 uint32_t RxRingAddrHI;
484
485 EEprom9346 eeprom;
6cadb320
FB		 486
487 uint32_t TCTR;
488 uint32_t TimerInt;
489 int64_t TCTR_base;
490
491 /* Tally counters */
492 RTL8139TallyCounters tally_counters;
493
494 /* Non-persistent data */
495 uint8_t *cplus_txbuffer;
496 int cplus_txbuffer_len;
497 int cplus_txbuffer_offset;
498
499 /* PCI interrupt timer */
500 QEMUTimer *timer;
05447803 501 int64_t TimerExpire;
6cadb320 502
bd80f3fc
AK		 503 MemoryRegion bar_io;
504 MemoryRegion bar_mem;
505
c574ba5a
AW		 506 /* Support migration to/from old versions */
507 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 508} RTL8139State;
509
3ada003a
EGM		 510/* Writes tally counters to memory via DMA */
511static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
512
05447803
FZ		 513static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
514
9596ebb7 515static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 516{
7cdeb319 517 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 518
519 switch (command & Chip9346_op_mask)
520 {
521 case Chip9346_op_read:
522 {
523 eeprom->address = command & EEPROM_9346_ADDR_MASK;
524 eeprom->output = eeprom->contents[eeprom->address];
525 eeprom->eedo = 0;
526 eeprom->tick = 0;
527 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 528 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
529 eeprom->address, eeprom->output);
a41b2ff2
PB		 530 }
531 break;
532
533 case Chip9346_op_write:
534 {
535 eeprom->address = command & EEPROM_9346_ADDR_MASK;
536 eeprom->input = 0;
537 eeprom->tick = 0;
538 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 539 DPRINTF("eeprom begin write to address 0x%02x\n",
540 eeprom->address);
a41b2ff2
PB		 541 }
542 break;
543 default:
544 eeprom->mode = Chip9346_none;
545 switch (command & Chip9346_op_ext_mask)
546 {
547 case Chip9346_op_write_enable:
7cdeb319 548 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 549 break;
550 case Chip9346_op_write_all:
7cdeb319 551 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 552 break;
553 case Chip9346_op_write_disable:
7cdeb319 554 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 555 break;
556 }
557 break;
558 }
559}
560
9596ebb7 561static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 562{
563 int bit = eeprom->eedi?1:0;
564
565 ++ eeprom->tick;
566
7cdeb319
BP		 567 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
568 eeprom->eedo);
a41b2ff2
PB		 569
570 switch (eeprom->mode)
571 {
572 case Chip9346_enter_command_mode:
573 if (bit)
574 {
575 eeprom->mode = Chip9346_read_command;
576 eeprom->tick = 0;
577 eeprom->input = 0;
7cdeb319 578 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 579 }
580 break;
581
582 case Chip9346_read_command:
583 eeprom->input = (eeprom->input << 1) | (bit & 1);
584 if (eeprom->tick == 8)
585 {
586 prom9346_decode_command(eeprom, eeprom->input & 0xff);
587 }
588 break;
589
590 case Chip9346_data_read:
591 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
592 eeprom->output <<= 1;
593 if (eeprom->tick == 16)
594 {
6cadb320
FB		 595#if 1
596 // the FreeBSD drivers (rl and re) don't explicitly toggle
597 // CS between reads (or does setting Cfg9346 to 0 count too?),
598 // so we need to enter wait-for-command state here
599 eeprom->mode = Chip9346_enter_command_mode;
600 eeprom->input = 0;
601 eeprom->tick = 0;
602
7cdeb319 603 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 604#else
605 // original behaviour
a41b2ff2
PB		 606 ++eeprom->address;
607 eeprom->address &= EEPROM_9346_ADDR_MASK;
608 eeprom->output = eeprom->contents[eeprom->address];
609 eeprom->tick = 0;
610
7cdeb319
BP		 611 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
612 eeprom->address, eeprom->output);
a41b2ff2
PB		 613#endif
614 }
615 break;
616
617 case Chip9346_data_write:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
7cdeb319
BP		 621 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
622 eeprom->address, eeprom->input);
6cadb320 623
a41b2ff2
PB		 624 eeprom->contents[eeprom->address] = eeprom->input;
625 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
626 eeprom->tick = 0;
627 eeprom->input = 0;
628 }
629 break;
630
631 case Chip9346_data_write_all:
632 eeprom->input = (eeprom->input << 1) | (bit & 1);
633 if (eeprom->tick == 16)
634 {
635 int i;
636 for (i = 0; i < EEPROM_9346_SIZE; i++)
637 {
638 eeprom->contents[i] = eeprom->input;
639 }
7cdeb319 640 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 641
a41b2ff2
PB		 642 eeprom->mode = Chip9346_enter_command_mode;
643 eeprom->tick = 0;
644 eeprom->input = 0;
645 }
646 break;
647
648 default:
649 break;
650 }
651}
652
9596ebb7 653static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 654{
655 EEprom9346 *eeprom = &s->eeprom;
656 if (!eeprom->eecs)
657 return 0;
658
659 return eeprom->eedo;
660}
661
9596ebb7
PB		 662/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
663static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 664{
665 EEprom9346 *eeprom = &s->eeprom;
666 uint8_t old_eecs = eeprom->eecs;
667 uint8_t old_eesk = eeprom->eesk;
668
669 eeprom->eecs = eecs;
670 eeprom->eesk = eesk;
671 eeprom->eedi = eedi;
672
7cdeb319
BP		 673 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
674 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 675
676 if (!old_eecs && eecs)
677 {
678 /* Synchronize start */
679 eeprom->tick = 0;
680 eeprom->input = 0;
681 eeprom->output = 0;
682 eeprom->mode = Chip9346_enter_command_mode;
683
7cdeb319 684 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 685 }
686
687 if (!eecs)
688 {
7cdeb319 689 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 690 return;
691 }
692
693 if (!old_eesk && eesk)
694 {
695 /* SK front rules */
696 prom9346_shift_clock(eeprom);
697 }
698}
699
700static void rtl8139_update_irq(RTL8139State *s)
701{
702 int isr;
703 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 704
7cdeb319
BP		 705 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
706 s->IntrMask);
6cadb320 707
efd6dd45 708 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 709}
710
711#define POLYNOMIAL 0x04c11db6
712
713/* From FreeBSD */
714/* XXX: optimize */
715static int compute_mcast_idx(const uint8_t *ep)
716{
717 uint32_t crc;
718 int carry, i, j;
719 uint8_t b;
720
721 crc = 0xffffffff;
722 for (i = 0; i < 6; i++) {
723 b = *ep++;
724 for (j = 0; j < 8; j++) {
725 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
726 crc <<= 1;
727 b >>= 1;
728 if (carry)
729 crc = ((crc ^ POLYNOMIAL) | carry);
730 }
731 }
732 return (crc >> 26);
733}
734
735static int rtl8139_RxWrap(RTL8139State *s)
736{
737 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
738 return (s->RxConfig & (1 << 7));
739}
740
741static int rtl8139_receiver_enabled(RTL8139State *s)
742{
743 return s->bChipCmdState & CmdRxEnb;
744}
745
746static int rtl8139_transmitter_enabled(RTL8139State *s)
747{
748 return s->bChipCmdState & CmdTxEnb;
749}
750
751static int rtl8139_cp_receiver_enabled(RTL8139State *s)
752{
753 return s->CpCmd & CPlusRxEnb;
754}
755
756static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
757{
758 return s->CpCmd & CPlusTxEnb;
759}
760
761static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
762{
763 if (s->RxBufAddr + size > s->RxBufferSize)
764 {
765 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
766
767 /* write packet data */
ccf1d14a 768 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 769 {
7cdeb319 770 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 771
772 if (size > wrapped)
773 {
3ada003a
EGM		 774 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
775 buf, size-wrapped);
a41b2ff2
PB		 776 }
777
778 /* reset buffer pointer */
779 s->RxBufAddr = 0;
780
3ada003a
EGM		 781 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
782 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 783
784 s->RxBufAddr = wrapped;
785
786 return;
787 }
788 }
789
790 /* non-wrapping path or overwrapping enabled */
3ada003a 791 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 792
793 s->RxBufAddr += size;
794}
795
796#define MIN_BUF_SIZE 60
3ada003a 797static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 798{
799#if TARGET_PHYS_ADDR_BITS > 32
c227f099 800 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 801#else
802 return low;
803#endif
804}
805
1673ad51 806static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 807{
1673ad51 808 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 809 int avail;
810
aa1f17c1 811 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 812 if (!s->clock_enabled)
813 return 1;
814 if (!rtl8139_receiver_enabled(s))
815 return 1;
816
817 if (rtl8139_cp_receiver_enabled(s)) {
818 /* ??? Flow control not implemented in c+ mode.
819 This is a hack to work around slirp deficiencies anyway. */
820 return 1;
821 } else {
822 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
823 s->RxBufferSize);
824 return (avail == 0 || avail >= 1514);
825 }
826}
827
1673ad51 828static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 829{
1673ad51 830 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 831 /* size is the length of the buffer passed to the driver */
4f1c942b 832 int size = size_;
18dabfd1 833 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 834
835 uint32_t packet_header = 0;
836
18dabfd1 837 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 838 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 839 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
840
7cdeb319 841 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 842
843 /* test if board clock is stopped */
844 if (!s->clock_enabled)
845 {
7cdeb319 846 DPRINTF("stopped ==========================\n");
4f1c942b 847 return -1;
a41b2ff2
PB		 848 }
849
850 /* first check if receiver is enabled */
851
852 if (!rtl8139_receiver_enabled(s))
853 {
7cdeb319 854 DPRINTF("receiver disabled ================\n");
4f1c942b 855 return -1;
a41b2ff2
PB		 856 }
857
858 /* XXX: check this */
859 if (s->RxConfig & AcceptAllPhys) {
860 /* promiscuous: receive all */
7cdeb319 861 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 862
863 } else {
864 if (!memcmp(buf, broadcast_macaddr, 6)) {
865 /* broadcast address */
866 if (!(s->RxConfig & AcceptBroadcast))
867 {
7cdeb319 868 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 869
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
872
4f1c942b 873 return size;
a41b2ff2
PB		 874 }
875
876 packet_header |= RxBroadcast;
877
7cdeb319 878 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 879
880 /* update tally counter */
881 ++s->tally_counters.RxOkBrd;
882
a41b2ff2
PB		 883 } else if (buf[0] & 0x01) {
884 /* multicast */
885 if (!(s->RxConfig & AcceptMulticast))
886 {
7cdeb319 887 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 888
889 /* update tally counter */
890 ++s->tally_counters.RxERR;
891
4f1c942b 892 return size;
a41b2ff2
PB		 893 }
894
895 int mcast_idx = compute_mcast_idx(buf);
896
897 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
898 {
7cdeb319 899 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 900
901 /* update tally counter */
902 ++s->tally_counters.RxERR;
903
4f1c942b 904 return size;
a41b2ff2
PB		 905 }
906
907 packet_header |= RxMulticast;
908
7cdeb319 909 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 910
911 /* update tally counter */
912 ++s->tally_counters.RxOkMul;
913
a41b2ff2 914 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 915 s->phys[1] == buf[1] &&
916 s->phys[2] == buf[2] &&
917 s->phys[3] == buf[3] &&
918 s->phys[4] == buf[4] &&
a41b2ff2
PB		 919 s->phys[5] == buf[5]) {
920 /* match */
921 if (!(s->RxConfig & AcceptMyPhys))
922 {
7cdeb319 923 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 924
925 /* update tally counter */
926 ++s->tally_counters.RxERR;
927
4f1c942b 928 return size;
a41b2ff2
PB		 929 }
930
931 packet_header |= RxPhysical;
932
7cdeb319 933 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 934
935 /* update tally counter */
936 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 937
938 } else {
939
7cdeb319 940 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 941
942 /* update tally counter */
943 ++s->tally_counters.RxERR;
944
4f1c942b 945 return size;
a41b2ff2
PB		 946 }
947 }
948
18dabfd1
BP		 949 /* if too small buffer, then expand it
950 * Include some tailroom in case a vlan tag is later removed. */
951 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 952 memcpy(buf1, buf, size);
18dabfd1 953 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 954 buf = buf1;
18dabfd1
BP		 955 if (size < MIN_BUF_SIZE) {
956 size = MIN_BUF_SIZE;
957 }
a41b2ff2
PB		 958 }
959
960 if (rtl8139_cp_receiver_enabled(s))
961 {
7cdeb319 962 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 963
964 /* begin C+ receiver mode */
965
966/* w0 ownership flag */
967#define CP_RX_OWN (1<<31)
968/* w0 end of ring flag */
969#define CP_RX_EOR (1<<30)
970/* w0 bits 0...12 : buffer size */
971#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
972/* w1 tag available flag */
973#define CP_RX_TAVA (1<<16)
974/* w1 bits 0...15 : VLAN tag */
975#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
976/* w2 low 32bit of Rx buffer ptr */
977/* w3 high 32bit of Rx buffer ptr */
978
979 int descriptor = s->currCPlusRxDesc;
3ada003a 980 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 981
982 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
983 cplus_rx_ring_desc += 16 * descriptor;
984
7cdeb319 985 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 986 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 987 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 988
989 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
990
a6a29eea 991 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
a41b2ff2 992 rxdw0 = le32_to_cpu(val);
a6a29eea 993 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 994 rxdw1 = le32_to_cpu(val);
a6a29eea 995 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 996 rxbufLO = le32_to_cpu(val);
a6a29eea 997 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 998 rxbufHI = le32_to_cpu(val);
999
7cdeb319
BP		 1000 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
1001 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 1002
1003 if (!(rxdw0 & CP_RX_OWN))
1004 {
7cdeb319
BP		 1005 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1006 descriptor);
6cadb320 1007
a41b2ff2
PB		 1008 s->IntrStatus |= RxOverflow;
1009 ++s->RxMissed;
6cadb320
FB		 1010
1011 /* update tally counter */
1012 ++s->tally_counters.RxERR;
1013 ++s->tally_counters.MissPkt;
1014
a41b2ff2 1015 rtl8139_update_irq(s);
4f1c942b 1016 return size_;
a41b2ff2
PB		 1017 }
1018
1019 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1020
18dabfd1
BP		 1021 /* write VLAN info to descriptor variables. */
1022 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1023 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1024 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1025 size -= VLAN_HLEN;
1026 /* if too small buffer, use the tailroom added duing expansion */
1027 if (size < MIN_BUF_SIZE) {
1028 size = MIN_BUF_SIZE;
1029 }
1030
1031 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1032 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1033 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1034 &dot1q_buf[ETHER_TYPE_LEN]);
1035
7cdeb319
BP		 1036 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1037 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1038 } else {
1039 /* reset VLAN tag flag */
1040 rxdw1 &= ~CP_RX_TAVA;
1041 }
1042
6cadb320
FB		 1043 /* TODO: scatter the packet over available receive ring descriptors space */
1044
a41b2ff2
PB		 1045 if (size+4 > rx_space)
1046 {
7cdeb319
BP		 1047 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1048 descriptor, rx_space, size);
6cadb320 1049
a41b2ff2
PB		 1050 s->IntrStatus |= RxOverflow;
1051 ++s->RxMissed;
6cadb320
FB		 1052
1053 /* update tally counter */
1054 ++s->tally_counters.RxERR;
1055 ++s->tally_counters.MissPkt;
1056
a41b2ff2 1057 rtl8139_update_irq(s);
4f1c942b 1058 return size_;
a41b2ff2
PB		 1059 }
1060
3ada003a 1061 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1062
1063 /* receive/copy to target memory */
18dabfd1 1064 if (dot1q_buf) {
3ada003a
EGM		 1065 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1066 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1067 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1068 size - 2 * ETHER_ADDR_LEN);
18dabfd1 1069 } else {
3ada003a 1070 pci_dma_write(&s->dev, rx_addr, buf, size);
18dabfd1 1071 }
a41b2ff2 1072
6cadb320
FB		 1073 if (s->CpCmd & CPlusRxChkSum)
1074 {
1075 /* do some packet checksumming */
1076 }
1077
a41b2ff2 1078 /* write checksum */
18dabfd1 1079 val = cpu_to_le32(crc32(0, buf, size_));
3ada003a 1080 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1081
1082/* first segment of received packet flag */
1083#define CP_RX_STATUS_FS (1<<29)
1084/* last segment of received packet flag */
1085#define CP_RX_STATUS_LS (1<<28)
1086/* multicast packet flag */
1087#define CP_RX_STATUS_MAR (1<<26)
1088/* physical-matching packet flag */
1089#define CP_RX_STATUS_PAM (1<<25)
1090/* broadcast packet flag */
1091#define CP_RX_STATUS_BAR (1<<24)
1092/* runt packet flag */
1093#define CP_RX_STATUS_RUNT (1<<19)
1094/* crc error flag */
1095#define CP_RX_STATUS_CRC (1<<18)
1096/* IP checksum error flag */
1097#define CP_RX_STATUS_IPF (1<<15)
1098/* UDP checksum error flag */
1099#define CP_RX_STATUS_UDPF (1<<14)
1100/* TCP checksum error flag */
1101#define CP_RX_STATUS_TCPF (1<<13)
1102
1103 /* transfer ownership to target */
1104 rxdw0 &= ~CP_RX_OWN;
1105
1106 /* set first segment bit */
1107 rxdw0 |= CP_RX_STATUS_FS;
1108
1109 /* set last segment bit */
1110 rxdw0 |= CP_RX_STATUS_LS;
1111
1112 /* set received packet type flags */
1113 if (packet_header & RxBroadcast)
1114 rxdw0 |= CP_RX_STATUS_BAR;
1115 if (packet_header & RxMulticast)
1116 rxdw0 |= CP_RX_STATUS_MAR;
1117 if (packet_header & RxPhysical)
1118 rxdw0 |= CP_RX_STATUS_PAM;
1119
1120 /* set received size */
1121 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1122 rxdw0 |= (size+4);
1123
a41b2ff2
PB		 1124 /* update ring data */
1125 val = cpu_to_le32(rxdw0);
3ada003a 1126 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1127 val = cpu_to_le32(rxdw1);
3ada003a 1128 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1129
6cadb320
FB		 1130 /* update tally counter */
1131 ++s->tally_counters.RxOk;
1132
a41b2ff2
PB		 1133 /* seek to next Rx descriptor */
1134 if (rxdw0 & CP_RX_EOR)
1135 {
1136 s->currCPlusRxDesc = 0;
1137 }
1138 else
1139 {
1140 ++s->currCPlusRxDesc;
1141 }
1142
7cdeb319 1143 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1144
1145 }
1146 else
1147 {
7cdeb319 1148 DPRINTF("in ring Rx mode ================\n");
6cadb320 1149
a41b2ff2
PB		 1150 /* begin ring receiver mode */
1151 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1152
1153 /* if receiver buffer is empty then avail == 0 */
1154
1155 if (avail != 0 && size + 8 >= avail)
1156 {
7cdeb319
BP		 1157 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1158 "read 0x%04x === available 0x%04x need 0x%04x\n",
1159 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1160
a41b2ff2
PB		 1161 s->IntrStatus |= RxOverflow;
1162 ++s->RxMissed;
1163 rtl8139_update_irq(s);
4f1c942b 1164 return size_;
a41b2ff2
PB		 1165 }
1166
1167 packet_header |= RxStatusOK;
1168
1169 packet_header |= (((size+4) << 16) & 0xffff0000);
1170
1171 /* write header */
1172 uint32_t val = cpu_to_le32(packet_header);
1173
1174 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1175
1176 rtl8139_write_buffer(s, buf, size);
1177
1178 /* write checksum */
ccf1d14a 1179 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1180 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1181
1182 /* correct buffer write pointer */
1183 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1184
1185 /* now we can signal we have received something */
1186
7cdeb319
BP		 1187 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1188 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1189 }
1190
1191 s->IntrStatus |= RxOK;
6cadb320
FB		 1192
1193 if (do_interrupt)
1194 {
1195 rtl8139_update_irq(s);
1196 }
4f1c942b
MM		 1197
1198 return size_;
6cadb320
FB		 1199}
1200
1673ad51 1201static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1202{
1673ad51 1203 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1204}
1205
1206static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1207{
1208 s->RxBufferSize = bufferSize;
1209 s->RxBufPtr = 0;
1210 s->RxBufAddr = 0;
1211}
1212
7f23f812 1213static void rtl8139_reset(DeviceState *d)
a41b2ff2 1214{
7f23f812 1215 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1216 int i;
1217
1218 /* restore MAC address */
254111ec 1219 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1220
1221 /* reset interrupt mask */
1222 s->IntrStatus = 0;
1223 s->IntrMask = 0;
1224
1225 rtl8139_update_irq(s);
1226
a41b2ff2
PB		 1227 /* mark all status registers as owned by host */
1228 for (i = 0; i < 4; ++i)
1229 {
1230 s->TxStatus[i] = TxHostOwns;
1231 }
1232
1233 s->currTxDesc = 0;
1234 s->currCPlusRxDesc = 0;
1235 s->currCPlusTxDesc = 0;
1236
1237 s->RxRingAddrLO = 0;
1238 s->RxRingAddrHI = 0;
1239
1240 s->RxBuf = 0;
1241
1242 rtl8139_reset_rxring(s, 8192);
1243
1244 /* ACK the reset */
1245 s->TxConfig = 0;
1246
1247#if 0
1248// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1249 s->clock_enabled = 0;
1250#else
6cadb320 1251 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1252 s->clock_enabled = 1;
1253#endif
1254
1255 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1256
1257 /* set initial state data */
1258 s->Config0 = 0x0; /* No boot ROM */
1259 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1260 s->Config3 = 0x1; /* fast back-to-back compatible */
1261 s->Config5 = 0x0;
1262
5fafdf24 1263 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1264
1265 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1266 s->cplus_enabled = 0;
1267
a41b2ff2
PB		 1268
1269// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1270// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1271 s->BasicModeCtrl = 0x1000; // autonegotiation
1272
1273 s->BasicModeStatus = 0x7809;
1274 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1275 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1276 s->BasicModeStatus |= 0x0004; /* link is up */
1277
1278 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1279 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1280 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1281
1282 /* also reset timer and disable timer interrupt */
1283 s->TCTR = 0;
1284 s->TimerInt = 0;
1285 s->TCTR_base = 0;
1286
1287 /* reset tally counters */
1288 RTL8139TallyCounters_clear(&s->tally_counters);
1289}
1290
b1d8e52e 1291static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1292{
1293 counters->TxOk = 0;
1294 counters->RxOk = 0;
1295 counters->TxERR = 0;
1296 counters->RxERR = 0;
1297 counters->MissPkt = 0;
1298 counters->FAE = 0;
1299 counters->Tx1Col = 0;
1300 counters->TxMCol = 0;
1301 counters->RxOkPhy = 0;
1302 counters->RxOkBrd = 0;
1303 counters->RxOkMul = 0;
1304 counters->TxAbt = 0;
1305 counters->TxUndrn = 0;
1306}
1307
3ada003a 1308static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1309{
3ada003a 1310 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1311 uint16_t val16;
1312 uint32_t val32;
1313 uint64_t val64;
1314
1315 val64 = cpu_to_le64(tally_counters->TxOk);
3ada003a 1316 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1317
1318 val64 = cpu_to_le64(tally_counters->RxOk);
3ada003a 1319 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1320
1321 val64 = cpu_to_le64(tally_counters->TxERR);
3ada003a 1322 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1323
1324 val32 = cpu_to_le32(tally_counters->RxERR);
3ada003a 1325 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1326
1327 val16 = cpu_to_le16(tally_counters->MissPkt);
3ada003a 1328 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1329
1330 val16 = cpu_to_le16(tally_counters->FAE);
3ada003a 1331 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1332
1333 val32 = cpu_to_le32(tally_counters->Tx1Col);
3ada003a 1334 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1335
1336 val32 = cpu_to_le32(tally_counters->TxMCol);
3ada003a 1337 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1338
1339 val64 = cpu_to_le64(tally_counters->RxOkPhy);
3ada003a 1340 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1341
1342 val64 = cpu_to_le64(tally_counters->RxOkBrd);
3ada003a 1343 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1344
1345 val32 = cpu_to_le32(tally_counters->RxOkMul);
3ada003a 1346 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1347
1348 val16 = cpu_to_le16(tally_counters->TxAbt);
3ada003a 1349 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1350
1351 val16 = cpu_to_le16(tally_counters->TxUndrn);
3ada003a 1352 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1353}
1354
1355/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1356
1357static const VMStateDescription vmstate_tally_counters = {
1358 .name = "tally_counters",
1359 .version_id = 1,
1360 .minimum_version_id = 1,
1361 .minimum_version_id_old = 1,
1362 .fields = (VMStateField []) {
1363 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1364 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1365 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1366 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1367 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1368 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1369 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1370 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1371 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1372 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1373 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1374 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1375 VMSTATE_END_OF_LIST()
1376 }
1377};
a41b2ff2
PB		 1378
1379static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1380{
1381 val &= 0xff;
1382
7cdeb319 1383 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1384
1385 if (val & CmdReset)
1386 {
7cdeb319 1387 DPRINTF("ChipCmd reset\n");
7f23f812 1388 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1389 }
1390 if (val & CmdRxEnb)
1391 {
7cdeb319 1392 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1393
1394 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1395 }
1396 if (val & CmdTxEnb)
1397 {
7cdeb319 1398 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1399
1400 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1401 }
1402
ebabb67a 1403 /* mask unwritable bits */
a41b2ff2
PB		 1404 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1405
1406 /* Deassert reset pin before next read */
1407 val &= ~CmdReset;
1408
1409 s->bChipCmdState = val;
1410}
1411
1412static int rtl8139_RxBufferEmpty(RTL8139State *s)
1413{
1414 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1415
1416 if (unread != 0)
1417 {
7cdeb319 1418 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1419 return 0;
1420 }
1421
7cdeb319 1422 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1423
1424 return 1;
1425}
1426
1427static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1428{
1429 uint32_t ret = s->bChipCmdState;
1430
1431 if (rtl8139_RxBufferEmpty(s))
1432 ret |= RxBufEmpty;
1433
7cdeb319 1434 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1435
1436 return ret;
1437}
1438
1439static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1440{
1441 val &= 0xffff;
1442
7cdeb319 1443 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1444
2c3891ab
AL		 1445 s->cplus_enabled = 1;
1446
ebabb67a 1447 /* mask unwritable bits */
a41b2ff2
PB		 1448 val = SET_MASKED(val, 0xff84, s->CpCmd);
1449
1450 s->CpCmd = val;
1451}
1452
1453static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1454{
1455 uint32_t ret = s->CpCmd;
1456
7cdeb319 1457 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1458
1459 return ret;
1460}
1461
1462static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1463{
7cdeb319 1464 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1465}
1466
1467static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1468{
1469 uint32_t ret = 0;
1470
7cdeb319 1471 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1472
1473 return ret;
1474}
1475
ebabb67a 1476static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2
PB		 1477{
1478 if (s->Cfg9346 & Cfg9346_Unlock)
1479 {
1480 return 1;
1481 }
1482
7cdeb319 1483 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1484
1485 return 0;
1486}
1487
1488static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1489{
1490 val &= 0xffff;
1491
7cdeb319 1492 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1493
ebabb67a 1494 /* mask unwritable bits */
e3d7e843 1495 uint32_t mask = 0x4cff;
a41b2ff2 1496
ebabb67a 1497 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1498 {
1499 /* Speed setting and autonegotiation enable bits are read-only */
1500 mask |= 0x3000;
1501 /* Duplex mode setting is read-only */
1502 mask |= 0x0100;
1503 }
1504
1505 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1506
1507 s->BasicModeCtrl = val;
1508}
1509
1510static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1511{
1512 uint32_t ret = s->BasicModeCtrl;
1513
7cdeb319 1514 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1515
1516 return ret;
1517}
1518
1519static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1520{
1521 val &= 0xffff;
1522
7cdeb319 1523 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1524
ebabb67a 1525 /* mask unwritable bits */
a41b2ff2
PB		 1526 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1527
1528 s->BasicModeStatus = val;
1529}
1530
1531static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1532{
1533 uint32_t ret = s->BasicModeStatus;
1534
7cdeb319 1535 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1536
1537 return ret;
1538}
1539
1540static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1541{
1542 val &= 0xff;
1543
7cdeb319 1544 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1545
ebabb67a 1546 /* mask unwritable bits */
a41b2ff2
PB		 1547 val = SET_MASKED(val, 0x31, s->Cfg9346);
1548
1549 uint32_t opmode = val & 0xc0;
1550 uint32_t eeprom_val = val & 0xf;
1551
1552 if (opmode == 0x80) {
1553 /* eeprom access */
1554 int eecs = (eeprom_val & 0x08)?1:0;
1555 int eesk = (eeprom_val & 0x04)?1:0;
1556 int eedi = (eeprom_val & 0x02)?1:0;
1557 prom9346_set_wire(s, eecs, eesk, eedi);
1558 } else if (opmode == 0x40) {
1559 /* Reset. */
1560 val = 0;
7f23f812 1561 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1562 }
1563
1564 s->Cfg9346 = val;
1565}
1566
1567static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1568{
1569 uint32_t ret = s->Cfg9346;
1570
1571 uint32_t opmode = ret & 0xc0;
1572
1573 if (opmode == 0x80)
1574 {
1575 /* eeprom access */
1576 int eedo = prom9346_get_wire(s);
1577 if (eedo)
1578 {
1579 ret |= 0x01;
1580 }
1581 else
1582 {
1583 ret &= ~0x01;
1584 }
1585 }
1586
7cdeb319 1587 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1588
1589 return ret;
1590}
1591
1592static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1593{
1594 val &= 0xff;
1595
7cdeb319 1596 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1597
ebabb67a 1598 if (!rtl8139_config_writable(s)) {
a41b2ff2 1599 return;
ebabb67a 1600 }
a41b2ff2 1601
ebabb67a 1602 /* mask unwritable bits */
a41b2ff2
PB		 1603 val = SET_MASKED(val, 0xf8, s->Config0);
1604
1605 s->Config0 = val;
1606}
1607
1608static uint32_t rtl8139_Config0_read(RTL8139State *s)
1609{
1610 uint32_t ret = s->Config0;
1611
7cdeb319 1612 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1613
1614 return ret;
1615}
1616
1617static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1618{
1619 val &= 0xff;
1620
7cdeb319 1621 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1622
ebabb67a 1623 if (!rtl8139_config_writable(s)) {
a41b2ff2 1624 return;
ebabb67a 1625 }
a41b2ff2 1626
ebabb67a 1627 /* mask unwritable bits */
a41b2ff2
PB		 1628 val = SET_MASKED(val, 0xC, s->Config1);
1629
1630 s->Config1 = val;
1631}
1632
1633static uint32_t rtl8139_Config1_read(RTL8139State *s)
1634{
1635 uint32_t ret = s->Config1;
1636
7cdeb319 1637 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1638
1639 return ret;
1640}
1641
1642static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1643{
1644 val &= 0xff;
1645
7cdeb319 1646 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1647
ebabb67a 1648 if (!rtl8139_config_writable(s)) {
a41b2ff2 1649 return;
ebabb67a 1650 }
a41b2ff2 1651
ebabb67a 1652 /* mask unwritable bits */
a41b2ff2
PB		 1653 val = SET_MASKED(val, 0x8F, s->Config3);
1654
1655 s->Config3 = val;
1656}
1657
1658static uint32_t rtl8139_Config3_read(RTL8139State *s)
1659{
1660 uint32_t ret = s->Config3;
1661
7cdeb319 1662 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1663
1664 return ret;
1665}
1666
1667static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1668{
1669 val &= 0xff;
1670
7cdeb319 1671 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1672
ebabb67a 1673 if (!rtl8139_config_writable(s)) {
a41b2ff2 1674 return;
ebabb67a 1675 }
a41b2ff2 1676
ebabb67a 1677 /* mask unwritable bits */
a41b2ff2
PB		 1678 val = SET_MASKED(val, 0x0a, s->Config4);
1679
1680 s->Config4 = val;
1681}
1682
1683static uint32_t rtl8139_Config4_read(RTL8139State *s)
1684{
1685 uint32_t ret = s->Config4;
1686
7cdeb319 1687 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1688
1689 return ret;
1690}
1691
1692static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1693{
1694 val &= 0xff;
1695
7cdeb319 1696 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1697
ebabb67a 1698 /* mask unwritable bits */
a41b2ff2
PB		 1699 val = SET_MASKED(val, 0x80, s->Config5);
1700
1701 s->Config5 = val;
1702}
1703
1704static uint32_t rtl8139_Config5_read(RTL8139State *s)
1705{
1706 uint32_t ret = s->Config5;
1707
7cdeb319 1708 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1709
1710 return ret;
1711}
1712
1713static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1714{
1715 if (!rtl8139_transmitter_enabled(s))
1716 {
7cdeb319 1717 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1718 return;
1719 }
1720
7cdeb319 1721 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1722
1723 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1724
1725 s->TxConfig = val;
1726}
1727
1728static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1729{
7cdeb319 1730 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1731
1732 uint32_t tc = s->TxConfig;
1733 tc &= 0xFFFFFF00;
1734 tc |= (val & 0x000000FF);
1735 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1736}
1737
1738static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1739{
1740 uint32_t ret = s->TxConfig;
1741
7cdeb319 1742 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1743
1744 return ret;
1745}
1746
1747static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1748{
7cdeb319 1749 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1750
ebabb67a 1751 /* mask unwritable bits */
a41b2ff2
PB		 1752 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1753
1754 s->RxConfig = val;
1755
1756 /* reset buffer size and read/write pointers */
1757 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1758
7cdeb319 1759 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1760}
1761
1762static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1763{
1764 uint32_t ret = s->RxConfig;
1765
7cdeb319 1766 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1767
1768 return ret;
1769}
1770
bf6b87a8
BP		 1771static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1772 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1773{
bf6b87a8
BP		 1774 struct iovec *iov = NULL;
1775
718da2b9
FB		 1776 if (!size)
1777 {
7cdeb319 1778 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1779 return;
1780 }
1781
bf6b87a8
BP		 1782 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1783 iov = (struct iovec[3]) {
1784 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1785 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1786 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1787 .iov_len = size - ETHER_ADDR_LEN * 2 },
1788 };
1789 }
1790
718da2b9
FB		 1791 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1792 {
bf6b87a8
BP		 1793 size_t buf2_size;
1794 uint8_t *buf2;
1795
1796 if (iov) {
1797 buf2_size = iov_size(iov, 3);
7267c094 1798 buf2 = g_malloc(buf2_size);
bf6b87a8
BP		 1799 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1800 buf = buf2;
1801 }
1802
7cdeb319 1803 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1804 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1805
1806 if (iov) {
7267c094 1807 g_free(buf2);
bf6b87a8 1808 }
718da2b9
FB		 1809 }
1810 else
1811 {
bf6b87a8
BP		 1812 if (iov) {
1813 qemu_sendv_packet(&s->nic->nc, iov, 3);
1814 } else {
1815 qemu_send_packet(&s->nic->nc, buf, size);
1816 }
718da2b9
FB		 1817 }
1818}
1819
a41b2ff2
PB		 1820static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1821{
1822 if (!rtl8139_transmitter_enabled(s))
1823 {
7cdeb319
BP		 1824 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1825 "disabled\n", descriptor);
a41b2ff2
PB		 1826 return 0;
1827 }
1828
1829 if (s->TxStatus[descriptor] & TxHostOwns)
1830 {
7cdeb319
BP		 1831 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1832 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1833 return 0;
1834 }
1835
7cdeb319 1836 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1837
1838 int txsize = s->TxStatus[descriptor] & 0x1fff;
1839 uint8_t txbuffer[0x2000];
1840
7cdeb319
BP		 1841 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1842 txsize, s->TxAddr[descriptor]);
a41b2ff2 1843
3ada003a 1844 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1845
1846 /* Mark descriptor as transferred */
1847 s->TxStatus[descriptor] |= TxHostOwns;
1848 s->TxStatus[descriptor] |= TxStatOK;
1849
bf6b87a8 1850 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1851
7cdeb319
BP		 1852 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1853 descriptor);
a41b2ff2
PB		 1854
1855 /* update interrupt */
1856 s->IntrStatus |= TxOK;
1857 rtl8139_update_irq(s);
1858
1859 return 1;
1860}
1861
718da2b9
FB		 1862/* structures and macros for task offloading */
1863typedef struct ip_header
1864{
1865 uint8_t ip_ver_len; /* version and header length */
1866 uint8_t ip_tos; /* type of service */
1867 uint16_t ip_len; /* total length */
1868 uint16_t ip_id; /* identification */
1869 uint16_t ip_off; /* fragment offset field */
1870 uint8_t ip_ttl; /* time to live */
1871 uint8_t ip_p; /* protocol */
1872 uint16_t ip_sum; /* checksum */
1873 uint32_t ip_src,ip_dst; /* source and dest address */
1874} ip_header;
1875
1876#define IP_HEADER_VERSION_4 4
1877#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1878#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1879
1880typedef struct tcp_header
1881{
1882 uint16_t th_sport; /* source port */
1883 uint16_t th_dport; /* destination port */
1884 uint32_t th_seq; /* sequence number */
1885 uint32_t th_ack; /* acknowledgement number */
1886 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1887 uint16_t th_win; /* window */
1888 uint16_t th_sum; /* checksum */
1889 uint16_t th_urp; /* urgent pointer */
1890} tcp_header;
1891
1892typedef struct udp_header
1893{
1894 uint16_t uh_sport; /* source port */
1895 uint16_t uh_dport; /* destination port */
1896 uint16_t uh_ulen; /* udp length */
1897 uint16_t uh_sum; /* udp checksum */
1898} udp_header;
1899
1900typedef struct ip_pseudo_header
1901{
1902 uint32_t ip_src;
1903 uint32_t ip_dst;
1904 uint8_t zeros;
1905 uint8_t ip_proto;
1906 uint16_t ip_payload;
1907} ip_pseudo_header;
1908
1909#define IP_PROTO_TCP 6
1910#define IP_PROTO_UDP 17
1911
1912#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1913#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1914#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1915
1916#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1917
1918#define TCP_FLAG_FIN 0x01
1919#define TCP_FLAG_PUSH 0x08
1920
1921/* produces ones' complement sum of data */
1922static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1923{
1924 uint32_t result = 0;
1925
1926 for (; len > 1; data+=2, len-=2)
1927 {
1928 result += *(uint16_t*)data;
1929 }
1930
1931 /* add the remainder byte */
1932 if (len)
1933 {
1934 uint8_t odd[2] = {*data, 0};
1935 result += *(uint16_t*)odd;
1936 }
1937
1938 while (result>>16)
1939 result = (result & 0xffff) + (result >> 16);
1940
1941 return result;
1942}
1943
1944static uint16_t ip_checksum(void *data, size_t len)
1945{
1946 return ~ones_complement_sum((uint8_t*)data, len);
1947}
1948
a41b2ff2
PB		 1949static int rtl8139_cplus_transmit_one(RTL8139State *s)
1950{
1951 if (!rtl8139_transmitter_enabled(s))
1952 {
7cdeb319 1953 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1954 return 0;
1955 }
1956
1957 if (!rtl8139_cp_transmitter_enabled(s))
1958 {
7cdeb319 1959 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1960 return 0 ;
1961 }
1962
1963 int descriptor = s->currCPlusTxDesc;
1964
3ada003a 1965 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1966
1967 /* Normal priority ring */
1968 cplus_tx_ring_desc += 16 * descriptor;
1969
7cdeb319 1970 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1971 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1972 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1973
1974 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1975
3ada003a 1976 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1977 txdw0 = le32_to_cpu(val);
3ada003a 1978 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1979 txdw1 = le32_to_cpu(val);
3ada003a 1980 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1981 txbufLO = le32_to_cpu(val);
3ada003a 1982 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1983 txbufHI = le32_to_cpu(val);
1984
7cdeb319
BP		 1985 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1986 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1987
1988/* w0 ownership flag */
1989#define CP_TX_OWN (1<<31)
1990/* w0 end of ring flag */
1991#define CP_TX_EOR (1<<30)
1992/* first segment of received packet flag */
1993#define CP_TX_FS (1<<29)
1994/* last segment of received packet flag */
1995#define CP_TX_LS (1<<28)
1996/* large send packet flag */
1997#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1998/* large send MSS mask, bits 16...25 */
1999#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
2000
a41b2ff2
PB		 2001/* IP checksum offload flag */
2002#define CP_TX_IPCS (1<<18)
2003/* UDP checksum offload flag */
2004#define CP_TX_UDPCS (1<<17)
2005/* TCP checksum offload flag */
2006#define CP_TX_TCPCS (1<<16)
2007
2008/* w0 bits 0...15 : buffer size */
2009#define CP_TX_BUFFER_SIZE (1<<16)
2010#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 2011/* w1 add tag flag */
2012#define CP_TX_TAGC (1<<17)
2013/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2014#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2015/* w2 low 32bit of Rx buffer ptr */
2016/* w3 high 32bit of Rx buffer ptr */
2017
2018/* set after transmission */
2019/* FIFO underrun flag */
2020#define CP_TX_STATUS_UNF (1<<25)
2021/* transmit error summary flag, valid if set any of three below */
2022#define CP_TX_STATUS_TES (1<<23)
2023/* out-of-window collision flag */
2024#define CP_TX_STATUS_OWC (1<<22)
2025/* link failure flag */
2026#define CP_TX_STATUS_LNKF (1<<21)
2027/* excessive collisions flag */
2028#define CP_TX_STATUS_EXC (1<<20)
2029
2030 if (!(txdw0 & CP_TX_OWN))
2031 {
7cdeb319 2032 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2033 return 0 ;
2034 }
2035
7cdeb319 2036 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2037
2038 if (txdw0 & CP_TX_FS)
2039 {
7cdeb319
BP		 2040 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2041 "descriptor\n", descriptor);
6cadb320
FB		 2042
2043 /* reset internal buffer offset */
2044 s->cplus_txbuffer_offset = 0;
2045 }
a41b2ff2
PB		 2046
2047 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 2048 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2049
6cadb320
FB		 2050 /* make sure we have enough space to assemble the packet */
2051 if (!s->cplus_txbuffer)
2052 {
2053 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 2054 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 2055 s->cplus_txbuffer_offset = 0;
718da2b9 2056
7cdeb319
BP		 2057 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2058 s->cplus_txbuffer_len);
6cadb320
FB		 2059 }
2060
cde31a0e 2061 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 2062 {
cde31a0e
JW		 2063 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2064 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2065 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2066 "length to %d\n", txsize);
6cadb320
FB		 2067 }
2068
2069 if (!s->cplus_txbuffer)
2070 {
2071 /* out of memory */
a41b2ff2 2072
7cdeb319
BP		 2073 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2074 s->cplus_txbuffer_len);
6cadb320
FB		 2075
2076 /* update tally counter */
2077 ++s->tally_counters.TxERR;
2078 ++s->tally_counters.TxAbt;
2079
2080 return 0;
2081 }
2082
2083 /* append more data to the packet */
2084
7cdeb319 2085 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2086 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2087 s->cplus_txbuffer_offset);
6cadb320 2088
3ada003a
EGM		 2089 pci_dma_read(&s->dev, tx_addr,
2090 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2091 s->cplus_txbuffer_offset += txsize;
2092
2093 /* seek to next Rx descriptor */
2094 if (txdw0 & CP_TX_EOR)
2095 {
2096 s->currCPlusTxDesc = 0;
2097 }
2098 else
2099 {
2100 ++s->currCPlusTxDesc;
2101 if (s->currCPlusTxDesc >= 64)
2102 s->currCPlusTxDesc = 0;
2103 }
a41b2ff2
PB		 2104
2105 /* transfer ownership to target */
2106 txdw0 &= ~CP_RX_OWN;
2107
2108 /* reset error indicator bits */
2109 txdw0 &= ~CP_TX_STATUS_UNF;
2110 txdw0 &= ~CP_TX_STATUS_TES;
2111 txdw0 &= ~CP_TX_STATUS_OWC;
2112 txdw0 &= ~CP_TX_STATUS_LNKF;
2113 txdw0 &= ~CP_TX_STATUS_EXC;
2114
2115 /* update ring data */
2116 val = cpu_to_le32(txdw0);
3ada003a 2117 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2118
6cadb320
FB		 2119 /* Now decide if descriptor being processed is holding the last segment of packet */
2120 if (txdw0 & CP_TX_LS)
a41b2ff2 2121 {
bf6b87a8
BP		 2122 uint8_t dot1q_buffer_space[VLAN_HLEN];
2123 uint16_t *dot1q_buffer;
2124
7cdeb319
BP		 2125 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2126 descriptor);
6cadb320
FB		 2127
2128 /* can transfer fully assembled packet */
2129
2130 uint8_t *saved_buffer = s->cplus_txbuffer;
2131 int saved_size = s->cplus_txbuffer_offset;
2132 int saved_buffer_len = s->cplus_txbuffer_len;
2133
bf6b87a8
BP		 2134 /* create vlan tag */
2135 if (txdw1 & CP_TX_TAGC) {
2136 /* the vlan tag is in BE byte order in the descriptor
2137 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2138 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2139 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2140
2141 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2142 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2143 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2144 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2145 } else {
2146 dot1q_buffer = NULL;
2147 }
2148
6cadb320
FB		 2149 /* reset the card space to protect from recursive call */
2150 s->cplus_txbuffer = NULL;
2151 s->cplus_txbuffer_offset = 0;
2152 s->cplus_txbuffer_len = 0;
2153
718da2b9 2154 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2155 {
7cdeb319 2156 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2157
6cadb320 2158 /* ip packet header */
660f11be 2159 ip_header *ip = NULL;
6cadb320 2160 int hlen = 0;
718da2b9
FB		 2161 uint8_t ip_protocol = 0;
2162 uint16_t ip_data_len = 0;
6cadb320 2163
660f11be 2164 uint8_t *eth_payload_data = NULL;
718da2b9 2165 size_t eth_payload_len = 0;
6cadb320 2166
718da2b9 2167 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2168 if (proto == ETH_P_IP)
2169 {
7cdeb319 2170 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2171
2172 /* not aligned */
718da2b9
FB		 2173 eth_payload_data = saved_buffer + ETH_HLEN;
2174 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2175
718da2b9 2176 ip = (ip_header*)eth_payload_data;
6cadb320 2177
718da2b9 2178 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2179 DPRINTF("+++ C+ mode packet has bad IP version %d "
2180 "expected %d\n", IP_HEADER_VERSION(ip),
2181 IP_HEADER_VERSION_4);
6cadb320
FB		 2182 ip = NULL;
2183 } else {
718da2b9
FB		 2184 hlen = IP_HEADER_LENGTH(ip);
2185 ip_protocol = ip->ip_p;
2186 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2187 }
2188 }
2189
2190 if (ip)
2191 {
2192 if (txdw0 & CP_TX_IPCS)
2193 {
7cdeb319 2194 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2195
718da2b9 2196 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2197 /* bad packet header len */
2198 /* or packet too short */
2199 }
2200 else
2201 {
2202 ip->ip_sum = 0;
718da2b9 2203 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2204 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2205 hlen, ip->ip_sum);
6cadb320
FB		 2206 }
2207 }
2208
718da2b9 2209 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2210 {
718da2b9 2211 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2212
7cdeb319
BP		 2213 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2214 "frame data %d specified MSS=%d\n", ETH_MTU,
2215 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2216
718da2b9
FB		 2217 int tcp_send_offset = 0;
2218 int send_count = 0;
6cadb320
FB		 2219
2220 /* maximum IP header length is 60 bytes */
2221 uint8_t saved_ip_header[60];
6cadb320 2222
718da2b9
FB		 2223 /* save IP header template; data area is used in tcp checksum calculation */
2224 memcpy(saved_ip_header, eth_payload_data, hlen);
2225
2226 /* a placeholder for checksum calculation routine in tcp case */
2227 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2228 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2229
2230 /* pointer to TCP header */
2231 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2232
2233 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2234
2235 /* ETH_MTU = ip header len + tcp header len + payload */
2236 int tcp_data_len = ip_data_len - tcp_hlen;
2237 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2238
7cdeb319
BP		 2239 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2240 "data len %d TCP chunk size %d\n", ip_data_len,
2241 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2242
2243 /* note the cycle below overwrites IP header data,
2244 but restores it from saved_ip_header before sending packet */
2245
2246 int is_last_frame = 0;
2247
2248 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2249 {
2250 uint16_t chunk_size = tcp_chunk_size;
2251
2252 /* check if this is the last frame */
2253 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2254 {
2255 is_last_frame = 1;
2256 chunk_size = tcp_data_len - tcp_send_offset;
2257 }
2258
7cdeb319
BP		 2259 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2260 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2261
2262 /* add 4 TCP pseudoheader fields */
2263 /* copy IP source and destination fields */
2264 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2265
7cdeb319
BP		 2266 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2267 "packet with %d bytes data\n", tcp_hlen +
2268 chunk_size);
718da2b9
FB		 2269
2270 if (tcp_send_offset)
2271 {
2272 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2273 }
2274
2275 /* keep PUSH and FIN flags only for the last frame */
2276 if (!is_last_frame)
2277 {
2278 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2279 }
6cadb320 2280
718da2b9
FB		 2281 /* recalculate TCP checksum */
2282 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2283 p_tcpip_hdr->zeros = 0;
2284 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2285 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2286
2287 p_tcp_hdr->th_sum = 0;
2288
2289 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2290 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2291 tcp_checksum);
718da2b9
FB		 2292
2293 p_tcp_hdr->th_sum = tcp_checksum;
2294
2295 /* restore IP header */
2296 memcpy(eth_payload_data, saved_ip_header, hlen);
2297
2298 /* set IP data length and recalculate IP checksum */
2299 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2300
2301 /* increment IP id for subsequent frames */
2302 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2303
2304 ip->ip_sum = 0;
2305 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2306 DPRINTF("+++ C+ mode TSO IP header len=%d "
2307 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2308
2309 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2310 DPRINTF("+++ C+ mode TSO transferring packet size "
2311 "%d\n", tso_send_size);
bf6b87a8
BP		 2312 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2313 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2314
2315 /* add transferred count to TCP sequence number */
2316 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2317 ++send_count;
2318 }
2319
2320 /* Stop sending this frame */
2321 saved_size = 0;
2322 }
2323 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2324 {
7cdeb319 2325 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2326
2327 /* maximum IP header length is 60 bytes */
2328 uint8_t saved_ip_header[60];
2329 memcpy(saved_ip_header, eth_payload_data, hlen);
2330
2331 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2332 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2333
2334 /* add 4 TCP pseudoheader fields */
2335 /* copy IP source and destination fields */
718da2b9 2336 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2337
718da2b9 2338 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2339 {
7cdeb319
BP		 2340 DPRINTF("+++ C+ mode calculating TCP checksum for "
2341 "packet with %d bytes data\n", ip_data_len);
6cadb320 2342
718da2b9
FB		 2343 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2344 p_tcpip_hdr->zeros = 0;
2345 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2346 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2347
718da2b9 2348 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2349
2350 p_tcp_hdr->th_sum = 0;
2351
718da2b9 2352 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2353 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2354 tcp_checksum);
6cadb320
FB		 2355
2356 p_tcp_hdr->th_sum = tcp_checksum;
2357 }
718da2b9 2358 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2359 {
7cdeb319
BP		 2360 DPRINTF("+++ C+ mode calculating UDP checksum for "
2361 "packet with %d bytes data\n", ip_data_len);
6cadb320 2362
718da2b9
FB		 2363 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2364 p_udpip_hdr->zeros = 0;
2365 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2366 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2367
718da2b9 2368 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2369
6cadb320
FB		 2370 p_udp_hdr->uh_sum = 0;
2371
718da2b9 2372 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2373 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2374 udp_checksum);
6cadb320 2375
6cadb320
FB		 2376 p_udp_hdr->uh_sum = udp_checksum;
2377 }
2378
2379 /* restore IP header */
718da2b9 2380 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2381 }
2382 }
2383 }
2384
2385 /* update tally counter */
2386 ++s->tally_counters.TxOk;
2387
7cdeb319 2388 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2389
bf6b87a8
BP		 2390 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2391 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2392
2393 /* restore card space if there was no recursion and reset offset */
2394 if (!s->cplus_txbuffer)
2395 {
2396 s->cplus_txbuffer = saved_buffer;
2397 s->cplus_txbuffer_len = saved_buffer_len;
2398 s->cplus_txbuffer_offset = 0;
2399 }
2400 else
2401 {
7267c094 2402 g_free(saved_buffer);
6cadb320 2403 }
a41b2ff2
PB		 2404 }
2405 else
2406 {
7cdeb319 2407 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2408 }
2409
a41b2ff2
PB		 2410 return 1;
2411}
2412
2413static void rtl8139_cplus_transmit(RTL8139State *s)
2414{
2415 int txcount = 0;
2416
2417 while (rtl8139_cplus_transmit_one(s))
2418 {
2419 ++txcount;
2420 }
2421
2422 /* Mark transfer completed */
2423 if (!txcount)
2424 {
7cdeb319
BP		 2425 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2426 s->currCPlusTxDesc);
a41b2ff2
PB		 2427 }
2428 else
2429 {
2430 /* update interrupt status */
2431 s->IntrStatus |= TxOK;
2432 rtl8139_update_irq(s);
2433 }
2434}
2435
2436static void rtl8139_transmit(RTL8139State *s)
2437{
2438 int descriptor = s->currTxDesc, txcount = 0;
2439
2440 /*while*/
2441 if (rtl8139_transmit_one(s, descriptor))
2442 {
2443 ++s->currTxDesc;
2444 s->currTxDesc %= 4;
2445 ++txcount;
2446 }
2447
2448 /* Mark transfer completed */
2449 if (!txcount)
2450 {
7cdeb319
BP		 2451 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2452 s->currTxDesc);
a41b2ff2
PB		 2453 }
2454}
2455
2456static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2457{
2458
2459 int descriptor = txRegOffset/4;
6cadb320
FB		 2460
2461 /* handle C+ transmit mode register configuration */
2462
2c3891ab 2463 if (s->cplus_enabled)
6cadb320 2464 {
7cdeb319
BP		 2465 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2466 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2467
2468 /* handle Dump Tally Counters command */
2469 s->TxStatus[descriptor] = val;
2470
2471 if (descriptor == 0 && (val & 0x8))
2472 {
c227f099 2473 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2474
2475 /* dump tally counters to specified memory location */
3ada003a 2476 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2477
2478 /* mark dump completed */
2479 s->TxStatus[0] &= ~0x8;
2480 }
2481
2482 return;
2483 }
2484
7cdeb319
BP		 2485 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2486 txRegOffset, val, descriptor);
a41b2ff2
PB		 2487
2488 /* mask only reserved bits */
2489 val &= ~0xff00c000; /* these bits are reset on write */
2490 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2491
2492 s->TxStatus[descriptor] = val;
2493
2494 /* attempt to start transmission */
2495 rtl8139_transmit(s);
2496}
2497
afe0a595 2498static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint8_t addr, int size)
a41b2ff2 2499{
afe0a595
JW		 2500 uint32_t reg = (addr - TxStatus0) / 4;
2501 uint32_t offset = addr & 0x3;
2502 uint32_t ret = 0;
2503
2504 if (addr & (size - 1)) {
2505 DPRINTF("not implemented read for TxStatus addr=0x%x size=0x%x\n", addr,
2506 size);
2507 return ret;
2508 }
a41b2ff2 2509
afe0a595
JW		 2510 switch (size) {
2511 case 1: /* fall through */
2512 case 2: /* fall through */
2513 case 4:
2514 ret = (s->TxStatus[reg] >> offset * 8) & ((1 << (size * 8)) - 1);
2515 DPRINTF("TxStatus[%d] read addr=0x%x size=0x%x val=0x%08x\n", reg, addr,
2516 size, ret);
2517 break;
2518 default:
2519 DPRINTF("unsupported size 0x%x of TxStatus reading\n", size);
2520 break;
2521 }
a41b2ff2
PB		 2522
2523 return ret;
2524}
2525
2526static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2527{
2528 uint16_t ret = 0;
2529
2530 /* Simulate TSAD, it is read only anyway */
2531
2532 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2533 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2534 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2535 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2536
2537 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2538 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2539 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2540 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2541
a41b2ff2
PB		 2542 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2543 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2544 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2545 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2546
a41b2ff2
PB		 2547 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2548 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2549 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2550 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2551
a41b2ff2 2552
7cdeb319 2553 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2554
2555 return ret;
2556}
2557
2558static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2559{
2560 uint16_t ret = s->CSCR;
2561
7cdeb319 2562 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2563
2564 return ret;
2565}
2566
2567static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2568{
7cdeb319 2569 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2570
290a0933 2571 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2572}
2573
2574static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2575{
290a0933 2576 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2577
7cdeb319 2578 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2579
2580 return ret;
2581}
2582
2583static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2584{
7cdeb319 2585 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2586
2587 /* this value is off by 16 */
2588 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2589
7cdeb319
BP		 2590 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2591 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2592}
2593
2594static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2595{
2596 /* this value is off by 16 */
2597 uint32_t ret = s->RxBufPtr - 0x10;
2598
7cdeb319 2599 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2600
2601 return ret;
2602}
2603
2604static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2605{
2606 /* this value is NOT off by 16 */
2607 uint32_t ret = s->RxBufAddr;
2608
7cdeb319 2609 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2610
2611 return ret;
2612}
2613
2614static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2615{
7cdeb319 2616 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2617
2618 s->RxBuf = val;
2619
2620 /* may need to reset rxring here */
2621}
2622
2623static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2624{
2625 uint32_t ret = s->RxBuf;
2626
7cdeb319 2627 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2628
2629 return ret;
2630}
2631
2632static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2633{
7cdeb319 2634 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2635
ebabb67a 2636 /* mask unwritable bits */
a41b2ff2
PB		 2637 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2638
2639 s->IntrMask = val;
2640
74475455 2641 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2642 rtl8139_update_irq(s);
05447803 2643
a41b2ff2
PB		 2644}
2645
2646static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2647{
2648 uint32_t ret = s->IntrMask;
2649
7cdeb319 2650 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2651
2652 return ret;
2653}
2654
2655static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2656{
7cdeb319 2657 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2658
2659#if 0
2660
2661 /* writing to ISR has no effect */
2662
2663 return;
2664
2665#else
2666 uint16_t newStatus = s->IntrStatus & ~val;
2667
ebabb67a 2668 /* mask unwritable bits */
a41b2ff2
PB		 2669 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2670
2671 /* writing 1 to interrupt status register bit clears it */
2672 s->IntrStatus = 0;
2673 rtl8139_update_irq(s);
2674
2675 s->IntrStatus = newStatus;
05447803
FZ		 2676 /*
2677 * Computing if we miss an interrupt here is not that correct but
2678 * considered that we should have had already an interrupt
2679 * and probably emulated is slower is better to assume this resetting was
26404edc 2680 * done before testing on previous rtl8139_update_irq lead to IRQ losing
05447803 2681 */
74475455 2682 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2683 rtl8139_update_irq(s);
05447803 2684
a41b2ff2
PB		 2685#endif
2686}
2687
2688static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2689{
74475455 2690 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2691
a41b2ff2
PB		 2692 uint32_t ret = s->IntrStatus;
2693
7cdeb319 2694 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2695
2696#if 0
2697
2698 /* reading ISR clears all interrupts */
2699 s->IntrStatus = 0;
2700
2701 rtl8139_update_irq(s);
2702
2703#endif
2704
2705 return ret;
2706}
2707
2708static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2709{
7cdeb319 2710 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2711
ebabb67a 2712 /* mask unwritable bits */
a41b2ff2
PB		 2713 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2714
2715 s->MultiIntr = val;
2716}
2717
2718static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2719{
2720 uint32_t ret = s->MultiIntr;
2721
7cdeb319 2722 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2723
2724 return ret;
2725}
2726
2727static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2728{
2729 RTL8139State *s = opaque;
2730
a41b2ff2
PB		 2731 switch (addr)
2732 {
2733 case MAC0 ... MAC0+5:
2734 s->phys[addr - MAC0] = val;
2735 break;
2736 case MAC0+6 ... MAC0+7:
2737 /* reserved */
2738 break;
2739 case MAR0 ... MAR0+7:
2740 s->mult[addr - MAR0] = val;
2741 break;
2742 case ChipCmd:
2743 rtl8139_ChipCmd_write(s, val);
2744 break;
2745 case Cfg9346:
2746 rtl8139_Cfg9346_write(s, val);
2747 break;
2748 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2749 rtl8139_TxConfig_writeb(s, val);
2750 break;
2751 case Config0:
2752 rtl8139_Config0_write(s, val);
2753 break;
2754 case Config1:
2755 rtl8139_Config1_write(s, val);
2756 break;
2757 case Config3:
2758 rtl8139_Config3_write(s, val);
2759 break;
2760 case Config4:
2761 rtl8139_Config4_write(s, val);
2762 break;
2763 case Config5:
2764 rtl8139_Config5_write(s, val);
2765 break;
2766 case MediaStatus:
2767 /* ignore */
7cdeb319
BP		 2768 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2769 val);
a41b2ff2
PB		 2770 break;
2771
2772 case HltClk:
7cdeb319 2773 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2774 if (val == 'R')
2775 {
2776 s->clock_enabled = 1;
2777 }
2778 else if (val == 'H')
2779 {
2780 s->clock_enabled = 0;
2781 }
2782 break;
2783
2784 case TxThresh:
7cdeb319 2785 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2786 s->TxThresh = val;
2787 break;
2788
2789 case TxPoll:
7cdeb319 2790 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2791 if (val & (1 << 7))
2792 {
7cdeb319
BP		 2793 DPRINTF("C+ TxPoll high priority transmission (not "
2794 "implemented)\n");
a41b2ff2
PB		 2795 //rtl8139_cplus_transmit(s);
2796 }
2797 if (val & (1 << 6))
2798 {
7cdeb319 2799 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2800 rtl8139_cplus_transmit(s);
2801 }
2802
2803 break;
2804
2805 default:
7cdeb319
BP		 2806 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2807 val);
a41b2ff2
PB		 2808 break;
2809 }
2810}
2811
2812static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2813{
2814 RTL8139State *s = opaque;
2815
a41b2ff2
PB		 2816 switch (addr)
2817 {
2818 case IntrMask:
2819 rtl8139_IntrMask_write(s, val);
2820 break;
2821
2822 case IntrStatus:
2823 rtl8139_IntrStatus_write(s, val);
2824 break;
2825
2826 case MultiIntr:
2827 rtl8139_MultiIntr_write(s, val);
2828 break;
2829
2830 case RxBufPtr:
2831 rtl8139_RxBufPtr_write(s, val);
2832 break;
2833
2834 case BasicModeCtrl:
2835 rtl8139_BasicModeCtrl_write(s, val);
2836 break;
2837 case BasicModeStatus:
2838 rtl8139_BasicModeStatus_write(s, val);
2839 break;
2840 case NWayAdvert:
7cdeb319 2841 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2842 s->NWayAdvert = val;
2843 break;
2844 case NWayLPAR:
7cdeb319 2845 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2846 break;
2847 case NWayExpansion:
7cdeb319 2848 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2849 s->NWayExpansion = val;
2850 break;
2851
2852 case CpCmd:
2853 rtl8139_CpCmd_write(s, val);
2854 break;
2855
6cadb320
FB		 2856 case IntrMitigate:
2857 rtl8139_IntrMitigate_write(s, val);
2858 break;
2859
a41b2ff2 2860 default:
7cdeb319
BP		 2861 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2862 addr, val);
a41b2ff2 2863
a41b2ff2
PB		 2864 rtl8139_io_writeb(opaque, addr, val & 0xff);
2865 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2866 break;
2867 }
2868}
2869
05447803
FZ		 2870static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2871{
2872 int64_t pci_time, next_time;
2873 uint32_t low_pci;
2874
7cdeb319 2875 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2876
2877 if (s->TimerExpire && current_time >= s->TimerExpire) {
2878 s->IntrStatus |= PCSTimeout;
2879 rtl8139_update_irq(s);
2880 }
2881
2882 /* Set QEMU timer only if needed that is
2883 * - TimerInt <> 0 (we have a timer)
2884 * - mask = 1 (we want an interrupt timer)
2885 * - irq = 0 (irq is not already active)
2886 * If any of above change we need to compute timer again
2887 * Also we must check if timer is passed without QEMU timer
2888 */
2889 s->TimerExpire = 0;
2890 if (!s->TimerInt) {
2891 return;
2892 }
2893
2894 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2895 get_ticks_per_sec());
2896 low_pci = pci_time & 0xffffffff;
2897 pci_time = pci_time - low_pci + s->TimerInt;
2898 if (low_pci >= s->TimerInt) {
2899 pci_time += 0x100000000LL;
2900 }
2901 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2902 PCI_FREQUENCY);
2903 s->TimerExpire = next_time;
2904
2905 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2906 qemu_mod_timer(s->timer, next_time);
2907 }
2908}
2909
a41b2ff2
PB		 2910static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2911{
2912 RTL8139State *s = opaque;
2913
a41b2ff2
PB		 2914 switch (addr)
2915 {
2916 case RxMissed:
7cdeb319 2917 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2918 s->RxMissed = 0;
2919 break;
2920
2921 case TxConfig:
2922 rtl8139_TxConfig_write(s, val);
2923 break;
2924
2925 case RxConfig:
2926 rtl8139_RxConfig_write(s, val);
2927 break;
2928
2929 case TxStatus0 ... TxStatus0+4*4-1:
2930 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2931 break;
2932
2933 case TxAddr0 ... TxAddr0+4*4-1:
2934 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2935 break;
2936
2937 case RxBuf:
2938 rtl8139_RxBuf_write(s, val);
2939 break;
2940
2941 case RxRingAddrLO:
7cdeb319 2942 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2943 s->RxRingAddrLO = val;
2944 break;
2945
2946 case RxRingAddrHI:
7cdeb319 2947 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2948 s->RxRingAddrHI = val;
2949 break;
2950
6cadb320 2951 case Timer:
7cdeb319 2952 DPRINTF("TCTR Timer reset on write\n");
74475455 2953 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2954 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2955 break;
2956
2957 case FlashReg:
7cdeb319 2958 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2959 if (s->TimerInt != val) {
2960 s->TimerInt = val;
74475455 2961 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2962 }
6cadb320
FB		 2963 break;
2964
a41b2ff2 2965 default:
7cdeb319
BP		 2966 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2967 addr, val);
a41b2ff2
PB		 2968 rtl8139_io_writeb(opaque, addr, val & 0xff);
2969 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2970 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2971 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2972 break;
2973 }
2974}
2975
2976static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2977{
2978 RTL8139State *s = opaque;
2979 int ret;
2980
a41b2ff2
PB		 2981 switch (addr)
2982 {
2983 case MAC0 ... MAC0+5:
2984 ret = s->phys[addr - MAC0];
2985 break;
2986 case MAC0+6 ... MAC0+7:
2987 ret = 0;
2988 break;
2989 case MAR0 ... MAR0+7:
2990 ret = s->mult[addr - MAR0];
2991 break;
afe0a595
JW		 2992 case TxStatus0 ... TxStatus0+4*4-1:
2993 ret = rtl8139_TxStatus_read(s, addr, 1);
2994 break;
a41b2ff2
PB		 2995 case ChipCmd:
2996 ret = rtl8139_ChipCmd_read(s);
2997 break;
2998 case Cfg9346:
2999 ret = rtl8139_Cfg9346_read(s);
3000 break;
3001 case Config0:
3002 ret = rtl8139_Config0_read(s);
3003 break;
3004 case Config1:
3005 ret = rtl8139_Config1_read(s);
3006 break;
3007 case Config3:
3008 ret = rtl8139_Config3_read(s);
3009 break;
3010 case Config4:
3011 ret = rtl8139_Config4_read(s);
3012 break;
3013 case Config5:
3014 ret = rtl8139_Config5_read(s);
3015 break;
3016
3017 case MediaStatus:
3018 ret = 0xd0;
7cdeb319 3019 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3020 break;
3021
3022 case HltClk:
3023 ret = s->clock_enabled;
7cdeb319 3024 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3025 break;
3026
3027 case PCIRevisionID:
6cadb320 3028 ret = RTL8139_PCI_REVID;
7cdeb319 3029 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3030 break;
3031
3032 case TxThresh:
3033 ret = s->TxThresh;
7cdeb319 3034 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3035 break;
3036
3037 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3038 ret = s->TxConfig >> 24;
7cdeb319 3039 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3040 break;
3041
3042 default:
7cdeb319 3043 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3044 ret = 0;
3045 break;
3046 }
3047
3048 return ret;
3049}
3050
3051static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3052{
3053 RTL8139State *s = opaque;
3054 uint32_t ret;
3055
a41b2ff2
PB		 3056 switch (addr)
3057 {
afe0a595
JW		 3058 case TxAddr0 ... TxAddr0+4*4-1:
3059 ret = rtl8139_TxStatus_read(s, addr, 2);
3060 break;
a41b2ff2
PB		 3061 case IntrMask:
3062 ret = rtl8139_IntrMask_read(s);
3063 break;
3064
3065 case IntrStatus:
3066 ret = rtl8139_IntrStatus_read(s);
3067 break;
3068
3069 case MultiIntr:
3070 ret = rtl8139_MultiIntr_read(s);
3071 break;
3072
3073 case RxBufPtr:
3074 ret = rtl8139_RxBufPtr_read(s);
3075 break;
3076
6cadb320
FB		 3077 case RxBufAddr:
3078 ret = rtl8139_RxBufAddr_read(s);
3079 break;
3080
a41b2ff2
PB		 3081 case BasicModeCtrl:
3082 ret = rtl8139_BasicModeCtrl_read(s);
3083 break;
3084 case BasicModeStatus:
3085 ret = rtl8139_BasicModeStatus_read(s);
3086 break;
3087 case NWayAdvert:
3088 ret = s->NWayAdvert;
7cdeb319 3089 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3090 break;
3091 case NWayLPAR:
3092 ret = s->NWayLPAR;
7cdeb319 3093 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3094 break;
3095 case NWayExpansion:
3096 ret = s->NWayExpansion;
7cdeb319 3097 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3098 break;
3099
3100 case CpCmd:
3101 ret = rtl8139_CpCmd_read(s);
3102 break;
3103
6cadb320
FB		 3104 case IntrMitigate:
3105 ret = rtl8139_IntrMitigate_read(s);
3106 break;
3107
a41b2ff2
PB		 3108 case TxSummary:
3109 ret = rtl8139_TSAD_read(s);
3110 break;
3111
3112 case CSCR:
3113 ret = rtl8139_CSCR_read(s);
3114 break;
3115
3116 default:
7cdeb319 3117 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3118
a41b2ff2
PB		 3119 ret = rtl8139_io_readb(opaque, addr);
3120 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3121
7cdeb319 3122 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3123 break;
3124 }
3125
3126 return ret;
3127}
3128
3129static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3130{
3131 RTL8139State *s = opaque;
3132 uint32_t ret;
3133
a41b2ff2
PB		 3134 switch (addr)
3135 {
3136 case RxMissed:
3137 ret = s->RxMissed;
3138
7cdeb319 3139 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3140 break;
3141
3142 case TxConfig:
3143 ret = rtl8139_TxConfig_read(s);
3144 break;
3145
3146 case RxConfig:
3147 ret = rtl8139_RxConfig_read(s);
3148 break;
3149
3150 case TxStatus0 ... TxStatus0+4*4-1:
afe0a595 3151 ret = rtl8139_TxStatus_read(s, addr, 4);
a41b2ff2
PB		 3152 break;
3153
3154 case TxAddr0 ... TxAddr0+4*4-1:
3155 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3156 break;
3157
3158 case RxBuf:
3159 ret = rtl8139_RxBuf_read(s);
3160 break;
3161
3162 case RxRingAddrLO:
3163 ret = s->RxRingAddrLO;
7cdeb319 3164 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3165 break;
3166
3167 case RxRingAddrHI:
3168 ret = s->RxRingAddrHI;
7cdeb319 3169 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3170 break;
3171
3172 case Timer:
74475455 3173 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3174 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3175 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3176 break;
3177
3178 case FlashReg:
3179 ret = s->TimerInt;
7cdeb319 3180 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3181 break;
3182
3183 default:
7cdeb319 3184 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3185
a41b2ff2
PB		 3186 ret = rtl8139_io_readb(opaque, addr);
3187 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3188 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3189 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3190
7cdeb319 3191 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3192 break;
3193 }
3194
3195 return ret;
3196}
3197
3198/* */
3199
3200static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3201{
3202 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3203}
3204
3205static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3206{
3207 rtl8139_io_writew(opaque, addr & 0xFF, val);
3208}
3209
3210static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3211{
3212 rtl8139_io_writel(opaque, addr & 0xFF, val);
3213}
3214
3215static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3216{
3217 return rtl8139_io_readb(opaque, addr & 0xFF);
3218}
3219
3220static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3221{
3222 return rtl8139_io_readw(opaque, addr & 0xFF);
3223}
3224
3225static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3226{
3227 return rtl8139_io_readl(opaque, addr & 0xFF);
3228}
3229
3230/* */
3231
c227f099 3232static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3233{
3234 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3235}
3236
c227f099 3237static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3238{
3239 rtl8139_io_writew(opaque, addr & 0xFF, val);
3240}
3241
c227f099 3242static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3243{
3244 rtl8139_io_writel(opaque, addr & 0xFF, val);
3245}
3246
c227f099 3247static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3248{
3249 return rtl8139_io_readb(opaque, addr & 0xFF);
3250}
3251
c227f099 3252static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3253{
5fedc612 3254 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3255 return val;
a41b2ff2
PB		 3256}
3257
c227f099 3258static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3259{
5fedc612 3260 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3261 return val;
a41b2ff2
PB		 3262}
3263
060110c3 3264static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3265{
6597ebbb 3266 RTL8139State* s = opaque;
74475455 3267 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3268 if (version_id < 4) {
2c3891ab
AL		 3269 s->cplus_enabled = s->CpCmd != 0;
3270 }
3271
a41b2ff2
PB		 3272 return 0;
3273}
3274
c574ba5a
AW		 3275static bool rtl8139_hotplug_ready_needed(void *opaque)
3276{
3277 return qdev_machine_modified();
3278}
3279
3280static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3281 .name = "rtl8139/hotplug_ready",
3282 .version_id = 1,
3283 .minimum_version_id = 1,
3284 .minimum_version_id_old = 1,
3285 .fields = (VMStateField []) {
3286 VMSTATE_END_OF_LIST()
3287 }
3288};
3289
05447803
FZ		 3290static void rtl8139_pre_save(void *opaque)
3291{
3292 RTL8139State* s = opaque;
74475455 3293 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3294
3295 /* set IntrStatus correctly */
3296 rtl8139_set_next_tctr_time(s, current_time);
3297 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3298 get_ticks_per_sec());
bd80f3fc 3299 s->rtl8139_mmio_io_addr_dummy = 0;
05447803
FZ		 3300}
3301
060110c3
JQ		 3302static const VMStateDescription vmstate_rtl8139 = {
3303 .name = "rtl8139",
3304 .version_id = 4,
3305 .minimum_version_id = 3,
3306 .minimum_version_id_old = 3,
3307 .post_load = rtl8139_post_load,
05447803 3308 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3309 .fields = (VMStateField []) {
3310 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3311 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3312 VMSTATE_BUFFER(mult, RTL8139State),
3313 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3314 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3315
3316 VMSTATE_UINT32(RxBuf, RTL8139State),
3317 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3318 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3319 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3320
3321 VMSTATE_UINT16(IntrStatus, RTL8139State),
3322 VMSTATE_UINT16(IntrMask, RTL8139State),
3323
3324 VMSTATE_UINT32(TxConfig, RTL8139State),
3325 VMSTATE_UINT32(RxConfig, RTL8139State),
3326 VMSTATE_UINT32(RxMissed, RTL8139State),
3327 VMSTATE_UINT16(CSCR, RTL8139State),
3328
3329 VMSTATE_UINT8(Cfg9346, RTL8139State),
3330 VMSTATE_UINT8(Config0, RTL8139State),
3331 VMSTATE_UINT8(Config1, RTL8139State),
3332 VMSTATE_UINT8(Config3, RTL8139State),
3333 VMSTATE_UINT8(Config4, RTL8139State),
3334 VMSTATE_UINT8(Config5, RTL8139State),
3335
3336 VMSTATE_UINT8(clock_enabled, RTL8139State),
3337 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3338
3339 VMSTATE_UINT16(MultiIntr, RTL8139State),
3340
3341 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3342 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3343 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3344 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3345 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3346
3347 VMSTATE_UINT16(CpCmd, RTL8139State),
3348 VMSTATE_UINT8(TxThresh, RTL8139State),
3349
3350 VMSTATE_UNUSED(4),
3351 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3352 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3353
3354 VMSTATE_UINT32(currTxDesc, RTL8139State),
3355 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3356 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3357 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3358 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3359
3360 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3361 VMSTATE_INT32(eeprom.mode, RTL8139State),
3362 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3363 VMSTATE_UINT8(eeprom.address, RTL8139State),
3364 VMSTATE_UINT16(eeprom.input, RTL8139State),
3365 VMSTATE_UINT16(eeprom.output, RTL8139State),
3366
3367 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3368 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3369 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3370 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3371
3372 VMSTATE_UINT32(TCTR, RTL8139State),
3373 VMSTATE_UINT32(TimerInt, RTL8139State),
3374 VMSTATE_INT64(TCTR_base, RTL8139State),
3375
3376 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3377 vmstate_tally_counters, RTL8139TallyCounters),
3378
3379 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3380 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3381 },
3382 .subsections = (VMStateSubsection []) {
3383 {
3384 .vmsd = &vmstate_rtl8139_hotplug_ready,
3385 .needed = rtl8139_hotplug_ready_needed,
3386 }, {
3387 /* empty */
3388 }
060110c3
JQ		 3389 }
3390};
3391
a41b2ff2
PB		 3392/***********************************************************/
3393/* PCI RTL8139 definitions */
3394
bd80f3fc
AK		 3395static const MemoryRegionPortio rtl8139_portio[] = {
3396 { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
3397 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
3398 { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
3399 { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
3400 { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
3401 { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
3402 PORTIO_END_OF_LIST()
3403};
a41b2ff2 3404
bd80f3fc
AK		 3405static const MemoryRegionOps rtl8139_io_ops = {
3406 .old_portio = rtl8139_portio,
3407 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3408};
3409
bd80f3fc
AK		 3410static const MemoryRegionOps rtl8139_mmio_ops = {
3411 .old_mmio = {
3412 .read = {
3413 rtl8139_mmio_readb,
3414 rtl8139_mmio_readw,
3415 rtl8139_mmio_readl,
3416 },
3417 .write = {
3418 rtl8139_mmio_writeb,
3419 rtl8139_mmio_writew,
3420 rtl8139_mmio_writel,
3421 },
3422 },
3423 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3424};
3425
6cadb320
FB		 3426static void rtl8139_timer(void *opaque)
3427{
3428 RTL8139State *s = opaque;
3429
6cadb320
FB		 3430 if (!s->clock_enabled)
3431 {
7cdeb319 3432 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3433 return;
3434 }
3435
05447803
FZ		 3436 s->IntrStatus |= PCSTimeout;
3437 rtl8139_update_irq(s);
74475455 3438 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3439}
6cadb320 3440
1673ad51 3441static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3442{
1673ad51 3443 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3444
1673ad51 3445 s->nic = NULL;
254111ec
GH		 3446}
3447
3448static int pci_rtl8139_uninit(PCIDevice *dev)
3449{
3450 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3451
bd80f3fc
AK		 3452 memory_region_destroy(&s->bar_io);
3453 memory_region_destroy(&s->bar_mem);
b946a153 3454 if (s->cplus_txbuffer) {
7267c094 3455 g_free(s->cplus_txbuffer);
b946a153
AL		 3456 s->cplus_txbuffer = NULL;
3457 }
b946a153
AL		 3458 qemu_del_timer(s->timer);
3459 qemu_free_timer(s->timer);
1673ad51 3460 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3461 return 0;
3462}
3463
1673ad51
MM		 3464static NetClientInfo net_rtl8139_info = {
3465 .type = NET_CLIENT_TYPE_NIC,
3466 .size = sizeof(NICState),
3467 .can_receive = rtl8139_can_receive,
3468 .receive = rtl8139_receive,
3469 .cleanup = rtl8139_cleanup,
3470};
3471
81a322d4 3472static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3473{
efd6dd45 3474 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3475 uint8_t *pci_conf;
3b46e624 3476
efd6dd45 3477 pci_conf = s->dev.config;
817e0b6f 3478 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3479 /* TODO: start of capability list, but no capability
3480 * list bit in status register, and offset 0xdc seems unused. */
3481 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3482
bd80f3fc
AK		 3483 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3484 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
e824b2cc
AK		 3485 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3486 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3487
254111ec 3488 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3489
7165448a
WD		 3490 /* prepare eeprom */
3491 s->eeprom.contents[0] = 0x8129;
3492#if 1
3493 /* PCI vendor and device ID should be mirrored here */
3494 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3495 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3496#endif
3497 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3498 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3499 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3500
1673ad51 3501 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
f79f2bfc 3502 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
1673ad51 3503 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3504
3505 s->cplus_txbuffer = NULL;
3506 s->cplus_txbuffer_len = 0;
3507 s->cplus_txbuffer_offset = 0;
3b46e624 3508
05447803 3509 s->TimerExpire = 0;
74475455
PB		 3510 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3511 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3512
3513 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3514
81a322d4 3515 return 0;
a41b2ff2 3516}
9d07d757 3517
40021f08
AL		 3518static Property rtl8139_properties[] = {
3519 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3520 DEFINE_PROP_END_OF_LIST(),
3521};
3522
3523static void rtl8139_class_init(ObjectClass *klass, void *data)
3524{
39bffca2 3525 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3526 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3527
3528 k->init = pci_rtl8139_init;
3529 k->exit = pci_rtl8139_uninit;
3530 k->romfile = "pxe-rtl8139.rom";
3531 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3532 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3533 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3534 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3535 dc->reset = rtl8139_reset;
3536 dc->vmsd = &vmstate_rtl8139;
3537 dc->props = rtl8139_properties;
40021f08
AL		 3538}
3539
39bffca2
AL		 3540static TypeInfo rtl8139_info = {
3541 .name = "rtl8139",
3542 .parent = TYPE_PCI_DEVICE,
3543 .instance_size = sizeof(RTL8139State),
3544 .class_init = rtl8139_class_init,
0aab0d3a
GH		 3545};
3546
83f7d43a 3547static void rtl8139_register_types(void)
9d07d757 3548{
39bffca2 3549 type_register_static(&rtl8139_info);
9d07d757
PB		 3550}
3551
83f7d43a 3552type_init(rtl8139_register_types)
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