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Commit | Line | Data |
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5fafdf24 | 1 | /* |
a1bb27b1 PB |
2 | * Arm PrimeCell PL181 MultiMedia Card Interface |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
a1bb27b1 PB |
8 | */ |
9 | ||
8ef94f0b | 10 | #include "qemu/osdep.h" |
9c17d615 | 11 | #include "sysemu/blockdev.h" |
83c9f4ca | 12 | #include "hw/sysbus.h" |
d6454270 | 13 | #include "migration/vmstate.h" |
64552b6b | 14 | #include "hw/irq.h" |
e3382ef0 | 15 | #include "hw/sd/sd.h" |
03dd024f | 16 | #include "qemu/log.h" |
0b8fa32f | 17 | #include "qemu/module.h" |
4858e256 | 18 | #include "qemu/error-report.h" |
0d554cb0 | 19 | #include "qapi/error.h" |
583d09f0 | 20 | #include "trace.h" |
db1015e9 | 21 | #include "qom/object.h" |
a1bb27b1 PB |
22 | |
23 | #define PL181_FIFO_LEN 16 | |
24 | ||
630f4442 | 25 | #define TYPE_PL181 "pl181" |
db1015e9 | 26 | typedef struct PL181State PL181State; |
8110fa1d EH |
27 | DECLARE_INSTANCE_CHECKER(PL181State, PL181, |
28 | TYPE_PL181) | |
630f4442 | 29 | |
2762eed1 PMD |
30 | #define TYPE_PL181_BUS "pl181-bus" |
31 | ||
db1015e9 | 32 | struct PL181State { |
630f4442 AF |
33 | SysBusDevice parent_obj; |
34 | ||
ca45842a | 35 | MemoryRegion iomem; |
2762eed1 | 36 | SDBus sdbus; |
a1bb27b1 PB |
37 | uint32_t clock; |
38 | uint32_t power; | |
39 | uint32_t cmdarg; | |
40 | uint32_t cmd; | |
41 | uint32_t datatimer; | |
42 | uint32_t datalength; | |
43 | uint32_t respcmd; | |
44 | uint32_t response[4]; | |
45 | uint32_t datactrl; | |
46 | uint32_t datacnt; | |
47 | uint32_t status; | |
48 | uint32_t mask[2]; | |
624923be PM |
49 | int32_t fifo_pos; |
50 | int32_t fifo_len; | |
6361cdb6 | 51 | /* The linux 2.6.21 driver is buggy, and misbehaves if new data arrives |
67cc32eb | 52 | while it is reading the FIFO. We hack around this by deferring |
6361cdb6 PB |
53 | subsequent transfers until after the driver polls the status word. |
54 | http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=4446/1 | |
55 | */ | |
624923be | 56 | int32_t linux_hack; |
0e33730c | 57 | uint32_t fifo[PL181_FIFO_LEN]; /* TODO use Fifo32 */ |
d537cf6c | 58 | qemu_irq irq[2]; |
c31a4724 | 59 | /* GPIO outputs for 'card is readonly' and 'card inserted' */ |
26c5b0f4 PMD |
60 | qemu_irq card_readonly; |
61 | qemu_irq card_inserted; | |
db1015e9 | 62 | }; |
a1bb27b1 | 63 | |
624923be PM |
64 | static const VMStateDescription vmstate_pl181 = { |
65 | .name = "pl181", | |
66 | .version_id = 1, | |
67 | .minimum_version_id = 1, | |
68 | .fields = (VMStateField[]) { | |
1d998d93 AF |
69 | VMSTATE_UINT32(clock, PL181State), |
70 | VMSTATE_UINT32(power, PL181State), | |
71 | VMSTATE_UINT32(cmdarg, PL181State), | |
72 | VMSTATE_UINT32(cmd, PL181State), | |
73 | VMSTATE_UINT32(datatimer, PL181State), | |
74 | VMSTATE_UINT32(datalength, PL181State), | |
75 | VMSTATE_UINT32(respcmd, PL181State), | |
76 | VMSTATE_UINT32_ARRAY(response, PL181State, 4), | |
77 | VMSTATE_UINT32(datactrl, PL181State), | |
78 | VMSTATE_UINT32(datacnt, PL181State), | |
79 | VMSTATE_UINT32(status, PL181State), | |
80 | VMSTATE_UINT32_ARRAY(mask, PL181State, 2), | |
81 | VMSTATE_INT32(fifo_pos, PL181State), | |
82 | VMSTATE_INT32(fifo_len, PL181State), | |
83 | VMSTATE_INT32(linux_hack, PL181State), | |
84 | VMSTATE_UINT32_ARRAY(fifo, PL181State, PL181_FIFO_LEN), | |
624923be PM |
85 | VMSTATE_END_OF_LIST() |
86 | } | |
87 | }; | |
88 | ||
a1bb27b1 PB |
89 | #define PL181_CMD_INDEX 0x3f |
90 | #define PL181_CMD_RESPONSE (1 << 6) | |
91 | #define PL181_CMD_LONGRESP (1 << 7) | |
92 | #define PL181_CMD_INTERRUPT (1 << 8) | |
93 | #define PL181_CMD_PENDING (1 << 9) | |
94 | #define PL181_CMD_ENABLE (1 << 10) | |
95 | ||
96 | #define PL181_DATA_ENABLE (1 << 0) | |
97 | #define PL181_DATA_DIRECTION (1 << 1) | |
98 | #define PL181_DATA_MODE (1 << 2) | |
99 | #define PL181_DATA_DMAENABLE (1 << 3) | |
100 | ||
101 | #define PL181_STATUS_CMDCRCFAIL (1 << 0) | |
102 | #define PL181_STATUS_DATACRCFAIL (1 << 1) | |
103 | #define PL181_STATUS_CMDTIMEOUT (1 << 2) | |
104 | #define PL181_STATUS_DATATIMEOUT (1 << 3) | |
105 | #define PL181_STATUS_TXUNDERRUN (1 << 4) | |
106 | #define PL181_STATUS_RXOVERRUN (1 << 5) | |
107 | #define PL181_STATUS_CMDRESPEND (1 << 6) | |
108 | #define PL181_STATUS_CMDSENT (1 << 7) | |
109 | #define PL181_STATUS_DATAEND (1 << 8) | |
110 | #define PL181_STATUS_DATABLOCKEND (1 << 10) | |
111 | #define PL181_STATUS_CMDACTIVE (1 << 11) | |
112 | #define PL181_STATUS_TXACTIVE (1 << 12) | |
113 | #define PL181_STATUS_RXACTIVE (1 << 13) | |
114 | #define PL181_STATUS_TXFIFOHALFEMPTY (1 << 14) | |
115 | #define PL181_STATUS_RXFIFOHALFFULL (1 << 15) | |
116 | #define PL181_STATUS_TXFIFOFULL (1 << 16) | |
117 | #define PL181_STATUS_RXFIFOFULL (1 << 17) | |
118 | #define PL181_STATUS_TXFIFOEMPTY (1 << 18) | |
119 | #define PL181_STATUS_RXFIFOEMPTY (1 << 19) | |
120 | #define PL181_STATUS_TXDATAAVLBL (1 << 20) | |
121 | #define PL181_STATUS_RXDATAAVLBL (1 << 21) | |
122 | ||
123 | #define PL181_STATUS_TX_FIFO (PL181_STATUS_TXACTIVE \ | |
124 | |PL181_STATUS_TXFIFOHALFEMPTY \ | |
125 | |PL181_STATUS_TXFIFOFULL \ | |
126 | |PL181_STATUS_TXFIFOEMPTY \ | |
127 | |PL181_STATUS_TXDATAAVLBL) | |
128 | #define PL181_STATUS_RX_FIFO (PL181_STATUS_RXACTIVE \ | |
129 | |PL181_STATUS_RXFIFOHALFFULL \ | |
130 | |PL181_STATUS_RXFIFOFULL \ | |
131 | |PL181_STATUS_RXFIFOEMPTY \ | |
132 | |PL181_STATUS_RXDATAAVLBL) | |
133 | ||
134 | static const unsigned char pl181_id[] = | |
135 | { 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; | |
136 | ||
1d998d93 | 137 | static void pl181_update(PL181State *s) |
a1bb27b1 PB |
138 | { |
139 | int i; | |
140 | for (i = 0; i < 2; i++) { | |
d537cf6c | 141 | qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0); |
a1bb27b1 PB |
142 | } |
143 | } | |
144 | ||
1d998d93 | 145 | static void pl181_fifo_push(PL181State *s, uint32_t value) |
a1bb27b1 PB |
146 | { |
147 | int n; | |
148 | ||
149 | if (s->fifo_len == PL181_FIFO_LEN) { | |
4858e256 | 150 | error_report("%s: FIFO overflow", __func__); |
a1bb27b1 PB |
151 | return; |
152 | } | |
153 | n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1); | |
154 | s->fifo_len++; | |
155 | s->fifo[n] = value; | |
583d09f0 | 156 | trace_pl181_fifo_push(value); |
a1bb27b1 PB |
157 | } |
158 | ||
1d998d93 | 159 | static uint32_t pl181_fifo_pop(PL181State *s) |
a1bb27b1 PB |
160 | { |
161 | uint32_t value; | |
162 | ||
163 | if (s->fifo_len == 0) { | |
4858e256 | 164 | error_report("%s: FIFO underflow", __func__); |
a1bb27b1 PB |
165 | return 0; |
166 | } | |
167 | value = s->fifo[s->fifo_pos]; | |
168 | s->fifo_len--; | |
169 | s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1); | |
583d09f0 | 170 | trace_pl181_fifo_pop(value); |
a1bb27b1 PB |
171 | return value; |
172 | } | |
173 | ||
b67cd8f5 | 174 | static void pl181_do_command(PL181State *s) |
a1bb27b1 | 175 | { |
bc24a225 | 176 | SDRequest request; |
a1bb27b1 PB |
177 | uint8_t response[16]; |
178 | int rlen; | |
179 | ||
180 | request.cmd = s->cmd & PL181_CMD_INDEX; | |
181 | request.arg = s->cmdarg; | |
583d09f0 | 182 | trace_pl181_command_send(request.cmd, request.arg); |
2762eed1 | 183 | rlen = sdbus_do_command(&s->sdbus, &request, response); |
a1bb27b1 PB |
184 | if (rlen < 0) |
185 | goto error; | |
186 | if (s->cmd & PL181_CMD_RESPONSE) { | |
a1bb27b1 PB |
187 | if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP))) |
188 | goto error; | |
189 | if (rlen != 4 && rlen != 16) | |
190 | goto error; | |
b3141c06 | 191 | s->response[0] = ldl_be_p(&response[0]); |
a1bb27b1 PB |
192 | if (rlen == 4) { |
193 | s->response[1] = s->response[2] = s->response[3] = 0; | |
194 | } else { | |
b3141c06 PMD |
195 | s->response[1] = ldl_be_p(&response[4]); |
196 | s->response[2] = ldl_be_p(&response[8]); | |
197 | s->response[3] = ldl_be_p(&response[12]) & ~1; | |
a1bb27b1 | 198 | } |
583d09f0 | 199 | trace_pl181_command_response_pending(); |
a1bb27b1 | 200 | s->status |= PL181_STATUS_CMDRESPEND; |
a1bb27b1 | 201 | } else { |
583d09f0 | 202 | trace_pl181_command_sent(); |
a1bb27b1 PB |
203 | s->status |= PL181_STATUS_CMDSENT; |
204 | } | |
205 | return; | |
206 | ||
207 | error: | |
583d09f0 | 208 | trace_pl181_command_timeout(); |
a1bb27b1 PB |
209 | s->status |= PL181_STATUS_CMDTIMEOUT; |
210 | } | |
211 | ||
aa1f17c1 | 212 | /* Transfer data between the card and the FIFO. This is complicated by |
a1bb27b1 PB |
213 | the FIFO holding 32-bit words and the card taking data in single byte |
214 | chunks. FIFO bytes are transferred in little-endian order. */ | |
3b46e624 | 215 | |
1d998d93 | 216 | static void pl181_fifo_run(PL181State *s) |
a1bb27b1 PB |
217 | { |
218 | uint32_t bits; | |
f21126df | 219 | uint32_t value = 0; |
a1bb27b1 | 220 | int n; |
a1bb27b1 PB |
221 | int is_read; |
222 | ||
223 | is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0; | |
2762eed1 | 224 | if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus)) |
6361cdb6 | 225 | && !s->linux_hack) { |
bc3b26f5 PB |
226 | if (is_read) { |
227 | n = 0; | |
bc3b26f5 | 228 | while (s->datacnt && s->fifo_len < PL181_FIFO_LEN) { |
8467f622 | 229 | value |= (uint32_t)sdbus_read_byte(&s->sdbus) << (n * 8); |
bc3b26f5 | 230 | s->datacnt--; |
a1bb27b1 PB |
231 | n++; |
232 | if (n == 4) { | |
233 | pl181_fifo_push(s, value); | |
a1bb27b1 | 234 | n = 0; |
bc3b26f5 | 235 | value = 0; |
a1bb27b1 | 236 | } |
bc3b26f5 PB |
237 | } |
238 | if (n != 0) { | |
239 | pl181_fifo_push(s, value); | |
240 | } | |
241 | } else { /* write */ | |
242 | n = 0; | |
243 | while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { | |
a1bb27b1 PB |
244 | if (n == 0) { |
245 | value = pl181_fifo_pop(s); | |
246 | n = 4; | |
247 | } | |
bc3b26f5 PB |
248 | n--; |
249 | s->datacnt--; | |
39017143 | 250 | sdbus_write_byte(&s->sdbus, value & 0xff); |
a1bb27b1 | 251 | value >>= 8; |
a1bb27b1 | 252 | } |
a1bb27b1 PB |
253 | } |
254 | } | |
255 | s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO); | |
256 | if (s->datacnt == 0) { | |
257 | s->status |= PL181_STATUS_DATAEND; | |
258 | /* HACK: */ | |
259 | s->status |= PL181_STATUS_DATABLOCKEND; | |
583d09f0 | 260 | trace_pl181_fifo_transfer_complete(); |
a1bb27b1 | 261 | } |
6361cdb6 | 262 | if (s->datacnt == 0 && s->fifo_len == 0) { |
a1bb27b1 | 263 | s->datactrl &= ~PL181_DATA_ENABLE; |
583d09f0 | 264 | trace_pl181_data_engine_idle(); |
a1bb27b1 PB |
265 | } else { |
266 | /* Update FIFO bits. */ | |
267 | bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE; | |
268 | if (s->fifo_len == 0) { | |
269 | bits |= PL181_STATUS_TXFIFOEMPTY; | |
270 | bits |= PL181_STATUS_RXFIFOEMPTY; | |
271 | } else { | |
272 | bits |= PL181_STATUS_TXDATAAVLBL; | |
273 | bits |= PL181_STATUS_RXDATAAVLBL; | |
274 | } | |
275 | if (s->fifo_len == 16) { | |
276 | bits |= PL181_STATUS_TXFIFOFULL; | |
277 | bits |= PL181_STATUS_RXFIFOFULL; | |
278 | } | |
279 | if (s->fifo_len <= 8) { | |
280 | bits |= PL181_STATUS_TXFIFOHALFEMPTY; | |
281 | } | |
282 | if (s->fifo_len >= 8) { | |
283 | bits |= PL181_STATUS_RXFIFOHALFFULL; | |
284 | } | |
285 | if (s->datactrl & PL181_DATA_DIRECTION) { | |
286 | bits &= PL181_STATUS_RX_FIFO; | |
287 | } else { | |
288 | bits &= PL181_STATUS_TX_FIFO; | |
289 | } | |
290 | s->status |= bits; | |
291 | } | |
292 | } | |
293 | ||
a8170e5e | 294 | static uint64_t pl181_read(void *opaque, hwaddr offset, |
ca45842a | 295 | unsigned size) |
a1bb27b1 | 296 | { |
1d998d93 | 297 | PL181State *s = (PL181State *)opaque; |
6361cdb6 | 298 | uint32_t tmp; |
a1bb27b1 | 299 | |
a1bb27b1 PB |
300 | if (offset >= 0xfe0 && offset < 0x1000) { |
301 | return pl181_id[(offset - 0xfe0) >> 2]; | |
302 | } | |
303 | switch (offset) { | |
304 | case 0x00: /* Power */ | |
305 | return s->power; | |
306 | case 0x04: /* Clock */ | |
307 | return s->clock; | |
308 | case 0x08: /* Argument */ | |
309 | return s->cmdarg; | |
310 | case 0x0c: /* Command */ | |
311 | return s->cmd; | |
312 | case 0x10: /* RespCmd */ | |
313 | return s->respcmd; | |
314 | case 0x14: /* Response0 */ | |
315 | return s->response[0]; | |
316 | case 0x18: /* Response1 */ | |
317 | return s->response[1]; | |
318 | case 0x1c: /* Response2 */ | |
319 | return s->response[2]; | |
320 | case 0x20: /* Response3 */ | |
321 | return s->response[3]; | |
322 | case 0x24: /* DataTimer */ | |
323 | return s->datatimer; | |
324 | case 0x28: /* DataLength */ | |
325 | return s->datalength; | |
326 | case 0x2c: /* DataCtrl */ | |
327 | return s->datactrl; | |
328 | case 0x30: /* DataCnt */ | |
329 | return s->datacnt; | |
330 | case 0x34: /* Status */ | |
6361cdb6 PB |
331 | tmp = s->status; |
332 | if (s->linux_hack) { | |
333 | s->linux_hack = 0; | |
334 | pl181_fifo_run(s); | |
335 | pl181_update(s); | |
336 | } | |
337 | return tmp; | |
a1bb27b1 PB |
338 | case 0x3c: /* Mask0 */ |
339 | return s->mask[0]; | |
340 | case 0x40: /* Mask1 */ | |
341 | return s->mask[1]; | |
342 | case 0x48: /* FifoCnt */ | |
6361cdb6 PB |
343 | /* The documentation is somewhat vague about exactly what FifoCnt |
344 | does. On real hardware it appears to be when decrememnted | |
66a0a2cb | 345 | when a word is transferred between the FIFO and the serial |
6361cdb6 | 346 | data engine. DataCnt is decremented after each byte is |
66a0a2cb | 347 | transferred between the serial engine and the card. |
6361cdb6 PB |
348 | We don't emulate this level of detail, so both can be the same. */ |
349 | tmp = (s->datacnt + 3) >> 2; | |
350 | if (s->linux_hack) { | |
351 | s->linux_hack = 0; | |
352 | pl181_fifo_run(s); | |
353 | pl181_update(s); | |
354 | } | |
355 | return tmp; | |
a1bb27b1 PB |
356 | case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ |
357 | case 0x90: case 0x94: case 0x98: case 0x9c: | |
358 | case 0xa0: case 0xa4: case 0xa8: case 0xac: | |
359 | case 0xb0: case 0xb4: case 0xb8: case 0xbc: | |
6361cdb6 | 360 | if (s->fifo_len == 0) { |
9351d708 | 361 | qemu_log_mask(LOG_GUEST_ERROR, "pl181: Unexpected FIFO read\n"); |
a1bb27b1 PB |
362 | return 0; |
363 | } else { | |
364 | uint32_t value; | |
a1bb27b1 | 365 | value = pl181_fifo_pop(s); |
6361cdb6 | 366 | s->linux_hack = 1; |
a1bb27b1 PB |
367 | pl181_fifo_run(s); |
368 | pl181_update(s); | |
369 | return value; | |
370 | } | |
371 | default: | |
9351d708 PM |
372 | qemu_log_mask(LOG_GUEST_ERROR, |
373 | "pl181_read: Bad offset %x\n", (int)offset); | |
a1bb27b1 PB |
374 | return 0; |
375 | } | |
376 | } | |
377 | ||
a8170e5e | 378 | static void pl181_write(void *opaque, hwaddr offset, |
ca45842a | 379 | uint64_t value, unsigned size) |
a1bb27b1 | 380 | { |
1d998d93 | 381 | PL181State *s = (PL181State *)opaque; |
a1bb27b1 | 382 | |
a1bb27b1 PB |
383 | switch (offset) { |
384 | case 0x00: /* Power */ | |
385 | s->power = value & 0xff; | |
386 | break; | |
387 | case 0x04: /* Clock */ | |
388 | s->clock = value & 0xff; | |
389 | break; | |
390 | case 0x08: /* Argument */ | |
391 | s->cmdarg = value; | |
392 | break; | |
393 | case 0x0c: /* Command */ | |
394 | s->cmd = value; | |
395 | if (s->cmd & PL181_CMD_ENABLE) { | |
396 | if (s->cmd & PL181_CMD_INTERRUPT) { | |
9351d708 PM |
397 | qemu_log_mask(LOG_UNIMP, |
398 | "pl181: Interrupt mode not implemented\n"); | |
a1bb27b1 | 399 | } if (s->cmd & PL181_CMD_PENDING) { |
9351d708 PM |
400 | qemu_log_mask(LOG_UNIMP, |
401 | "pl181: Pending commands not implemented\n"); | |
a1bb27b1 | 402 | } else { |
b67cd8f5 | 403 | pl181_do_command(s); |
a1bb27b1 PB |
404 | pl181_fifo_run(s); |
405 | } | |
406 | /* The command has completed one way or the other. */ | |
407 | s->cmd &= ~PL181_CMD_ENABLE; | |
408 | } | |
409 | break; | |
410 | case 0x24: /* DataTimer */ | |
411 | s->datatimer = value; | |
412 | break; | |
413 | case 0x28: /* DataLength */ | |
414 | s->datalength = value & 0xffff; | |
415 | break; | |
416 | case 0x2c: /* DataCtrl */ | |
417 | s->datactrl = value & 0xff; | |
418 | if (value & PL181_DATA_ENABLE) { | |
419 | s->datacnt = s->datalength; | |
a1bb27b1 PB |
420 | pl181_fifo_run(s); |
421 | } | |
422 | break; | |
423 | case 0x38: /* Clear */ | |
424 | s->status &= ~(value & 0x7ff); | |
425 | break; | |
426 | case 0x3c: /* Mask0 */ | |
427 | s->mask[0] = value; | |
428 | break; | |
429 | case 0x40: /* Mask1 */ | |
430 | s->mask[1] = value; | |
431 | break; | |
432 | case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ | |
433 | case 0x90: case 0x94: case 0x98: case 0x9c: | |
434 | case 0xa0: case 0xa4: case 0xa8: case 0xac: | |
435 | case 0xb0: case 0xb4: case 0xb8: case 0xbc: | |
6361cdb6 | 436 | if (s->datacnt == 0) { |
9351d708 | 437 | qemu_log_mask(LOG_GUEST_ERROR, "pl181: Unexpected FIFO write\n"); |
a1bb27b1 | 438 | } else { |
a1bb27b1 PB |
439 | pl181_fifo_push(s, value); |
440 | pl181_fifo_run(s); | |
441 | } | |
442 | break; | |
443 | default: | |
9351d708 PM |
444 | qemu_log_mask(LOG_GUEST_ERROR, |
445 | "pl181_write: Bad offset %x\n", (int)offset); | |
a1bb27b1 PB |
446 | } |
447 | pl181_update(s); | |
448 | } | |
449 | ||
ca45842a AK |
450 | static const MemoryRegionOps pl181_ops = { |
451 | .read = pl181_read, | |
452 | .write = pl181_write, | |
453 | .endianness = DEVICE_NATIVE_ENDIAN, | |
a1bb27b1 PB |
454 | }; |
455 | ||
2762eed1 PMD |
456 | static void pl181_set_readonly(DeviceState *dev, bool level) |
457 | { | |
458 | PL181State *s = (PL181State *)dev; | |
459 | ||
460 | qemu_set_irq(s->card_readonly, level); | |
461 | } | |
462 | ||
463 | static void pl181_set_inserted(DeviceState *dev, bool level) | |
464 | { | |
465 | PL181State *s = (PL181State *)dev; | |
466 | ||
467 | qemu_set_irq(s->card_inserted, level); | |
468 | } | |
469 | ||
624923be | 470 | static void pl181_reset(DeviceState *d) |
a1bb27b1 | 471 | { |
630f4442 | 472 | PL181State *s = PL181(d); |
a1bb27b1 PB |
473 | |
474 | s->power = 0; | |
475 | s->cmdarg = 0; | |
476 | s->cmd = 0; | |
477 | s->datatimer = 0; | |
478 | s->datalength = 0; | |
479 | s->respcmd = 0; | |
480 | s->response[0] = 0; | |
481 | s->response[1] = 0; | |
482 | s->response[2] = 0; | |
483 | s->response[3] = 0; | |
484 | s->datatimer = 0; | |
485 | s->datalength = 0; | |
486 | s->datactrl = 0; | |
487 | s->datacnt = 0; | |
488 | s->status = 0; | |
6361cdb6 | 489 | s->linux_hack = 0; |
a1bb27b1 PB |
490 | s->mask[0] = 0; |
491 | s->mask[1] = 0; | |
c31a4724 | 492 | |
2762eed1 PMD |
493 | /* Reset other state based on current card insertion/readonly status */ |
494 | pl181_set_inserted(DEVICE(s), sdbus_get_inserted(&s->sdbus)); | |
495 | pl181_set_readonly(DEVICE(s), sdbus_get_readonly(&s->sdbus)); | |
a1bb27b1 PB |
496 | } |
497 | ||
0d554cb0 | 498 | static void pl181_init(Object *obj) |
a1bb27b1 | 499 | { |
0d554cb0 XZ |
500 | DeviceState *dev = DEVICE(obj); |
501 | PL181State *s = PL181(obj); | |
502 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
a1bb27b1 | 503 | |
0d554cb0 | 504 | memory_region_init_io(&s->iomem, obj, &pl181_ops, s, "pl181", 0x1000); |
630f4442 AF |
505 | sysbus_init_mmio(sbd, &s->iomem); |
506 | sysbus_init_irq(sbd, &s->irq[0]); | |
507 | sysbus_init_irq(sbd, &s->irq[1]); | |
26c5b0f4 PMD |
508 | qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1); |
509 | qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1); | |
2762eed1 PMD |
510 | |
511 | qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | |
512 | TYPE_PL181_BUS, dev, "sd-bus"); | |
0d554cb0 XZ |
513 | } |
514 | ||
999e12bb AL |
515 | static void pl181_class_init(ObjectClass *klass, void *data) |
516 | { | |
39bffca2 | 517 | DeviceClass *k = DEVICE_CLASS(klass); |
999e12bb | 518 | |
39bffca2 AL |
519 | k->vmsd = &vmstate_pl181; |
520 | k->reset = pl181_reset; | |
26c607b8 | 521 | /* Reason: output IRQs should be wired up */ |
e90f2a8c | 522 | k->user_creatable = false; |
999e12bb AL |
523 | } |
524 | ||
8c43a6f0 | 525 | static const TypeInfo pl181_info = { |
630f4442 | 526 | .name = TYPE_PL181, |
39bffca2 | 527 | .parent = TYPE_SYS_BUS_DEVICE, |
1d998d93 | 528 | .instance_size = sizeof(PL181State), |
0d554cb0 | 529 | .instance_init = pl181_init, |
39bffca2 | 530 | .class_init = pl181_class_init, |
624923be PM |
531 | }; |
532 | ||
2762eed1 PMD |
533 | static void pl181_bus_class_init(ObjectClass *klass, void *data) |
534 | { | |
535 | SDBusClass *sbc = SD_BUS_CLASS(klass); | |
536 | ||
537 | sbc->set_inserted = pl181_set_inserted; | |
538 | sbc->set_readonly = pl181_set_readonly; | |
539 | } | |
540 | ||
541 | static const TypeInfo pl181_bus_info = { | |
542 | .name = TYPE_PL181_BUS, | |
543 | .parent = TYPE_SD_BUS, | |
544 | .instance_size = sizeof(SDBus), | |
545 | .class_init = pl181_bus_class_init, | |
546 | }; | |
547 | ||
83f7d43a | 548 | static void pl181_register_types(void) |
aa9311d8 | 549 | { |
39bffca2 | 550 | type_register_static(&pl181_info); |
2762eed1 | 551 | type_register_static(&pl181_bus_info); |
aa9311d8 PB |
552 | } |
553 | ||
83f7d43a | 554 | type_init(pl181_register_types) |