[mirror_qemu.git] / hw / sd / pxa2xx_mmci.c

/*
 * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPLv2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"
#include "hw/sd/sd.h"
#include "hw/qdev.h"
#include "hw/qdev-properties.h"

#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)

struct PXA2xxMMCIState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;

    BlockBackend *blk;
    SDState *card;

    uint32_t status;
    uint32_t clkrt;
    uint32_t spi;
    uint32_t cmdat;
    uint32_t resp_tout;
    uint32_t read_tout;
    int blklen;
    int numblk;
    uint32_t intmask;
    uint32_t intreq;
    int cmd;
    uint32_t arg;

    int active;
    int bytesleft;
    uint8_t tx_fifo[64];
    int tx_start;
    int tx_len;
    uint8_t rx_fifo[32];
    int rx_start;
    int rx_len;
    uint16_t resp_fifo[9];
    int resp_len;

    int cmdreq;
};

#define MMC_STRPCL	0x00	/* MMC Clock Start/Stop register */
#define MMC_STAT	0x04	/* MMC Status register */
#define MMC_CLKRT	0x08	/* MMC Clock Rate register */
#define MMC_SPI		0x0c	/* MMC SPI Mode register */
#define MMC_CMDAT	0x10	/* MMC Command/Data register */
#define MMC_RESTO	0x14	/* MMC Response Time-Out register */
#define MMC_RDTO	0x18	/* MMC Read Time-Out register */
#define MMC_BLKLEN	0x1c	/* MMC Block Length register */
#define MMC_NUMBLK	0x20	/* MMC Number of Blocks register */
#define MMC_PRTBUF	0x24	/* MMC Buffer Partly Full register */
#define MMC_I_MASK	0x28	/* MMC Interrupt Mask register */
#define MMC_I_REG	0x2c	/* MMC Interrupt Request register */
#define MMC_CMD		0x30	/* MMC Command register */
#define MMC_ARGH	0x34	/* MMC Argument High register */
#define MMC_ARGL	0x38	/* MMC Argument Low register */
#define MMC_RES		0x3c	/* MMC Response FIFO */
#define MMC_RXFIFO	0x40	/* MMC Receive FIFO */
#define MMC_TXFIFO	0x44	/* MMC Transmit FIFO */
#define MMC_RDWAIT	0x48	/* MMC RD_WAIT register */
#define MMC_BLKS_REM	0x4c	/* MMC Blocks Remaining register */

/* Bitfield masks */
#define STRPCL_STOP_CLK	(1 << 0)
#define STRPCL_STRT_CLK	(1 << 1)
#define STAT_TOUT_RES	(1 << 1)
#define STAT_CLK_EN	(1 << 8)
#define STAT_DATA_DONE	(1 << 11)
#define STAT_PRG_DONE	(1 << 12)
#define STAT_END_CMDRES	(1 << 13)
#define SPI_SPI_MODE	(1 << 0)
#define CMDAT_RES_TYPE	(3 << 0)
#define CMDAT_DATA_EN	(1 << 2)
#define CMDAT_WR_RD	(1 << 3)
#define CMDAT_DMA_EN	(1 << 7)
#define CMDAT_STOP_TRAN	(1 << 10)
#define INT_DATA_DONE	(1 << 0)
#define INT_PRG_DONE	(1 << 1)
#define INT_END_CMD	(1 << 2)
#define INT_STOP_CMD	(1 << 3)
#define INT_CLK_OFF	(1 << 4)
#define INT_RXFIFO_REQ	(1 << 5)
#define INT_TXFIFO_REQ	(1 << 6)
#define INT_TINT	(1 << 7)
#define INT_DAT_ERR	(1 << 8)
#define INT_RES_ERR	(1 << 9)
#define INT_RD_STALLED	(1 << 10)
#define INT_SDIO_INT	(1 << 11)
#define INT_SDIO_SACK	(1 << 12)
#define PRTBUF_PRT_BUF	(1 << 0)

/* Route internal interrupt lines to the global IC and DMA */
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
{
    uint32_t mask = s->intmask;
    if (s->cmdat & CMDAT_DMA_EN) {
        mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;

        qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
        qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
    }

    qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}

static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
{
    if (!s->active)
        return;

    if (s->cmdat & CMDAT_WR_RD) {
        while (s->bytesleft && s->tx_len) {
            sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
            s->tx_start &= 0x1f;
            s->tx_len --;
            s->bytesleft --;
        }
        if (s->bytesleft)
            s->intreq |= INT_TXFIFO_REQ;
    } else
        while (s->bytesleft && s->rx_len < 32) {
            s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
                sd_read_data(s->card);
            s->bytesleft --;
            s->intreq |= INT_RXFIFO_REQ;
        }

    if (!s->bytesleft) {
        s->active = 0;
        s->intreq |= INT_DATA_DONE;
        s->status |= STAT_DATA_DONE;

        if (s->cmdat & CMDAT_WR_RD) {
            s->intreq |= INT_PRG_DONE;
            s->status |= STAT_PRG_DONE;
        }
    }

    pxa2xx_mmci_int_update(s);
}

static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
{
    int rsplen, i;
    SDRequest request;
    uint8_t response[16];

    s->active = 1;
    s->rx_len = 0;
    s->tx_len = 0;
    s->cmdreq = 0;

    request.cmd = s->cmd;
    request.arg = s->arg;
    request.crc = 0;	/* FIXME */

    rsplen = sd_do_command(s->card, &request, response);
    s->intreq |= INT_END_CMD;

    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
    switch (s->cmdat & CMDAT_RES_TYPE) {
#define PXAMMCI_RESP(wd, value0, value1)	\
        s->resp_fifo[(wd) + 0] |= (value0);	\
        s->resp_fifo[(wd) + 1] |= (value1) << 8;
    case 0:	/* No response */
        goto complete;

    case 1:	/* R1, R4, R5 or R6 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    case 2:	/* R2 */
        if (rsplen < 16)
            goto timeout;
        goto complete;

    case 3:	/* R3 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    complete:
        for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
            PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
        }
        s->status |= STAT_END_CMDRES;

        if (!(s->cmdat & CMDAT_DATA_EN))
            s->active = 0;
        else
            s->bytesleft = s->numblk * s->blklen;

        s->resp_len = 0;
        break;

    timeout:
        s->active = 0;
        s->status |= STAT_TOUT_RES;
        break;
    }

    pxa2xx_mmci_fifo_update(s);
}

static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    uint32_t ret;

    switch (offset) {
    case MMC_STRPCL:
        return 0;
    case MMC_STAT:
        return s->status;
    case MMC_CLKRT:
        return s->clkrt;
    case MMC_SPI:
        return s->spi;
    case MMC_CMDAT:
        return s->cmdat;
    case MMC_RESTO:
        return s->resp_tout;
    case MMC_RDTO:
        return s->read_tout;
    case MMC_BLKLEN:
        return s->blklen;
    case MMC_NUMBLK:
        return s->numblk;
    case MMC_PRTBUF:
        return 0;
    case MMC_I_MASK:
        return s->intmask;
    case MMC_I_REG:
        return s->intreq;
    case MMC_CMD:
        return s->cmd | 0x40;
    case MMC_ARGH:
        return s->arg >> 16;
    case MMC_ARGL:
        return s->arg & 0xffff;
    case MMC_RES:
        if (s->resp_len < 9)
            return s->resp_fifo[s->resp_len ++];
        return 0;
    case MMC_RXFIFO:
        ret = 0;
        while (size-- && s->rx_len) {
            ret |= s->rx_fifo[s->rx_start++] << (size << 3);
            s->rx_start &= 0x1f;
            s->rx_len --;
        }
        s->intreq &= ~INT_RXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        return ret;
    case MMC_RDWAIT:
        return 0;
    case MMC_BLKS_REM:
        return s->numblk;
    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_mmci_write(void *opaque,
                              hwaddr offset, uint64_t value, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;

    switch (offset) {
    case MMC_STRPCL:
        if (value & STRPCL_STRT_CLK) {
            s->status |= STAT_CLK_EN;
            s->intreq &= ~INT_CLK_OFF;

            if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
                s->status &= STAT_CLK_EN;
                pxa2xx_mmci_wakequeues(s);
            }
        }

        if (value & STRPCL_STOP_CLK) {
            s->status &= ~STAT_CLK_EN;
            s->intreq |= INT_CLK_OFF;
            s->active = 0;
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CLKRT:
        s->clkrt = value & 7;
        break;

    case MMC_SPI:
        s->spi = value & 0xf;
        if (value & SPI_SPI_MODE)
            printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
        break;

    case MMC_CMDAT:
        s->cmdat = value & 0x3dff;
        s->active = 0;
        s->cmdreq = 1;
        if (!(value & CMDAT_STOP_TRAN)) {
            s->status &= STAT_CLK_EN;

            if (s->status & STAT_CLK_EN)
                pxa2xx_mmci_wakequeues(s);
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_RESTO:
        s->resp_tout = value & 0x7f;
        break;

    case MMC_RDTO:
        s->read_tout = value & 0xffff;
        break;

    case MMC_BLKLEN:
        s->blklen = value & 0xfff;
        break;

    case MMC_NUMBLK:
        s->numblk = value & 0xffff;
        break;

    case MMC_PRTBUF:
        if (value & PRTBUF_PRT_BUF) {
            s->tx_start ^= 32;
            s->tx_len = 0;
        }
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_I_MASK:
        s->intmask = value & 0x1fff;
        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CMD:
        s->cmd = value & 0x3f;
        break;

    case MMC_ARGH:
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case MMC_ARGL:
        s->arg &= 0xffff0000;
        s->arg |= value & 0x0000ffff;
        break;

    case MMC_TXFIFO:
        while (size-- && s->tx_len < 0x20)
            s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
                    (value >> (size << 3)) & 0xff;
        s->intreq &= ~INT_TXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_RDWAIT:
    case MMC_BLKS_REM:
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static const MemoryRegionOps pxa2xx_mmci_ops = {
    .read = pxa2xx_mmci_read,
    .write = pxa2xx_mmci_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    int i;

    qemu_put_be32s(f, &s->status);
    qemu_put_be32s(f, &s->clkrt);
    qemu_put_be32s(f, &s->spi);
    qemu_put_be32s(f, &s->cmdat);
    qemu_put_be32s(f, &s->resp_tout);
    qemu_put_be32s(f, &s->read_tout);
    qemu_put_be32(f, s->blklen);
    qemu_put_be32(f, s->numblk);
    qemu_put_be32s(f, &s->intmask);
    qemu_put_be32s(f, &s->intreq);
    qemu_put_be32(f, s->cmd);
    qemu_put_be32s(f, &s->arg);
    qemu_put_be32(f, s->cmdreq);
    qemu_put_be32(f, s->active);
    qemu_put_be32(f, s->bytesleft);

    qemu_put_byte(f, s->tx_len);
    for (i = 0; i < s->tx_len; i ++)
        qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);

    qemu_put_byte(f, s->rx_len);
    for (i = 0; i < s->rx_len; i ++)
        qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);

    qemu_put_byte(f, s->resp_len);
    for (i = s->resp_len; i < 9; i ++)
        qemu_put_be16s(f, &s->resp_fifo[i]);
}

static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    int i;

    qemu_get_be32s(f, &s->status);
    qemu_get_be32s(f, &s->clkrt);
    qemu_get_be32s(f, &s->spi);
    qemu_get_be32s(f, &s->cmdat);
    qemu_get_be32s(f, &s->resp_tout);
    qemu_get_be32s(f, &s->read_tout);
    s->blklen = qemu_get_be32(f);
    s->numblk = qemu_get_be32(f);
    qemu_get_be32s(f, &s->intmask);
    qemu_get_be32s(f, &s->intreq);
    s->cmd = qemu_get_be32(f);
    qemu_get_be32s(f, &s->arg);
    s->cmdreq = qemu_get_be32(f);
    s->active = qemu_get_be32(f);
    s->bytesleft = qemu_get_be32(f);

    s->tx_len = qemu_get_byte(f);
    s->tx_start = 0;
    if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0)
        return -EINVAL;
    for (i = 0; i < s->tx_len; i ++)
        s->tx_fifo[i] = qemu_get_byte(f);

    s->rx_len = qemu_get_byte(f);
    s->rx_start = 0;
    if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0)
        return -EINVAL;
    for (i = 0; i < s->rx_len; i ++)
        s->rx_fifo[i] = qemu_get_byte(f);

    s->resp_len = qemu_get_byte(f);
    if (s->resp_len > 9 || s->resp_len < 0)
        return -EINVAL;
    for (i = s->resp_len; i < 9; i ++)
         qemu_get_be16s(f, &s->resp_fifo[i]);

    return 0;
}

PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
                hwaddr base,
                BlockBackend *blk, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma)
{
    DeviceState *dev;
    SysBusDevice *sbd;
    PXA2xxMMCIState *s;

    dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
    s = PXA2XX_MMCI(dev);
    /* Reach into the device and initialize the SD card. This is
     * unclean but will vanish when we update to SDBus APIs.
     */
    s->card = sd_init(s->blk, false);
    if (s->card == NULL) {
        exit(1);
    }
    qdev_init_nofail(dev);
    sbd = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(sbd, 0, base);
    sysbus_connect_irq(sbd, 0, irq);
    qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
    qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
    return s;
}

void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                          qemu_irq coverswitch)
{
    sd_set_cb(s->card, readonly, coverswitch);
}

static void pxa2xx_mmci_instance_init(Object *obj)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
                          "pxa2xx-mmci", 0x00100000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
    qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);

    register_savevm(NULL, "pxa2xx_mmci", 0, 0,
                    pxa2xx_mmci_save, pxa2xx_mmci_load, s);
}

static const TypeInfo pxa2xx_mmci_info = {
    .name = TYPE_PXA2XX_MMCI,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxMMCIState),
    .instance_init = pxa2xx_mmci_instance_init,
};

static void pxa2xx_mmci_register_types(void)
{
    type_register_static(&pxa2xx_mmci_info);
}

type_init(pxa2xx_mmci_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPLv2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
a171fe39 AZ	11	*/
a171fe39 AZ	12
8ef94f0b	13	#include "qemu/osdep.h"
83c9f4ca	14	#include "hw/hw.h"
7a9468c9	15	#include "hw/sysbus.h"
0d09e41a	16	#include "hw/arm/pxa.h"
e3382ef0	17	#include "hw/sd/sd.h"
83c9f4ca	18	#include "hw/qdev.h"
7a9468c9 PM	19	#include "hw/qdev-properties.h"
	20
	21	#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
	22	#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
a171fe39	23
bc24a225	24	struct PXA2xxMMCIState {
7a9468c9 PM	25	SysBusDevice parent_obj;
7a9468c9 PM	26
2bf90458	27	MemoryRegion iomem;
a171fe39	28	qemu_irq irq;
2115c019 AZ	29	qemu_irq rx_dma;
2115c019 AZ	30	qemu_irq tx_dma;
a171fe39	31
7a9468c9	32	BlockBackend *blk;
a171fe39 AZ	33	SDState *card;
	34
	35	uint32_t status;
	36	uint32_t clkrt;
	37	uint32_t spi;
	38	uint32_t cmdat;
	39	uint32_t resp_tout;
	40	uint32_t read_tout;
	41	int blklen;
	42	int numblk;
	43	uint32_t intmask;
	44	uint32_t intreq;
	45	int cmd;
	46	uint32_t arg;
	47
	48	int active;
	49	int bytesleft;
	50	uint8_t tx_fifo[64];
	51	int tx_start;
	52	int tx_len;
	53	uint8_t rx_fifo[32];
	54	int rx_start;
	55	int rx_len;
	56	uint16_t resp_fifo[9];
	57	int resp_len;
	58
	59	int cmdreq;
a171fe39 AZ	60	};
	61
	62	#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
	63	#define MMC_STAT 0x04 /* MMC Status register */
	64	#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
	65	#define MMC_SPI 0x0c /* MMC SPI Mode register */
	66	#define MMC_CMDAT 0x10 /* MMC Command/Data register */
	67	#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
	68	#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
	69	#define MMC_BLKLEN 0x1c /* MMC Block Length register */
	70	#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
	71	#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
	72	#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
	73	#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
	74	#define MMC_CMD 0x30 /* MMC Command register */
	75	#define MMC_ARGH 0x34 /* MMC Argument High register */
	76	#define MMC_ARGL 0x38 /* MMC Argument Low register */
	77	#define MMC_RES 0x3c /* MMC Response FIFO */
	78	#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
	79	#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
	80	#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
	81	#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
	82
	83	/* Bitfield masks */
	84	#define STRPCL_STOP_CLK (1 << 0)
	85	#define STRPCL_STRT_CLK (1 << 1)
	86	#define STAT_TOUT_RES (1 << 1)
	87	#define STAT_CLK_EN (1 << 8)
	88	#define STAT_DATA_DONE (1 << 11)
	89	#define STAT_PRG_DONE (1 << 12)
	90	#define STAT_END_CMDRES (1 << 13)
	91	#define SPI_SPI_MODE (1 << 0)
	92	#define CMDAT_RES_TYPE (3 << 0)
	93	#define CMDAT_DATA_EN (1 << 2)
	94	#define CMDAT_WR_RD (1 << 3)
	95	#define CMDAT_DMA_EN (1 << 7)
	96	#define CMDAT_STOP_TRAN (1 << 10)
	97	#define INT_DATA_DONE (1 << 0)
	98	#define INT_PRG_DONE (1 << 1)
	99	#define INT_END_CMD (1 << 2)
	100	#define INT_STOP_CMD (1 << 3)
	101	#define INT_CLK_OFF (1 << 4)
	102	#define INT_RXFIFO_REQ (1 << 5)
	103	#define INT_TXFIFO_REQ (1 << 6)
	104	#define INT_TINT (1 << 7)
	105	#define INT_DAT_ERR (1 << 8)
	106	#define INT_RES_ERR (1 << 9)
	107	#define INT_RD_STALLED (1 << 10)
	108	#define INT_SDIO_INT (1 << 11)
	109	#define INT_SDIO_SACK (1 << 12)
	110	#define PRTBUF_PRT_BUF (1 << 0)
	111
	112	/* Route internal interrupt lines to the global IC and DMA */
bc24a225	113	static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
a171fe39 AZ	114	{
	115	uint32_t mask = s->intmask;
	116	if (s->cmdat & CMDAT_DMA_EN) {
	117	mask \|= INT_RXFIFO_REQ \| INT_TXFIFO_REQ;
	118
2115c019 AZ	119	qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
2115c019 AZ	120	qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
a171fe39 AZ	121	}
	122
	123	qemu_set_irq(s->irq, !!(s->intreq & ~mask));
	124	}
	125
bc24a225	126	static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
a171fe39 AZ	127	{
	128	if (!s->active)
	129	return;
	130
	131	if (s->cmdat & CMDAT_WR_RD) {
	132	while (s->bytesleft && s->tx_len) {
	133	sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
	134	s->tx_start &= 0x1f;
	135	s->tx_len --;
	136	s->bytesleft --;
	137	}
	138	if (s->bytesleft)
	139	s->intreq \|= INT_TXFIFO_REQ;
	140	} else
	141	while (s->bytesleft && s->rx_len < 32) {
	142	s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
	143	sd_read_data(s->card);
	144	s->bytesleft --;
	145	s->intreq \|= INT_RXFIFO_REQ;
	146	}
	147
	148	if (!s->bytesleft) {
	149	s->active = 0;
	150	s->intreq \|= INT_DATA_DONE;
	151	s->status \|= STAT_DATA_DONE;
	152
	153	if (s->cmdat & CMDAT_WR_RD) {
	154	s->intreq \|= INT_PRG_DONE;
	155	s->status \|= STAT_PRG_DONE;
	156	}
	157	}
	158
	159	pxa2xx_mmci_int_update(s);
	160	}
	161
bc24a225	162	static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
a171fe39 AZ	163	{
a171fe39 AZ	164	int rsplen, i;
bc24a225	165	SDRequest request;
a171fe39 AZ	166	uint8_t response[16];
	167
	168	s->active = 1;
	169	s->rx_len = 0;
	170	s->tx_len = 0;
	171	s->cmdreq = 0;
	172
	173	request.cmd = s->cmd;
	174	request.arg = s->arg;
	175	request.crc = 0; /* FIXME */
	176
	177	rsplen = sd_do_command(s->card, &request, response);
	178	s->intreq \|= INT_END_CMD;
	179
	180	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	181	switch (s->cmdat & CMDAT_RES_TYPE) {
	182	#define PXAMMCI_RESP(wd, value0, value1) \
	183	s->resp_fifo[(wd) + 0] \|= (value0); \
	184	s->resp_fifo[(wd) + 1] \|= (value1) << 8;
	185	case 0: /* No response */
	186	goto complete;
	187
	188	case 1: /* R1, R4, R5 or R6 */
	189	if (rsplen < 4)
	190	goto timeout;
	191	goto complete;
	192
	193	case 2: /* R2 */
	194	if (rsplen < 16)
	195	goto timeout;
	196	goto complete;
	197
	198	case 3: /* R3 */
	199	if (rsplen < 4)
	200	goto timeout;
	201	goto complete;
	202
	203	complete:
	204	for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
	205	PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
	206	}
	207	s->status \|= STAT_END_CMDRES;
	208
	209	if (!(s->cmdat & CMDAT_DATA_EN))
	210	s->active = 0;
	211	else
	212	s->bytesleft = s->numblk * s->blklen;
	213
	214	s->resp_len = 0;
	215	break;
	216
	217	timeout:
	218	s->active = 0;
	219	s->status \|= STAT_TOUT_RES;
	220	break;
	221	}
	222
	223	pxa2xx_mmci_fifo_update(s);
	224	}
	225
13e1e476	226	static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
a171fe39	227	{
bc24a225	228	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39	229	uint32_t ret;
a171fe39 AZ	230
	231	switch (offset) {
	232	case MMC_STRPCL:
	233	return 0;
	234	case MMC_STAT:
	235	return s->status;
	236	case MMC_CLKRT:
	237	return s->clkrt;
	238	case MMC_SPI:
	239	return s->spi;
	240	case MMC_CMDAT:
	241	return s->cmdat;
	242	case MMC_RESTO:
	243	return s->resp_tout;
	244	case MMC_RDTO:
	245	return s->read_tout;
	246	case MMC_BLKLEN:
	247	return s->blklen;
	248	case MMC_NUMBLK:
	249	return s->numblk;
	250	case MMC_PRTBUF:
	251	return 0;
	252	case MMC_I_MASK:
	253	return s->intmask;
	254	case MMC_I_REG:
	255	return s->intreq;
	256	case MMC_CMD:
	257	return s->cmd \| 0x40;
	258	case MMC_ARGH:
	259	return s->arg >> 16;
	260	case MMC_ARGL:
	261	return s->arg & 0xffff;
	262	case MMC_RES:
	263	if (s->resp_len < 9)
	264	return s->resp_fifo[s->resp_len ++];
	265	return 0;
	266	case MMC_RXFIFO:
	267	ret = 0;
13e1e476 PM	268	while (size-- && s->rx_len) {
13e1e476 PM	269	ret \|= s->rx_fifo[s->rx_start++] << (size << 3);
a171fe39 AZ	270	s->rx_start &= 0x1f;
	271	s->rx_len --;
	272	}
	273	s->intreq &= ~INT_RXFIFO_REQ;
	274	pxa2xx_mmci_fifo_update(s);
	275	return ret;
	276	case MMC_RDWAIT:
	277	return 0;
	278	case MMC_BLKS_REM:
	279	return s->numblk;
	280	default:
2ac71179	281	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39 AZ	282	}
	283
	284	return 0;
	285	}
	286
	287	static void pxa2xx_mmci_write(void *opaque,
13e1e476	288	hwaddr offset, uint64_t value, unsigned size)
a171fe39	289	{
bc24a225	290	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	291
	292	switch (offset) {
	293	case MMC_STRPCL:
	294	if (value & STRPCL_STRT_CLK) {
	295	s->status \|= STAT_CLK_EN;
	296	s->intreq &= ~INT_CLK_OFF;
	297
	298	if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
	299	s->status &= STAT_CLK_EN;
	300	pxa2xx_mmci_wakequeues(s);
	301	}
	302	}
	303
	304	if (value & STRPCL_STOP_CLK) {
	305	s->status &= ~STAT_CLK_EN;
	306	s->intreq \|= INT_CLK_OFF;
	307	s->active = 0;
	308	}
	309
	310	pxa2xx_mmci_int_update(s);
	311	break;
	312
	313	case MMC_CLKRT:
	314	s->clkrt = value & 7;
	315	break;
	316
	317	case MMC_SPI:
	318	s->spi = value & 0xf;
	319	if (value & SPI_SPI_MODE)
	320	printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
	321	break;
	322
	323	case MMC_CMDAT:
	324	s->cmdat = value & 0x3dff;
	325	s->active = 0;
	326	s->cmdreq = 1;
	327	if (!(value & CMDAT_STOP_TRAN)) {
	328	s->status &= STAT_CLK_EN;
	329
	330	if (s->status & STAT_CLK_EN)
	331	pxa2xx_mmci_wakequeues(s);
	332	}
	333
	334	pxa2xx_mmci_int_update(s);
	335	break;
	336
	337	case MMC_RESTO:
	338	s->resp_tout = value & 0x7f;
	339	break;
	340
	341	case MMC_RDTO:
	342	s->read_tout = value & 0xffff;
	343	break;
	344
	345	case MMC_BLKLEN:
	346	s->blklen = value & 0xfff;
	347	break;
	348
	349	case MMC_NUMBLK:
	350	s->numblk = value & 0xffff;
	351	break;
	352
	353	case MMC_PRTBUF:
	354	if (value & PRTBUF_PRT_BUF) {
355	s->tx_start ^= 32;
356	s->tx_len = 0;
357	}
358	pxa2xx_mmci_fifo_update(s);
359	break;
360
361	case MMC_I_MASK:
362	s->intmask = value & 0x1fff;
363	pxa2xx_mmci_int_update(s);
364	break;
365
366	case MMC_CMD:
367	s->cmd = value & 0x3f;
368	break;
369
370	case MMC_ARGH:
371	s->arg &= 0x0000ffff;
372	s->arg \|= value << 16;
373	break;
374
375	case MMC_ARGL:
376	s->arg &= 0xffff0000;
377	s->arg \|= value & 0x0000ffff;
378	break;
379
380	case MMC_TXFIFO:
13e1e476	381	while (size-- && s->tx_len < 0x20)
a171fe39	382	s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
13e1e476	383	(value >> (size << 3)) & 0xff;
a171fe39 AZ	384	s->intreq &= ~INT_TXFIFO_REQ;
	385	pxa2xx_mmci_fifo_update(s);
	386	break;
	387
	388	case MMC_RDWAIT:
	389	case MMC_BLKS_REM:
	390	break;
	391
	392	default:
2ac71179	393	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39 AZ	394	}
	395	}
	396
2bf90458	397	static const MemoryRegionOps pxa2xx_mmci_ops = {
13e1e476 PM	398	.read = pxa2xx_mmci_read,
13e1e476 PM	399	.write = pxa2xx_mmci_write,
2bf90458	400	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	401	};
a171fe39 AZ	402
aa941b94 AZ	403	static void pxa2xx_mmci_save(QEMUFile f, void opaque)
aa941b94 AZ	404	{
bc24a225	405	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
aa941b94 AZ	406	int i;
	407
	408	qemu_put_be32s(f, &s->status);
	409	qemu_put_be32s(f, &s->clkrt);
	410	qemu_put_be32s(f, &s->spi);
	411	qemu_put_be32s(f, &s->cmdat);
	412	qemu_put_be32s(f, &s->resp_tout);
	413	qemu_put_be32s(f, &s->read_tout);
	414	qemu_put_be32(f, s->blklen);
	415	qemu_put_be32(f, s->numblk);
	416	qemu_put_be32s(f, &s->intmask);
	417	qemu_put_be32s(f, &s->intreq);
	418	qemu_put_be32(f, s->cmd);
	419	qemu_put_be32s(f, &s->arg);
	420	qemu_put_be32(f, s->cmdreq);
	421	qemu_put_be32(f, s->active);
	422	qemu_put_be32(f, s->bytesleft);
	423
	424	qemu_put_byte(f, s->tx_len);
	425	for (i = 0; i < s->tx_len; i ++)
	426	qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
	427
	428	qemu_put_byte(f, s->rx_len);
	429	for (i = 0; i < s->rx_len; i ++)
	430	qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
	431
	432	qemu_put_byte(f, s->resp_len);
	433	for (i = s->resp_len; i < 9; i ++)
	434	qemu_put_be16s(f, &s->resp_fifo[i]);
	435	}
	436
	437	static int pxa2xx_mmci_load(QEMUFile f, void opaque, int version_id)
	438	{
bc24a225	439	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
aa941b94 AZ	440	int i;
	441
	442	qemu_get_be32s(f, &s->status);
	443	qemu_get_be32s(f, &s->clkrt);
	444	qemu_get_be32s(f, &s->spi);
	445	qemu_get_be32s(f, &s->cmdat);
	446	qemu_get_be32s(f, &s->resp_tout);
	447	qemu_get_be32s(f, &s->read_tout);
	448	s->blklen = qemu_get_be32(f);
	449	s->numblk = qemu_get_be32(f);
	450	qemu_get_be32s(f, &s->intmask);
	451	qemu_get_be32s(f, &s->intreq);
	452	s->cmd = qemu_get_be32(f);
	453	qemu_get_be32s(f, &s->arg);
	454	s->cmdreq = qemu_get_be32(f);
	455	s->active = qemu_get_be32(f);
	456	s->bytesleft = qemu_get_be32(f);
	457
	458	s->tx_len = qemu_get_byte(f);
	459	s->tx_start = 0;
	460	if (s->tx_len >= sizeof(s->tx_fifo) \|\| s->tx_len < 0)
	461	return -EINVAL;
	462	for (i = 0; i < s->tx_len; i ++)
	463	s->tx_fifo[i] = qemu_get_byte(f);
	464
	465	s->rx_len = qemu_get_byte(f);
	466	s->rx_start = 0;
	467	if (s->rx_len >= sizeof(s->rx_fifo) \|\| s->rx_len < 0)
	468	return -EINVAL;
	469	for (i = 0; i < s->rx_len; i ++)
	470	s->rx_fifo[i] = qemu_get_byte(f);
	471
	472	s->resp_len = qemu_get_byte(f);
	473	if (s->resp_len > 9 \|\| s->resp_len < 0)
	474	return -EINVAL;
	475	for (i = s->resp_len; i < 9; i ++)
	476	qemu_get_be16s(f, &s->resp_fifo[i]);
	477
	478	return 0;
	479	}
	480
2bf90458	481	PXA2xxMMCIState pxa2xx_mmci_init(MemoryRegion sysmem,
a8170e5e	482	hwaddr base,
4be74634	483	BlockBackend *blk, qemu_irq irq,
2115c019	484	qemu_irq rx_dma, qemu_irq tx_dma)
a171fe39	485	{
7a9468c9 PM	486	DeviceState *dev;
7a9468c9 PM	487	SysBusDevice *sbd;
bc24a225	488	PXA2xxMMCIState *s;
a171fe39	489
7a9468c9 PM	490	dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
	491	s = PXA2XX_MMCI(dev);
	492	/* Reach into the device and initialize the SD card. This is
	493	* unclean but will vanish when we update to SDBus APIs.
	494	*/
	495	s->card = sd_init(s->blk, false);
4f8a066b KW	496	if (s->card == NULL) {
	497	exit(1);
	498	}
7a9468c9 PM	499	qdev_init_nofail(dev);
	500	sbd = SYS_BUS_DEVICE(dev);
	501	sysbus_mmio_map(sbd, 0, base);
	502	sysbus_connect_irq(sbd, 0, irq);
	503	qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
	504	qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
a171fe39 AZ	505	return s;
	506	}
	507
bc24a225	508	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
7a9468c9	509	qemu_irq coverswitch)
a171fe39	510	{
e1dad5a6	511	sd_set_cb(s->card, readonly, coverswitch);
a171fe39	512	}
7a9468c9 PM	513
	514	static void pxa2xx_mmci_instance_init(Object *obj)
	515	{
	516	PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
	517	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	518	DeviceState *dev = DEVICE(obj);
	519
	520	memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
	521	"pxa2xx-mmci", 0x00100000);
	522	sysbus_init_mmio(sbd, &s->iomem);
	523	sysbus_init_irq(sbd, &s->irq);
	524	qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
	525	qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
	526
	527	register_savevm(NULL, "pxa2xx_mmci", 0, 0,
	528	pxa2xx_mmci_save, pxa2xx_mmci_load, s);
	529	}
	530
	531	static const TypeInfo pxa2xx_mmci_info = {
	532	.name = TYPE_PXA2XX_MMCI,
	533	.parent = TYPE_SYS_BUS_DEVICE,
	534	.instance_size = sizeof(PXA2xxMMCIState),
	535	.instance_init = pxa2xx_mmci_instance_init,
	536	};
	537
	538	static void pxa2xx_mmci_register_types(void)
	539	{
	540	type_register_static(&pxa2xx_mmci_info);
	541	}
	542
	543	type_init(pxa2xx_mmci_register_types)