[mirror_qemu.git] / hw / spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 * Copyright (c) 2010 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */
#include "sysemu.h"
#include "hw.h"
#include "elf.h"
#include "net.h"
#include "blockdev.h"

#include "hw/boards.h"
#include "hw/ppc.h"
#include "hw/loader.h"

#include "hw/spapr.h"
#include "hw/spapr_vio.h"
#include "hw/xics.h"

#include "kvm.h"
#include "kvm_ppc.h"

#include <libfdt.h>

#define KERNEL_LOAD_ADDR        0x00000000
#define INITRD_LOAD_ADDR        0x02800000
#define FDT_MAX_SIZE            0x10000
#define RTAS_MAX_SIZE           0x10000
#define FW_MAX_SIZE             0x400000
#define FW_FILE_NAME            "slof.bin"

#define MIN_RAM_SLOF		512UL

#define TIMEBASE_FREQ           512000000ULL

#define MAX_CPUS                256
#define XICS_IRQS		1024

#define PHANDLE_XICP            0x00001111

sPAPREnvironment *spapr;

static void *spapr_create_fdt_skel(const char *cpu_model,
                                   target_phys_addr_t initrd_base,
                                   target_phys_addr_t initrd_size,
                                   const char *boot_device,
                                   const char *kernel_cmdline,
                                   long hash_shift)
{
    void *fdt;
    CPUState *env;
    uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) };
    uint32_t start_prop = cpu_to_be32(initrd_base);
    uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
    uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
    char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
        "\0hcall-tce\0hcall-vio\0hcall-splpar";
    uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
    int i;
    char *modelname;

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
                    #exp, fdt_strerror(ret));                      \
            exit(1);                                               \
        }                                                          \
    } while (0)

    fdt = g_malloc0(FDT_MAX_SIZE);
    _FDT((fdt_create(fdt, FDT_MAX_SIZE)));

    _FDT((fdt_finish_reservemap(fdt)));

    /* Root node */
    _FDT((fdt_begin_node(fdt, "")));
    _FDT((fdt_property_string(fdt, "device_type", "chrp")));
    _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));

    /* /chosen */
    _FDT((fdt_begin_node(fdt, "chosen")));

    _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
    _FDT((fdt_property(fdt, "linux,initrd-start",
                       &start_prop, sizeof(start_prop))));
    _FDT((fdt_property(fdt, "linux,initrd-end",
                       &end_prop, sizeof(end_prop))));
    _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));

    _FDT((fdt_end_node(fdt)));

    /* memory node */
    _FDT((fdt_begin_node(fdt, "memory@0")));

    _FDT((fdt_property_string(fdt, "device_type", "memory")));
    _FDT((fdt_property(fdt, "reg",
                       mem_reg_property, sizeof(mem_reg_property))));

    _FDT((fdt_end_node(fdt)));

    /* cpus */
    _FDT((fdt_begin_node(fdt, "cpus")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));

    modelname = g_strdup(cpu_model);

    for (i = 0; i < strlen(modelname); i++) {
        modelname[i] = toupper(modelname[i]);
    }

    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        int index = env->cpu_index;
        uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */
        char *nodename;
        uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
                           0xffffffff, 0xffffffff};
        uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
        uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;

        if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
            fprintf(stderr, "Allocation failure\n");
            exit(1);
        }

        _FDT((fdt_begin_node(fdt, nodename)));

        free(nodename);

        _FDT((fdt_property_cell(fdt, "reg", index)));
        _FDT((fdt_property_string(fdt, "device_type", "cpu")));

        _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
        _FDT((fdt_property_cell(fdt, "dcache-block-size",
                                env->dcache_line_size)));
        _FDT((fdt_property_cell(fdt, "icache-block-size",
                                env->icache_line_size)));
        _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
        _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
        _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
        _FDT((fdt_property(fdt, "ibm,pft-size",
                           pft_size_prop, sizeof(pft_size_prop))));
        _FDT((fdt_property_string(fdt, "status", "okay")));
        _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
        _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index)));
        _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
                           gserver_prop, sizeof(gserver_prop))));

        if (env->mmu_model & POWERPC_MMU_1TSEG) {
            _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
                               segs, sizeof(segs))));
        }

        _FDT((fdt_end_node(fdt)));
    }

    g_free(modelname);

    _FDT((fdt_end_node(fdt)));

    /* RTAS */
    _FDT((fdt_begin_node(fdt, "rtas")));

    _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
                       sizeof(hypertas_prop))));

    _FDT((fdt_end_node(fdt)));

    /* interrupt controller */
    _FDT((fdt_begin_node(fdt, "interrupt-controller")));

    _FDT((fdt_property_string(fdt, "device_type",
                              "PowerPC-External-Interrupt-Presentation")));
    _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
    _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
                       interrupt_server_ranges_prop,
                       sizeof(interrupt_server_ranges_prop))));
    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
    _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
    _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));

    _FDT((fdt_end_node(fdt)));

    /* vdevice */
    _FDT((fdt_begin_node(fdt, "vdevice")));

    _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
    _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));

    _FDT((fdt_end_node(fdt)));

    _FDT((fdt_end_node(fdt))); /* close root node */
    _FDT((fdt_finish(fdt)));

    return fdt;
}

static void spapr_finalize_fdt(sPAPREnvironment *spapr,
                               target_phys_addr_t fdt_addr,
                               target_phys_addr_t rtas_addr,
                               target_phys_addr_t rtas_size)
{
    int ret;
    void *fdt;

    fdt = g_malloc(FDT_MAX_SIZE);

    /* open out the base tree into a temp buffer for the final tweaks */
    _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));

    ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
    if (ret < 0) {
        fprintf(stderr, "couldn't setup vio devices in fdt\n");
        exit(1);
    }

    /* RTAS */
    ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
    if (ret < 0) {
        fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
    }

    _FDT((fdt_pack(fdt)));

    cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));

    g_free(fdt);
}

static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}

static void emulate_spapr_hypercall(CPUState *env)
{
    env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
}

static void spapr_reset(void *opaque)
{
    sPAPREnvironment *spapr = (sPAPREnvironment *)opaque;

    fprintf(stderr, "sPAPR reset\n");

    /* flush out the hash table */
    memset(spapr->htab, 0, spapr->htab_size);

    /* Load the fdt */
    spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
                       spapr->rtas_size);

    /* Set up the entry state */
    first_cpu->gpr[3] = spapr->fdt_addr;
    first_cpu->gpr[5] = 0;
    first_cpu->halted = 0;
    first_cpu->nip = spapr->entry_point;

}

/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size,
                           const char *boot_device,
                           const char *kernel_filename,
                           const char *kernel_cmdline,
                           const char *initrd_filename,
                           const char *cpu_model)
{
    CPUState *env;
    int i;
    ram_addr_t ram_offset;
    uint32_t initrd_base;
    long kernel_size, initrd_size, fw_size;
    long pteg_shift = 17;
    char *filename;

    spapr = g_malloc(sizeof(*spapr));
    cpu_ppc_hypercall = emulate_spapr_hypercall;

    /* We place the device tree just below either the top of RAM, or
     * 2GB, so that it can be processed with 32-bit code if
     * necessary */
    spapr->fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
    spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "POWER7";
    }
    for (i = 0; i < smp_cpus; i++) {
        env = cpu_init(cpu_model);

        if (!env) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        /* Set time-base frequency to 512 MHz */
        cpu_ppc_tb_init(env, TIMEBASE_FREQ);
        qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);

        env->hreset_vector = 0x60;
        env->hreset_excp_prefix = 0;
        env->gpr[3] = env->cpu_index;
    }

    /* allocate RAM */
    spapr->ram_limit = ram_size;
    ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", spapr->ram_limit);
    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate hash page table.  For now we always make this 16mb,
     * later we should probably make it scale to the size of guest
     * RAM */
    spapr->htab_size = 1ULL << (pteg_shift + 7);
    spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);

    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        env->external_htab = spapr->htab;
        env->htab_base = -1;
        env->htab_mask = spapr->htab_size - 1;

        /* Tell KVM that we're in PAPR mode */
        env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
                             ((pteg_shift + 7) - 18);
        env->spr[SPR_HIOR] = 0;

        if (kvm_enabled()) {
            kvmppc_set_papr(env);
        }
    }

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
    spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
                                           ram_size - spapr->rtas_addr);
    if (spapr->rtas_size < 0) {
        hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
        exit(1);
    }
    g_free(filename);

    /* Set up Interrupt Controller */
    spapr->icp = xics_system_init(XICS_IRQS);

    /* Set up VIO bus */
    spapr->vio_bus = spapr_vio_bus_init();

    for (i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i,
                             serial_hds[i]);
        }
    }

    for (i = 0; i < nb_nics; i++) {
        NICInfo *nd = &nd_table[i];

        if (!nd->model) {
            nd->model = g_strdup("ibmveth");
        }

        if (strcmp(nd->model, "ibmveth") == 0) {
            spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
        } else {
            fprintf(stderr, "pSeries (sPAPR) platform does not support "
                    "NIC model '%s' (only ibmveth is supported)\n",
                    nd->model);
            exit(1);
        }
    }

    for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
        spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
    }

    if (kernel_filename) {
        uint64_t lowaddr = 0;

        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename,
                                              KERNEL_LOAD_ADDR,
                                              ram_size - KERNEL_LOAD_ADDR);
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }

        spapr->entry_point = KERNEL_LOAD_ADDR;
    } else {
        if (ram_size < (MIN_RAM_SLOF << 20)) {
            fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
                    "%ldM guest RAM\n", MIN_RAM_SLOF);
            exit(1);
        }
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
        fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
        if (fw_size < 0) {
            hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
            exit(1);
        }
        g_free(filename);
        spapr->entry_point = 0x100;
        initrd_base = 0;
        initrd_size = 0;

        /* SLOF will startup the secondary CPUs using RTAS,
           rather than expecting a kexec() style entry */
        for (env = first_cpu; env != NULL; env = env->next_cpu) {
            env->halted = 1;
        }
    }

    /* Prepare the device tree */
    spapr->fdt_skel = spapr_create_fdt_skel(cpu_model,
                                            initrd_base, initrd_size,
                                            boot_device, kernel_cmdline,
                                            pteg_shift + 7);
    assert(spapr->fdt_skel != NULL);

    qemu_register_reset(spapr_reset, spapr);
}

static QEMUMachine spapr_machine = {
    .name = "pseries",
    .desc = "pSeries Logical Partition (PAPR compliant)",
    .init = ppc_spapr_init,
    .max_cpus = MAX_CPUS,
    .no_vga = 1,
    .no_parallel = 1,
    .use_scsi = 1,
};

static void spapr_machine_init(void)
{
    qemu_register_machine(&spapr_machine);
}

machine_init(spapr_machine_init);
Commit	Line	Data
9fdf0c29 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* Copyright (c) 2004-2007 Fabrice Bellard
	5	* Copyright (c) 2007 Jocelyn Mayer
	6	* Copyright (c) 2010 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27	#include "sysemu.h"
9fdf0c29 DG	28	#include "hw.h"
9fdf0c29 DG	29	#include "elf.h"
8d90ad90	30	#include "net.h"
6e270446	31	#include "blockdev.h"
9fdf0c29 DG	32
	33	#include "hw/boards.h"
	34	#include "hw/ppc.h"
	35	#include "hw/loader.h"
	36
	37	#include "hw/spapr.h"
4040ab72	38	#include "hw/spapr_vio.h"
b5cec4c5	39	#include "hw/xics.h"
9fdf0c29	40
f61b4bed AG	41	#include "kvm.h"
	42	#include "kvm_ppc.h"
	43
9fdf0c29 DG	44	#include <libfdt.h>
	45
	46	#define KERNEL_LOAD_ADDR 0x00000000
	47	#define INITRD_LOAD_ADDR 0x02800000
	48	#define FDT_MAX_SIZE 0x10000
39ac8455	49	#define RTAS_MAX_SIZE 0x10000
a9f8ad8f DG	50	#define FW_MAX_SIZE 0x400000
	51	#define FW_FILE_NAME "slof.bin"
	52
	53	#define MIN_RAM_SLOF 512UL
9fdf0c29 DG	54
	55	#define TIMEBASE_FREQ 512000000ULL
	56
41019fec	57	#define MAX_CPUS 256
b5cec4c5	58	#define XICS_IRQS 1024
9fdf0c29	59
0c103f8e DG	60	#define PHANDLE_XICP 0x00001111
0c103f8e DG	61
9fdf0c29 DG	62	sPAPREnvironment *spapr;
9fdf0c29 DG	63
a3467baa DG	64	static void spapr_create_fdt_skel(const char cpu_model,
	65	target_phys_addr_t initrd_base,
	66	target_phys_addr_t initrd_size,
	67	const char *boot_device,
	68	const char *kernel_cmdline,
	69	long hash_shift)
9fdf0c29 DG	70	{
9fdf0c29 DG	71	void *fdt;
c7a5c0c9	72	CPUState *env;
a3467baa	73	uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) };
9fdf0c29 DG	74	uint32_t start_prop = cpu_to_be32(initrd_base);
9fdf0c29 DG	75	uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
f43e3525	76	uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
ee86dfee	77	char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
ed120055	78	"\0hcall-tce\0hcall-vio\0hcall-splpar";
b5cec4c5	79	uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
9fdf0c29 DG	80	int i;
	81	char *modelname;
	82
	83	#define _FDT(exp) \
	84	do { \
	85	int ret = (exp); \
	86	if (ret < 0) { \
	87	fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
	88	#exp, fdt_strerror(ret)); \
	89	exit(1); \
	90	} \
	91	} while (0)
	92
7267c094	93	fdt = g_malloc0(FDT_MAX_SIZE);
9fdf0c29 DG	94	_FDT((fdt_create(fdt, FDT_MAX_SIZE)));
	95
	96	_FDT((fdt_finish_reservemap(fdt)));
	97
	98	/* Root node */
	99	_FDT((fdt_begin_node(fdt, "")));
	100	_FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66	101	_FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
9fdf0c29 DG	102
	103	_FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
	104	_FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
	105
	106	/* /chosen */
	107	_FDT((fdt_begin_node(fdt, "chosen")));
	108
	109	_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
	110	_FDT((fdt_property(fdt, "linux,initrd-start",
	111	&start_prop, sizeof(start_prop))));
	112	_FDT((fdt_property(fdt, "linux,initrd-end",
	113	&end_prop, sizeof(end_prop))));
a9f8ad8f	114	_FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
9fdf0c29 DG	115
	116	_FDT((fdt_end_node(fdt)));
	117
	118	/* memory node */
	119	_FDT((fdt_begin_node(fdt, "memory@0")));
	120
	121	_FDT((fdt_property_string(fdt, "device_type", "memory")));
	122	_FDT((fdt_property(fdt, "reg",
	123	mem_reg_property, sizeof(mem_reg_property))));
	124
	125	_FDT((fdt_end_node(fdt)));
	126
	127	/* cpus */
	128	_FDT((fdt_begin_node(fdt, "cpus")));
	129
	130	_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
	131	_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
	132
7267c094	133	modelname = g_strdup(cpu_model);
9fdf0c29 DG	134
	135	for (i = 0; i < strlen(modelname); i++) {
	136	modelname[i] = toupper(modelname[i]);
	137	}
	138
c7a5c0c9 DG	139	for (env = first_cpu; env != NULL; env = env->next_cpu) {
	140	int index = env->cpu_index;
	141	uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */
9fdf0c29 DG	142	char *nodename;
	143	uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
	144	0xffffffff, 0xffffffff};
0a8b2938 AG	145	uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
0a8b2938 AG	146	uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
9fdf0c29	147
c7a5c0c9	148	if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
9fdf0c29 DG	149	fprintf(stderr, "Allocation failure\n");
	150	exit(1);
	151	}
	152
	153	_FDT((fdt_begin_node(fdt, nodename)));
	154
	155	free(nodename);
	156
c7a5c0c9	157	_FDT((fdt_property_cell(fdt, "reg", index)));
9fdf0c29 DG	158	_FDT((fdt_property_string(fdt, "device_type", "cpu")));
	159
	160	_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
	161	_FDT((fdt_property_cell(fdt, "dcache-block-size",
	162	env->dcache_line_size)));
	163	_FDT((fdt_property_cell(fdt, "icache-block-size",
	164	env->icache_line_size)));
0a8b2938 AG	165	_FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
0a8b2938 AG	166	_FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
9fdf0c29	167	_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
f43e3525 DG	168	_FDT((fdt_property(fdt, "ibm,pft-size",
f43e3525 DG	169	pft_size_prop, sizeof(pft_size_prop))));
9fdf0c29 DG	170	_FDT((fdt_property_string(fdt, "status", "okay")));
9fdf0c29 DG	171	_FDT((fdt_property(fdt, "64-bit", NULL, 0)));
c7a5c0c9	172	_FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index)));
b5cec4c5 DG	173	_FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
b5cec4c5 DG	174	gserver_prop, sizeof(gserver_prop))));
9fdf0c29	175
c7a5c0c9	176	if (env->mmu_model & POWERPC_MMU_1TSEG) {
9fdf0c29 DG	177	_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
	178	segs, sizeof(segs))));
	179	}
	180
	181	_FDT((fdt_end_node(fdt)));
	182	}
	183
7267c094	184	g_free(modelname);
9fdf0c29 DG	185
	186	_FDT((fdt_end_node(fdt)));
	187
f43e3525 DG	188	/* RTAS */
	189	_FDT((fdt_begin_node(fdt, "rtas")));
	190
	191	_FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
	192	sizeof(hypertas_prop))));
	193
	194	_FDT((fdt_end_node(fdt)));
	195
b5cec4c5	196	/* interrupt controller */
9dfef5aa	197	_FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5 DG	198
	199	_FDT((fdt_property_string(fdt, "device_type",
	200	"PowerPC-External-Interrupt-Presentation")));
	201	_FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5 DG	202	_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
	203	_FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
	204	interrupt_server_ranges_prop,
	205	sizeof(interrupt_server_ranges_prop))));
0c103f8e DG	206	_FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
	207	_FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
	208	_FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5 DG	209
	210	_FDT((fdt_end_node(fdt)));
	211
4040ab72 DG	212	/* vdevice */
	213	_FDT((fdt_begin_node(fdt, "vdevice")));
	214
	215	_FDT((fdt_property_string(fdt, "device_type", "vdevice")));
	216	_FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
	217	_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
	218	_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5 DG	219	_FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
b5cec4c5 DG	220	_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72 DG	221
	222	_FDT((fdt_end_node(fdt)));
	223
9fdf0c29 DG	224	_FDT((fdt_end_node(fdt))); /* close root node */
	225	_FDT((fdt_finish(fdt)));
	226
a3467baa DG	227	return fdt;
	228	}
	229
	230	static void spapr_finalize_fdt(sPAPREnvironment *spapr,
	231	target_phys_addr_t fdt_addr,
	232	target_phys_addr_t rtas_addr,
	233	target_phys_addr_t rtas_size)
	234	{
	235	int ret;
	236	void *fdt;
	237
7267c094	238	fdt = g_malloc(FDT_MAX_SIZE);
a3467baa DG	239
	240	/* open out the base tree into a temp buffer for the final tweaks */
	241	_FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 DG	242
	243	ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
	244	if (ret < 0) {
	245	fprintf(stderr, "couldn't setup vio devices in fdt\n");
	246	exit(1);
	247	}
	248
39ac8455 DG	249	/* RTAS */
	250	ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
	251	if (ret < 0) {
	252	fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
	253	}
	254
4040ab72 DG	255	_FDT((fdt_pack(fdt)));
4040ab72 DG	256
a3467baa	257	cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29	258
7267c094	259	g_free(fdt);
9fdf0c29 DG	260	}
	261
	262	static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
	263	{
	264	return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
	265	}
	266
	267	static void emulate_spapr_hypercall(CPUState *env)
	268	{
	269	env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
	270	}
	271
a3467baa DG	272	static void spapr_reset(void *opaque)
	273	{
	274	sPAPREnvironment spapr = (sPAPREnvironment )opaque;
	275
	276	fprintf(stderr, "sPAPR reset\n");
	277
	278	/* flush out the hash table */
	279	memset(spapr->htab, 0, spapr->htab_size);
	280
	281	/* Load the fdt */
	282	spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
	283	spapr->rtas_size);
	284
	285	/* Set up the entry state */
	286	first_cpu->gpr[3] = spapr->fdt_addr;
	287	first_cpu->gpr[5] = 0;
	288	first_cpu->halted = 0;
	289	first_cpu->nip = spapr->entry_point;
	290
	291	}
	292
9fdf0c29 DG	293	/* pSeries LPAR / sPAPR hardware init */
	294	static void ppc_spapr_init(ram_addr_t ram_size,
	295	const char *boot_device,
	296	const char *kernel_filename,
	297	const char *kernel_cmdline,
	298	const char *initrd_filename,
	299	const char *cpu_model)
	300	{
c7a5c0c9	301	CPUState *env;
9fdf0c29 DG	302	int i;
9fdf0c29 DG	303	ram_addr_t ram_offset;
a3467baa DG	304	uint32_t initrd_base;
a3467baa DG	305	long kernel_size, initrd_size, fw_size;
f43e3525	306	long pteg_shift = 17;
39ac8455	307	char *filename;
9fdf0c29	308
7267c094	309	spapr = g_malloc(sizeof(*spapr));
9fdf0c29 DG	310	cpu_ppc_hypercall = emulate_spapr_hypercall;
	311
	312	/* We place the device tree just below either the top of RAM, or
	313	* 2GB, so that it can be processed with 32-bit code if
	314	* necessary */
a3467baa DG	315	spapr->fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
a3467baa DG	316	spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE;
9fdf0c29 DG	317
	318	/* init CPUs */
	319	if (cpu_model == NULL) {
	320	cpu_model = "POWER7";
	321	}
	322	for (i = 0; i < smp_cpus; i++) {
c7a5c0c9	323	env = cpu_init(cpu_model);
9fdf0c29 DG	324
	325	if (!env) {
	326	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	327	exit(1);
	328	}
	329	/* Set time-base frequency to 512 MHz */
	330	cpu_ppc_tb_init(env, TIMEBASE_FREQ);
	331	qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
	332
	333	env->hreset_vector = 0x60;
	334	env->hreset_excp_prefix = 0;
c7a5c0c9	335	env->gpr[3] = env->cpu_index;
9fdf0c29 DG	336	}
	337
	338	/* allocate RAM */
f73a2575 DG	339	spapr->ram_limit = ram_size;
f73a2575 DG	340	ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", spapr->ram_limit);
9fdf0c29 DG	341	cpu_register_physical_memory(0, ram_size, ram_offset);
9fdf0c29 DG	342
f43e3525 DG	343	/* allocate hash page table. For now we always make this 16mb,
	344	* later we should probably make it scale to the size of guest
	345	* RAM */
a3467baa	346	spapr->htab_size = 1ULL << (pteg_shift + 7);
f61b4bed	347	spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);
f43e3525	348
c7a5c0c9	349	for (env = first_cpu; env != NULL; env = env->next_cpu) {
a3467baa	350	env->external_htab = spapr->htab;
c7a5c0c9	351	env->htab_base = -1;
a3467baa	352	env->htab_mask = spapr->htab_size - 1;
f61b4bed AG	353
	354	/* Tell KVM that we're in PAPR mode */
	355	env->spr[SPR_SDR1] = (unsigned long)spapr->htab \|
	356	((pteg_shift + 7) - 18);
	357	env->spr[SPR_HIOR] = 0;
	358
	359	if (kvm_enabled()) {
	360	kvmppc_set_papr(env);
	361	}
f43e3525 DG	362	}
f43e3525 DG	363
39ac8455	364	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
a3467baa DG	365	spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
	366	ram_size - spapr->rtas_addr);
	367	if (spapr->rtas_size < 0) {
39ac8455 DG	368	hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
	369	exit(1);
	370	}
7267c094	371	g_free(filename);
39ac8455	372
b5cec4c5	373	/* Set up Interrupt Controller */
c7a5c0c9	374	spapr->icp = xics_system_init(XICS_IRQS);
b5cec4c5 DG	375
b5cec4c5 DG	376	/* Set up VIO bus */
4040ab72 DG	377	spapr->vio_bus = spapr_vio_bus_init();
4040ab72 DG	378
277f9acf	379	for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72	380	if (serial_hds[i]) {
b4a78527	381	spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i,
277f9acf	382	serial_hds[i]);
4040ab72 DG	383	}
4040ab72 DG	384	}
9fdf0c29	385
277f9acf	386	for (i = 0; i < nb_nics; i++) {
8d90ad90 DG	387	NICInfo *nd = &nd_table[i];
	388
	389	if (!nd->model) {
7267c094	390	nd->model = g_strdup("ibmveth");
8d90ad90 DG	391	}
	392
	393	if (strcmp(nd->model, "ibmveth") == 0) {
277f9acf	394	spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
8d90ad90 DG	395	} else {
	396	fprintf(stderr, "pSeries (sPAPR) platform does not support "
	397	"NIC model '%s' (only ibmveth is supported)\n",
	398	nd->model);
	399	exit(1);
	400	}
	401	}
	402
6e270446	403	for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
277f9acf	404	spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
6e270446 BH	405	}
6e270446 BH	406
9fdf0c29 DG	407	if (kernel_filename) {
	408	uint64_t lowaddr = 0;
	409
9fdf0c29 DG	410	kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
	411	NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
	412	if (kernel_size < 0) {
a3467baa DG	413	kernel_size = load_image_targphys(kernel_filename,
	414	KERNEL_LOAD_ADDR,
	415	ram_size - KERNEL_LOAD_ADDR);
9fdf0c29 DG	416	}
	417	if (kernel_size < 0) {
	418	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	419	kernel_filename);
	420	exit(1);
	421	}
	422
	423	/* load initrd */
	424	if (initrd_filename) {
	425	initrd_base = INITRD_LOAD_ADDR;
	426	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	427	ram_size - initrd_base);
	428	if (initrd_size < 0) {
	429	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	430	initrd_filename);
	431	exit(1);
	432	}
	433	} else {
	434	initrd_base = 0;
	435	initrd_size = 0;
	436	}
a3467baa DG	437
a3467baa DG	438	spapr->entry_point = KERNEL_LOAD_ADDR;
9fdf0c29	439	} else {
a9f8ad8f DG	440	if (ram_size < (MIN_RAM_SLOF << 20)) {
	441	fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
	442	"%ldM guest RAM\n", MIN_RAM_SLOF);
	443	exit(1);
	444	}
68722054	445	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
a9f8ad8f DG	446	fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
	447	if (fw_size < 0) {
	448	hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
	449	exit(1);
	450	}
7267c094	451	g_free(filename);
a3467baa	452	spapr->entry_point = 0x100;
a9f8ad8f DG	453	initrd_base = 0;
	454	initrd_size = 0;
	455
	456	/* SLOF will startup the secondary CPUs using RTAS,
	457	rather than expecting a kexec() style entry */
c7a5c0c9 DG	458	for (env = first_cpu; env != NULL; env = env->next_cpu) {
c7a5c0c9 DG	459	env->halted = 1;
a9f8ad8f	460	}
9fdf0c29 DG	461	}
	462
	463	/* Prepare the device tree */
a3467baa DG	464	spapr->fdt_skel = spapr_create_fdt_skel(cpu_model,
	465	initrd_base, initrd_size,
	466	boot_device, kernel_cmdline,
	467	pteg_shift + 7);
	468	assert(spapr->fdt_skel != NULL);
9fdf0c29	469
a3467baa	470	qemu_register_reset(spapr_reset, spapr);
9fdf0c29 DG	471	}
	472
	473	static QEMUMachine spapr_machine = {
	474	.name = "pseries",
	475	.desc = "pSeries Logical Partition (PAPR compliant)",
	476	.init = ppc_spapr_init,
	477	.max_cpus = MAX_CPUS,
	478	.no_vga = 1,
	479	.no_parallel = 1,
6e270446	480	.use_scsi = 1,
9fdf0c29 DG	481	};
	482
	483	static void spapr_machine_init(void)
	484	{
	485	qemu_register_machine(&spapr_machine);
	486	}
	487
	488	machine_init(spapr_machine_init);