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9fdf0c29 DG |
1 | #include "sysemu.h" |
2 | #include "cpu.h" | |
3 | #include "qemu-char.h" | |
f43e3525 DG |
4 | #include "sysemu.h" |
5 | #include "qemu-char.h" | |
6 | #include "exec-all.h" | |
ed120055 DG |
7 | #include "exec.h" |
8 | #include "helper_regs.h" | |
9fdf0c29 DG |
9 | #include "hw/spapr.h" |
10 | ||
f43e3525 DG |
11 | #define HPTES_PER_GROUP 8 |
12 | ||
13 | #define HPTE_V_SSIZE_SHIFT 62 | |
14 | #define HPTE_V_AVPN_SHIFT 7 | |
15 | #define HPTE_V_AVPN 0x3fffffffffffff80ULL | |
16 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) | |
17 | #define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) | |
18 | #define HPTE_V_BOLTED 0x0000000000000010ULL | |
19 | #define HPTE_V_LOCK 0x0000000000000008ULL | |
20 | #define HPTE_V_LARGE 0x0000000000000004ULL | |
21 | #define HPTE_V_SECONDARY 0x0000000000000002ULL | |
22 | #define HPTE_V_VALID 0x0000000000000001ULL | |
23 | ||
24 | #define HPTE_R_PP0 0x8000000000000000ULL | |
25 | #define HPTE_R_TS 0x4000000000000000ULL | |
26 | #define HPTE_R_KEY_HI 0x3000000000000000ULL | |
27 | #define HPTE_R_RPN_SHIFT 12 | |
28 | #define HPTE_R_RPN 0x3ffffffffffff000ULL | |
29 | #define HPTE_R_FLAGS 0x00000000000003ffULL | |
30 | #define HPTE_R_PP 0x0000000000000003ULL | |
31 | #define HPTE_R_N 0x0000000000000004ULL | |
32 | #define HPTE_R_G 0x0000000000000008ULL | |
33 | #define HPTE_R_M 0x0000000000000010ULL | |
34 | #define HPTE_R_I 0x0000000000000020ULL | |
35 | #define HPTE_R_W 0x0000000000000040ULL | |
36 | #define HPTE_R_WIMG 0x0000000000000078ULL | |
37 | #define HPTE_R_C 0x0000000000000080ULL | |
38 | #define HPTE_R_R 0x0000000000000100ULL | |
39 | #define HPTE_R_KEY_LO 0x0000000000000e00ULL | |
40 | ||
41 | #define HPTE_V_1TB_SEG 0x4000000000000000ULL | |
42 | #define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL | |
43 | ||
44 | #define HPTE_V_HVLOCK 0x40ULL | |
45 | ||
46 | static inline int lock_hpte(void *hpte, target_ulong bits) | |
47 | { | |
48 | uint64_t pteh; | |
49 | ||
50 | pteh = ldq_p(hpte); | |
51 | ||
52 | /* We're protected by qemu's global lock here */ | |
53 | if (pteh & bits) { | |
54 | return 0; | |
55 | } | |
56 | stq_p(hpte, pteh | HPTE_V_HVLOCK); | |
57 | return 1; | |
58 | } | |
59 | ||
60 | static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, | |
61 | target_ulong pte_index) | |
62 | { | |
63 | target_ulong rb, va_low; | |
64 | ||
65 | rb = (v & ~0x7fULL) << 16; /* AVA field */ | |
66 | va_low = pte_index >> 3; | |
67 | if (v & HPTE_V_SECONDARY) { | |
68 | va_low = ~va_low; | |
69 | } | |
70 | /* xor vsid from AVA */ | |
71 | if (!(v & HPTE_V_1TB_SEG)) { | |
72 | va_low ^= v >> 12; | |
73 | } else { | |
74 | va_low ^= v >> 24; | |
75 | } | |
76 | va_low &= 0x7ff; | |
77 | if (v & HPTE_V_LARGE) { | |
78 | rb |= 1; /* L field */ | |
79 | #if 0 /* Disable that P7 specific bit for now */ | |
80 | if (r & 0xff000) { | |
81 | /* non-16MB large page, must be 64k */ | |
82 | /* (masks depend on page size) */ | |
83 | rb |= 0x1000; /* page encoding in LP field */ | |
84 | rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */ | |
85 | rb |= (va_low & 0xfe); /* AVAL field */ | |
86 | } | |
87 | #endif | |
88 | } else { | |
89 | /* 4kB page */ | |
90 | rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ | |
91 | } | |
92 | rb |= (v >> 54) & 0x300; /* B field */ | |
93 | return rb; | |
94 | } | |
95 | ||
96 | static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr, | |
97 | target_ulong opcode, target_ulong *args) | |
98 | { | |
99 | target_ulong flags = args[0]; | |
100 | target_ulong pte_index = args[1]; | |
101 | target_ulong pteh = args[2]; | |
102 | target_ulong ptel = args[3]; | |
103 | target_ulong porder; | |
104 | target_ulong i, pa; | |
105 | uint8_t *hpte; | |
106 | ||
107 | /* only handle 4k and 16M pages for now */ | |
108 | porder = 12; | |
109 | if (pteh & HPTE_V_LARGE) { | |
110 | #if 0 /* We don't support 64k pages yet */ | |
111 | if ((ptel & 0xf000) == 0x1000) { | |
112 | /* 64k page */ | |
113 | porder = 16; | |
114 | } else | |
115 | #endif | |
116 | if ((ptel & 0xff000) == 0) { | |
117 | /* 16M page */ | |
118 | porder = 24; | |
119 | /* lowest AVA bit must be 0 for 16M pages */ | |
120 | if (pteh & 0x80) { | |
121 | return H_PARAMETER; | |
122 | } | |
123 | } else { | |
124 | return H_PARAMETER; | |
125 | } | |
126 | } | |
127 | ||
128 | pa = ptel & HPTE_R_RPN; | |
129 | /* FIXME: bounds check the pa? */ | |
130 | ||
131 | /* Check WIMG */ | |
132 | if ((ptel & HPTE_R_WIMG) != HPTE_R_M) { | |
133 | return H_PARAMETER; | |
134 | } | |
135 | pteh &= ~0x60ULL; | |
136 | ||
137 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
138 | return H_PARAMETER; | |
139 | } | |
140 | if (likely((flags & H_EXACT) == 0)) { | |
141 | pte_index &= ~7ULL; | |
142 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
143 | for (i = 0; ; ++i) { | |
144 | if (i == 8) { | |
145 | return H_PTEG_FULL; | |
146 | } | |
147 | if (((ldq_p(hpte) & HPTE_V_VALID) == 0) && | |
148 | lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) { | |
149 | break; | |
150 | } | |
151 | hpte += HASH_PTE_SIZE_64; | |
152 | } | |
153 | } else { | |
154 | i = 0; | |
155 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
156 | if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) { | |
157 | return H_PTEG_FULL; | |
158 | } | |
159 | } | |
160 | stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel); | |
161 | /* eieio(); FIXME: need some sort of barrier for smp? */ | |
162 | stq_p(hpte, pteh); | |
163 | ||
164 | assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); | |
165 | args[0] = pte_index + i; | |
166 | return H_SUCCESS; | |
167 | } | |
168 | ||
169 | static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr, | |
170 | target_ulong opcode, target_ulong *args) | |
171 | { | |
172 | target_ulong flags = args[0]; | |
173 | target_ulong pte_index = args[1]; | |
174 | target_ulong avpn = args[2]; | |
175 | uint8_t *hpte; | |
176 | target_ulong v, r, rb; | |
177 | ||
178 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
179 | return H_PARAMETER; | |
180 | } | |
181 | ||
182 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
183 | while (!lock_hpte(hpte, HPTE_V_HVLOCK)) { | |
184 | /* We have no real concurrency in qemu soft-emulation, so we | |
185 | * will never actually have a contested lock */ | |
186 | assert(0); | |
187 | } | |
188 | ||
189 | v = ldq_p(hpte); | |
190 | r = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
191 | ||
192 | if ((v & HPTE_V_VALID) == 0 || | |
193 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || | |
194 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
195 | stq_p(hpte, v & ~HPTE_V_HVLOCK); | |
196 | assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); | |
197 | return H_NOT_FOUND; | |
198 | } | |
199 | args[0] = v & ~HPTE_V_HVLOCK; | |
200 | args[1] = r; | |
201 | stq_p(hpte, 0); | |
202 | rb = compute_tlbie_rb(v, r, pte_index); | |
203 | ppc_tlb_invalidate_one(env, rb); | |
204 | assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); | |
205 | return H_SUCCESS; | |
206 | } | |
207 | ||
208 | static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr, | |
209 | target_ulong opcode, target_ulong *args) | |
210 | { | |
211 | target_ulong flags = args[0]; | |
212 | target_ulong pte_index = args[1]; | |
213 | target_ulong avpn = args[2]; | |
214 | uint8_t *hpte; | |
215 | target_ulong v, r, rb; | |
216 | ||
217 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
218 | return H_PARAMETER; | |
219 | } | |
220 | ||
221 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
222 | while (!lock_hpte(hpte, HPTE_V_HVLOCK)) { | |
223 | /* We have no real concurrency in qemu soft-emulation, so we | |
224 | * will never actually have a contested lock */ | |
225 | assert(0); | |
226 | } | |
227 | ||
228 | v = ldq_p(hpte); | |
229 | r = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
230 | ||
231 | if ((v & HPTE_V_VALID) == 0 || | |
232 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { | |
233 | stq_p(hpte, v & ~HPTE_V_HVLOCK); | |
234 | assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); | |
235 | return H_NOT_FOUND; | |
236 | } | |
237 | ||
238 | r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N | | |
239 | HPTE_R_KEY_HI | HPTE_R_KEY_LO); | |
240 | r |= (flags << 55) & HPTE_R_PP0; | |
241 | r |= (flags << 48) & HPTE_R_KEY_HI; | |
242 | r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO); | |
243 | rb = compute_tlbie_rb(v, r, pte_index); | |
244 | stq_p(hpte, v & ~HPTE_V_VALID); | |
245 | ppc_tlb_invalidate_one(env, rb); | |
246 | stq_p(hpte + (HASH_PTE_SIZE_64/2), r); | |
247 | /* Don't need a memory barrier, due to qemu's global lock */ | |
248 | stq_p(hpte, v & ~HPTE_V_HVLOCK); | |
249 | assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); | |
250 | return H_SUCCESS; | |
251 | } | |
252 | ||
821303f5 DG |
253 | static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr, |
254 | target_ulong opcode, target_ulong *args) | |
255 | { | |
256 | /* FIXME: actually implement this */ | |
257 | return H_HARDWARE; | |
258 | } | |
259 | ||
ed120055 DG |
260 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
261 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
262 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
263 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
264 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
265 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
266 | ||
267 | #define VPA_MIN_SIZE 640 | |
268 | #define VPA_SIZE_OFFSET 0x4 | |
269 | #define VPA_SHARED_PROC_OFFSET 0x9 | |
270 | #define VPA_SHARED_PROC_VAL 0x2 | |
271 | ||
272 | static target_ulong register_vpa(CPUState *env, target_ulong vpa) | |
273 | { | |
274 | uint16_t size; | |
275 | uint8_t tmp; | |
276 | ||
277 | if (vpa == 0) { | |
278 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
279 | return H_HARDWARE; | |
280 | } | |
281 | ||
282 | if (vpa % env->dcache_line_size) { | |
283 | return H_PARAMETER; | |
284 | } | |
285 | /* FIXME: bounds check the address */ | |
286 | ||
287 | size = lduw_phys(vpa + 0x4); | |
288 | ||
289 | if (size < VPA_MIN_SIZE) { | |
290 | return H_PARAMETER; | |
291 | } | |
292 | ||
293 | /* VPA is not allowed to cross a page boundary */ | |
294 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
295 | return H_PARAMETER; | |
296 | } | |
297 | ||
298 | env->vpa = vpa; | |
299 | ||
300 | tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET); | |
301 | tmp |= VPA_SHARED_PROC_VAL; | |
302 | stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp); | |
303 | ||
304 | return H_SUCCESS; | |
305 | } | |
306 | ||
307 | static target_ulong deregister_vpa(CPUState *env, target_ulong vpa) | |
308 | { | |
309 | if (env->slb_shadow) { | |
310 | return H_RESOURCE; | |
311 | } | |
312 | ||
313 | if (env->dispatch_trace_log) { | |
314 | return H_RESOURCE; | |
315 | } | |
316 | ||
317 | env->vpa = 0; | |
318 | return H_SUCCESS; | |
319 | } | |
320 | ||
321 | static target_ulong register_slb_shadow(CPUState *env, target_ulong addr) | |
322 | { | |
323 | uint32_t size; | |
324 | ||
325 | if (addr == 0) { | |
326 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
327 | return H_HARDWARE; | |
328 | } | |
329 | ||
330 | size = ldl_phys(addr + 0x4); | |
331 | if (size < 0x8) { | |
332 | return H_PARAMETER; | |
333 | } | |
334 | ||
335 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
336 | return H_PARAMETER; | |
337 | } | |
338 | ||
339 | if (!env->vpa) { | |
340 | return H_RESOURCE; | |
341 | } | |
342 | ||
343 | env->slb_shadow = addr; | |
344 | ||
345 | return H_SUCCESS; | |
346 | } | |
347 | ||
348 | static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr) | |
349 | { | |
350 | env->slb_shadow = 0; | |
351 | return H_SUCCESS; | |
352 | } | |
353 | ||
354 | static target_ulong register_dtl(CPUState *env, target_ulong addr) | |
355 | { | |
356 | uint32_t size; | |
357 | ||
358 | if (addr == 0) { | |
359 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
360 | return H_HARDWARE; | |
361 | } | |
362 | ||
363 | size = ldl_phys(addr + 0x4); | |
364 | ||
365 | if (size < 48) { | |
366 | return H_PARAMETER; | |
367 | } | |
368 | ||
369 | if (!env->vpa) { | |
370 | return H_RESOURCE; | |
371 | } | |
372 | ||
373 | env->dispatch_trace_log = addr; | |
374 | env->dtl_size = size; | |
375 | ||
376 | return H_SUCCESS; | |
377 | } | |
378 | ||
379 | static target_ulong deregister_dtl(CPUState *emv, target_ulong addr) | |
380 | { | |
381 | env->dispatch_trace_log = 0; | |
382 | env->dtl_size = 0; | |
383 | ||
384 | return H_SUCCESS; | |
385 | } | |
386 | ||
387 | static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr, | |
388 | target_ulong opcode, target_ulong *args) | |
389 | { | |
390 | target_ulong flags = args[0]; | |
391 | target_ulong procno = args[1]; | |
392 | target_ulong vpa = args[2]; | |
393 | target_ulong ret = H_PARAMETER; | |
394 | CPUState *tenv; | |
395 | ||
396 | for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) { | |
397 | if (tenv->cpu_index == procno) { | |
398 | break; | |
399 | } | |
400 | } | |
401 | ||
402 | if (!tenv) { | |
403 | return H_PARAMETER; | |
404 | } | |
405 | ||
406 | switch (flags) { | |
407 | case FLAGS_REGISTER_VPA: | |
408 | ret = register_vpa(tenv, vpa); | |
409 | break; | |
410 | ||
411 | case FLAGS_DEREGISTER_VPA: | |
412 | ret = deregister_vpa(tenv, vpa); | |
413 | break; | |
414 | ||
415 | case FLAGS_REGISTER_SLBSHADOW: | |
416 | ret = register_slb_shadow(tenv, vpa); | |
417 | break; | |
418 | ||
419 | case FLAGS_DEREGISTER_SLBSHADOW: | |
420 | ret = deregister_slb_shadow(tenv, vpa); | |
421 | break; | |
422 | ||
423 | case FLAGS_REGISTER_DTL: | |
424 | ret = register_dtl(tenv, vpa); | |
425 | break; | |
426 | ||
427 | case FLAGS_DEREGISTER_DTL: | |
428 | ret = deregister_dtl(tenv, vpa); | |
429 | break; | |
430 | } | |
431 | ||
432 | return ret; | |
433 | } | |
434 | ||
435 | static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr, | |
436 | target_ulong opcode, target_ulong *args) | |
437 | { | |
438 | env->msr |= (1ULL << MSR_EE); | |
439 | hreg_compute_hflags(env); | |
440 | if (!cpu_has_work(env)) { | |
441 | env->halted = 1; | |
442 | } | |
443 | return H_SUCCESS; | |
444 | } | |
445 | ||
39ac8455 DG |
446 | static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr, |
447 | target_ulong opcode, target_ulong *args) | |
448 | { | |
449 | target_ulong rtas_r3 = args[0]; | |
450 | uint32_t token = ldl_phys(rtas_r3); | |
451 | uint32_t nargs = ldl_phys(rtas_r3 + 4); | |
452 | uint32_t nret = ldl_phys(rtas_r3 + 8); | |
453 | ||
454 | return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12, | |
455 | nret, rtas_r3 + 12 + 4*nargs); | |
456 | } | |
457 | ||
458 | spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; | |
459 | spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
460 | |
461 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
462 | { | |
39ac8455 DG |
463 | spapr_hcall_fn *slot; |
464 | ||
465 | if (opcode <= MAX_HCALL_OPCODE) { | |
466 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 467 | |
39ac8455 DG |
468 | slot = &papr_hypercall_table[opcode / 4]; |
469 | } else { | |
470 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 471 | |
9fdf0c29 | 472 | |
39ac8455 DG |
473 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
474 | } | |
9fdf0c29 | 475 | |
39ac8455 DG |
476 | assert(!(*slot) || (fn == *slot)); |
477 | *slot = fn; | |
9fdf0c29 DG |
478 | } |
479 | ||
480 | target_ulong spapr_hypercall(CPUState *env, target_ulong opcode, | |
481 | target_ulong *args) | |
482 | { | |
483 | if (msr_pr) { | |
484 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
485 | return H_PRIVILEGE; | |
486 | } | |
487 | ||
488 | if ((opcode <= MAX_HCALL_OPCODE) | |
489 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
490 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
491 | ||
492 | if (fn) { | |
493 | return fn(env, spapr, opcode, args); | |
494 | } | |
495 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
496 | (opcode <= KVMPPC_HCALL_MAX)) { | |
497 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
498 | |
499 | if (fn) { | |
500 | return fn(env, spapr, opcode, args); | |
501 | } | |
502 | } | |
503 | ||
504 | hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); | |
505 | return H_FUNCTION; | |
506 | } | |
f43e3525 DG |
507 | |
508 | static void hypercall_init(void) | |
509 | { | |
510 | /* hcall-pft */ | |
511 | spapr_register_hypercall(H_ENTER, h_enter); | |
512 | spapr_register_hypercall(H_REMOVE, h_remove); | |
513 | spapr_register_hypercall(H_PROTECT, h_protect); | |
39ac8455 | 514 | |
821303f5 DG |
515 | /* hcall-dabr */ |
516 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); | |
517 | ||
ed120055 DG |
518 | /* hcall-splpar */ |
519 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
520 | spapr_register_hypercall(H_CEDE, h_cede); | |
521 | ||
39ac8455 DG |
522 | /* qemu/KVM-PPC specific hcalls */ |
523 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
f43e3525 DG |
524 | } |
525 | device_init(hypercall_init); |