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4040ab72 DG |
1 | #ifndef _HW_SPAPR_VIO_H |
2 | #define _HW_SPAPR_VIO_H | |
3 | /* | |
4 | * QEMU sPAPR VIO bus definitions | |
5 | * | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation <david@gibson.dropbear.id.au> | |
7 | * Based on the s390 virtio bus definitions: | |
8 | * Copyright (c) 2009 Alexander Graf <agraf@suse.de> | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
22 | */ | |
23 | ||
ee86dfee DG |
24 | #define SPAPR_VIO_TCE_PAGE_SHIFT 12 |
25 | #define SPAPR_VIO_TCE_PAGE_SIZE (1ULL << SPAPR_VIO_TCE_PAGE_SHIFT) | |
26 | #define SPAPR_VIO_TCE_PAGE_MASK (SPAPR_VIO_TCE_PAGE_SIZE - 1) | |
27 | ||
28 | enum VIOsPAPR_TCEAccess { | |
29 | SPAPR_TCE_FAULT = 0, | |
30 | SPAPR_TCE_RO = 1, | |
31 | SPAPR_TCE_WO = 2, | |
32 | SPAPR_TCE_RW = 3, | |
33 | }; | |
34 | ||
35 | typedef struct VIOsPAPR_RTCE { | |
36 | uint64_t tce; | |
37 | } VIOsPAPR_RTCE; | |
38 | ||
4040ab72 DG |
39 | typedef struct VIOsPAPRDevice { |
40 | DeviceState qdev; | |
41 | uint32_t reg; | |
00dc738d DG |
42 | qemu_irq qirq; |
43 | uint32_t vio_irq_num; | |
44 | target_ulong signal_state; | |
ee86dfee DG |
45 | uint32_t rtce_window_size; |
46 | VIOsPAPR_RTCE *rtce_table; | |
4040ab72 DG |
47 | } VIOsPAPRDevice; |
48 | ||
49 | typedef struct VIOsPAPRBus { | |
50 | BusState bus; | |
51 | } VIOsPAPRBus; | |
52 | ||
53 | typedef struct { | |
54 | DeviceInfo qdev; | |
55 | const char *dt_name, *dt_type, *dt_compatible; | |
00dc738d | 56 | target_ulong signal_mask; |
4040ab72 DG |
57 | int (*init)(VIOsPAPRDevice *dev); |
58 | void (*hcalls)(VIOsPAPRBus *bus); | |
59 | int (*devnode)(VIOsPAPRDevice *dev, void *fdt, int node_off); | |
60 | } VIOsPAPRDeviceInfo; | |
61 | ||
62 | extern VIOsPAPRBus *spapr_vio_bus_init(void); | |
63 | extern VIOsPAPRDevice *spapr_vio_find_by_reg(VIOsPAPRBus *bus, uint32_t reg); | |
64 | extern void spapr_vio_bus_register_withprop(VIOsPAPRDeviceInfo *info); | |
65 | extern int spapr_populate_vdevice(VIOsPAPRBus *bus, void *fdt); | |
66 | ||
00dc738d DG |
67 | extern int spapr_vio_signal(VIOsPAPRDevice *dev, target_ulong mode); |
68 | ||
ee86dfee DG |
69 | int spapr_vio_check_tces(VIOsPAPRDevice *dev, target_ulong ioba, |
70 | target_ulong len, | |
71 | enum VIOsPAPR_TCEAccess access); | |
72 | ||
73 | int spapr_tce_dma_read(VIOsPAPRDevice *dev, uint64_t taddr, | |
74 | void *buf, uint32_t size); | |
75 | int spapr_tce_dma_write(VIOsPAPRDevice *dev, uint64_t taddr, | |
76 | const void *buf, uint32_t size); | |
77 | int spapr_tce_dma_zero(VIOsPAPRDevice *dev, uint64_t taddr, uint32_t size); | |
78 | void stb_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint8_t val); | |
79 | void sth_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint16_t val); | |
80 | void stw_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint32_t val); | |
81 | void stq_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint64_t val); | |
82 | uint64_t ldq_tce(VIOsPAPRDevice *dev, uint64_t taddr); | |
83 | ||
4040ab72 DG |
84 | void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len); |
85 | void spapr_vty_create(VIOsPAPRBus *bus, | |
0201e2da DG |
86 | uint32_t reg, CharDriverState *chardev, |
87 | qemu_irq qirq, uint32_t vio_irq_num); | |
4040ab72 DG |
88 | |
89 | #endif /* _HW_SPAPR_VIO_H */ |