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Commit | Line | Data |
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420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/sysbus.h" |
1de7afc9 | 25 | #include "qemu/timer.h" |
0d09e41a PB |
26 | #include "hw/sparc/sun4m.h" |
27 | #include "hw/timer/m48t59.h" | |
28 | #include "hw/sparc/sparc32_dma.h" | |
29 | #include "hw/block/fdc.h" | |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
1422e32d | 31 | #include "net/net.h" |
83c9f4ca | 32 | #include "hw/boards.h" |
ec0503b4 | 33 | #include "hw/nvram/openbios_firmware_abi.h" |
0d09e41a PB |
34 | #include "hw/scsi/esp.h" |
35 | #include "hw/i386/pc.h" | |
36 | #include "hw/isa/isa.h" | |
37 | #include "hw/nvram/fw_cfg.h" | |
38 | #include "hw/char/escc.h" | |
83c9f4ca | 39 | #include "hw/empty_slot.h" |
83c9f4ca | 40 | #include "hw/loader.h" |
ca20cf32 | 41 | #include "elf.h" |
9c17d615 | 42 | #include "sysemu/blockdev.h" |
97bf4851 | 43 | #include "trace.h" |
420557e8 | 44 | |
36cd9210 BS |
45 | /* |
46 | * Sun4m architecture was used in the following machines: | |
47 | * | |
48 | * SPARCserver 6xxMP/xx | |
77f193da BS |
49 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
50 | * SPARCclassic X (4/10) | |
36cd9210 BS |
51 | * SPARCstation LX/ZX (4/30) |
52 | * SPARCstation Voyager | |
53 | * SPARCstation 10/xx, SPARCserver 10/xx | |
54 | * SPARCstation 5, SPARCserver 5 | |
55 | * SPARCstation 20/xx, SPARCserver 20 | |
56 | * SPARCstation 4 | |
57 | * | |
58 | * See for example: http://www.sunhelp.org/faq/sunref1.html | |
59 | */ | |
60 | ||
420557e8 | 61 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 62 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 63 | #define INITRD_LOAD_ADDR 0x00800000 |
a7227727 | 64 | #define PROM_SIZE_MAX (1024 * 1024) |
40ce0a9a | 65 | #define PROM_VADDR 0xffd00000 |
f930d07e | 66 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 67 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 68 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b96919e0 MCA |
69 | #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) |
70 | #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) | |
b8174937 | 71 | |
ba3c64fb | 72 | #define MAX_CPUS 16 |
b3a23197 | 73 | #define MAX_PILS 16 |
9a62fb24 | 74 | #define MAX_VSIMMS 4 |
420557e8 | 75 | |
b4ed08e0 BS |
76 | #define ESCC_CLOCK 4915200 |
77 | ||
8137cde8 | 78 | struct sun4m_hwdef { |
a8170e5e AK |
79 | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
80 | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; | |
81 | hwaddr serial_base, fd_base; | |
82 | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; | |
83 | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; | |
84 | hwaddr bpp_base, dbri_base, sx_base; | |
9a62fb24 | 85 | struct { |
a8170e5e | 86 | hwaddr reg_base, vram_base; |
9a62fb24 | 87 | } vsimm[MAX_VSIMMS]; |
a8170e5e | 88 | hwaddr ecc_base; |
3ebf5aaf BS |
89 | uint64_t max_mem; |
90 | const char * const default_cpu_model; | |
61999750 BS |
91 | uint32_t ecc_version; |
92 | uint32_t iommu_version; | |
93 | uint16_t machine_id; | |
94 | uint8_t nvram_machine_id; | |
36cd9210 BS |
95 | }; |
96 | ||
6f7e9aec FB |
97 | int DMA_get_channel_mode (int nchan) |
98 | { | |
99 | return 0; | |
100 | } | |
101 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
102 | { | |
103 | return 0; | |
104 | } | |
105 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
106 | { | |
107 | return 0; | |
108 | } | |
109 | void DMA_hold_DREQ (int nchan) {} | |
110 | void DMA_release_DREQ (int nchan) {} | |
111 | void DMA_schedule(int nchan) {} | |
4556bd8b BS |
112 | |
113 | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) | |
114 | { | |
115 | } | |
116 | ||
6f7e9aec FB |
117 | void DMA_register_channel (int nchan, |
118 | DMA_transfer_handler transfer_handler, | |
119 | void *opaque) | |
120 | { | |
121 | } | |
122 | ||
513f789f | 123 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 124 | { |
513f789f | 125 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
126 | return 0; |
127 | } | |
128 | ||
43a34704 BS |
129 | static void nvram_init(M48t59State *nvram, uint8_t *macaddr, |
130 | const char *cmdline, const char *boot_devices, | |
131 | ram_addr_t RAM_size, uint32_t kernel_size, | |
f930d07e | 132 | int width, int height, int depth, |
905fdcb5 | 133 | int nvram_machine_id, const char *arch) |
e80cfcfc | 134 | { |
d2c63fc1 | 135 | unsigned int i; |
66508601 | 136 | uint32_t start, end; |
d2c63fc1 | 137 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
138 | struct OpenBIOS_nvpart_v1 *part_header; |
139 | ||
140 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 141 | |
513f789f | 142 | start = 0; |
b6f479d3 | 143 | |
66508601 BS |
144 | // OpenBIOS nvram variables |
145 | // Variable partition | |
d2c63fc1 BS |
146 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
147 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 148 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 149 | |
d2c63fc1 | 150 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 151 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
152 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
153 | ||
154 | // End marker | |
155 | image[end++] = '\0'; | |
66508601 | 156 | |
66508601 | 157 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 158 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
159 | |
160 | // free partition | |
161 | start = end; | |
d2c63fc1 BS |
162 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
163 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 164 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
165 | |
166 | end = 0x1fd0; | |
d2c63fc1 BS |
167 | OpenBIOS_finish_partition(part_header, end - start); |
168 | ||
905fdcb5 BS |
169 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
170 | nvram_machine_id); | |
d2c63fc1 BS |
171 | |
172 | for (i = 0; i < sizeof(image); i++) | |
173 | m48t59_write(nvram, i, image[i]); | |
e80cfcfc FB |
174 | } |
175 | ||
d453c2c3 | 176 | static DeviceState *slavio_intctl; |
e80cfcfc | 177 | |
84f2d0ea | 178 | void sun4m_pic_info(Monitor *mon, const QDict *qdict) |
e80cfcfc | 179 | { |
7d85892b | 180 | if (slavio_intctl) |
376253ec | 181 | slavio_pic_info(mon, slavio_intctl); |
e80cfcfc FB |
182 | } |
183 | ||
84f2d0ea | 184 | void sun4m_irq_info(Monitor *mon, const QDict *qdict) |
e80cfcfc | 185 | { |
7d85892b | 186 | if (slavio_intctl) |
376253ec | 187 | slavio_irq_info(mon, slavio_intctl); |
e80cfcfc FB |
188 | } |
189 | ||
98cec4a2 | 190 | void cpu_check_irqs(CPUSPARCState *env) |
327ac2e7 | 191 | { |
d8ed887b AF |
192 | CPUState *cs; |
193 | ||
327ac2e7 BS |
194 | if (env->pil_in && (env->interrupt_index == 0 || |
195 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
196 | unsigned int i; | |
197 | ||
198 | for (i = 15; i > 0; i--) { | |
199 | if (env->pil_in & (1 << i)) { | |
200 | int old_interrupt = env->interrupt_index; | |
201 | ||
202 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 | 203 | if (old_interrupt != env->interrupt_index) { |
c3affe56 | 204 | cs = CPU(sparc_env_get_cpu(env)); |
97bf4851 | 205 | trace_sun4m_cpu_interrupt(i); |
c3affe56 | 206 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
f32d7ec5 | 207 | } |
327ac2e7 BS |
208 | break; |
209 | } | |
210 | } | |
211 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
d8ed887b | 212 | cs = CPU(sparc_env_get_cpu(env)); |
97bf4851 | 213 | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); |
327ac2e7 | 214 | env->interrupt_index = 0; |
d8ed887b | 215 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
327ac2e7 BS |
216 | } |
217 | } | |
218 | ||
38c66cf2 | 219 | static void cpu_kick_irq(SPARCCPU *cpu) |
94ad5b00 | 220 | { |
38c66cf2 | 221 | CPUSPARCState *env = &cpu->env; |
259186a7 | 222 | CPUState *cs = CPU(cpu); |
38c66cf2 | 223 | |
259186a7 | 224 | cs->halted = 0; |
94ad5b00 | 225 | cpu_check_irqs(env); |
259186a7 | 226 | qemu_cpu_kick(cs); |
94ad5b00 PB |
227 | } |
228 | ||
b3a23197 BS |
229 | static void cpu_set_irq(void *opaque, int irq, int level) |
230 | { | |
e0bbf9b5 AF |
231 | SPARCCPU *cpu = opaque; |
232 | CPUSPARCState *env = &cpu->env; | |
b3a23197 BS |
233 | |
234 | if (level) { | |
97bf4851 | 235 | trace_sun4m_cpu_set_irq_raise(irq); |
327ac2e7 | 236 | env->pil_in |= 1 << irq; |
38c66cf2 | 237 | cpu_kick_irq(cpu); |
b3a23197 | 238 | } else { |
97bf4851 | 239 | trace_sun4m_cpu_set_irq_lower(irq); |
327ac2e7 BS |
240 | env->pil_in &= ~(1 << irq); |
241 | cpu_check_irqs(env); | |
b3a23197 BS |
242 | } |
243 | } | |
244 | ||
245 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
246 | { | |
247 | } | |
248 | ||
c68ea704 FB |
249 | static void main_cpu_reset(void *opaque) |
250 | { | |
5414dec6 | 251 | SPARCCPU *cpu = opaque; |
259186a7 | 252 | CPUState *cs = CPU(cpu); |
3d29fbef | 253 | |
259186a7 AF |
254 | cpu_reset(cs); |
255 | cs->halted = 0; | |
3d29fbef BS |
256 | } |
257 | ||
258 | static void secondary_cpu_reset(void *opaque) | |
259 | { | |
5414dec6 | 260 | SPARCCPU *cpu = opaque; |
259186a7 | 261 | CPUState *cs = CPU(cpu); |
3d29fbef | 262 | |
259186a7 AF |
263 | cpu_reset(cs); |
264 | cs->halted = 1; | |
c68ea704 FB |
265 | } |
266 | ||
6d0c293d BS |
267 | static void cpu_halt_signal(void *opaque, int irq, int level) |
268 | { | |
4917cf44 AF |
269 | if (level && current_cpu) { |
270 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); | |
c3affe56 | 271 | } |
6d0c293d BS |
272 | } |
273 | ||
409dbce5 AJ |
274 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
275 | { | |
276 | return addr - 0xf0000000ULL; | |
277 | } | |
278 | ||
3ebf5aaf | 279 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc | 280 | const char *initrd_filename, |
c227f099 | 281 | ram_addr_t RAM_size) |
3ebf5aaf BS |
282 | { |
283 | int linux_boot; | |
284 | unsigned int i; | |
285 | long initrd_size, kernel_size; | |
3c178e72 | 286 | uint8_t *ptr; |
3ebf5aaf BS |
287 | |
288 | linux_boot = (kernel_filename != NULL); | |
289 | ||
290 | kernel_size = 0; | |
291 | if (linux_boot) { | |
ca20cf32 BS |
292 | int bswap_needed; |
293 | ||
294 | #ifdef BSWAP_NEEDED | |
295 | bswap_needed = 1; | |
296 | #else | |
297 | bswap_needed = 0; | |
298 | #endif | |
409dbce5 AJ |
299 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
300 | NULL, NULL, NULL, 1, ELF_MACHINE, 0); | |
3ebf5aaf | 301 | if (kernel_size < 0) |
293f78bc | 302 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
303 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
304 | TARGET_PAGE_SIZE); | |
3ebf5aaf | 305 | if (kernel_size < 0) |
293f78bc BS |
306 | kernel_size = load_image_targphys(kernel_filename, |
307 | KERNEL_LOAD_ADDR, | |
308 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf BS |
309 | if (kernel_size < 0) { |
310 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
311 | kernel_filename); | |
312 | exit(1); | |
313 | } | |
314 | ||
315 | /* load initrd */ | |
316 | initrd_size = 0; | |
317 | if (initrd_filename) { | |
293f78bc BS |
318 | initrd_size = load_image_targphys(initrd_filename, |
319 | INITRD_LOAD_ADDR, | |
320 | RAM_size - INITRD_LOAD_ADDR); | |
3ebf5aaf BS |
321 | if (initrd_size < 0) { |
322 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
323 | initrd_filename); | |
324 | exit(1); | |
325 | } | |
326 | } | |
327 | if (initrd_size > 0) { | |
328 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
3c178e72 GH |
329 | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
330 | if (ldl_p(ptr) == 0x48647253) { // HdrS | |
331 | stl_p(ptr + 16, INITRD_LOAD_ADDR); | |
332 | stl_p(ptr + 20, initrd_size); | |
3ebf5aaf BS |
333 | break; |
334 | } | |
335 | } | |
336 | } | |
337 | } | |
338 | return kernel_size; | |
339 | } | |
340 | ||
a8170e5e | 341 | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
4b48bf05 BS |
342 | { |
343 | DeviceState *dev; | |
344 | SysBusDevice *s; | |
345 | ||
346 | dev = qdev_create(NULL, "iommu"); | |
347 | qdev_prop_set_uint32(dev, "version", version); | |
e23a1b33 | 348 | qdev_init_nofail(dev); |
1356b98d | 349 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
350 | sysbus_connect_irq(s, 0, irq); |
351 | sysbus_mmio_map(s, 0, addr); | |
352 | ||
353 | return s; | |
354 | } | |
355 | ||
a8170e5e | 356 | static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, |
86d1c388 | 357 | void *iommu, qemu_irq *dev_irq, int is_ledma) |
74ff8d90 BS |
358 | { |
359 | DeviceState *dev; | |
360 | SysBusDevice *s; | |
361 | ||
362 | dev = qdev_create(NULL, "sparc32_dma"); | |
363 | qdev_prop_set_ptr(dev, "iommu_opaque", iommu); | |
86d1c388 | 364 | qdev_prop_set_uint32(dev, "is_ledma", is_ledma); |
e23a1b33 | 365 | qdev_init_nofail(dev); |
1356b98d | 366 | s = SYS_BUS_DEVICE(dev); |
74ff8d90 BS |
367 | sysbus_connect_irq(s, 0, parent_irq); |
368 | *dev_irq = qdev_get_gpio_in(dev, 0); | |
369 | sysbus_mmio_map(s, 0, daddr); | |
370 | ||
371 | return s; | |
372 | } | |
373 | ||
a8170e5e | 374 | static void lance_init(NICInfo *nd, hwaddr leaddr, |
74ff8d90 | 375 | void *dma_opaque, qemu_irq irq) |
9d07d757 PB |
376 | { |
377 | DeviceState *dev; | |
378 | SysBusDevice *s; | |
74ff8d90 | 379 | qemu_irq reset; |
9d07d757 PB |
380 | |
381 | qemu_check_nic_model(&nd_table[0], "lance"); | |
382 | ||
383 | dev = qdev_create(NULL, "lance"); | |
76224833 | 384 | qdev_set_nic_properties(dev, nd); |
daa65491 | 385 | qdev_prop_set_ptr(dev, "dma", dma_opaque); |
e23a1b33 | 386 | qdev_init_nofail(dev); |
1356b98d | 387 | s = SYS_BUS_DEVICE(dev); |
9d07d757 PB |
388 | sysbus_mmio_map(s, 0, leaddr); |
389 | sysbus_connect_irq(s, 0, irq); | |
74ff8d90 BS |
390 | reset = qdev_get_gpio_in(dev, 0); |
391 | qdev_connect_gpio_out(dma_opaque, 0, reset); | |
9d07d757 PB |
392 | } |
393 | ||
a8170e5e AK |
394 | static DeviceState *slavio_intctl_init(hwaddr addr, |
395 | hwaddr addrg, | |
462eda24 | 396 | qemu_irq **parent_irq) |
4b48bf05 BS |
397 | { |
398 | DeviceState *dev; | |
399 | SysBusDevice *s; | |
400 | unsigned int i, j; | |
401 | ||
402 | dev = qdev_create(NULL, "slavio_intctl"); | |
e23a1b33 | 403 | qdev_init_nofail(dev); |
4b48bf05 | 404 | |
1356b98d | 405 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
406 | |
407 | for (i = 0; i < MAX_CPUS; i++) { | |
408 | for (j = 0; j < MAX_PILS; j++) { | |
409 | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); | |
410 | } | |
411 | } | |
412 | sysbus_mmio_map(s, 0, addrg); | |
413 | for (i = 0; i < MAX_CPUS; i++) { | |
414 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); | |
415 | } | |
416 | ||
417 | return dev; | |
418 | } | |
419 | ||
420 | #define SYS_TIMER_OFFSET 0x10000ULL | |
421 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | |
422 | ||
a8170e5e | 423 | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
4b48bf05 BS |
424 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
425 | { | |
426 | DeviceState *dev; | |
427 | SysBusDevice *s; | |
428 | unsigned int i; | |
429 | ||
430 | dev = qdev_create(NULL, "slavio_timer"); | |
431 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); | |
e23a1b33 | 432 | qdev_init_nofail(dev); |
1356b98d | 433 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
434 | sysbus_connect_irq(s, 0, master_irq); |
435 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); | |
436 | ||
437 | for (i = 0; i < MAX_CPUS; i++) { | |
a8170e5e | 438 | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); |
4b48bf05 BS |
439 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
440 | } | |
441 | } | |
442 | ||
bea42280 IM |
443 | static qemu_irq slavio_system_powerdown; |
444 | ||
445 | static void slavio_powerdown_req(Notifier *n, void *opaque) | |
446 | { | |
447 | qemu_irq_raise(slavio_system_powerdown); | |
448 | } | |
449 | ||
450 | static Notifier slavio_system_powerdown_notifier = { | |
451 | .notify = slavio_powerdown_req | |
452 | }; | |
453 | ||
4b48bf05 BS |
454 | #define MISC_LEDS 0x01600000 |
455 | #define MISC_CFG 0x01800000 | |
456 | #define MISC_DIAG 0x01a00000 | |
457 | #define MISC_MDM 0x01b00000 | |
458 | #define MISC_SYS 0x01f00000 | |
459 | ||
a8170e5e AK |
460 | static void slavio_misc_init(hwaddr base, |
461 | hwaddr aux1_base, | |
462 | hwaddr aux2_base, qemu_irq irq, | |
b2b6f6ec | 463 | qemu_irq fdc_tc) |
4b48bf05 BS |
464 | { |
465 | DeviceState *dev; | |
466 | SysBusDevice *s; | |
467 | ||
468 | dev = qdev_create(NULL, "slavio_misc"); | |
e23a1b33 | 469 | qdev_init_nofail(dev); |
1356b98d | 470 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
471 | if (base) { |
472 | /* 8 bit registers */ | |
473 | /* Slavio control */ | |
474 | sysbus_mmio_map(s, 0, base + MISC_CFG); | |
475 | /* Diagnostics */ | |
476 | sysbus_mmio_map(s, 1, base + MISC_DIAG); | |
477 | /* Modem control */ | |
478 | sysbus_mmio_map(s, 2, base + MISC_MDM); | |
479 | /* 16 bit registers */ | |
480 | /* ss600mp diag LEDs */ | |
481 | sysbus_mmio_map(s, 3, base + MISC_LEDS); | |
482 | /* 32 bit registers */ | |
483 | /* System control */ | |
484 | sysbus_mmio_map(s, 4, base + MISC_SYS); | |
485 | } | |
486 | if (aux1_base) { | |
487 | /* AUX 1 (Misc System Functions) */ | |
488 | sysbus_mmio_map(s, 5, aux1_base); | |
489 | } | |
490 | if (aux2_base) { | |
491 | /* AUX 2 (Software Powerdown Control) */ | |
492 | sysbus_mmio_map(s, 6, aux2_base); | |
493 | } | |
494 | sysbus_connect_irq(s, 0, irq); | |
495 | sysbus_connect_irq(s, 1, fdc_tc); | |
bea42280 IM |
496 | slavio_system_powerdown = qdev_get_gpio_in(dev, 0); |
497 | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); | |
4b48bf05 BS |
498 | } |
499 | ||
a8170e5e | 500 | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
4b48bf05 BS |
501 | { |
502 | DeviceState *dev; | |
503 | SysBusDevice *s; | |
504 | ||
505 | dev = qdev_create(NULL, "eccmemctl"); | |
506 | qdev_prop_set_uint32(dev, "version", version); | |
e23a1b33 | 507 | qdev_init_nofail(dev); |
1356b98d | 508 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
509 | sysbus_connect_irq(s, 0, irq); |
510 | sysbus_mmio_map(s, 0, base); | |
511 | if (version == 0) { // SS-600MP only | |
512 | sysbus_mmio_map(s, 1, base + 0x1000); | |
513 | } | |
514 | } | |
515 | ||
a8170e5e | 516 | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
4b48bf05 BS |
517 | { |
518 | DeviceState *dev; | |
519 | SysBusDevice *s; | |
520 | ||
521 | dev = qdev_create(NULL, "apc"); | |
e23a1b33 | 522 | qdev_init_nofail(dev); |
1356b98d | 523 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
524 | /* Power management (APC) XXX: not a Slavio device */ |
525 | sysbus_mmio_map(s, 0, power_base); | |
526 | sysbus_connect_irq(s, 0, cpu_halt); | |
527 | } | |
528 | ||
a8170e5e | 529 | static void tcx_init(hwaddr addr, int vram_size, int width, |
4b48bf05 BS |
530 | int height, int depth) |
531 | { | |
532 | DeviceState *dev; | |
533 | SysBusDevice *s; | |
534 | ||
535 | dev = qdev_create(NULL, "SUNW,tcx"); | |
4b48bf05 BS |
536 | qdev_prop_set_uint32(dev, "vram_size", vram_size); |
537 | qdev_prop_set_uint16(dev, "width", width); | |
538 | qdev_prop_set_uint16(dev, "height", height); | |
539 | qdev_prop_set_uint16(dev, "depth", depth); | |
e23a1b33 | 540 | qdev_init_nofail(dev); |
1356b98d | 541 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
542 | /* 8-bit plane */ |
543 | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); | |
544 | /* DAC */ | |
545 | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); | |
546 | /* TEC (dummy) */ | |
547 | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); | |
548 | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */ | |
549 | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); | |
550 | if (depth == 24) { | |
551 | /* 24-bit plane */ | |
552 | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); | |
553 | /* Control plane */ | |
554 | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); | |
555 | } else { | |
556 | /* THC 8 bit (dummy) */ | |
557 | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); | |
558 | } | |
559 | } | |
560 | ||
325f2747 BS |
561 | /* NCR89C100/MACIO Internal ID register */ |
562 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; | |
563 | ||
a8170e5e | 564 | static void idreg_init(hwaddr addr) |
325f2747 BS |
565 | { |
566 | DeviceState *dev; | |
567 | SysBusDevice *s; | |
568 | ||
569 | dev = qdev_create(NULL, "macio_idreg"); | |
e23a1b33 | 570 | qdev_init_nofail(dev); |
1356b98d | 571 | s = SYS_BUS_DEVICE(dev); |
325f2747 BS |
572 | |
573 | sysbus_mmio_map(s, 0, addr); | |
574 | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); | |
575 | } | |
576 | ||
3150fa50 AK |
577 | typedef struct IDRegState { |
578 | SysBusDevice busdev; | |
579 | MemoryRegion mem; | |
580 | } IDRegState; | |
581 | ||
81a322d4 | 582 | static int idreg_init1(SysBusDevice *dev) |
325f2747 | 583 | { |
3150fa50 | 584 | IDRegState *s = FROM_SYSBUS(IDRegState, dev); |
325f2747 | 585 | |
29776739 PB |
586 | memory_region_init_ram(&s->mem, OBJECT(s), |
587 | "sun4m.idreg", sizeof(idreg_data)); | |
c5705a77 | 588 | vmstate_register_ram_global(&s->mem); |
3150fa50 | 589 | memory_region_set_readonly(&s->mem, true); |
750ecd44 | 590 | sysbus_init_mmio(dev, &s->mem); |
81a322d4 | 591 | return 0; |
325f2747 BS |
592 | } |
593 | ||
999e12bb AL |
594 | static void idreg_class_init(ObjectClass *klass, void *data) |
595 | { | |
596 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
597 | ||
598 | k->init = idreg_init1; | |
599 | } | |
600 | ||
8c43a6f0 | 601 | static const TypeInfo idreg_info = { |
39bffca2 AL |
602 | .name = "macio_idreg", |
603 | .parent = TYPE_SYS_BUS_DEVICE, | |
604 | .instance_size = sizeof(IDRegState), | |
605 | .class_init = idreg_class_init, | |
325f2747 BS |
606 | }; |
607 | ||
3150fa50 AK |
608 | typedef struct AFXState { |
609 | SysBusDevice busdev; | |
610 | MemoryRegion mem; | |
611 | } AFXState; | |
612 | ||
c5de386a | 613 | /* SS-5 TCX AFX register */ |
a8170e5e | 614 | static void afx_init(hwaddr addr) |
c5de386a AT |
615 | { |
616 | DeviceState *dev; | |
617 | SysBusDevice *s; | |
618 | ||
619 | dev = qdev_create(NULL, "tcx_afx"); | |
620 | qdev_init_nofail(dev); | |
1356b98d | 621 | s = SYS_BUS_DEVICE(dev); |
c5de386a AT |
622 | |
623 | sysbus_mmio_map(s, 0, addr); | |
624 | } | |
625 | ||
626 | static int afx_init1(SysBusDevice *dev) | |
627 | { | |
3150fa50 | 628 | AFXState *s = FROM_SYSBUS(AFXState, dev); |
c5de386a | 629 | |
29776739 | 630 | memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4); |
c5705a77 | 631 | vmstate_register_ram_global(&s->mem); |
750ecd44 | 632 | sysbus_init_mmio(dev, &s->mem); |
c5de386a AT |
633 | return 0; |
634 | } | |
635 | ||
999e12bb AL |
636 | static void afx_class_init(ObjectClass *klass, void *data) |
637 | { | |
638 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
639 | ||
640 | k->init = afx_init1; | |
641 | } | |
642 | ||
8c43a6f0 | 643 | static const TypeInfo afx_info = { |
39bffca2 AL |
644 | .name = "tcx_afx", |
645 | .parent = TYPE_SYS_BUS_DEVICE, | |
646 | .instance_size = sizeof(AFXState), | |
647 | .class_init = afx_class_init, | |
c5de386a AT |
648 | }; |
649 | ||
3150fa50 AK |
650 | typedef struct PROMState { |
651 | SysBusDevice busdev; | |
652 | MemoryRegion prom; | |
653 | } PROMState; | |
654 | ||
f48f6569 | 655 | /* Boot PROM (OpenBIOS) */ |
409dbce5 AJ |
656 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
657 | { | |
a8170e5e | 658 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
659 | return addr + *base_addr - PROM_VADDR; |
660 | } | |
661 | ||
a8170e5e | 662 | static void prom_init(hwaddr addr, const char *bios_name) |
f48f6569 BS |
663 | { |
664 | DeviceState *dev; | |
665 | SysBusDevice *s; | |
666 | char *filename; | |
667 | int ret; | |
668 | ||
669 | dev = qdev_create(NULL, "openprom"); | |
e23a1b33 | 670 | qdev_init_nofail(dev); |
1356b98d | 671 | s = SYS_BUS_DEVICE(dev); |
f48f6569 BS |
672 | |
673 | sysbus_mmio_map(s, 0, addr); | |
674 | ||
675 | /* load boot prom */ | |
676 | if (bios_name == NULL) { | |
677 | bios_name = PROM_FILENAME; | |
678 | } | |
679 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
680 | if (filename) { | |
409dbce5 AJ |
681 | ret = load_elf(filename, translate_prom_address, &addr, NULL, |
682 | NULL, NULL, 1, ELF_MACHINE, 0); | |
f48f6569 BS |
683 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
684 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
685 | } | |
7267c094 | 686 | g_free(filename); |
f48f6569 BS |
687 | } else { |
688 | ret = -1; | |
689 | } | |
690 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
691 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
692 | exit(1); | |
693 | } | |
694 | } | |
695 | ||
81a322d4 | 696 | static int prom_init1(SysBusDevice *dev) |
f48f6569 | 697 | { |
3150fa50 | 698 | PROMState *s = FROM_SYSBUS(PROMState, dev); |
f48f6569 | 699 | |
29776739 | 700 | memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX); |
c5705a77 | 701 | vmstate_register_ram_global(&s->prom); |
3150fa50 | 702 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 703 | sysbus_init_mmio(dev, &s->prom); |
81a322d4 | 704 | return 0; |
f48f6569 BS |
705 | } |
706 | ||
999e12bb AL |
707 | static Property prom_properties[] = { |
708 | {/* end of property list */}, | |
709 | }; | |
710 | ||
711 | static void prom_class_init(ObjectClass *klass, void *data) | |
712 | { | |
39bffca2 | 713 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
714 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
715 | ||
716 | k->init = prom_init1; | |
39bffca2 | 717 | dc->props = prom_properties; |
999e12bb AL |
718 | } |
719 | ||
8c43a6f0 | 720 | static const TypeInfo prom_info = { |
39bffca2 AL |
721 | .name = "openprom", |
722 | .parent = TYPE_SYS_BUS_DEVICE, | |
723 | .instance_size = sizeof(PROMState), | |
724 | .class_init = prom_class_init, | |
f48f6569 BS |
725 | }; |
726 | ||
ee6847d1 GH |
727 | typedef struct RamDevice |
728 | { | |
729 | SysBusDevice busdev; | |
3150fa50 | 730 | MemoryRegion ram; |
04843626 | 731 | uint64_t size; |
ee6847d1 GH |
732 | } RamDevice; |
733 | ||
a350db85 | 734 | /* System RAM */ |
81a322d4 | 735 | static int ram_init1(SysBusDevice *dev) |
a350db85 | 736 | { |
ee6847d1 | 737 | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
a350db85 | 738 | |
29776739 | 739 | memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size); |
c5705a77 | 740 | vmstate_register_ram_global(&d->ram); |
750ecd44 | 741 | sysbus_init_mmio(dev, &d->ram); |
81a322d4 | 742 | return 0; |
a350db85 BS |
743 | } |
744 | ||
a8170e5e | 745 | static void ram_init(hwaddr addr, ram_addr_t RAM_size, |
a350db85 BS |
746 | uint64_t max_mem) |
747 | { | |
748 | DeviceState *dev; | |
749 | SysBusDevice *s; | |
ee6847d1 | 750 | RamDevice *d; |
a350db85 BS |
751 | |
752 | /* allocate RAM */ | |
753 | if ((uint64_t)RAM_size > max_mem) { | |
754 | fprintf(stderr, | |
755 | "qemu: Too much memory for this machine: %d, maximum %d\n", | |
756 | (unsigned int)(RAM_size / (1024 * 1024)), | |
757 | (unsigned int)(max_mem / (1024 * 1024))); | |
758 | exit(1); | |
759 | } | |
760 | dev = qdev_create(NULL, "memory"); | |
1356b98d | 761 | s = SYS_BUS_DEVICE(dev); |
a350db85 | 762 | |
ee6847d1 GH |
763 | d = FROM_SYSBUS(RamDevice, s); |
764 | d->size = RAM_size; | |
e23a1b33 | 765 | qdev_init_nofail(dev); |
ee6847d1 | 766 | |
a350db85 BS |
767 | sysbus_mmio_map(s, 0, addr); |
768 | } | |
769 | ||
999e12bb AL |
770 | static Property ram_properties[] = { |
771 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
772 | DEFINE_PROP_END_OF_LIST(), | |
773 | }; | |
774 | ||
775 | static void ram_class_init(ObjectClass *klass, void *data) | |
776 | { | |
39bffca2 | 777 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
778 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
779 | ||
780 | k->init = ram_init1; | |
39bffca2 | 781 | dc->props = ram_properties; |
999e12bb AL |
782 | } |
783 | ||
8c43a6f0 | 784 | static const TypeInfo ram_info = { |
39bffca2 AL |
785 | .name = "memory", |
786 | .parent = TYPE_SYS_BUS_DEVICE, | |
787 | .instance_size = sizeof(RamDevice), | |
788 | .class_init = ram_class_init, | |
a350db85 BS |
789 | }; |
790 | ||
89835363 BS |
791 | static void cpu_devinit(const char *cpu_model, unsigned int id, |
792 | uint64_t prom_addr, qemu_irq **cpu_irqs) | |
666713c0 | 793 | { |
259186a7 | 794 | CPUState *cs; |
8968f588 | 795 | SPARCCPU *cpu; |
98cec4a2 | 796 | CPUSPARCState *env; |
666713c0 | 797 | |
8968f588 AF |
798 | cpu = cpu_sparc_init(cpu_model); |
799 | if (cpu == NULL) { | |
666713c0 BS |
800 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); |
801 | exit(1); | |
802 | } | |
8968f588 | 803 | env = &cpu->env; |
666713c0 BS |
804 | |
805 | cpu_sparc_set_id(env, id); | |
806 | if (id == 0) { | |
5414dec6 | 807 | qemu_register_reset(main_cpu_reset, cpu); |
666713c0 | 808 | } else { |
5414dec6 | 809 | qemu_register_reset(secondary_cpu_reset, cpu); |
259186a7 AF |
810 | cs = CPU(cpu); |
811 | cs->halted = 1; | |
666713c0 | 812 | } |
e0bbf9b5 | 813 | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
666713c0 | 814 | env->prom_addr = prom_addr; |
666713c0 BS |
815 | } |
816 | ||
acfbe712 BS |
817 | static void dummy_fdc_tc(void *opaque, int irq, int level) |
818 | { | |
819 | } | |
820 | ||
c227f099 | 821 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
3ebf5aaf | 822 | const char *boot_device, |
3023f332 | 823 | const char *kernel_filename, |
3ebf5aaf BS |
824 | const char *kernel_cmdline, |
825 | const char *initrd_filename, const char *cpu_model) | |
420557e8 | 826 | { |
713c45fa | 827 | unsigned int i; |
cfb9de9c | 828 | void *iommu, *espdma, *ledma, *nvram; |
a1961a4b | 829 | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], |
6f6260c7 | 830 | espdma_irq, ledma_irq; |
73d74342 | 831 | qemu_irq esp_reset, dma_enable; |
2582cfa0 | 832 | qemu_irq fdc_tc; |
6d0c293d | 833 | qemu_irq *cpu_halt; |
5c6602c5 | 834 | unsigned long kernel_size; |
fd8014e1 | 835 | DriveInfo *fd[MAX_FD]; |
a88b362c | 836 | FWCfgState *fw_cfg; |
9a62fb24 | 837 | unsigned int num_vsimms; |
420557e8 | 838 | |
ba3c64fb | 839 | /* init CPUs */ |
3ebf5aaf BS |
840 | if (!cpu_model) |
841 | cpu_model = hwdef->default_cpu_model; | |
b3a23197 | 842 | |
ba3c64fb | 843 | for(i = 0; i < smp_cpus; i++) { |
89835363 | 844 | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
ba3c64fb | 845 | } |
b3a23197 BS |
846 | |
847 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
848 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
849 | ||
3ebf5aaf | 850 | |
3ebf5aaf | 851 | /* set up devices */ |
a350db85 | 852 | ram_init(0, RAM_size, hwdef->max_mem); |
676d9b9b AT |
853 | /* models without ECC don't trap when missing ram is accessed */ |
854 | if (!hwdef->ecc_base) { | |
855 | empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); | |
856 | } | |
a350db85 | 857 | |
f48f6569 BS |
858 | prom_init(hwdef->slavio_base, bios_name); |
859 | ||
d453c2c3 BS |
860 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
861 | hwdef->intctl_base + 0x10000ULL, | |
462eda24 | 862 | cpu_irqs); |
a1961a4b BS |
863 | |
864 | for (i = 0; i < 32; i++) { | |
d453c2c3 | 865 | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
a1961a4b BS |
866 | } |
867 | for (i = 0; i < MAX_CPUS; i++) { | |
d453c2c3 | 868 | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); |
a1961a4b | 869 | } |
b3a23197 | 870 | |
fe096129 | 871 | if (hwdef->idreg_base) { |
325f2747 | 872 | idreg_init(hwdef->idreg_base); |
4c2485de BS |
873 | } |
874 | ||
c5de386a AT |
875 | if (hwdef->afx_base) { |
876 | afx_init(hwdef->afx_base); | |
877 | } | |
878 | ||
ff403da6 | 879 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
c533e0b3 | 880 | slavio_irq[30]); |
ff403da6 | 881 | |
3386376c AT |
882 | if (hwdef->iommu_pad_base) { |
883 | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. | |
884 | Software shouldn't use aliased addresses, neither should it crash | |
885 | when does. Using empty_slot instead of aliasing can help with | |
886 | debugging such accesses */ | |
887 | empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); | |
888 | } | |
889 | ||
c533e0b3 | 890 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], |
86d1c388 | 891 | iommu, &espdma_irq, 0); |
2d069bab | 892 | |
5aca8c3b | 893 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, |
86d1c388 | 894 | slavio_irq[16], iommu, &ledma_irq, 1); |
ba3c64fb | 895 | |
eee0b836 BS |
896 | if (graphic_depth != 8 && graphic_depth != 24) { |
897 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
898 | exit (1); | |
899 | } | |
9a62fb24 BB |
900 | num_vsimms = 0; |
901 | if (num_vsimms == 0) { | |
902 | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height, | |
903 | graphic_depth); | |
904 | } | |
905 | ||
906 | for (i = num_vsimms; i < MAX_VSIMMS; i++) { | |
907 | /* vsimm registers probed by OBP */ | |
908 | if (hwdef->vsimm[i].reg_base) { | |
909 | empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); | |
910 | } | |
911 | } | |
912 | ||
913 | if (hwdef->sx_base) { | |
914 | empty_slot_init(hwdef->sx_base, 0x2000); | |
915 | } | |
dbe06e18 | 916 | |
74ff8d90 | 917 | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); |
dbe06e18 | 918 | |
d95d8f1c | 919 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
81732d19 | 920 | |
c533e0b3 | 921 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); |
81732d19 | 922 | |
c533e0b3 | 923 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], |
993fbfdb | 924 | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1); |
5cbdb3a3 SW |
925 | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device |
926 | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ | |
c533e0b3 | 927 | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
aeeb69c7 | 928 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
741402f9 | 929 | |
6d0c293d | 930 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
2582cfa0 BS |
931 | if (hwdef->apc_base) { |
932 | apc_init(hwdef->apc_base, cpu_halt[0]); | |
933 | } | |
2be17ebd | 934 | |
fe096129 | 935 | if (hwdef->fd_base) { |
e4bcb14c | 936 | /* there is zero or one floppy drive */ |
309e60bd | 937 | memset(fd, 0, sizeof(fd)); |
fd8014e1 | 938 | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
c533e0b3 | 939 | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, |
2582cfa0 | 940 | &fdc_tc); |
acfbe712 BS |
941 | } else { |
942 | fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); | |
e4bcb14c TS |
943 | } |
944 | ||
acfbe712 BS |
945 | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
946 | slavio_irq[30], fdc_tc); | |
947 | ||
e4bcb14c TS |
948 | if (drive_get_max_bus(IF_SCSI) > 0) { |
949 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
950 | exit(1); | |
951 | } | |
952 | ||
cfb9de9c PB |
953 | esp_init(hwdef->esp_base, 2, |
954 | espdma_memory_read, espdma_memory_write, | |
73d74342 | 955 | espdma, espdma_irq, &esp_reset, &dma_enable); |
74ff8d90 | 956 | |
73d74342 BS |
957 | qdev_connect_gpio_out(espdma, 0, esp_reset); |
958 | qdev_connect_gpio_out(espdma, 1, dma_enable); | |
f1587550 | 959 | |
fa28ec52 BS |
960 | if (hwdef->cs_base) { |
961 | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, | |
c533e0b3 | 962 | slavio_irq[5]); |
fa28ec52 | 963 | } |
b3ceef24 | 964 | |
9a62fb24 BB |
965 | if (hwdef->dbri_base) { |
966 | /* ISDN chip with attached CS4215 audio codec */ | |
967 | /* prom space */ | |
968 | empty_slot_init(hwdef->dbri_base+0x1000, 0x30); | |
969 | /* reg space */ | |
970 | empty_slot_init(hwdef->dbri_base+0x10000, 0x100); | |
971 | } | |
972 | ||
973 | if (hwdef->bpp_base) { | |
974 | /* parallel port */ | |
975 | empty_slot_init(hwdef->bpp_base, 0x20); | |
976 | } | |
977 | ||
293f78bc BS |
978 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
979 | RAM_size); | |
36cd9210 | 980 | |
36cd9210 | 981 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
b3ceef24 | 982 | boot_device, RAM_size, kernel_size, graphic_width, |
905fdcb5 BS |
983 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
984 | "Sun4m"); | |
7eb0c8e8 | 985 | |
fe096129 | 986 | if (hwdef->ecc_base) |
c533e0b3 | 987 | ecc_init(hwdef->ecc_base, slavio_irq[28], |
e42c20b4 | 988 | hwdef->ecc_version); |
3cce6243 BS |
989 | |
990 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); | |
70db9222 | 991 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
3cce6243 | 992 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); |
905fdcb5 BS |
993 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
994 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
fbfcf955 | 995 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
b96919e0 MCA |
996 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); |
997 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); | |
513f789f BS |
998 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
999 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
1000 | if (kernel_cmdline) { | |
1001 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
3c178e72 | 1002 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
0e0d2d62 | 1003 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
748a4ee3 BS |
1004 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
1005 | strlen(kernel_cmdline) + 1); | |
513f789f BS |
1006 | } else { |
1007 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
748a4ee3 | 1008 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f BS |
1009 | } |
1010 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1011 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
1012 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]); | |
1013 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); | |
36cd9210 BS |
1014 | } |
1015 | ||
905fdcb5 | 1016 | enum { |
905fdcb5 BS |
1017 | ss5_id = 32, |
1018 | vger_id, | |
1019 | lx_id, | |
1020 | ss4_id, | |
1021 | scls_id, | |
1022 | sbook_id, | |
1023 | ss10_id = 64, | |
1024 | ss20_id, | |
1025 | ss600mp_id, | |
905fdcb5 BS |
1026 | }; |
1027 | ||
8137cde8 | 1028 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
36cd9210 BS |
1029 | /* SS-5 */ |
1030 | { | |
1031 | .iommu_base = 0x10000000, | |
3386376c AT |
1032 | .iommu_pad_base = 0x10004000, |
1033 | .iommu_pad_len = 0x0fffb000, | |
36cd9210 BS |
1034 | .tcx_base = 0x50000000, |
1035 | .cs_base = 0x6c000000, | |
384ccb5d | 1036 | .slavio_base = 0x70000000, |
36cd9210 BS |
1037 | .ms_kb_base = 0x71000000, |
1038 | .serial_base = 0x71100000, | |
1039 | .nvram_base = 0x71200000, | |
1040 | .fd_base = 0x71400000, | |
1041 | .counter_base = 0x71d00000, | |
1042 | .intctl_base = 0x71e00000, | |
4c2485de | 1043 | .idreg_base = 0x78000000, |
36cd9210 BS |
1044 | .dma_base = 0x78400000, |
1045 | .esp_base = 0x78800000, | |
1046 | .le_base = 0x78c00000, | |
127fc407 | 1047 | .apc_base = 0x6a000000, |
c5de386a | 1048 | .afx_base = 0x6e000000, |
0019ad53 BS |
1049 | .aux1_base = 0x71900000, |
1050 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1051 | .nvram_machine_id = 0x80, |
1052 | .machine_id = ss5_id, | |
cf3102ac | 1053 | .iommu_version = 0x05000000, |
3ebf5aaf BS |
1054 | .max_mem = 0x10000000, |
1055 | .default_cpu_model = "Fujitsu MB86904", | |
e0353fe2 BS |
1056 | }, |
1057 | /* SS-10 */ | |
e0353fe2 | 1058 | { |
5dcb6b91 BS |
1059 | .iommu_base = 0xfe0000000ULL, |
1060 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
1061 | .slavio_base = 0xff0000000ULL, |
1062 | .ms_kb_base = 0xff1000000ULL, | |
1063 | .serial_base = 0xff1100000ULL, | |
1064 | .nvram_base = 0xff1200000ULL, | |
1065 | .fd_base = 0xff1700000ULL, | |
1066 | .counter_base = 0xff1300000ULL, | |
1067 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1068 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
1069 | .dma_base = 0xef0400000ULL, |
1070 | .esp_base = 0xef0800000ULL, | |
1071 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 1072 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1073 | .aux1_base = 0xff1800000ULL, |
1074 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
1075 | .ecc_base = 0xf00000000ULL, |
1076 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
905fdcb5 BS |
1077 | .nvram_machine_id = 0x72, |
1078 | .machine_id = ss10_id, | |
7fbfb139 | 1079 | .iommu_version = 0x03000000, |
6ef05b95 | 1080 | .max_mem = 0xf00000000ULL, |
3ebf5aaf | 1081 | .default_cpu_model = "TI SuperSparc II", |
36cd9210 | 1082 | }, |
6a3b9cc9 BS |
1083 | /* SS-600MP */ |
1084 | { | |
1085 | .iommu_base = 0xfe0000000ULL, | |
1086 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
1087 | .slavio_base = 0xff0000000ULL, |
1088 | .ms_kb_base = 0xff1000000ULL, | |
1089 | .serial_base = 0xff1100000ULL, | |
1090 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
1091 | .counter_base = 0xff1300000ULL, |
1092 | .intctl_base = 0xff1400000ULL, | |
1093 | .dma_base = 0xef0081000ULL, | |
1094 | .esp_base = 0xef0080000ULL, | |
1095 | .le_base = 0xef0060000ULL, | |
0019ad53 | 1096 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1097 | .aux1_base = 0xff1800000ULL, |
1098 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
1099 | .ecc_base = 0xf00000000ULL, |
1100 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
905fdcb5 BS |
1101 | .nvram_machine_id = 0x71, |
1102 | .machine_id = ss600mp_id, | |
7fbfb139 | 1103 | .iommu_version = 0x01000000, |
6ef05b95 | 1104 | .max_mem = 0xf00000000ULL, |
3ebf5aaf | 1105 | .default_cpu_model = "TI SuperSparc II", |
6a3b9cc9 | 1106 | }, |
ae40972f BS |
1107 | /* SS-20 */ |
1108 | { | |
1109 | .iommu_base = 0xfe0000000ULL, | |
1110 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
1111 | .slavio_base = 0xff0000000ULL, |
1112 | .ms_kb_base = 0xff1000000ULL, | |
1113 | .serial_base = 0xff1100000ULL, | |
1114 | .nvram_base = 0xff1200000ULL, | |
1115 | .fd_base = 0xff1700000ULL, | |
1116 | .counter_base = 0xff1300000ULL, | |
1117 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1118 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
1119 | .dma_base = 0xef0400000ULL, |
1120 | .esp_base = 0xef0800000ULL, | |
1121 | .le_base = 0xef0c00000ULL, | |
9a62fb24 | 1122 | .bpp_base = 0xef4800000ULL, |
0019ad53 | 1123 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
1124 | .aux1_base = 0xff1800000ULL, |
1125 | .aux2_base = 0xff1a01000ULL, | |
9a62fb24 BB |
1126 | .dbri_base = 0xee0000000ULL, |
1127 | .sx_base = 0xf80000000ULL, | |
1128 | .vsimm = { | |
1129 | { | |
1130 | .reg_base = 0x9c000000ULL, | |
1131 | .vram_base = 0xfc000000ULL | |
1132 | }, { | |
1133 | .reg_base = 0x90000000ULL, | |
1134 | .vram_base = 0xf0000000ULL | |
1135 | }, { | |
1136 | .reg_base = 0x94000000ULL | |
1137 | }, { | |
1138 | .reg_base = 0x98000000ULL | |
1139 | } | |
1140 | }, | |
ae40972f BS |
1141 | .ecc_base = 0xf00000000ULL, |
1142 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
905fdcb5 BS |
1143 | .nvram_machine_id = 0x72, |
1144 | .machine_id = ss20_id, | |
ae40972f | 1145 | .iommu_version = 0x13000000, |
6ef05b95 | 1146 | .max_mem = 0xf00000000ULL, |
ae40972f BS |
1147 | .default_cpu_model = "TI SuperSparc II", |
1148 | }, | |
a526a31c BS |
1149 | /* Voyager */ |
1150 | { | |
1151 | .iommu_base = 0x10000000, | |
1152 | .tcx_base = 0x50000000, | |
a526a31c BS |
1153 | .slavio_base = 0x70000000, |
1154 | .ms_kb_base = 0x71000000, | |
1155 | .serial_base = 0x71100000, | |
1156 | .nvram_base = 0x71200000, | |
1157 | .fd_base = 0x71400000, | |
1158 | .counter_base = 0x71d00000, | |
1159 | .intctl_base = 0x71e00000, | |
1160 | .idreg_base = 0x78000000, | |
1161 | .dma_base = 0x78400000, | |
1162 | .esp_base = 0x78800000, | |
1163 | .le_base = 0x78c00000, | |
1164 | .apc_base = 0x71300000, // pmc | |
1165 | .aux1_base = 0x71900000, | |
1166 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1167 | .nvram_machine_id = 0x80, |
1168 | .machine_id = vger_id, | |
a526a31c | 1169 | .iommu_version = 0x05000000, |
a526a31c BS |
1170 | .max_mem = 0x10000000, |
1171 | .default_cpu_model = "Fujitsu MB86904", | |
1172 | }, | |
1173 | /* LX */ | |
1174 | { | |
1175 | .iommu_base = 0x10000000, | |
3386376c AT |
1176 | .iommu_pad_base = 0x10004000, |
1177 | .iommu_pad_len = 0x0fffb000, | |
a526a31c | 1178 | .tcx_base = 0x50000000, |
a526a31c BS |
1179 | .slavio_base = 0x70000000, |
1180 | .ms_kb_base = 0x71000000, | |
1181 | .serial_base = 0x71100000, | |
1182 | .nvram_base = 0x71200000, | |
1183 | .fd_base = 0x71400000, | |
1184 | .counter_base = 0x71d00000, | |
1185 | .intctl_base = 0x71e00000, | |
1186 | .idreg_base = 0x78000000, | |
1187 | .dma_base = 0x78400000, | |
1188 | .esp_base = 0x78800000, | |
1189 | .le_base = 0x78c00000, | |
a526a31c BS |
1190 | .aux1_base = 0x71900000, |
1191 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1192 | .nvram_machine_id = 0x80, |
1193 | .machine_id = lx_id, | |
a526a31c | 1194 | .iommu_version = 0x04000000, |
a526a31c BS |
1195 | .max_mem = 0x10000000, |
1196 | .default_cpu_model = "TI MicroSparc I", | |
1197 | }, | |
1198 | /* SS-4 */ | |
1199 | { | |
1200 | .iommu_base = 0x10000000, | |
1201 | .tcx_base = 0x50000000, | |
1202 | .cs_base = 0x6c000000, | |
1203 | .slavio_base = 0x70000000, | |
1204 | .ms_kb_base = 0x71000000, | |
1205 | .serial_base = 0x71100000, | |
1206 | .nvram_base = 0x71200000, | |
1207 | .fd_base = 0x71400000, | |
1208 | .counter_base = 0x71d00000, | |
1209 | .intctl_base = 0x71e00000, | |
1210 | .idreg_base = 0x78000000, | |
1211 | .dma_base = 0x78400000, | |
1212 | .esp_base = 0x78800000, | |
1213 | .le_base = 0x78c00000, | |
1214 | .apc_base = 0x6a000000, | |
1215 | .aux1_base = 0x71900000, | |
1216 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1217 | .nvram_machine_id = 0x80, |
1218 | .machine_id = ss4_id, | |
a526a31c | 1219 | .iommu_version = 0x05000000, |
a526a31c BS |
1220 | .max_mem = 0x10000000, |
1221 | .default_cpu_model = "Fujitsu MB86904", | |
1222 | }, | |
1223 | /* SPARCClassic */ | |
1224 | { | |
1225 | .iommu_base = 0x10000000, | |
1226 | .tcx_base = 0x50000000, | |
a526a31c BS |
1227 | .slavio_base = 0x70000000, |
1228 | .ms_kb_base = 0x71000000, | |
1229 | .serial_base = 0x71100000, | |
1230 | .nvram_base = 0x71200000, | |
1231 | .fd_base = 0x71400000, | |
1232 | .counter_base = 0x71d00000, | |
1233 | .intctl_base = 0x71e00000, | |
1234 | .idreg_base = 0x78000000, | |
1235 | .dma_base = 0x78400000, | |
1236 | .esp_base = 0x78800000, | |
1237 | .le_base = 0x78c00000, | |
1238 | .apc_base = 0x6a000000, | |
1239 | .aux1_base = 0x71900000, | |
1240 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1241 | .nvram_machine_id = 0x80, |
1242 | .machine_id = scls_id, | |
a526a31c | 1243 | .iommu_version = 0x05000000, |
a526a31c BS |
1244 | .max_mem = 0x10000000, |
1245 | .default_cpu_model = "TI MicroSparc I", | |
1246 | }, | |
1247 | /* SPARCbook */ | |
1248 | { | |
1249 | .iommu_base = 0x10000000, | |
1250 | .tcx_base = 0x50000000, // XXX | |
a526a31c BS |
1251 | .slavio_base = 0x70000000, |
1252 | .ms_kb_base = 0x71000000, | |
1253 | .serial_base = 0x71100000, | |
1254 | .nvram_base = 0x71200000, | |
1255 | .fd_base = 0x71400000, | |
1256 | .counter_base = 0x71d00000, | |
1257 | .intctl_base = 0x71e00000, | |
1258 | .idreg_base = 0x78000000, | |
1259 | .dma_base = 0x78400000, | |
1260 | .esp_base = 0x78800000, | |
1261 | .le_base = 0x78c00000, | |
1262 | .apc_base = 0x6a000000, | |
1263 | .aux1_base = 0x71900000, | |
1264 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1265 | .nvram_machine_id = 0x80, |
1266 | .machine_id = sbook_id, | |
a526a31c | 1267 | .iommu_version = 0x05000000, |
a526a31c BS |
1268 | .max_mem = 0x10000000, |
1269 | .default_cpu_model = "TI MicroSparc I", | |
1270 | }, | |
36cd9210 BS |
1271 | }; |
1272 | ||
36cd9210 | 1273 | /* SPARCstation 5 hardware initialisation */ |
5f072e1f | 1274 | static void ss5_init(QEMUMachineInitArgs *args) |
36cd9210 | 1275 | { |
5f072e1f EH |
1276 | ram_addr_t RAM_size = args->ram_size; |
1277 | const char *cpu_model = args->cpu_model; | |
1278 | const char *kernel_filename = args->kernel_filename; | |
1279 | const char *kernel_cmdline = args->kernel_cmdline; | |
1280 | const char *initrd_filename = args->initrd_filename; | |
1281 | const char *boot_device = args->boot_device; | |
3023f332 | 1282 | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 1283 | kernel_cmdline, initrd_filename, cpu_model); |
420557e8 | 1284 | } |
c0e564d5 | 1285 | |
e0353fe2 | 1286 | /* SPARCstation 10 hardware initialisation */ |
5f072e1f | 1287 | static void ss10_init(QEMUMachineInitArgs *args) |
e0353fe2 | 1288 | { |
5f072e1f EH |
1289 | ram_addr_t RAM_size = args->ram_size; |
1290 | const char *cpu_model = args->cpu_model; | |
1291 | const char *kernel_filename = args->kernel_filename; | |
1292 | const char *kernel_cmdline = args->kernel_cmdline; | |
1293 | const char *initrd_filename = args->initrd_filename; | |
1294 | const char *boot_device = args->boot_device; | |
3023f332 | 1295 | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 1296 | kernel_cmdline, initrd_filename, cpu_model); |
e0353fe2 BS |
1297 | } |
1298 | ||
6a3b9cc9 | 1299 | /* SPARCserver 600MP hardware initialisation */ |
5f072e1f | 1300 | static void ss600mp_init(QEMUMachineInitArgs *args) |
6a3b9cc9 | 1301 | { |
5f072e1f EH |
1302 | ram_addr_t RAM_size = args->ram_size; |
1303 | const char *cpu_model = args->cpu_model; | |
1304 | const char *kernel_filename = args->kernel_filename; | |
1305 | const char *kernel_cmdline = args->kernel_cmdline; | |
1306 | const char *initrd_filename = args->initrd_filename; | |
1307 | const char *boot_device = args->boot_device; | |
3023f332 | 1308 | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename, |
3ebf5aaf | 1309 | kernel_cmdline, initrd_filename, cpu_model); |
6a3b9cc9 BS |
1310 | } |
1311 | ||
ae40972f | 1312 | /* SPARCstation 20 hardware initialisation */ |
5f072e1f | 1313 | static void ss20_init(QEMUMachineInitArgs *args) |
ae40972f | 1314 | { |
5f072e1f EH |
1315 | ram_addr_t RAM_size = args->ram_size; |
1316 | const char *cpu_model = args->cpu_model; | |
1317 | const char *kernel_filename = args->kernel_filename; | |
1318 | const char *kernel_cmdline = args->kernel_cmdline; | |
1319 | const char *initrd_filename = args->initrd_filename; | |
1320 | const char *boot_device = args->boot_device; | |
3023f332 | 1321 | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename, |
ee76f82e BS |
1322 | kernel_cmdline, initrd_filename, cpu_model); |
1323 | } | |
1324 | ||
a526a31c | 1325 | /* SPARCstation Voyager hardware initialisation */ |
5f072e1f | 1326 | static void vger_init(QEMUMachineInitArgs *args) |
a526a31c | 1327 | { |
5f072e1f EH |
1328 | ram_addr_t RAM_size = args->ram_size; |
1329 | const char *cpu_model = args->cpu_model; | |
1330 | const char *kernel_filename = args->kernel_filename; | |
1331 | const char *kernel_cmdline = args->kernel_cmdline; | |
1332 | const char *initrd_filename = args->initrd_filename; | |
1333 | const char *boot_device = args->boot_device; | |
3023f332 | 1334 | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1335 | kernel_cmdline, initrd_filename, cpu_model); |
1336 | } | |
1337 | ||
1338 | /* SPARCstation LX hardware initialisation */ | |
5f072e1f | 1339 | static void ss_lx_init(QEMUMachineInitArgs *args) |
a526a31c | 1340 | { |
5f072e1f EH |
1341 | ram_addr_t RAM_size = args->ram_size; |
1342 | const char *cpu_model = args->cpu_model; | |
1343 | const char *kernel_filename = args->kernel_filename; | |
1344 | const char *kernel_cmdline = args->kernel_cmdline; | |
1345 | const char *initrd_filename = args->initrd_filename; | |
1346 | const char *boot_device = args->boot_device; | |
3023f332 | 1347 | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1348 | kernel_cmdline, initrd_filename, cpu_model); |
1349 | } | |
1350 | ||
1351 | /* SPARCstation 4 hardware initialisation */ | |
5f072e1f | 1352 | static void ss4_init(QEMUMachineInitArgs *args) |
a526a31c | 1353 | { |
5f072e1f EH |
1354 | ram_addr_t RAM_size = args->ram_size; |
1355 | const char *cpu_model = args->cpu_model; | |
1356 | const char *kernel_filename = args->kernel_filename; | |
1357 | const char *kernel_cmdline = args->kernel_cmdline; | |
1358 | const char *initrd_filename = args->initrd_filename; | |
1359 | const char *boot_device = args->boot_device; | |
3023f332 | 1360 | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1361 | kernel_cmdline, initrd_filename, cpu_model); |
1362 | } | |
1363 | ||
1364 | /* SPARCClassic hardware initialisation */ | |
5f072e1f | 1365 | static void scls_init(QEMUMachineInitArgs *args) |
a526a31c | 1366 | { |
5f072e1f EH |
1367 | ram_addr_t RAM_size = args->ram_size; |
1368 | const char *cpu_model = args->cpu_model; | |
1369 | const char *kernel_filename = args->kernel_filename; | |
1370 | const char *kernel_cmdline = args->kernel_cmdline; | |
1371 | const char *initrd_filename = args->initrd_filename; | |
1372 | const char *boot_device = args->boot_device; | |
3023f332 | 1373 | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1374 | kernel_cmdline, initrd_filename, cpu_model); |
1375 | } | |
1376 | ||
1377 | /* SPARCbook hardware initialisation */ | |
5f072e1f | 1378 | static void sbook_init(QEMUMachineInitArgs *args) |
a526a31c | 1379 | { |
5f072e1f EH |
1380 | ram_addr_t RAM_size = args->ram_size; |
1381 | const char *cpu_model = args->cpu_model; | |
1382 | const char *kernel_filename = args->kernel_filename; | |
1383 | const char *kernel_cmdline = args->kernel_cmdline; | |
1384 | const char *initrd_filename = args->initrd_filename; | |
1385 | const char *boot_device = args->boot_device; | |
3023f332 | 1386 | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename, |
a526a31c BS |
1387 | kernel_cmdline, initrd_filename, cpu_model); |
1388 | } | |
1389 | ||
f80f9ec9 | 1390 | static QEMUMachine ss5_machine = { |
66de733b BS |
1391 | .name = "SS-5", |
1392 | .desc = "Sun4m platform, SPARCstation 5", | |
1393 | .init = ss5_init, | |
2d0d2837 | 1394 | .block_default_type = IF_SCSI, |
0c257437 | 1395 | .is_default = 1, |
e4ada29e | 1396 | DEFAULT_MACHINE_OPTIONS, |
c0e564d5 | 1397 | }; |
e0353fe2 | 1398 | |
f80f9ec9 | 1399 | static QEMUMachine ss10_machine = { |
66de733b BS |
1400 | .name = "SS-10", |
1401 | .desc = "Sun4m platform, SPARCstation 10", | |
1402 | .init = ss10_init, | |
2d0d2837 | 1403 | .block_default_type = IF_SCSI, |
1bcee014 | 1404 | .max_cpus = 4, |
e4ada29e | 1405 | DEFAULT_MACHINE_OPTIONS, |
e0353fe2 | 1406 | }; |
6a3b9cc9 | 1407 | |
f80f9ec9 | 1408 | static QEMUMachine ss600mp_machine = { |
66de733b BS |
1409 | .name = "SS-600MP", |
1410 | .desc = "Sun4m platform, SPARCserver 600MP", | |
1411 | .init = ss600mp_init, | |
2d0d2837 | 1412 | .block_default_type = IF_SCSI, |
1bcee014 | 1413 | .max_cpus = 4, |
e4ada29e | 1414 | DEFAULT_MACHINE_OPTIONS, |
6a3b9cc9 | 1415 | }; |
ae40972f | 1416 | |
f80f9ec9 | 1417 | static QEMUMachine ss20_machine = { |
66de733b BS |
1418 | .name = "SS-20", |
1419 | .desc = "Sun4m platform, SPARCstation 20", | |
1420 | .init = ss20_init, | |
2d0d2837 | 1421 | .block_default_type = IF_SCSI, |
1bcee014 | 1422 | .max_cpus = 4, |
e4ada29e | 1423 | DEFAULT_MACHINE_OPTIONS, |
ae40972f BS |
1424 | }; |
1425 | ||
f80f9ec9 | 1426 | static QEMUMachine voyager_machine = { |
66de733b BS |
1427 | .name = "Voyager", |
1428 | .desc = "Sun4m platform, SPARCstation Voyager", | |
1429 | .init = vger_init, | |
2d0d2837 | 1430 | .block_default_type = IF_SCSI, |
e4ada29e | 1431 | DEFAULT_MACHINE_OPTIONS, |
a526a31c BS |
1432 | }; |
1433 | ||
f80f9ec9 | 1434 | static QEMUMachine ss_lx_machine = { |
66de733b BS |
1435 | .name = "LX", |
1436 | .desc = "Sun4m platform, SPARCstation LX", | |
1437 | .init = ss_lx_init, | |
2d0d2837 | 1438 | .block_default_type = IF_SCSI, |
e4ada29e | 1439 | DEFAULT_MACHINE_OPTIONS, |
a526a31c BS |
1440 | }; |
1441 | ||
f80f9ec9 | 1442 | static QEMUMachine ss4_machine = { |
66de733b BS |
1443 | .name = "SS-4", |
1444 | .desc = "Sun4m platform, SPARCstation 4", | |
1445 | .init = ss4_init, | |
2d0d2837 | 1446 | .block_default_type = IF_SCSI, |
e4ada29e | 1447 | DEFAULT_MACHINE_OPTIONS, |
a526a31c BS |
1448 | }; |
1449 | ||
f80f9ec9 | 1450 | static QEMUMachine scls_machine = { |
66de733b BS |
1451 | .name = "SPARCClassic", |
1452 | .desc = "Sun4m platform, SPARCClassic", | |
1453 | .init = scls_init, | |
2d0d2837 | 1454 | .block_default_type = IF_SCSI, |
e4ada29e | 1455 | DEFAULT_MACHINE_OPTIONS, |
a526a31c BS |
1456 | }; |
1457 | ||
f80f9ec9 | 1458 | static QEMUMachine sbook_machine = { |
66de733b BS |
1459 | .name = "SPARCbook", |
1460 | .desc = "Sun4m platform, SPARCbook", | |
1461 | .init = sbook_init, | |
2d0d2837 | 1462 | .block_default_type = IF_SCSI, |
e4ada29e | 1463 | DEFAULT_MACHINE_OPTIONS, |
a526a31c BS |
1464 | }; |
1465 | ||
83f7d43a AF |
1466 | static void sun4m_register_types(void) |
1467 | { | |
1468 | type_register_static(&idreg_info); | |
1469 | type_register_static(&afx_info); | |
1470 | type_register_static(&prom_info); | |
1471 | type_register_static(&ram_info); | |
1472 | } | |
1473 | ||
6a4e1771 | 1474 | static void sun4m_machine_init(void) |
f80f9ec9 AL |
1475 | { |
1476 | qemu_register_machine(&ss5_machine); | |
1477 | qemu_register_machine(&ss10_machine); | |
1478 | qemu_register_machine(&ss600mp_machine); | |
1479 | qemu_register_machine(&ss20_machine); | |
1480 | qemu_register_machine(&voyager_machine); | |
1481 | qemu_register_machine(&ss_lx_machine); | |
1482 | qemu_register_machine(&ss4_machine); | |
1483 | qemu_register_machine(&scls_machine); | |
1484 | qemu_register_machine(&sbook_machine); | |
f80f9ec9 AL |
1485 | } |
1486 | ||
83f7d43a | 1487 | type_init(sun4m_register_types) |
6a4e1771 | 1488 | machine_init(sun4m_machine_init); |