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Commit | Line | Data |
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420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
71e8a915 | 24 | |
db5ebe5f | 25 | #include "qemu/osdep.h" |
0a2e467b | 26 | #include "qemu/units.h" |
da34e65c | 27 | #include "qapi/error.h" |
2c65db5e | 28 | #include "qemu/datadir.h" |
4771d756 PB |
29 | #include "qemu-common.h" |
30 | #include "cpu.h" | |
83c9f4ca | 31 | #include "hw/sysbus.h" |
af87bf29 | 32 | #include "qemu/error-report.h" |
1de7afc9 | 33 | #include "qemu/timer.h" |
1527f488 | 34 | #include "hw/sparc/sun4m_iommu.h" |
819ce6b2 | 35 | #include "hw/rtc/m48t59.h" |
d6454270 | 36 | #include "migration/vmstate.h" |
0d09e41a PB |
37 | #include "hw/sparc/sparc32_dma.h" |
38 | #include "hw/block/fdc.h" | |
71e8a915 | 39 | #include "sysemu/reset.h" |
54d31236 | 40 | #include "sysemu/runstate.h" |
9c17d615 | 41 | #include "sysemu/sysemu.h" |
1422e32d | 42 | #include "net/net.h" |
83c9f4ca | 43 | #include "hw/boards.h" |
0d09e41a | 44 | #include "hw/scsi/esp.h" |
c6363bae | 45 | #include "hw/nvram/sun_nvram.h" |
a27bd6c7 | 46 | #include "hw/qdev-properties.h" |
2024c014 | 47 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
48 | #include "hw/nvram/fw_cfg.h" |
49 | #include "hw/char/escc.h" | |
6007523a | 50 | #include "hw/misc/empty_slot.h" |
077f0f3d | 51 | #include "hw/misc/unimp.h" |
64552b6b | 52 | #include "hw/irq.h" |
a879306c | 53 | #include "hw/or-irq.h" |
83c9f4ca | 54 | #include "hw/loader.h" |
ca20cf32 | 55 | #include "elf.h" |
97bf4851 | 56 | #include "trace.h" |
db1015e9 | 57 | #include "qom/object.h" |
420557e8 | 58 | |
36cd9210 BS |
59 | /* |
60 | * Sun4m architecture was used in the following machines: | |
61 | * | |
62 | * SPARCserver 6xxMP/xx | |
77f193da BS |
63 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
64 | * SPARCclassic X (4/10) | |
36cd9210 BS |
65 | * SPARCstation LX/ZX (4/30) |
66 | * SPARCstation Voyager | |
67 | * SPARCstation 10/xx, SPARCserver 10/xx | |
68 | * SPARCstation 5, SPARCserver 5 | |
69 | * SPARCstation 20/xx, SPARCserver 20 | |
70 | * SPARCstation 4 | |
71 | * | |
72 | * See for example: http://www.sunhelp.org/faq/sunref1.html | |
73 | */ | |
74 | ||
420557e8 | 75 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 76 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 77 | #define INITRD_LOAD_ADDR 0x00800000 |
0a2e467b | 78 | #define PROM_SIZE_MAX (1 * MiB) |
40ce0a9a | 79 | #define PROM_VADDR 0xffd00000 |
f930d07e | 80 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 81 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 82 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b96919e0 MCA |
83 | #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) |
84 | #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) | |
b8174937 | 85 | |
ba3c64fb | 86 | #define MAX_CPUS 16 |
b3a23197 | 87 | #define MAX_PILS 16 |
9a62fb24 | 88 | #define MAX_VSIMMS 4 |
420557e8 | 89 | |
b4ed08e0 BS |
90 | #define ESCC_CLOCK 4915200 |
91 | ||
8137cde8 | 92 | struct sun4m_hwdef { |
a8170e5e AK |
93 | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
94 | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; | |
95 | hwaddr serial_base, fd_base; | |
96 | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; | |
97 | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; | |
98 | hwaddr bpp_base, dbri_base, sx_base; | |
9a62fb24 | 99 | struct { |
a8170e5e | 100 | hwaddr reg_base, vram_base; |
9a62fb24 | 101 | } vsimm[MAX_VSIMMS]; |
a8170e5e | 102 | hwaddr ecc_base; |
3ebf5aaf | 103 | uint64_t max_mem; |
61999750 BS |
104 | uint32_t ecc_version; |
105 | uint32_t iommu_version; | |
106 | uint16_t machine_id; | |
107 | uint8_t nvram_machine_id; | |
36cd9210 BS |
108 | }; |
109 | ||
95bc47de PMD |
110 | struct Sun4mMachineClass { |
111 | /*< private >*/ | |
112 | MachineClass parent_obj; | |
113 | /*< public >*/ | |
114 | const struct sun4m_hwdef *hwdef; | |
115 | }; | |
116 | typedef struct Sun4mMachineClass Sun4mMachineClass; | |
117 | ||
828d01b7 | 118 | #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") |
95bc47de | 119 | DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) |
828d01b7 | 120 | |
d5a42d19 PMD |
121 | const char *fw_cfg_arch_key_name(uint16_t key) |
122 | { | |
123 | static const struct { | |
124 | uint16_t key; | |
125 | const char *name; | |
126 | } fw_cfg_arch_wellknown_keys[] = { | |
127 | {FW_CFG_SUN4M_DEPTH, "depth"}, | |
128 | {FW_CFG_SUN4M_WIDTH, "width"}, | |
129 | {FW_CFG_SUN4M_HEIGHT, "height"}, | |
130 | }; | |
131 | ||
132 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { | |
133 | if (fw_cfg_arch_wellknown_keys[i].key == key) { | |
134 | return fw_cfg_arch_wellknown_keys[i].name; | |
135 | } | |
136 | } | |
137 | return NULL; | |
138 | } | |
139 | ||
ddcd5531 GA |
140 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
141 | Error **errp) | |
81864572 | 142 | { |
48779e50 | 143 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
144 | } |
145 | ||
31688246 | 146 | static void nvram_init(Nvram *nvram, uint8_t *macaddr, |
43a34704 BS |
147 | const char *cmdline, const char *boot_devices, |
148 | ram_addr_t RAM_size, uint32_t kernel_size, | |
f930d07e | 149 | int width, int height, int depth, |
905fdcb5 | 150 | int nvram_machine_id, const char *arch) |
e80cfcfc | 151 | { |
d2c63fc1 | 152 | unsigned int i; |
2024c014 | 153 | int sysp_end; |
d2c63fc1 | 154 | uint8_t image[0x1ff0]; |
31688246 | 155 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
156 | |
157 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 158 | |
2024c014 | 159 | /* OpenBIOS nvram variables partition */ |
37035df5 | 160 | sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); |
b6f479d3 | 161 | |
2024c014 TH |
162 | /* Free space partition */ |
163 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 164 | |
905fdcb5 BS |
165 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
166 | nvram_machine_id); | |
d2c63fc1 | 167 | |
31688246 HP |
168 | for (i = 0; i < sizeof(image); i++) { |
169 | (k->write)(nvram, i, image[i]); | |
170 | } | |
e80cfcfc FB |
171 | } |
172 | ||
98cec4a2 | 173 | void cpu_check_irqs(CPUSPARCState *env) |
327ac2e7 | 174 | { |
d8ed887b AF |
175 | CPUState *cs; |
176 | ||
5ee59930 AB |
177 | /* We should be holding the BQL before we mess with IRQs */ |
178 | g_assert(qemu_mutex_iothread_locked()); | |
179 | ||
327ac2e7 BS |
180 | if (env->pil_in && (env->interrupt_index == 0 || |
181 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
182 | unsigned int i; | |
183 | ||
184 | for (i = 15; i > 0; i--) { | |
185 | if (env->pil_in & (1 << i)) { | |
186 | int old_interrupt = env->interrupt_index; | |
187 | ||
188 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 | 189 | if (old_interrupt != env->interrupt_index) { |
5a59fbce | 190 | cs = env_cpu(env); |
97bf4851 | 191 | trace_sun4m_cpu_interrupt(i); |
c3affe56 | 192 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
f32d7ec5 | 193 | } |
327ac2e7 BS |
194 | break; |
195 | } | |
196 | } | |
197 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
5a59fbce | 198 | cs = env_cpu(env); |
97bf4851 | 199 | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); |
327ac2e7 | 200 | env->interrupt_index = 0; |
d8ed887b | 201 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
327ac2e7 BS |
202 | } |
203 | } | |
204 | ||
38c66cf2 | 205 | static void cpu_kick_irq(SPARCCPU *cpu) |
94ad5b00 | 206 | { |
38c66cf2 | 207 | CPUSPARCState *env = &cpu->env; |
259186a7 | 208 | CPUState *cs = CPU(cpu); |
38c66cf2 | 209 | |
259186a7 | 210 | cs->halted = 0; |
94ad5b00 | 211 | cpu_check_irqs(env); |
259186a7 | 212 | qemu_cpu_kick(cs); |
94ad5b00 PB |
213 | } |
214 | ||
b3a23197 BS |
215 | static void cpu_set_irq(void *opaque, int irq, int level) |
216 | { | |
e0bbf9b5 AF |
217 | SPARCCPU *cpu = opaque; |
218 | CPUSPARCState *env = &cpu->env; | |
b3a23197 BS |
219 | |
220 | if (level) { | |
97bf4851 | 221 | trace_sun4m_cpu_set_irq_raise(irq); |
327ac2e7 | 222 | env->pil_in |= 1 << irq; |
38c66cf2 | 223 | cpu_kick_irq(cpu); |
b3a23197 | 224 | } else { |
97bf4851 | 225 | trace_sun4m_cpu_set_irq_lower(irq); |
327ac2e7 BS |
226 | env->pil_in &= ~(1 << irq); |
227 | cpu_check_irqs(env); | |
b3a23197 BS |
228 | } |
229 | } | |
230 | ||
231 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
232 | { | |
233 | } | |
234 | ||
24f675cd | 235 | static void sun4m_cpu_reset(void *opaque) |
c68ea704 | 236 | { |
5414dec6 | 237 | SPARCCPU *cpu = opaque; |
259186a7 | 238 | CPUState *cs = CPU(cpu); |
3d29fbef | 239 | |
259186a7 | 240 | cpu_reset(cs); |
3d29fbef BS |
241 | } |
242 | ||
6d0c293d BS |
243 | static void cpu_halt_signal(void *opaque, int irq, int level) |
244 | { | |
4917cf44 AF |
245 | if (level && current_cpu) { |
246 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); | |
c3affe56 | 247 | } |
6d0c293d BS |
248 | } |
249 | ||
409dbce5 AJ |
250 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
251 | { | |
252 | return addr - 0xf0000000ULL; | |
253 | } | |
254 | ||
3ebf5aaf | 255 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc | 256 | const char *initrd_filename, |
6031ff8b MCA |
257 | ram_addr_t RAM_size, |
258 | uint32_t *initrd_size) | |
3ebf5aaf BS |
259 | { |
260 | int linux_boot; | |
261 | unsigned int i; | |
6031ff8b | 262 | long kernel_size; |
3c178e72 | 263 | uint8_t *ptr; |
3ebf5aaf BS |
264 | |
265 | linux_boot = (kernel_filename != NULL); | |
266 | ||
267 | kernel_size = 0; | |
268 | if (linux_boot) { | |
ca20cf32 BS |
269 | int bswap_needed; |
270 | ||
271 | #ifdef BSWAP_NEEDED | |
272 | bswap_needed = 1; | |
273 | #else | |
274 | bswap_needed = 0; | |
275 | #endif | |
4366e1db LM |
276 | kernel_size = load_elf(kernel_filename, NULL, |
277 | translate_kernel_address, NULL, | |
6cdda0ff | 278 | NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); |
3ebf5aaf | 279 | if (kernel_size < 0) |
293f78bc | 280 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
281 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
282 | TARGET_PAGE_SIZE); | |
3ebf5aaf | 283 | if (kernel_size < 0) |
293f78bc BS |
284 | kernel_size = load_image_targphys(kernel_filename, |
285 | KERNEL_LOAD_ADDR, | |
286 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf | 287 | if (kernel_size < 0) { |
29bd7231 | 288 | error_report("could not load kernel '%s'", kernel_filename); |
3ebf5aaf BS |
289 | exit(1); |
290 | } | |
291 | ||
292 | /* load initrd */ | |
6031ff8b | 293 | *initrd_size = 0; |
3ebf5aaf | 294 | if (initrd_filename) { |
6031ff8b MCA |
295 | *initrd_size = load_image_targphys(initrd_filename, |
296 | INITRD_LOAD_ADDR, | |
297 | RAM_size - INITRD_LOAD_ADDR); | |
298 | if ((int)*initrd_size < 0) { | |
29bd7231 AF |
299 | error_report("could not load initial ram disk '%s'", |
300 | initrd_filename); | |
3ebf5aaf BS |
301 | exit(1); |
302 | } | |
303 | } | |
6031ff8b | 304 | if (*initrd_size > 0) { |
3ebf5aaf | 305 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
0f0f8b61 TH |
306 | ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); |
307 | if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ | |
3c178e72 | 308 | stl_p(ptr + 16, INITRD_LOAD_ADDR); |
6031ff8b | 309 | stl_p(ptr + 20, *initrd_size); |
3ebf5aaf BS |
310 | break; |
311 | } | |
312 | } | |
313 | } | |
314 | } | |
315 | return kernel_size; | |
316 | } | |
317 | ||
a8170e5e | 318 | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
4b48bf05 BS |
319 | { |
320 | DeviceState *dev; | |
321 | SysBusDevice *s; | |
322 | ||
3e80f690 | 323 | dev = qdev_new(TYPE_SUN4M_IOMMU); |
4b48bf05 | 324 | qdev_prop_set_uint32(dev, "version", version); |
1356b98d | 325 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 326 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
327 | sysbus_connect_irq(s, 0, irq); |
328 | sysbus_mmio_map(s, 0, addr); | |
329 | ||
330 | return s; | |
331 | } | |
332 | ||
6aa62ed6 MCA |
333 | static void *sparc32_dma_init(hwaddr dma_base, |
334 | hwaddr esp_base, qemu_irq espdma_irq, | |
c4210bc1 | 335 | hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) |
74ff8d90 | 336 | { |
6aa62ed6 MCA |
337 | DeviceState *dma; |
338 | ESPDMADeviceState *espdma; | |
339 | LEDMADeviceState *ledma; | |
340 | SysBusESPState *esp; | |
341 | SysBusPCNetState *lance; | |
74ff8d90 | 342 | |
3e80f690 | 343 | dma = qdev_new(TYPE_SPARC32_DMA); |
6aa62ed6 MCA |
344 | espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( |
345 | OBJECT(dma), "espdma")); | |
346 | sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); | |
347 | ||
84fbefed | 348 | esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); |
6aa62ed6 MCA |
349 | |
350 | ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( | |
351 | OBJECT(dma), "ledma")); | |
352 | sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); | |
353 | ||
354 | lance = SYSBUS_PCNET(object_resolve_path_component( | |
355 | OBJECT(ledma), "lance")); | |
c4210bc1 MCA |
356 | qdev_set_nic_properties(DEVICE(lance), nd); |
357 | ||
358 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); | |
359 | sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); | |
360 | ||
361 | sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); | |
362 | scsi_bus_legacy_handle_cmdline(&esp->esp.bus); | |
363 | ||
6aa62ed6 MCA |
364 | sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); |
365 | ||
366 | return dma; | |
74ff8d90 BS |
367 | } |
368 | ||
a8170e5e AK |
369 | static DeviceState *slavio_intctl_init(hwaddr addr, |
370 | hwaddr addrg, | |
462eda24 | 371 | qemu_irq **parent_irq) |
4b48bf05 BS |
372 | { |
373 | DeviceState *dev; | |
374 | SysBusDevice *s; | |
375 | unsigned int i, j; | |
376 | ||
3e80f690 | 377 | dev = qdev_new("slavio_intctl"); |
4b48bf05 | 378 | |
1356b98d | 379 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 380 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
381 | |
382 | for (i = 0; i < MAX_CPUS; i++) { | |
383 | for (j = 0; j < MAX_PILS; j++) { | |
384 | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); | |
385 | } | |
386 | } | |
387 | sysbus_mmio_map(s, 0, addrg); | |
388 | for (i = 0; i < MAX_CPUS; i++) { | |
389 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); | |
390 | } | |
391 | ||
392 | return dev; | |
393 | } | |
394 | ||
395 | #define SYS_TIMER_OFFSET 0x10000ULL | |
396 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | |
397 | ||
a8170e5e | 398 | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
4b48bf05 BS |
399 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
400 | { | |
401 | DeviceState *dev; | |
402 | SysBusDevice *s; | |
403 | unsigned int i; | |
404 | ||
3e80f690 | 405 | dev = qdev_new("slavio_timer"); |
4b48bf05 | 406 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); |
1356b98d | 407 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 408 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
409 | sysbus_connect_irq(s, 0, master_irq); |
410 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); | |
411 | ||
412 | for (i = 0; i < MAX_CPUS; i++) { | |
a8170e5e | 413 | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); |
4b48bf05 BS |
414 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
415 | } | |
416 | } | |
417 | ||
bea42280 IM |
418 | static qemu_irq slavio_system_powerdown; |
419 | ||
420 | static void slavio_powerdown_req(Notifier *n, void *opaque) | |
421 | { | |
422 | qemu_irq_raise(slavio_system_powerdown); | |
423 | } | |
424 | ||
425 | static Notifier slavio_system_powerdown_notifier = { | |
426 | .notify = slavio_powerdown_req | |
427 | }; | |
428 | ||
4b48bf05 BS |
429 | #define MISC_LEDS 0x01600000 |
430 | #define MISC_CFG 0x01800000 | |
431 | #define MISC_DIAG 0x01a00000 | |
432 | #define MISC_MDM 0x01b00000 | |
433 | #define MISC_SYS 0x01f00000 | |
434 | ||
a8170e5e AK |
435 | static void slavio_misc_init(hwaddr base, |
436 | hwaddr aux1_base, | |
437 | hwaddr aux2_base, qemu_irq irq, | |
b2b6f6ec | 438 | qemu_irq fdc_tc) |
4b48bf05 BS |
439 | { |
440 | DeviceState *dev; | |
441 | SysBusDevice *s; | |
442 | ||
3e80f690 | 443 | dev = qdev_new("slavio_misc"); |
1356b98d | 444 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 445 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
446 | if (base) { |
447 | /* 8 bit registers */ | |
448 | /* Slavio control */ | |
449 | sysbus_mmio_map(s, 0, base + MISC_CFG); | |
450 | /* Diagnostics */ | |
451 | sysbus_mmio_map(s, 1, base + MISC_DIAG); | |
452 | /* Modem control */ | |
453 | sysbus_mmio_map(s, 2, base + MISC_MDM); | |
454 | /* 16 bit registers */ | |
455 | /* ss600mp diag LEDs */ | |
456 | sysbus_mmio_map(s, 3, base + MISC_LEDS); | |
457 | /* 32 bit registers */ | |
458 | /* System control */ | |
459 | sysbus_mmio_map(s, 4, base + MISC_SYS); | |
460 | } | |
461 | if (aux1_base) { | |
462 | /* AUX 1 (Misc System Functions) */ | |
463 | sysbus_mmio_map(s, 5, aux1_base); | |
464 | } | |
465 | if (aux2_base) { | |
466 | /* AUX 2 (Software Powerdown Control) */ | |
467 | sysbus_mmio_map(s, 6, aux2_base); | |
468 | } | |
469 | sysbus_connect_irq(s, 0, irq); | |
470 | sysbus_connect_irq(s, 1, fdc_tc); | |
bea42280 IM |
471 | slavio_system_powerdown = qdev_get_gpio_in(dev, 0); |
472 | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); | |
4b48bf05 BS |
473 | } |
474 | ||
a8170e5e | 475 | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
4b48bf05 BS |
476 | { |
477 | DeviceState *dev; | |
478 | SysBusDevice *s; | |
479 | ||
3e80f690 | 480 | dev = qdev_new("eccmemctl"); |
4b48bf05 | 481 | qdev_prop_set_uint32(dev, "version", version); |
1356b98d | 482 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 483 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
484 | sysbus_connect_irq(s, 0, irq); |
485 | sysbus_mmio_map(s, 0, base); | |
486 | if (version == 0) { // SS-600MP only | |
487 | sysbus_mmio_map(s, 1, base + 0x1000); | |
488 | } | |
489 | } | |
490 | ||
a8170e5e | 491 | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
4b48bf05 BS |
492 | { |
493 | DeviceState *dev; | |
494 | SysBusDevice *s; | |
495 | ||
3e80f690 | 496 | dev = qdev_new("apc"); |
1356b98d | 497 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 498 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
499 | /* Power management (APC) XXX: not a Slavio device */ |
500 | sysbus_mmio_map(s, 0, power_base); | |
501 | sysbus_connect_irq(s, 0, cpu_halt); | |
502 | } | |
503 | ||
55d7bfe2 | 504 | static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
4b48bf05 BS |
505 | int height, int depth) |
506 | { | |
507 | DeviceState *dev; | |
508 | SysBusDevice *s; | |
509 | ||
e178113f | 510 | dev = qdev_new("sun-tcx"); |
4b48bf05 BS |
511 | qdev_prop_set_uint32(dev, "vram_size", vram_size); |
512 | qdev_prop_set_uint16(dev, "width", width); | |
513 | qdev_prop_set_uint16(dev, "height", height); | |
514 | qdev_prop_set_uint16(dev, "depth", depth); | |
1356b98d | 515 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 516 | sysbus_realize_and_unref(s, &error_fatal); |
55d7bfe2 MCA |
517 | |
518 | /* 10/ROM : FCode ROM */ | |
da87dd7b | 519 | sysbus_mmio_map(s, 0, addr); |
55d7bfe2 MCA |
520 | /* 2/STIP : Stipple */ |
521 | sysbus_mmio_map(s, 1, addr + 0x04000000ULL); | |
522 | /* 3/BLIT : Blitter */ | |
523 | sysbus_mmio_map(s, 2, addr + 0x06000000ULL); | |
524 | /* 5/RSTIP : Raw Stipple */ | |
525 | sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); | |
526 | /* 6/RBLIT : Raw Blitter */ | |
527 | sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); | |
528 | /* 7/TEC : Transform Engine */ | |
529 | sysbus_mmio_map(s, 5, addr + 0x00700000ULL); | |
530 | /* 8/CMAP : DAC */ | |
531 | sysbus_mmio_map(s, 6, addr + 0x00200000ULL); | |
532 | /* 9/THC : */ | |
533 | if (depth == 8) { | |
534 | sysbus_mmio_map(s, 7, addr + 0x00300000ULL); | |
4b48bf05 | 535 | } else { |
55d7bfe2 | 536 | sysbus_mmio_map(s, 7, addr + 0x00301000ULL); |
4b48bf05 | 537 | } |
55d7bfe2 MCA |
538 | /* 11/DHC : */ |
539 | sysbus_mmio_map(s, 8, addr + 0x00240000ULL); | |
540 | /* 12/ALT : */ | |
541 | sysbus_mmio_map(s, 9, addr + 0x00280000ULL); | |
542 | /* 0/DFB8 : 8-bit plane */ | |
543 | sysbus_mmio_map(s, 10, addr + 0x00800000ULL); | |
544 | /* 1/DFB24 : 24bit plane */ | |
545 | sysbus_mmio_map(s, 11, addr + 0x02000000ULL); | |
546 | /* 4/RDFB32: Raw framebuffer. Control plane */ | |
547 | sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); | |
548 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ | |
549 | if (depth == 8) { | |
550 | sysbus_mmio_map(s, 13, addr + 0x00301000ULL); | |
551 | } | |
552 | ||
553 | sysbus_connect_irq(s, 0, irq); | |
4b48bf05 BS |
554 | } |
555 | ||
af87bf29 MCA |
556 | static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
557 | int height, int depth) | |
558 | { | |
559 | DeviceState *dev; | |
560 | SysBusDevice *s; | |
561 | ||
3e80f690 | 562 | dev = qdev_new("cgthree"); |
af87bf29 MCA |
563 | qdev_prop_set_uint32(dev, "vram-size", vram_size); |
564 | qdev_prop_set_uint16(dev, "width", width); | |
565 | qdev_prop_set_uint16(dev, "height", height); | |
566 | qdev_prop_set_uint16(dev, "depth", depth); | |
af87bf29 | 567 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 568 | sysbus_realize_and_unref(s, &error_fatal); |
af87bf29 MCA |
569 | |
570 | /* FCode ROM */ | |
571 | sysbus_mmio_map(s, 0, addr); | |
572 | /* DAC */ | |
573 | sysbus_mmio_map(s, 1, addr + 0x400000ULL); | |
574 | /* 8-bit plane */ | |
575 | sysbus_mmio_map(s, 2, addr + 0x800000ULL); | |
576 | ||
577 | sysbus_connect_irq(s, 0, irq); | |
578 | } | |
579 | ||
325f2747 | 580 | /* NCR89C100/MACIO Internal ID register */ |
ef9dfa4c AF |
581 | |
582 | #define TYPE_MACIO_ID_REGISTER "macio_idreg" | |
583 | ||
325f2747 BS |
584 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
585 | ||
a8170e5e | 586 | static void idreg_init(hwaddr addr) |
325f2747 BS |
587 | { |
588 | DeviceState *dev; | |
589 | SysBusDevice *s; | |
590 | ||
3e80f690 | 591 | dev = qdev_new(TYPE_MACIO_ID_REGISTER); |
1356b98d | 592 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 593 | sysbus_realize_and_unref(s, &error_fatal); |
325f2747 BS |
594 | |
595 | sysbus_mmio_map(s, 0, addr); | |
3c8133f9 PM |
596 | address_space_write_rom(&address_space_memory, addr, |
597 | MEMTXATTRS_UNSPECIFIED, | |
598 | idreg_data, sizeof(idreg_data)); | |
325f2747 BS |
599 | } |
600 | ||
8063396b | 601 | OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) |
ef9dfa4c | 602 | |
db1015e9 | 603 | struct IDRegState { |
ef9dfa4c AF |
604 | SysBusDevice parent_obj; |
605 | ||
3150fa50 | 606 | MemoryRegion mem; |
db1015e9 | 607 | }; |
3150fa50 | 608 | |
a2a5a7b5 | 609 | static void idreg_realize(DeviceState *ds, Error **errp) |
325f2747 | 610 | { |
a2a5a7b5 TH |
611 | IDRegState *s = MACIO_ID_REGISTER(ds); |
612 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
613 | Error *local_err = NULL; | |
614 | ||
615 | memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", | |
616 | sizeof(idreg_data), &local_err); | |
617 | if (local_err) { | |
618 | error_propagate(errp, local_err); | |
619 | return; | |
620 | } | |
325f2747 | 621 | |
c5705a77 | 622 | vmstate_register_ram_global(&s->mem); |
3150fa50 | 623 | memory_region_set_readonly(&s->mem, true); |
750ecd44 | 624 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
625 | } |
626 | ||
a2a5a7b5 TH |
627 | static void idreg_class_init(ObjectClass *oc, void *data) |
628 | { | |
629 | DeviceClass *dc = DEVICE_CLASS(oc); | |
630 | ||
631 | dc->realize = idreg_realize; | |
632 | } | |
633 | ||
8c43a6f0 | 634 | static const TypeInfo idreg_info = { |
ef9dfa4c | 635 | .name = TYPE_MACIO_ID_REGISTER, |
39bffca2 AL |
636 | .parent = TYPE_SYS_BUS_DEVICE, |
637 | .instance_size = sizeof(IDRegState), | |
a2a5a7b5 | 638 | .class_init = idreg_class_init, |
325f2747 BS |
639 | }; |
640 | ||
b3a49965 | 641 | #define TYPE_TCX_AFX "tcx_afx" |
8063396b | 642 | OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) |
b3a49965 | 643 | |
db1015e9 | 644 | struct AFXState { |
b3a49965 AF |
645 | SysBusDevice parent_obj; |
646 | ||
3150fa50 | 647 | MemoryRegion mem; |
db1015e9 | 648 | }; |
3150fa50 | 649 | |
c5de386a | 650 | /* SS-5 TCX AFX register */ |
a8170e5e | 651 | static void afx_init(hwaddr addr) |
c5de386a AT |
652 | { |
653 | DeviceState *dev; | |
654 | SysBusDevice *s; | |
655 | ||
3e80f690 | 656 | dev = qdev_new(TYPE_TCX_AFX); |
1356b98d | 657 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 658 | sysbus_realize_and_unref(s, &error_fatal); |
c5de386a AT |
659 | |
660 | sysbus_mmio_map(s, 0, addr); | |
661 | } | |
662 | ||
a2a5a7b5 | 663 | static void afx_realize(DeviceState *ds, Error **errp) |
c5de386a | 664 | { |
a2a5a7b5 TH |
665 | AFXState *s = TCX_AFX(ds); |
666 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
667 | Error *local_err = NULL; | |
668 | ||
669 | memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, | |
670 | &local_err); | |
671 | if (local_err) { | |
672 | error_propagate(errp, local_err); | |
673 | return; | |
674 | } | |
c5de386a | 675 | |
c5705a77 | 676 | vmstate_register_ram_global(&s->mem); |
750ecd44 | 677 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
678 | } |
679 | ||
a2a5a7b5 TH |
680 | static void afx_class_init(ObjectClass *oc, void *data) |
681 | { | |
682 | DeviceClass *dc = DEVICE_CLASS(oc); | |
683 | ||
684 | dc->realize = afx_realize; | |
685 | } | |
686 | ||
8c43a6f0 | 687 | static const TypeInfo afx_info = { |
b3a49965 | 688 | .name = TYPE_TCX_AFX, |
39bffca2 AL |
689 | .parent = TYPE_SYS_BUS_DEVICE, |
690 | .instance_size = sizeof(AFXState), | |
a2a5a7b5 | 691 | .class_init = afx_class_init, |
c5de386a AT |
692 | }; |
693 | ||
e6f54c91 | 694 | #define TYPE_OPENPROM "openprom" |
db1015e9 | 695 | typedef struct PROMState PROMState; |
8110fa1d EH |
696 | DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, |
697 | TYPE_OPENPROM) | |
e6f54c91 | 698 | |
db1015e9 | 699 | struct PROMState { |
e6f54c91 AF |
700 | SysBusDevice parent_obj; |
701 | ||
3150fa50 | 702 | MemoryRegion prom; |
db1015e9 | 703 | }; |
3150fa50 | 704 | |
f48f6569 | 705 | /* Boot PROM (OpenBIOS) */ |
409dbce5 AJ |
706 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
707 | { | |
a8170e5e | 708 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
709 | return addr + *base_addr - PROM_VADDR; |
710 | } | |
711 | ||
a8170e5e | 712 | static void prom_init(hwaddr addr, const char *bios_name) |
f48f6569 BS |
713 | { |
714 | DeviceState *dev; | |
715 | SysBusDevice *s; | |
716 | char *filename; | |
717 | int ret; | |
718 | ||
3e80f690 | 719 | dev = qdev_new(TYPE_OPENPROM); |
1356b98d | 720 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 721 | sysbus_realize_and_unref(s, &error_fatal); |
f48f6569 BS |
722 | |
723 | sysbus_mmio_map(s, 0, addr); | |
724 | ||
725 | /* load boot prom */ | |
726 | if (bios_name == NULL) { | |
727 | bios_name = PROM_FILENAME; | |
728 | } | |
729 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
730 | if (filename) { | |
4366e1db LM |
731 | ret = load_elf(filename, NULL, |
732 | translate_prom_address, &addr, NULL, | |
6cdda0ff | 733 | NULL, NULL, NULL, 1, EM_SPARC, 0, 0); |
f48f6569 BS |
734 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
735 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
736 | } | |
7267c094 | 737 | g_free(filename); |
f48f6569 BS |
738 | } else { |
739 | ret = -1; | |
740 | } | |
741 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 742 | error_report("could not load prom '%s'", bios_name); |
f48f6569 BS |
743 | exit(1); |
744 | } | |
745 | } | |
746 | ||
a2a5a7b5 | 747 | static void prom_realize(DeviceState *ds, Error **errp) |
f48f6569 | 748 | { |
a2a5a7b5 TH |
749 | PROMState *s = OPENPROM(ds); |
750 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
751 | Error *local_err = NULL; | |
752 | ||
753 | memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", | |
754 | PROM_SIZE_MAX, &local_err); | |
755 | if (local_err) { | |
756 | error_propagate(errp, local_err); | |
757 | return; | |
758 | } | |
f48f6569 | 759 | |
c5705a77 | 760 | vmstate_register_ram_global(&s->prom); |
3150fa50 | 761 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 762 | sysbus_init_mmio(dev, &s->prom); |
f48f6569 BS |
763 | } |
764 | ||
999e12bb AL |
765 | static Property prom_properties[] = { |
766 | {/* end of property list */}, | |
767 | }; | |
768 | ||
769 | static void prom_class_init(ObjectClass *klass, void *data) | |
770 | { | |
39bffca2 | 771 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 772 | |
4f67d30b | 773 | device_class_set_props(dc, prom_properties); |
a2a5a7b5 | 774 | dc->realize = prom_realize; |
999e12bb AL |
775 | } |
776 | ||
8c43a6f0 | 777 | static const TypeInfo prom_info = { |
e6f54c91 | 778 | .name = TYPE_OPENPROM, |
39bffca2 AL |
779 | .parent = TYPE_SYS_BUS_DEVICE, |
780 | .instance_size = sizeof(PROMState), | |
781 | .class_init = prom_class_init, | |
f48f6569 BS |
782 | }; |
783 | ||
5ab6b4c6 | 784 | #define TYPE_SUN4M_MEMORY "memory" |
db1015e9 | 785 | typedef struct RamDevice RamDevice; |
8110fa1d EH |
786 | DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, |
787 | TYPE_SUN4M_MEMORY) | |
5ab6b4c6 | 788 | |
db1015e9 | 789 | struct RamDevice { |
5ab6b4c6 | 790 | SysBusDevice parent_obj; |
b2554752 | 791 | HostMemoryBackend *memdev; |
db1015e9 | 792 | }; |
ee6847d1 | 793 | |
a350db85 | 794 | /* System RAM */ |
dc8b6dd9 | 795 | static void ram_realize(DeviceState *dev, Error **errp) |
a350db85 | 796 | { |
5ab6b4c6 | 797 | RamDevice *d = SUN4M_RAM(dev); |
b2554752 | 798 | MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); |
a350db85 | 799 | |
b2554752 | 800 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); |
a350db85 BS |
801 | } |
802 | ||
b2554752 | 803 | static void ram_initfn(Object *obj) |
a350db85 | 804 | { |
b2554752 IM |
805 | RamDevice *d = SUN4M_RAM(obj); |
806 | object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, | |
807 | (Object **)&d->memdev, | |
808 | object_property_allow_set_link, | |
d2623129 | 809 | OBJ_PROP_LINK_STRONG); |
b2554752 | 810 | object_property_set_description(obj, "memdev", "Set RAM backend" |
7eecec7d | 811 | "Valid value is ID of a hostmem backend"); |
a350db85 BS |
812 | } |
813 | ||
999e12bb AL |
814 | static void ram_class_init(ObjectClass *klass, void *data) |
815 | { | |
39bffca2 | 816 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 817 | |
dc8b6dd9 | 818 | dc->realize = ram_realize; |
999e12bb AL |
819 | } |
820 | ||
8c43a6f0 | 821 | static const TypeInfo ram_info = { |
5ab6b4c6 | 822 | .name = TYPE_SUN4M_MEMORY, |
39bffca2 AL |
823 | .parent = TYPE_SYS_BUS_DEVICE, |
824 | .instance_size = sizeof(RamDevice), | |
b2554752 | 825 | .instance_init = ram_initfn, |
39bffca2 | 826 | .class_init = ram_class_init, |
a350db85 BS |
827 | }; |
828 | ||
49cbd887 | 829 | static void cpu_devinit(const char *cpu_type, unsigned int id, |
89835363 | 830 | uint64_t prom_addr, qemu_irq **cpu_irqs) |
666713c0 | 831 | { |
8968f588 | 832 | SPARCCPU *cpu; |
98cec4a2 | 833 | CPUSPARCState *env; |
666713c0 | 834 | |
24f675cd | 835 | cpu = SPARC_CPU(object_new(cpu_type)); |
8968f588 | 836 | env = &cpu->env; |
666713c0 BS |
837 | |
838 | cpu_sparc_set_id(env, id); | |
24f675cd TJB |
839 | qemu_register_reset(sun4m_cpu_reset, cpu); |
840 | object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, | |
841 | &error_fatal); | |
842 | qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); | |
e0bbf9b5 | 843 | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
666713c0 | 844 | env->prom_addr = prom_addr; |
666713c0 BS |
845 | } |
846 | ||
acfbe712 BS |
847 | static void dummy_fdc_tc(void *opaque, int irq, int level) |
848 | { | |
849 | } | |
850 | ||
95bc47de | 851 | static void sun4m_hw_init(MachineState *machine) |
420557e8 | 852 | { |
95bc47de | 853 | const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; |
61b97833 | 854 | DeviceState *slavio_intctl; |
713c45fa | 855 | unsigned int i; |
cb0fa36b | 856 | Nvram *nvram; |
9540619d | 857 | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; |
2582cfa0 | 858 | qemu_irq fdc_tc; |
5c6602c5 | 859 | unsigned long kernel_size; |
6031ff8b | 860 | uint32_t initrd_size; |
fd8014e1 | 861 | DriveInfo *fd[MAX_FD]; |
a88b362c | 862 | FWCfgState *fw_cfg; |
a879306c | 863 | DeviceState *dev, *ms_kb_orgate, *serial_orgate; |
2cc75c32 | 864 | SysBusDevice *s; |
33decbd2 LX |
865 | unsigned int smp_cpus = machine->smp.cpus; |
866 | unsigned int max_cpus = machine->smp.max_cpus; | |
b2554752 IM |
867 | Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, |
868 | TYPE_MEMORY_BACKEND, NULL); | |
c4210bc1 | 869 | NICInfo *nd = &nd_table[0]; |
b2554752 IM |
870 | |
871 | if (machine->ram_size > hwdef->max_mem) { | |
872 | error_report("Too much memory for this machine: %" PRId64 "," | |
873 | " maximum %" PRId64, | |
874 | machine->ram_size / MiB, hwdef->max_mem / MiB); | |
875 | exit(1); | |
876 | } | |
420557e8 | 877 | |
ba3c64fb FB |
878 | /* init CPUs */ |
879 | for(i = 0; i < smp_cpus; i++) { | |
49cbd887 | 880 | cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); |
ba3c64fb | 881 | } |
b3a23197 BS |
882 | |
883 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
884 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
885 | ||
b2554752 | 886 | /* Create and map RAM frontend */ |
3e80f690 | 887 | dev = qdev_new("memory"); |
5325cc34 | 888 | object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); |
3c6ef471 | 889 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
b2554752 | 890 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); |
3ebf5aaf | 891 | |
676d9b9b AT |
892 | /* models without ECC don't trap when missing ram is accessed */ |
893 | if (!hwdef->ecc_base) { | |
28c78fe8 PMD |
894 | empty_slot_init("ecc", machine->ram_size, |
895 | hwdef->max_mem - machine->ram_size); | |
676d9b9b | 896 | } |
a350db85 | 897 | |
377ce9cb | 898 | prom_init(hwdef->slavio_base, machine->firmware); |
f48f6569 | 899 | |
d453c2c3 BS |
900 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
901 | hwdef->intctl_base + 0x10000ULL, | |
462eda24 | 902 | cpu_irqs); |
a1961a4b BS |
903 | |
904 | for (i = 0; i < 32; i++) { | |
d453c2c3 | 905 | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
a1961a4b BS |
906 | } |
907 | for (i = 0; i < MAX_CPUS; i++) { | |
d453c2c3 | 908 | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); |
a1961a4b | 909 | } |
b3a23197 | 910 | |
fe096129 | 911 | if (hwdef->idreg_base) { |
325f2747 | 912 | idreg_init(hwdef->idreg_base); |
4c2485de BS |
913 | } |
914 | ||
c5de386a AT |
915 | if (hwdef->afx_base) { |
916 | afx_init(hwdef->afx_base); | |
917 | } | |
918 | ||
6aa62ed6 | 919 | iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); |
ff403da6 | 920 | |
3386376c AT |
921 | if (hwdef->iommu_pad_base) { |
922 | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. | |
923 | Software shouldn't use aliased addresses, neither should it crash | |
924 | when does. Using empty_slot instead of aliasing can help with | |
925 | debugging such accesses */ | |
28c78fe8 PMD |
926 | empty_slot_init("iommu.alias", |
927 | hwdef->iommu_pad_base, hwdef->iommu_pad_len); | |
3386376c AT |
928 | } |
929 | ||
c4210bc1 | 930 | qemu_check_nic_model(nd, TYPE_LANCE); |
6aa62ed6 MCA |
931 | sparc32_dma_init(hwdef->dma_base, |
932 | hwdef->esp_base, slavio_irq[18], | |
c4210bc1 | 933 | hwdef->le_base, slavio_irq[16], nd); |
e6ca02a4 | 934 | |
eee0b836 | 935 | if (graphic_depth != 8 && graphic_depth != 24) { |
af87bf29 | 936 | error_report("Unsupported depth: %d", graphic_depth); |
eee0b836 BS |
937 | exit (1); |
938 | } | |
6807874d | 939 | if (vga_interface_type != VGA_NONE) { |
af87bf29 MCA |
940 | if (vga_interface_type == VGA_CG3) { |
941 | if (graphic_depth != 8) { | |
942 | error_report("Unsupported depth: %d", graphic_depth); | |
943 | exit(1); | |
944 | } | |
945 | ||
946 | if (!(graphic_width == 1024 && graphic_height == 768) && | |
947 | !(graphic_width == 1152 && graphic_height == 900)) { | |
948 | error_report("Unsupported resolution: %d x %d", graphic_width, | |
949 | graphic_height); | |
950 | exit(1); | |
951 | } | |
952 | ||
953 | /* sbus irq 5 */ | |
954 | cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, | |
955 | graphic_width, graphic_height, graphic_depth); | |
956 | } else { | |
957 | /* If no display specified, default to TCX */ | |
958 | if (graphic_depth != 8 && graphic_depth != 24) { | |
959 | error_report("Unsupported depth: %d", graphic_depth); | |
960 | exit(1); | |
961 | } | |
962 | ||
963 | if (!(graphic_width == 1024 && graphic_height == 768)) { | |
964 | error_report("Unsupported resolution: %d x %d", | |
965 | graphic_width, graphic_height); | |
966 | exit(1); | |
967 | } | |
968 | ||
55d7bfe2 MCA |
969 | tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, |
970 | graphic_width, graphic_height, graphic_depth); | |
af87bf29 | 971 | } |
9a62fb24 BB |
972 | } |
973 | ||
6807874d | 974 | for (i = 0; i < MAX_VSIMMS; i++) { |
9a62fb24 BB |
975 | /* vsimm registers probed by OBP */ |
976 | if (hwdef->vsimm[i].reg_base) { | |
28c78fe8 PMD |
977 | char *name = g_strdup_printf("vsimm[%d]", i); |
978 | empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); | |
979 | g_free(name); | |
9a62fb24 BB |
980 | } |
981 | } | |
982 | ||
983 | if (hwdef->sx_base) { | |
e178113f | 984 | create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); |
9a62fb24 | 985 | } |
dbe06e18 | 986 | |
cb0fa36b MCA |
987 | dev = qdev_new("sysbus-m48t08"); |
988 | qdev_prop_set_int32(dev, "base-year", 1968); | |
989 | s = SYS_BUS_DEVICE(dev); | |
990 | sysbus_realize_and_unref(s, &error_fatal); | |
991 | sysbus_connect_irq(s, 0, slavio_irq[0]); | |
992 | sysbus_mmio_map(s, 0, hwdef->nvram_base); | |
993 | nvram = NVRAM(dev); | |
81732d19 | 994 | |
c533e0b3 | 995 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); |
81732d19 | 996 | |
5cbdb3a3 SW |
997 | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device |
998 | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ | |
3e80f690 | 999 | dev = qdev_new(TYPE_ESCC); |
2cc75c32 LV |
1000 | qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); |
1001 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); | |
1002 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
1003 | qdev_prop_set_chr(dev, "chrB", NULL); | |
1004 | qdev_prop_set_chr(dev, "chrA", NULL); | |
1005 | qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); | |
1006 | qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); | |
2cc75c32 | 1007 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 1008 | sysbus_realize_and_unref(s, &error_fatal); |
2cc75c32 LV |
1009 | sysbus_mmio_map(s, 0, hwdef->ms_kb_base); |
1010 | ||
a879306c MCA |
1011 | /* Logically OR both its IRQs together */ |
1012 | ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | |
1013 | object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); | |
1014 | qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); | |
1015 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); | |
1016 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); | |
1017 | qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]); | |
1018 | ||
3e80f690 | 1019 | dev = qdev_new(TYPE_ESCC); |
2cc75c32 LV |
1020 | qdev_prop_set_uint32(dev, "disabled", 0); |
1021 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); | |
1022 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
9bca0edb PM |
1023 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); |
1024 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); | |
2cc75c32 LV |
1025 | qdev_prop_set_uint32(dev, "chnBtype", escc_serial); |
1026 | qdev_prop_set_uint32(dev, "chnAtype", escc_serial); | |
2cc75c32 LV |
1027 | |
1028 | s = SYS_BUS_DEVICE(dev); | |
3c6ef471 | 1029 | sysbus_realize_and_unref(s, &error_fatal); |
2cc75c32 | 1030 | sysbus_mmio_map(s, 0, hwdef->serial_base); |
741402f9 | 1031 | |
a879306c MCA |
1032 | /* Logically OR both its IRQs together */ |
1033 | serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | |
1034 | object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, | |
1035 | &error_fatal); | |
1036 | qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); | |
1037 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); | |
1038 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); | |
1039 | qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]); | |
1040 | ||
2582cfa0 | 1041 | if (hwdef->apc_base) { |
ca43b97b | 1042 | apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); |
2582cfa0 | 1043 | } |
2be17ebd | 1044 | |
fe096129 | 1045 | if (hwdef->fd_base) { |
e4bcb14c | 1046 | /* there is zero or one floppy drive */ |
309e60bd | 1047 | memset(fd, 0, sizeof(fd)); |
fd8014e1 | 1048 | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
c533e0b3 | 1049 | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, |
2582cfa0 | 1050 | &fdc_tc); |
acfbe712 | 1051 | } else { |
ca43b97b | 1052 | fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); |
e4bcb14c TS |
1053 | } |
1054 | ||
acfbe712 BS |
1055 | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
1056 | slavio_irq[30], fdc_tc); | |
1057 | ||
fa28ec52 | 1058 | if (hwdef->cs_base) { |
e178113f | 1059 | sysbus_create_simple("sun-CS4231", hwdef->cs_base, |
c533e0b3 | 1060 | slavio_irq[5]); |
fa28ec52 | 1061 | } |
b3ceef24 | 1062 | |
9a62fb24 BB |
1063 | if (hwdef->dbri_base) { |
1064 | /* ISDN chip with attached CS4215 audio codec */ | |
1065 | /* prom space */ | |
e178113f | 1066 | create_unimplemented_device("sun-DBRI.prom", |
077f0f3d | 1067 | hwdef->dbri_base + 0x1000, 0x30); |
9a62fb24 | 1068 | /* reg space */ |
e178113f | 1069 | create_unimplemented_device("sun-DBRI", |
077f0f3d | 1070 | hwdef->dbri_base + 0x10000, 0x100); |
9a62fb24 BB |
1071 | } |
1072 | ||
1073 | if (hwdef->bpp_base) { | |
1074 | /* parallel port */ | |
e178113f | 1075 | create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); |
9a62fb24 BB |
1076 | } |
1077 | ||
6031ff8b | 1078 | initrd_size = 0; |
3ef96221 MA |
1079 | kernel_size = sun4m_load_kernel(machine->kernel_filename, |
1080 | machine->initrd_filename, | |
6031ff8b | 1081 | machine->ram_size, &initrd_size); |
36cd9210 | 1082 | |
c4210bc1 | 1083 | nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, |
3ef96221 MA |
1084 | machine->boot_order, machine->ram_size, kernel_size, |
1085 | graphic_width, graphic_height, graphic_depth, | |
1086 | hwdef->nvram_machine_id, "Sun4m"); | |
7eb0c8e8 | 1087 | |
fe096129 | 1088 | if (hwdef->ecc_base) |
c533e0b3 | 1089 | ecc_init(hwdef->ecc_base, slavio_irq[28], |
e42c20b4 | 1090 | hwdef->ecc_version); |
3cce6243 | 1091 | |
3e80f690 | 1092 | dev = qdev_new(TYPE_FW_CFG_MEM); |
84983214 MCA |
1093 | fw_cfg = FW_CFG(dev); |
1094 | qdev_prop_set_uint32(dev, "data_width", 1); | |
1095 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
1096 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, | |
d2623129 | 1097 | OBJECT(fw_cfg)); |
84983214 | 1098 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 1099 | sysbus_realize_and_unref(s, &error_fatal); |
84983214 MCA |
1100 | sysbus_mmio_map(s, 0, CFG_ADDR); |
1101 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); | |
1102 | ||
5836d168 | 1103 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 1104 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
b2554752 | 1105 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
905fdcb5 | 1106 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
fbfcf955 | 1107 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
b96919e0 MCA |
1108 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); |
1109 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); | |
513f789f BS |
1110 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1111 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 1112 | if (machine->kernel_cmdline) { |
513f789f | 1113 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
6b63ef4d | 1114 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, |
3ef96221 MA |
1115 | machine->kernel_cmdline); |
1116 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
748a4ee3 | 1117 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 | 1118 | strlen(machine->kernel_cmdline) + 1); |
513f789f BS |
1119 | } else { |
1120 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
748a4ee3 | 1121 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f BS |
1122 | } |
1123 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
6031ff8b | 1124 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
3ef96221 | 1125 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
513f789f | 1126 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
36cd9210 BS |
1127 | } |
1128 | ||
905fdcb5 | 1129 | enum { |
905fdcb5 BS |
1130 | ss5_id = 32, |
1131 | vger_id, | |
1132 | lx_id, | |
1133 | ss4_id, | |
1134 | scls_id, | |
1135 | sbook_id, | |
1136 | ss10_id = 64, | |
1137 | ss20_id, | |
1138 | ss600mp_id, | |
905fdcb5 BS |
1139 | }; |
1140 | ||
8137cde8 | 1141 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
36cd9210 BS |
1142 | /* SS-5 */ |
1143 | { | |
1144 | .iommu_base = 0x10000000, | |
3386376c AT |
1145 | .iommu_pad_base = 0x10004000, |
1146 | .iommu_pad_len = 0x0fffb000, | |
36cd9210 BS |
1147 | .tcx_base = 0x50000000, |
1148 | .cs_base = 0x6c000000, | |
384ccb5d | 1149 | .slavio_base = 0x70000000, |
36cd9210 BS |
1150 | .ms_kb_base = 0x71000000, |
1151 | .serial_base = 0x71100000, | |
1152 | .nvram_base = 0x71200000, | |
1153 | .fd_base = 0x71400000, | |
1154 | .counter_base = 0x71d00000, | |
1155 | .intctl_base = 0x71e00000, | |
4c2485de | 1156 | .idreg_base = 0x78000000, |
36cd9210 BS |
1157 | .dma_base = 0x78400000, |
1158 | .esp_base = 0x78800000, | |
1159 | .le_base = 0x78c00000, | |
127fc407 | 1160 | .apc_base = 0x6a000000, |
c5de386a | 1161 | .afx_base = 0x6e000000, |
0019ad53 BS |
1162 | .aux1_base = 0x71900000, |
1163 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1164 | .nvram_machine_id = 0x80, |
1165 | .machine_id = ss5_id, | |
cf3102ac | 1166 | .iommu_version = 0x05000000, |
3ebf5aaf | 1167 | .max_mem = 0x10000000, |
e0353fe2 BS |
1168 | }, |
1169 | /* SS-10 */ | |
e0353fe2 | 1170 | { |
5dcb6b91 BS |
1171 | .iommu_base = 0xfe0000000ULL, |
1172 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
1173 | .slavio_base = 0xff0000000ULL, |
1174 | .ms_kb_base = 0xff1000000ULL, | |
1175 | .serial_base = 0xff1100000ULL, | |
1176 | .nvram_base = 0xff1200000ULL, | |
1177 | .fd_base = 0xff1700000ULL, | |
1178 | .counter_base = 0xff1300000ULL, | |
1179 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1180 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
1181 | .dma_base = 0xef0400000ULL, |
1182 | .esp_base = 0xef0800000ULL, | |
1183 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 1184 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1185 | .aux1_base = 0xff1800000ULL, |
1186 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
1187 | .ecc_base = 0xf00000000ULL, |
1188 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
905fdcb5 BS |
1189 | .nvram_machine_id = 0x72, |
1190 | .machine_id = ss10_id, | |
7fbfb139 | 1191 | .iommu_version = 0x03000000, |
6ef05b95 | 1192 | .max_mem = 0xf00000000ULL, |
36cd9210 | 1193 | }, |
6a3b9cc9 BS |
1194 | /* SS-600MP */ |
1195 | { | |
1196 | .iommu_base = 0xfe0000000ULL, | |
1197 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
1198 | .slavio_base = 0xff0000000ULL, |
1199 | .ms_kb_base = 0xff1000000ULL, | |
1200 | .serial_base = 0xff1100000ULL, | |
1201 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
1202 | .counter_base = 0xff1300000ULL, |
1203 | .intctl_base = 0xff1400000ULL, | |
1204 | .dma_base = 0xef0081000ULL, | |
1205 | .esp_base = 0xef0080000ULL, | |
1206 | .le_base = 0xef0060000ULL, | |
0019ad53 | 1207 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1208 | .aux1_base = 0xff1800000ULL, |
1209 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
1210 | .ecc_base = 0xf00000000ULL, |
1211 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
905fdcb5 BS |
1212 | .nvram_machine_id = 0x71, |
1213 | .machine_id = ss600mp_id, | |
7fbfb139 | 1214 | .iommu_version = 0x01000000, |
6ef05b95 | 1215 | .max_mem = 0xf00000000ULL, |
6a3b9cc9 | 1216 | }, |
ae40972f BS |
1217 | /* SS-20 */ |
1218 | { | |
1219 | .iommu_base = 0xfe0000000ULL, | |
1220 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
1221 | .slavio_base = 0xff0000000ULL, |
1222 | .ms_kb_base = 0xff1000000ULL, | |
1223 | .serial_base = 0xff1100000ULL, | |
1224 | .nvram_base = 0xff1200000ULL, | |
1225 | .fd_base = 0xff1700000ULL, | |
1226 | .counter_base = 0xff1300000ULL, | |
1227 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1228 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
1229 | .dma_base = 0xef0400000ULL, |
1230 | .esp_base = 0xef0800000ULL, | |
1231 | .le_base = 0xef0c00000ULL, | |
9a62fb24 | 1232 | .bpp_base = 0xef4800000ULL, |
0019ad53 | 1233 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
1234 | .aux1_base = 0xff1800000ULL, |
1235 | .aux2_base = 0xff1a01000ULL, | |
9a62fb24 BB |
1236 | .dbri_base = 0xee0000000ULL, |
1237 | .sx_base = 0xf80000000ULL, | |
1238 | .vsimm = { | |
1239 | { | |
1240 | .reg_base = 0x9c000000ULL, | |
1241 | .vram_base = 0xfc000000ULL | |
1242 | }, { | |
1243 | .reg_base = 0x90000000ULL, | |
1244 | .vram_base = 0xf0000000ULL | |
1245 | }, { | |
1246 | .reg_base = 0x94000000ULL | |
1247 | }, { | |
1248 | .reg_base = 0x98000000ULL | |
1249 | } | |
1250 | }, | |
ae40972f BS |
1251 | .ecc_base = 0xf00000000ULL, |
1252 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
905fdcb5 BS |
1253 | .nvram_machine_id = 0x72, |
1254 | .machine_id = ss20_id, | |
ae40972f | 1255 | .iommu_version = 0x13000000, |
6ef05b95 | 1256 | .max_mem = 0xf00000000ULL, |
ae40972f | 1257 | }, |
a526a31c BS |
1258 | /* Voyager */ |
1259 | { | |
1260 | .iommu_base = 0x10000000, | |
1261 | .tcx_base = 0x50000000, | |
a526a31c BS |
1262 | .slavio_base = 0x70000000, |
1263 | .ms_kb_base = 0x71000000, | |
1264 | .serial_base = 0x71100000, | |
1265 | .nvram_base = 0x71200000, | |
1266 | .fd_base = 0x71400000, | |
1267 | .counter_base = 0x71d00000, | |
1268 | .intctl_base = 0x71e00000, | |
1269 | .idreg_base = 0x78000000, | |
1270 | .dma_base = 0x78400000, | |
1271 | .esp_base = 0x78800000, | |
1272 | .le_base = 0x78c00000, | |
1273 | .apc_base = 0x71300000, // pmc | |
1274 | .aux1_base = 0x71900000, | |
1275 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1276 | .nvram_machine_id = 0x80, |
1277 | .machine_id = vger_id, | |
a526a31c | 1278 | .iommu_version = 0x05000000, |
a526a31c | 1279 | .max_mem = 0x10000000, |
a526a31c BS |
1280 | }, |
1281 | /* LX */ | |
1282 | { | |
1283 | .iommu_base = 0x10000000, | |
3386376c AT |
1284 | .iommu_pad_base = 0x10004000, |
1285 | .iommu_pad_len = 0x0fffb000, | |
a526a31c | 1286 | .tcx_base = 0x50000000, |
a526a31c BS |
1287 | .slavio_base = 0x70000000, |
1288 | .ms_kb_base = 0x71000000, | |
1289 | .serial_base = 0x71100000, | |
1290 | .nvram_base = 0x71200000, | |
1291 | .fd_base = 0x71400000, | |
1292 | .counter_base = 0x71d00000, | |
1293 | .intctl_base = 0x71e00000, | |
1294 | .idreg_base = 0x78000000, | |
1295 | .dma_base = 0x78400000, | |
1296 | .esp_base = 0x78800000, | |
1297 | .le_base = 0x78c00000, | |
a526a31c BS |
1298 | .aux1_base = 0x71900000, |
1299 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1300 | .nvram_machine_id = 0x80, |
1301 | .machine_id = lx_id, | |
a526a31c | 1302 | .iommu_version = 0x04000000, |
a526a31c | 1303 | .max_mem = 0x10000000, |
a526a31c BS |
1304 | }, |
1305 | /* SS-4 */ | |
1306 | { | |
1307 | .iommu_base = 0x10000000, | |
1308 | .tcx_base = 0x50000000, | |
1309 | .cs_base = 0x6c000000, | |
1310 | .slavio_base = 0x70000000, | |
1311 | .ms_kb_base = 0x71000000, | |
1312 | .serial_base = 0x71100000, | |
1313 | .nvram_base = 0x71200000, | |
1314 | .fd_base = 0x71400000, | |
1315 | .counter_base = 0x71d00000, | |
1316 | .intctl_base = 0x71e00000, | |
1317 | .idreg_base = 0x78000000, | |
1318 | .dma_base = 0x78400000, | |
1319 | .esp_base = 0x78800000, | |
1320 | .le_base = 0x78c00000, | |
1321 | .apc_base = 0x6a000000, | |
1322 | .aux1_base = 0x71900000, | |
1323 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1324 | .nvram_machine_id = 0x80, |
1325 | .machine_id = ss4_id, | |
a526a31c | 1326 | .iommu_version = 0x05000000, |
a526a31c | 1327 | .max_mem = 0x10000000, |
a526a31c BS |
1328 | }, |
1329 | /* SPARCClassic */ | |
1330 | { | |
1331 | .iommu_base = 0x10000000, | |
1332 | .tcx_base = 0x50000000, | |
a526a31c BS |
1333 | .slavio_base = 0x70000000, |
1334 | .ms_kb_base = 0x71000000, | |
1335 | .serial_base = 0x71100000, | |
1336 | .nvram_base = 0x71200000, | |
1337 | .fd_base = 0x71400000, | |
1338 | .counter_base = 0x71d00000, | |
1339 | .intctl_base = 0x71e00000, | |
1340 | .idreg_base = 0x78000000, | |
1341 | .dma_base = 0x78400000, | |
1342 | .esp_base = 0x78800000, | |
1343 | .le_base = 0x78c00000, | |
1344 | .apc_base = 0x6a000000, | |
1345 | .aux1_base = 0x71900000, | |
1346 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1347 | .nvram_machine_id = 0x80, |
1348 | .machine_id = scls_id, | |
a526a31c | 1349 | .iommu_version = 0x05000000, |
a526a31c | 1350 | .max_mem = 0x10000000, |
a526a31c BS |
1351 | }, |
1352 | /* SPARCbook */ | |
1353 | { | |
1354 | .iommu_base = 0x10000000, | |
1355 | .tcx_base = 0x50000000, // XXX | |
a526a31c BS |
1356 | .slavio_base = 0x70000000, |
1357 | .ms_kb_base = 0x71000000, | |
1358 | .serial_base = 0x71100000, | |
1359 | .nvram_base = 0x71200000, | |
1360 | .fd_base = 0x71400000, | |
1361 | .counter_base = 0x71d00000, | |
1362 | .intctl_base = 0x71e00000, | |
1363 | .idreg_base = 0x78000000, | |
1364 | .dma_base = 0x78400000, | |
1365 | .esp_base = 0x78800000, | |
1366 | .le_base = 0x78c00000, | |
1367 | .apc_base = 0x6a000000, | |
1368 | .aux1_base = 0x71900000, | |
1369 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1370 | .nvram_machine_id = 0x80, |
1371 | .machine_id = sbook_id, | |
a526a31c | 1372 | .iommu_version = 0x05000000, |
a526a31c | 1373 | .max_mem = 0x10000000, |
a526a31c | 1374 | }, |
36cd9210 BS |
1375 | }; |
1376 | ||
36cd9210 | 1377 | /* SPARCstation 5 hardware initialisation */ |
3ef96221 | 1378 | static void ss5_init(MachineState *machine) |
36cd9210 | 1379 | { |
95bc47de | 1380 | sun4m_hw_init(machine); |
420557e8 | 1381 | } |
c0e564d5 | 1382 | |
e0353fe2 | 1383 | /* SPARCstation 10 hardware initialisation */ |
3ef96221 | 1384 | static void ss10_init(MachineState *machine) |
e0353fe2 | 1385 | { |
95bc47de | 1386 | sun4m_hw_init(machine); |
e0353fe2 BS |
1387 | } |
1388 | ||
6a3b9cc9 | 1389 | /* SPARCserver 600MP hardware initialisation */ |
3ef96221 | 1390 | static void ss600mp_init(MachineState *machine) |
6a3b9cc9 | 1391 | { |
95bc47de | 1392 | sun4m_hw_init(machine); |
6a3b9cc9 BS |
1393 | } |
1394 | ||
ae40972f | 1395 | /* SPARCstation 20 hardware initialisation */ |
3ef96221 | 1396 | static void ss20_init(MachineState *machine) |
ae40972f | 1397 | { |
95bc47de | 1398 | sun4m_hw_init(machine); |
ee76f82e BS |
1399 | } |
1400 | ||
a526a31c | 1401 | /* SPARCstation Voyager hardware initialisation */ |
3ef96221 | 1402 | static void vger_init(MachineState *machine) |
a526a31c | 1403 | { |
95bc47de | 1404 | sun4m_hw_init(machine); |
a526a31c BS |
1405 | } |
1406 | ||
1407 | /* SPARCstation LX hardware initialisation */ | |
3ef96221 | 1408 | static void ss_lx_init(MachineState *machine) |
a526a31c | 1409 | { |
95bc47de | 1410 | sun4m_hw_init(machine); |
a526a31c BS |
1411 | } |
1412 | ||
1413 | /* SPARCstation 4 hardware initialisation */ | |
3ef96221 | 1414 | static void ss4_init(MachineState *machine) |
a526a31c | 1415 | { |
95bc47de | 1416 | sun4m_hw_init(machine); |
a526a31c BS |
1417 | } |
1418 | ||
1419 | /* SPARCClassic hardware initialisation */ | |
3ef96221 | 1420 | static void scls_init(MachineState *machine) |
a526a31c | 1421 | { |
95bc47de | 1422 | sun4m_hw_init(machine); |
a526a31c BS |
1423 | } |
1424 | ||
1425 | /* SPARCbook hardware initialisation */ | |
3ef96221 | 1426 | static void sbook_init(MachineState *machine) |
a526a31c | 1427 | { |
95bc47de | 1428 | sun4m_hw_init(machine); |
a526a31c BS |
1429 | } |
1430 | ||
8a661aea | 1431 | static void ss5_class_init(ObjectClass *oc, void *data) |
e264d29d | 1432 | { |
8a661aea | 1433 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1434 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1435 | |
e264d29d EH |
1436 | mc->desc = "Sun4m platform, SPARCstation 5"; |
1437 | mc->init = ss5_init; | |
1438 | mc->block_default_type = IF_SCSI; | |
ea0ac7f6 | 1439 | mc->is_default = true; |
e264d29d | 1440 | mc->default_boot_order = "c"; |
49cbd887 | 1441 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
fcd23a67 | 1442 | mc->default_display = "tcx"; |
b2554752 | 1443 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1444 | smc->hwdef = &sun4m_hwdefs[0]; |
e264d29d | 1445 | } |
e0353fe2 | 1446 | |
8a661aea AF |
1447 | static const TypeInfo ss5_type = { |
1448 | .name = MACHINE_TYPE_NAME("SS-5"), | |
828d01b7 | 1449 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1450 | .class_init = ss5_class_init, |
1451 | }; | |
6a3b9cc9 | 1452 | |
8a661aea | 1453 | static void ss10_class_init(ObjectClass *oc, void *data) |
e264d29d | 1454 | { |
8a661aea | 1455 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1456 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1457 | |
e264d29d EH |
1458 | mc->desc = "Sun4m platform, SPARCstation 10"; |
1459 | mc->init = ss10_init; | |
1460 | mc->block_default_type = IF_SCSI; | |
1461 | mc->max_cpus = 4; | |
1462 | mc->default_boot_order = "c"; | |
49cbd887 | 1463 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
fcd23a67 | 1464 | mc->default_display = "tcx"; |
b2554752 | 1465 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1466 | smc->hwdef = &sun4m_hwdefs[1]; |
e264d29d | 1467 | } |
ae40972f | 1468 | |
8a661aea AF |
1469 | static const TypeInfo ss10_type = { |
1470 | .name = MACHINE_TYPE_NAME("SS-10"), | |
828d01b7 | 1471 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1472 | .class_init = ss10_class_init, |
1473 | }; | |
ae40972f | 1474 | |
8a661aea | 1475 | static void ss600mp_class_init(ObjectClass *oc, void *data) |
e264d29d | 1476 | { |
8a661aea | 1477 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1478 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1479 | |
e264d29d EH |
1480 | mc->desc = "Sun4m platform, SPARCserver 600MP"; |
1481 | mc->init = ss600mp_init; | |
1482 | mc->block_default_type = IF_SCSI; | |
1483 | mc->max_cpus = 4; | |
1484 | mc->default_boot_order = "c"; | |
49cbd887 | 1485 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
fcd23a67 | 1486 | mc->default_display = "tcx"; |
b2554752 | 1487 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1488 | smc->hwdef = &sun4m_hwdefs[2]; |
e264d29d | 1489 | } |
a526a31c | 1490 | |
8a661aea AF |
1491 | static const TypeInfo ss600mp_type = { |
1492 | .name = MACHINE_TYPE_NAME("SS-600MP"), | |
828d01b7 | 1493 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1494 | .class_init = ss600mp_class_init, |
1495 | }; | |
a526a31c | 1496 | |
8a661aea | 1497 | static void ss20_class_init(ObjectClass *oc, void *data) |
e264d29d | 1498 | { |
8a661aea | 1499 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1500 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1501 | |
e264d29d EH |
1502 | mc->desc = "Sun4m platform, SPARCstation 20"; |
1503 | mc->init = ss20_init; | |
1504 | mc->block_default_type = IF_SCSI; | |
1505 | mc->max_cpus = 4; | |
1506 | mc->default_boot_order = "c"; | |
49cbd887 | 1507 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
fcd23a67 | 1508 | mc->default_display = "tcx"; |
b2554752 | 1509 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1510 | smc->hwdef = &sun4m_hwdefs[3]; |
e264d29d | 1511 | } |
a526a31c | 1512 | |
8a661aea AF |
1513 | static const TypeInfo ss20_type = { |
1514 | .name = MACHINE_TYPE_NAME("SS-20"), | |
828d01b7 | 1515 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1516 | .class_init = ss20_class_init, |
1517 | }; | |
a526a31c | 1518 | |
8a661aea | 1519 | static void voyager_class_init(ObjectClass *oc, void *data) |
e264d29d | 1520 | { |
8a661aea | 1521 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1522 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1523 | |
e264d29d EH |
1524 | mc->desc = "Sun4m platform, SPARCstation Voyager"; |
1525 | mc->init = vger_init; | |
1526 | mc->block_default_type = IF_SCSI; | |
1527 | mc->default_boot_order = "c"; | |
49cbd887 | 1528 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
fcd23a67 | 1529 | mc->default_display = "tcx"; |
b2554752 | 1530 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1531 | smc->hwdef = &sun4m_hwdefs[4]; |
e264d29d EH |
1532 | } |
1533 | ||
8a661aea AF |
1534 | static const TypeInfo voyager_type = { |
1535 | .name = MACHINE_TYPE_NAME("Voyager"), | |
828d01b7 | 1536 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1537 | .class_init = voyager_class_init, |
1538 | }; | |
e264d29d | 1539 | |
8a661aea | 1540 | static void ss_lx_class_init(ObjectClass *oc, void *data) |
e264d29d | 1541 | { |
8a661aea | 1542 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1543 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1544 | |
e264d29d EH |
1545 | mc->desc = "Sun4m platform, SPARCstation LX"; |
1546 | mc->init = ss_lx_init; | |
1547 | mc->block_default_type = IF_SCSI; | |
1548 | mc->default_boot_order = "c"; | |
49cbd887 | 1549 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
fcd23a67 | 1550 | mc->default_display = "tcx"; |
b2554752 | 1551 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1552 | smc->hwdef = &sun4m_hwdefs[5]; |
e264d29d EH |
1553 | } |
1554 | ||
8a661aea AF |
1555 | static const TypeInfo ss_lx_type = { |
1556 | .name = MACHINE_TYPE_NAME("LX"), | |
828d01b7 | 1557 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1558 | .class_init = ss_lx_class_init, |
1559 | }; | |
e264d29d | 1560 | |
8a661aea | 1561 | static void ss4_class_init(ObjectClass *oc, void *data) |
e264d29d | 1562 | { |
8a661aea | 1563 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1564 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1565 | |
e264d29d EH |
1566 | mc->desc = "Sun4m platform, SPARCstation 4"; |
1567 | mc->init = ss4_init; | |
1568 | mc->block_default_type = IF_SCSI; | |
1569 | mc->default_boot_order = "c"; | |
49cbd887 | 1570 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
fcd23a67 | 1571 | mc->default_display = "tcx"; |
b2554752 | 1572 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1573 | smc->hwdef = &sun4m_hwdefs[6]; |
e264d29d EH |
1574 | } |
1575 | ||
8a661aea AF |
1576 | static const TypeInfo ss4_type = { |
1577 | .name = MACHINE_TYPE_NAME("SS-4"), | |
828d01b7 | 1578 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1579 | .class_init = ss4_class_init, |
1580 | }; | |
e264d29d | 1581 | |
8a661aea | 1582 | static void scls_class_init(ObjectClass *oc, void *data) |
e264d29d | 1583 | { |
8a661aea | 1584 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1585 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1586 | |
e264d29d EH |
1587 | mc->desc = "Sun4m platform, SPARCClassic"; |
1588 | mc->init = scls_init; | |
1589 | mc->block_default_type = IF_SCSI; | |
1590 | mc->default_boot_order = "c"; | |
49cbd887 | 1591 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
fcd23a67 | 1592 | mc->default_display = "tcx"; |
b2554752 | 1593 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1594 | smc->hwdef = &sun4m_hwdefs[7]; |
e264d29d EH |
1595 | } |
1596 | ||
8a661aea AF |
1597 | static const TypeInfo scls_type = { |
1598 | .name = MACHINE_TYPE_NAME("SPARCClassic"), | |
828d01b7 | 1599 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1600 | .class_init = scls_class_init, |
1601 | }; | |
e264d29d | 1602 | |
8a661aea | 1603 | static void sbook_class_init(ObjectClass *oc, void *data) |
e264d29d | 1604 | { |
8a661aea | 1605 | MachineClass *mc = MACHINE_CLASS(oc); |
95bc47de | 1606 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
8a661aea | 1607 | |
e264d29d EH |
1608 | mc->desc = "Sun4m platform, SPARCbook"; |
1609 | mc->init = sbook_init; | |
1610 | mc->block_default_type = IF_SCSI; | |
1611 | mc->default_boot_order = "c"; | |
49cbd887 | 1612 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
fcd23a67 | 1613 | mc->default_display = "tcx"; |
b2554752 | 1614 | mc->default_ram_id = "sun4m.ram"; |
95bc47de | 1615 | smc->hwdef = &sun4m_hwdefs[8]; |
e264d29d EH |
1616 | } |
1617 | ||
8a661aea AF |
1618 | static const TypeInfo sbook_type = { |
1619 | .name = MACHINE_TYPE_NAME("SPARCbook"), | |
828d01b7 | 1620 | .parent = TYPE_SUN4M_MACHINE, |
8a661aea AF |
1621 | .class_init = sbook_class_init, |
1622 | }; | |
a526a31c | 1623 | |
828d01b7 PMD |
1624 | static const TypeInfo sun4m_machine_types[] = { |
1625 | { | |
1626 | .name = TYPE_SUN4M_MACHINE, | |
1627 | .parent = TYPE_MACHINE, | |
95bc47de | 1628 | .class_size = sizeof(Sun4mMachineClass), |
828d01b7 PMD |
1629 | .abstract = true, |
1630 | } | |
1631 | }; | |
1632 | ||
1633 | DEFINE_TYPES(sun4m_machine_types) | |
1634 | ||
83f7d43a AF |
1635 | static void sun4m_register_types(void) |
1636 | { | |
1637 | type_register_static(&idreg_info); | |
1638 | type_register_static(&afx_info); | |
1639 | type_register_static(&prom_info); | |
1640 | type_register_static(&ram_info); | |
83f7d43a | 1641 | |
8a661aea AF |
1642 | type_register_static(&ss5_type); |
1643 | type_register_static(&ss10_type); | |
1644 | type_register_static(&ss600mp_type); | |
1645 | type_register_static(&ss20_type); | |
1646 | type_register_static(&voyager_type); | |
1647 | type_register_static(&ss_lx_type); | |
1648 | type_register_static(&ss4_type); | |
1649 | type_register_static(&scls_type); | |
1650 | type_register_static(&sbook_type); | |
1651 | } | |
1652 | ||
83f7d43a | 1653 | type_init(sun4m_register_types) |