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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
d6454270 | 24 | |
db5ebe5f | 25 | #include "qemu/osdep.h" |
0a2e467b | 26 | #include "qemu/units.h" |
29bd7231 | 27 | #include "qemu/error-report.h" |
da34e65c | 28 | #include "qapi/error.h" |
4771d756 PB |
29 | #include "qemu-common.h" |
30 | #include "cpu.h" | |
83c9f4ca | 31 | #include "hw/pci/pci.h" |
4272ad40 | 32 | #include "hw/pci/pci_bridge.h" |
6864fa38 | 33 | #include "hw/pci/pci_bus.h" |
0ea833c2 | 34 | #include "hw/pci/pci_host.h" |
a27bd6c7 | 35 | #include "hw/qdev-properties.h" |
9b301794 | 36 | #include "hw/pci-host/sabre.h" |
0d09e41a | 37 | #include "hw/char/serial.h" |
bb3d5ea8 | 38 | #include "hw/char/parallel.h" |
819ce6b2 | 39 | #include "hw/rtc/m48t59.h" |
d6454270 | 40 | #include "migration/vmstate.h" |
47973a2d | 41 | #include "hw/input/i8042.h" |
0d09e41a | 42 | #include "hw/block/fdc.h" |
1422e32d | 43 | #include "net/net.h" |
1de7afc9 | 44 | #include "qemu/timer.h" |
54d31236 | 45 | #include "sysemu/runstate.h" |
9c17d615 | 46 | #include "sysemu/sysemu.h" |
83c9f4ca | 47 | #include "hw/boards.h" |
c6363bae | 48 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 49 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 50 | #include "hw/sparc/sparc64.h" |
0d09e41a | 51 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca | 52 | #include "hw/sysbus.h" |
6864fa38 | 53 | #include "hw/ide/pci.h" |
83c9f4ca | 54 | #include "hw/loader.h" |
0a1d5c45 | 55 | #include "hw/fw-path-provider.h" |
ca20cf32 | 56 | #include "elf.h" |
69520948 | 57 | #include "trace.h" |
3475187d | 58 | |
83469015 FB |
59 | #define KERNEL_LOAD_ADDR 0x00404000 |
60 | #define CMDLINE_ADDR 0x003ff000 | |
0a2e467b | 61 | #define PROM_SIZE_MAX (4 * MiB) |
f930d07e | 62 | #define PROM_VADDR 0x000ffd00000ULL |
5795162a MCA |
63 | #define PBM_SPECIAL_BASE 0x1fe00000000ULL |
64 | #define PBM_MEM_BASE 0x1ff00000000ULL | |
65 | #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) | |
f930d07e | 66 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 67 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 68 | #define MAX_IDE_BUS 2 |
3cce6243 | 69 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
70 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
71 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
72 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 73 | |
852e82f3 | 74 | #define IVEC_MAX 0x40 |
9d926598 | 75 | |
c7ba218d | 76 | struct hwdef { |
905fdcb5 | 77 | uint16_t machine_id; |
e87231d4 BS |
78 | uint64_t prom_addr; |
79 | uint64_t console_serial_base; | |
c7ba218d BS |
80 | }; |
81 | ||
c5e6fb7e | 82 | typedef struct EbusState { |
ad6856e8 MCA |
83 | /*< private >*/ |
84 | PCIDevice parent_obj; | |
85 | ||
8c40b8d9 | 86 | ISABus *isa_bus; |
4b10c8d7 | 87 | qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; |
0fe22ffb | 88 | uint64_t console_serial_base; |
c5e6fb7e AK |
89 | MemoryRegion bar0; |
90 | MemoryRegion bar1; | |
91 | } EbusState; | |
92 | ||
ad6856e8 MCA |
93 | #define TYPE_EBUS "ebus" |
94 | #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) | |
95 | ||
a2b45ea5 PMD |
96 | const char *fw_cfg_arch_key_name(uint16_t key) |
97 | { | |
98 | static const struct { | |
99 | uint16_t key; | |
100 | const char *name; | |
101 | } fw_cfg_arch_wellknown_keys[] = { | |
102 | {FW_CFG_SPARC64_WIDTH, "width"}, | |
103 | {FW_CFG_SPARC64_HEIGHT, "height"}, | |
104 | {FW_CFG_SPARC64_DEPTH, "depth"}, | |
105 | }; | |
106 | ||
107 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { | |
108 | if (fw_cfg_arch_wellknown_keys[i].key == key) { | |
109 | return fw_cfg_arch_wellknown_keys[i].name; | |
110 | } | |
111 | } | |
112 | return NULL; | |
113 | } | |
114 | ||
ddcd5531 GA |
115 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
116 | Error **errp) | |
81864572 | 117 | { |
48779e50 | 118 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
119 | } |
120 | ||
31688246 | 121 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
122 | const char *arch, ram_addr_t RAM_size, |
123 | const char *boot_devices, | |
124 | uint32_t kernel_image, uint32_t kernel_size, | |
125 | const char *cmdline, | |
126 | uint32_t initrd_image, uint32_t initrd_size, | |
127 | uint32_t NVRAM_image, | |
128 | int width, int height, int depth, | |
129 | const uint8_t *macaddr) | |
83469015 | 130 | { |
66508601 | 131 | unsigned int i; |
2024c014 | 132 | int sysp_end; |
d2c63fc1 | 133 | uint8_t image[0x1ff0]; |
31688246 | 134 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
135 | |
136 | memset(image, '\0', sizeof(image)); | |
137 | ||
2024c014 TH |
138 | /* OpenBIOS nvram variables partition */ |
139 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
83469015 | 140 | |
2024c014 TH |
141 | /* Free space partition */ |
142 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 143 | |
0d31cb99 BS |
144 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
145 | ||
31688246 HP |
146 | for (i = 0; i < sizeof(image); i++) { |
147 | (k->write)(nvram, i, image[i]); | |
148 | } | |
66508601 | 149 | |
83469015 | 150 | return 0; |
3475187d | 151 | } |
5f2bf0fe BS |
152 | |
153 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
154 | const char *initrd_filename, | |
155 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
156 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
157 | uint64_t *kernel_entry) | |
636aa70a BS |
158 | { |
159 | int linux_boot; | |
160 | unsigned int i; | |
161 | long kernel_size; | |
6908d9ce | 162 | uint8_t *ptr; |
3ac24188 | 163 | uint64_t kernel_top = 0; |
636aa70a BS |
164 | |
165 | linux_boot = (kernel_filename != NULL); | |
166 | ||
167 | kernel_size = 0; | |
168 | if (linux_boot) { | |
ca20cf32 BS |
169 | int bswap_needed; |
170 | ||
171 | #ifdef BSWAP_NEEDED | |
172 | bswap_needed = 1; | |
173 | #else | |
174 | bswap_needed = 0; | |
175 | #endif | |
4366e1db | 176 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, |
6cdda0ff AM |
177 | kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0, |
178 | 0); | |
5f2bf0fe BS |
179 | if (kernel_size < 0) { |
180 | *kernel_addr = KERNEL_LOAD_ADDR; | |
181 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 182 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
183 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
184 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
185 | } |
186 | if (kernel_size < 0) { | |
636aa70a BS |
187 | kernel_size = load_image_targphys(kernel_filename, |
188 | KERNEL_LOAD_ADDR, | |
189 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 190 | } |
636aa70a | 191 | if (kernel_size < 0) { |
29bd7231 | 192 | error_report("could not load kernel '%s'", kernel_filename); |
636aa70a BS |
193 | exit(1); |
194 | } | |
5f2bf0fe | 195 | /* load initrd above kernel */ |
636aa70a | 196 | *initrd_size = 0; |
3ac24188 | 197 | if (initrd_filename && kernel_top) { |
5f2bf0fe BS |
198 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
199 | ||
636aa70a | 200 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
201 | *initrd_addr, |
202 | RAM_size - *initrd_addr); | |
203 | if ((int)*initrd_size < 0) { | |
29bd7231 AF |
204 | error_report("could not load initial ram disk '%s'", |
205 | initrd_filename); | |
636aa70a BS |
206 | exit(1); |
207 | } | |
208 | } | |
209 | if (*initrd_size > 0) { | |
210 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
0f0f8b61 TH |
211 | ptr = rom_ptr(*kernel_addr + i, 32); |
212 | if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ | |
5f2bf0fe | 213 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 214 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
215 | break; |
216 | } | |
217 | } | |
218 | } | |
219 | } | |
220 | return kernel_size; | |
221 | } | |
3475187d | 222 | |
e87231d4 | 223 | typedef struct ResetData { |
403d7a2d | 224 | SPARCCPU *cpu; |
44a99354 | 225 | uint64_t prom_addr; |
e87231d4 BS |
226 | } ResetData; |
227 | ||
25c5d5ac MCA |
228 | #define TYPE_SUN4U_POWER "power" |
229 | #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) | |
230 | ||
231 | typedef struct PowerDevice { | |
232 | SysBusDevice parent_obj; | |
233 | ||
234 | MemoryRegion power_mmio; | |
235 | } PowerDevice; | |
236 | ||
237 | /* Power */ | |
ad280559 PP |
238 | static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) |
239 | { | |
240 | return 0; | |
241 | } | |
242 | ||
25c5d5ac MCA |
243 | static void power_mem_write(void *opaque, hwaddr addr, |
244 | uint64_t val, unsigned size) | |
245 | { | |
246 | /* According to a real Ultra 5, bit 24 controls the power */ | |
247 | if (val & 0x1000000) { | |
248 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | |
249 | } | |
250 | } | |
251 | ||
252 | static const MemoryRegionOps power_mem_ops = { | |
ad280559 | 253 | .read = power_mem_read, |
25c5d5ac MCA |
254 | .write = power_mem_write, |
255 | .endianness = DEVICE_NATIVE_ENDIAN, | |
256 | .valid = { | |
257 | .min_access_size = 4, | |
258 | .max_access_size = 4, | |
259 | }, | |
260 | }; | |
261 | ||
262 | static void power_realize(DeviceState *dev, Error **errp) | |
263 | { | |
264 | PowerDevice *d = SUN4U_POWER(dev); | |
265 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
266 | ||
267 | memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, | |
268 | "power", sizeof(uint32_t)); | |
269 | ||
270 | sysbus_init_mmio(sbd, &d->power_mmio); | |
271 | } | |
272 | ||
273 | static void power_class_init(ObjectClass *klass, void *data) | |
274 | { | |
275 | DeviceClass *dc = DEVICE_CLASS(klass); | |
276 | ||
277 | dc->realize = power_realize; | |
278 | } | |
279 | ||
280 | static const TypeInfo power_info = { | |
281 | .name = TYPE_SUN4U_POWER, | |
282 | .parent = TYPE_SYS_BUS_DEVICE, | |
283 | .instance_size = sizeof(PowerDevice), | |
284 | .class_init = power_class_init, | |
285 | }; | |
286 | ||
4b10c8d7 | 287 | static void ebus_isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 288 | { |
4b10c8d7 MCA |
289 | EbusState *s = EBUS(opaque); |
290 | qemu_irq irq = s->isa_bus_irqs[n]; | |
291 | ||
292 | /* Pass ISA bus IRQs onto their gpio equivalent */ | |
69520948 | 293 | trace_ebus_isa_irq_handler(n, level); |
4b10c8d7 MCA |
294 | if (irq) { |
295 | qemu_set_irq(irq, level); | |
361dea40 | 296 | } |
1387fe4a BS |
297 | } |
298 | ||
c190ea07 | 299 | /* EBUS (Eight bit bus) bridge */ |
ad6856e8 | 300 | static void ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 301 | { |
ad6856e8 | 302 | EbusState *s = EBUS(pci_dev); |
25c5d5ac | 303 | SysBusDevice *sbd; |
0fe22ffb | 304 | DeviceState *dev; |
c796edda | 305 | qemu_irq *isa_irq; |
0fe22ffb MCA |
306 | DriveInfo *fd[MAX_FD]; |
307 | int i; | |
c5e6fb7e | 308 | |
8c40b8d9 MCA |
309 | s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
310 | pci_address_space_io(pci_dev), errp); | |
311 | if (!s->isa_bus) { | |
312 | error_setg(errp, "unable to instantiate EBUS ISA bus"); | |
d10e5432 MA |
313 | return; |
314 | } | |
c5e6fb7e | 315 | |
4b10c8d7 MCA |
316 | /* ISA bus */ |
317 | isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); | |
c796edda | 318 | isa_bus_irqs(s->isa_bus, isa_irq); |
4b10c8d7 MCA |
319 | qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", |
320 | ISA_NUM_IRQS); | |
c796edda | 321 | |
0fe22ffb MCA |
322 | /* Serial ports */ |
323 | i = 0; | |
324 | if (s->console_serial_base) { | |
325 | serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, | |
9bca0edb | 326 | 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); |
0fe22ffb MCA |
327 | i++; |
328 | } | |
def337ff | 329 | serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); |
0fe22ffb MCA |
330 | |
331 | /* Parallel ports */ | |
332 | parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); | |
333 | ||
334 | /* Keyboard */ | |
335 | isa_create_simple(s->isa_bus, "i8042"); | |
336 | ||
337 | /* Floppy */ | |
338 | for (i = 0; i < MAX_FD; i++) { | |
339 | fd[i] = drive_get(IF_FLOPPY, 0, i); | |
340 | } | |
341 | dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); | |
342 | if (fd[0]) { | |
343 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
344 | &error_abort); | |
345 | } | |
346 | if (fd[1]) { | |
347 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
348 | &error_abort); | |
349 | } | |
350 | qdev_prop_set_uint32(dev, "dma", -1); | |
351 | qdev_init_nofail(dev); | |
352 | ||
25c5d5ac MCA |
353 | /* Power */ |
354 | dev = qdev_create(NULL, TYPE_SUN4U_POWER); | |
355 | qdev_init_nofail(dev); | |
356 | sbd = SYS_BUS_DEVICE(dev); | |
357 | memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, | |
358 | sysbus_mmio_get_region(sbd, 0)); | |
359 | ||
0fe22ffb | 360 | /* PCI */ |
c5e6fb7e AK |
361 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
362 | pci_dev->config[0x05] = 0x00; | |
363 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
364 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
365 | pci_dev->config[0x09] = 0x00; // programming i/f | |
366 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
367 | ||
0a70e094 PB |
368 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
369 | 0, 0x1000000); | |
e824b2cc | 370 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 371 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
25c5d5ac | 372 | 0, 0x8000); |
a1cf8be5 | 373 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
374 | } |
375 | ||
0fe22ffb MCA |
376 | static Property ebus_properties[] = { |
377 | DEFINE_PROP_UINT64("console-serial-base", EbusState, | |
378 | console_serial_base, 0), | |
379 | DEFINE_PROP_END_OF_LIST(), | |
380 | }; | |
381 | ||
40021f08 AL |
382 | static void ebus_class_init(ObjectClass *klass, void *data) |
383 | { | |
384 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
0fe22ffb | 385 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 386 | |
ad6856e8 | 387 | k->realize = ebus_realize; |
40021f08 AL |
388 | k->vendor_id = PCI_VENDOR_ID_SUN; |
389 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
390 | k->revision = 0x01; | |
391 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
4f67d30b | 392 | device_class_set_props(dc, ebus_properties); |
40021f08 AL |
393 | } |
394 | ||
8c43a6f0 | 395 | static const TypeInfo ebus_info = { |
ad6856e8 | 396 | .name = TYPE_EBUS, |
39bffca2 | 397 | .parent = TYPE_PCI_DEVICE, |
39bffca2 | 398 | .class_init = ebus_class_init, |
ad6856e8 | 399 | .instance_size = sizeof(EbusState), |
fd3b02c8 EH |
400 | .interfaces = (InterfaceInfo[]) { |
401 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
402 | { }, | |
403 | }, | |
53e3c4f9 BS |
404 | }; |
405 | ||
13575cf6 AF |
406 | #define TYPE_OPENPROM "openprom" |
407 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
408 | ||
d4edce38 | 409 | typedef struct PROMState { |
13575cf6 AF |
410 | SysBusDevice parent_obj; |
411 | ||
d4edce38 AK |
412 | MemoryRegion prom; |
413 | } PROMState; | |
414 | ||
409dbce5 AJ |
415 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
416 | { | |
a8170e5e | 417 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
418 | return addr + *base_addr - PROM_VADDR; |
419 | } | |
420 | ||
1baffa46 | 421 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 422 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
423 | { |
424 | DeviceState *dev; | |
425 | SysBusDevice *s; | |
426 | char *filename; | |
427 | int ret; | |
428 | ||
13575cf6 | 429 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 430 | qdev_init_nofail(dev); |
1356b98d | 431 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
432 | |
433 | sysbus_mmio_map(s, 0, addr); | |
434 | ||
435 | /* load boot prom */ | |
436 | if (bios_name == NULL) { | |
437 | bios_name = PROM_FILENAME; | |
438 | } | |
439 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
440 | if (filename) { | |
4366e1db | 441 | ret = load_elf(filename, NULL, translate_prom_address, &addr, |
6cdda0ff | 442 | NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
443 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
444 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
445 | } | |
7267c094 | 446 | g_free(filename); |
1baffa46 BS |
447 | } else { |
448 | ret = -1; | |
449 | } | |
450 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 451 | error_report("could not load prom '%s'", bios_name); |
1baffa46 BS |
452 | exit(1); |
453 | } | |
454 | } | |
455 | ||
92b19880 | 456 | static void prom_realize(DeviceState *ds, Error **errp) |
1baffa46 | 457 | { |
92b19880 TH |
458 | PROMState *s = OPENPROM(ds); |
459 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
460 | Error *local_err = NULL; | |
461 | ||
462 | memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", | |
463 | PROM_SIZE_MAX, &local_err); | |
464 | if (local_err) { | |
465 | error_propagate(errp, local_err); | |
466 | return; | |
467 | } | |
1baffa46 | 468 | |
c5705a77 | 469 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 470 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 471 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
472 | } |
473 | ||
999e12bb AL |
474 | static Property prom_properties[] = { |
475 | {/* end of property list */}, | |
476 | }; | |
477 | ||
478 | static void prom_class_init(ObjectClass *klass, void *data) | |
479 | { | |
39bffca2 | 480 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 481 | |
4f67d30b | 482 | device_class_set_props(dc, prom_properties); |
92b19880 | 483 | dc->realize = prom_realize; |
999e12bb AL |
484 | } |
485 | ||
8c43a6f0 | 486 | static const TypeInfo prom_info = { |
13575cf6 | 487 | .name = TYPE_OPENPROM, |
39bffca2 AL |
488 | .parent = TYPE_SYS_BUS_DEVICE, |
489 | .instance_size = sizeof(PROMState), | |
490 | .class_init = prom_class_init, | |
1baffa46 BS |
491 | }; |
492 | ||
bda42033 | 493 | |
88c034d5 AF |
494 | #define TYPE_SUN4U_MEMORY "memory" |
495 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
496 | ||
497 | typedef struct RamDevice { | |
498 | SysBusDevice parent_obj; | |
499 | ||
d4edce38 | 500 | MemoryRegion ram; |
04843626 | 501 | uint64_t size; |
bda42033 BS |
502 | } RamDevice; |
503 | ||
504 | /* System RAM */ | |
78fb261d | 505 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 506 | { |
88c034d5 | 507 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 508 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 509 | |
1cfe48c1 | 510 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 511 | &error_fatal); |
c5705a77 | 512 | vmstate_register_ram_global(&d->ram); |
78fb261d | 513 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
514 | } |
515 | ||
a8170e5e | 516 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
517 | { |
518 | DeviceState *dev; | |
519 | SysBusDevice *s; | |
520 | RamDevice *d; | |
521 | ||
522 | /* allocate RAM */ | |
88c034d5 | 523 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 524 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 525 | |
88c034d5 | 526 | d = SUN4U_RAM(dev); |
bda42033 | 527 | d->size = RAM_size; |
e23a1b33 | 528 | qdev_init_nofail(dev); |
bda42033 BS |
529 | |
530 | sysbus_mmio_map(s, 0, addr); | |
531 | } | |
532 | ||
999e12bb AL |
533 | static Property ram_properties[] = { |
534 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
535 | DEFINE_PROP_END_OF_LIST(), | |
536 | }; | |
537 | ||
538 | static void ram_class_init(ObjectClass *klass, void *data) | |
539 | { | |
39bffca2 | 540 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 541 | |
78fb261d | 542 | dc->realize = ram_realize; |
4f67d30b | 543 | device_class_set_props(dc, ram_properties); |
999e12bb AL |
544 | } |
545 | ||
8c43a6f0 | 546 | static const TypeInfo ram_info = { |
88c034d5 | 547 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
548 | .parent = TYPE_SYS_BUS_DEVICE, |
549 | .instance_size = sizeof(RamDevice), | |
550 | .class_init = ram_class_init, | |
bda42033 BS |
551 | }; |
552 | ||
38bc50f7 | 553 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 554 | MachineState *machine, |
7b833f5b BS |
555 | const struct hwdef *hwdef) |
556 | { | |
f9d1465f | 557 | SPARCCPU *cpu; |
31688246 | 558 | Nvram *nvram; |
7b833f5b | 559 | unsigned int i; |
5f2bf0fe | 560 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
5795162a | 561 | SabreState *sabre; |
311f2b7a | 562 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 563 | PCIDevice *ebus, *pci_dev; |
f3b18f35 | 564 | SysBusDevice *s; |
aea5b071 | 565 | DeviceState *iommu, *dev; |
a88b362c | 566 | FWCfgState *fw_cfg; |
8d932971 | 567 | NICInfo *nd; |
6864fa38 MCA |
568 | MACAddr macaddr; |
569 | bool onboard_nic; | |
7b833f5b | 570 | |
7b833f5b | 571 | /* init CPUs */ |
58530461 | 572 | cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); |
7b833f5b | 573 | |
aea5b071 MCA |
574 | /* IOMMU */ |
575 | iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); | |
576 | qdev_init_nofail(iommu); | |
577 | ||
bda42033 | 578 | /* set up devices */ |
3ef96221 | 579 | ram_init(0, machine->ram_size); |
3475187d | 580 | |
1baffa46 | 581 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 582 | |
b14dcaf4 | 583 | /* Init sabre (PCI host bridge) */ |
5795162a MCA |
584 | sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); |
585 | qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); | |
586 | qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); | |
587 | object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", | |
588 | &error_abort); | |
589 | qdev_init_nofail(DEVICE(sabre)); | |
2a4d6af5 MCA |
590 | |
591 | /* Wire up PCI interrupts to CPU */ | |
592 | for (i = 0; i < IVEC_MAX; i++) { | |
5795162a | 593 | qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, |
2a4d6af5 MCA |
594 | qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); |
595 | } | |
596 | ||
5795162a MCA |
597 | pci_bus = PCI_HOST_BRIDGE(sabre)->bus; |
598 | pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); | |
599 | pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); | |
83469015 | 600 | |
5795162a | 601 | /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is |
6864fa38 MCA |
602 | reserved (leaving no slots free after on-board devices) however slots |
603 | 0-3 are free on busB */ | |
604 | pci_bus->slot_reserved_mask = 0xfffffffc; | |
605 | pci_busA->slot_reserved_mask = 0xfffffff1; | |
606 | pci_busB->slot_reserved_mask = 0xfffffff0; | |
607 | ||
ad6856e8 | 608 | ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); |
0fe22ffb MCA |
609 | qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", |
610 | hwdef->console_serial_base); | |
6864fa38 MCA |
611 | qdev_init_nofail(DEVICE(ebus)); |
612 | ||
5795162a | 613 | /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ |
4b10c8d7 | 614 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, |
5795162a | 615 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); |
4b10c8d7 | 616 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, |
5795162a | 617 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); |
4b10c8d7 | 618 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, |
5795162a | 619 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); |
4b10c8d7 | 620 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, |
5795162a | 621 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); |
4b10c8d7 | 622 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, |
5795162a | 623 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); |
4b10c8d7 | 624 | |
c3019efc TH |
625 | switch (vga_interface_type) { |
626 | case VGA_STD: | |
627 | pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); | |
628 | break; | |
629 | case VGA_NONE: | |
630 | break; | |
631 | default: | |
632 | abort(); /* Should not happen - types are checked in vl.c already */ | |
633 | } | |
6864fa38 MCA |
634 | |
635 | memset(&macaddr, 0, sizeof(MACAddr)); | |
636 | onboard_nic = false; | |
8d932971 MCA |
637 | for (i = 0; i < nb_nics; i++) { |
638 | nd = &nd_table[i]; | |
639 | ||
6864fa38 MCA |
640 | if (!nd->model || strcmp(nd->model, "sunhme") == 0) { |
641 | if (!onboard_nic) { | |
642 | pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), | |
643 | true, "sunhme"); | |
644 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); | |
645 | onboard_nic = true; | |
646 | } else { | |
bcf9e2c2 | 647 | pci_dev = pci_create(pci_busB, -1, "sunhme"); |
6864fa38 | 648 | } |
8d932971 | 649 | } else { |
bcf9e2c2 | 650 | pci_dev = pci_create(pci_busB, -1, nd->model); |
8d932971 | 651 | } |
6864fa38 MCA |
652 | |
653 | dev = &pci_dev->qdev; | |
654 | qdev_set_nic_properties(dev, nd); | |
655 | qdev_init_nofail(dev); | |
656 | } | |
657 | ||
658 | /* If we don't have an onboard NIC, grab a default MAC address so that | |
659 | * we have a valid machine id */ | |
660 | if (!onboard_nic) { | |
661 | qemu_macaddr_default_if_unset(&macaddr); | |
8d932971 | 662 | } |
83469015 | 663 | |
6864fa38 MCA |
664 | pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); |
665 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); | |
666 | qdev_init_nofail(&pci_dev->qdev); | |
be1765f3 | 667 | pci_ide_create_devs(pci_dev); |
3b898dda | 668 | |
f3b18f35 MCA |
669 | /* Map NVRAM into I/O (ebus) space */ |
670 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
671 | s = SYS_BUS_DEVICE(nvram); | |
07c84741 | 672 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 MCA |
673 | sysbus_mmio_get_region(s, 0)); |
674 | ||
636aa70a | 675 | initrd_size = 0; |
5f2bf0fe | 676 | initrd_addr = 0; |
3ef96221 MA |
677 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
678 | machine->initrd_filename, | |
5f2bf0fe BS |
679 | ram_size, &initrd_size, &initrd_addr, |
680 | &kernel_addr, &kernel_entry); | |
636aa70a | 681 | |
3ef96221 MA |
682 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
683 | machine->boot_order, | |
5f2bf0fe | 684 | kernel_addr, kernel_size, |
3ef96221 | 685 | machine->kernel_cmdline, |
5f2bf0fe | 686 | initrd_addr, initrd_size, |
0d31cb99 BS |
687 | /* XXX: need an option to load a NVRAM image */ |
688 | 0, | |
689 | graphic_width, graphic_height, graphic_depth, | |
6864fa38 | 690 | (uint8_t *)&macaddr); |
83469015 | 691 | |
d6acc8a5 MCA |
692 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
693 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
d2623129 | 694 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); |
d6acc8a5 | 695 | qdev_init_nofail(dev); |
07c84741 | 696 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
697 | &FW_CFG_IO(dev)->comb_iomem); |
698 | ||
699 | fw_cfg = FW_CFG(dev); | |
33decbd2 LX |
700 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); |
701 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); | |
905fdcb5 BS |
702 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
703 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
704 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
705 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 706 | if (machine->kernel_cmdline) { |
9c9b0512 | 707 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
708 | strlen(machine->kernel_cmdline) + 1); |
709 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 710 | } else { |
9c9b0512 | 711 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 712 | } |
5f2bf0fe BS |
713 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
714 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 715 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
716 | |
717 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
718 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
719 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
720 | ||
513f789f | 721 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
722 | } |
723 | ||
905fdcb5 BS |
724 | enum { |
725 | sun4u_id = 0, | |
726 | sun4v_id = 64, | |
727 | }; | |
728 | ||
0a1d5c45 MCA |
729 | /* |
730 | * Implementation of an interface to adjust firmware path | |
731 | * for the bootindex property handling. | |
732 | */ | |
733 | static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, | |
734 | DeviceState *dev) | |
735 | { | |
736 | PCIDevice *pci; | |
737 | IDEBus *ide_bus; | |
738 | IDEState *ide_s; | |
739 | int bus_id; | |
740 | ||
741 | if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { | |
742 | pci = PCI_DEVICE(dev); | |
743 | ||
744 | if (PCI_FUNC(pci->devfn)) { | |
745 | return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), | |
746 | PCI_FUNC(pci->devfn)); | |
747 | } else { | |
748 | return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); | |
749 | } | |
750 | } | |
751 | ||
752 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { | |
753 | ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); | |
754 | ide_s = idebus_active_if(ide_bus); | |
755 | bus_id = ide_bus->bus_id; | |
756 | ||
757 | if (ide_s->drive_kind == IDE_CD) { | |
758 | return g_strdup_printf("ide@%x/cdrom", bus_id); | |
759 | } | |
760 | ||
761 | return g_strdup_printf("ide@%x/disk", bus_id); | |
762 | } | |
763 | ||
764 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { | |
765 | return g_strdup("disk"); | |
766 | } | |
767 | ||
768 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { | |
769 | return g_strdup("cdrom"); | |
770 | } | |
771 | ||
772 | if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { | |
773 | return g_strdup("disk"); | |
774 | } | |
775 | ||
776 | return NULL; | |
777 | } | |
778 | ||
c7ba218d BS |
779 | static const struct hwdef hwdefs[] = { |
780 | /* Sun4u generic PC-like machine */ | |
781 | { | |
905fdcb5 | 782 | .machine_id = sun4u_id, |
e87231d4 BS |
783 | .prom_addr = 0x1fff0000000ULL, |
784 | .console_serial_base = 0, | |
c7ba218d BS |
785 | }, |
786 | /* Sun4v generic PC-like machine */ | |
787 | { | |
905fdcb5 | 788 | .machine_id = sun4v_id, |
e87231d4 BS |
789 | .prom_addr = 0x1fff0000000ULL, |
790 | .console_serial_base = 0, | |
791 | }, | |
c7ba218d BS |
792 | }; |
793 | ||
794 | /* Sun4u hardware initialisation */ | |
3ef96221 | 795 | static void sun4u_init(MachineState *machine) |
5f072e1f | 796 | { |
3ef96221 | 797 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
798 | } |
799 | ||
800 | /* Sun4v hardware initialisation */ | |
3ef96221 | 801 | static void sun4v_init(MachineState *machine) |
5f072e1f | 802 | { |
3ef96221 | 803 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
804 | } |
805 | ||
8a661aea | 806 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 807 | { |
8a661aea | 808 | MachineClass *mc = MACHINE_CLASS(oc); |
0a1d5c45 | 809 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
8a661aea | 810 | |
e264d29d EH |
811 | mc->desc = "Sun4u platform"; |
812 | mc->init = sun4u_init; | |
2059839b | 813 | mc->block_default_type = IF_IDE; |
e264d29d | 814 | mc->max_cpus = 1; /* XXX for now */ |
ea0ac7f6 | 815 | mc->is_default = true; |
e264d29d | 816 | mc->default_boot_order = "c"; |
58530461 | 817 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); |
0a1d5c45 | 818 | mc->ignore_boot_device_suffixes = true; |
9aed808e | 819 | mc->default_display = "std"; |
0a1d5c45 | 820 | fwc->get_dev_path = sun4u_fw_dev_path; |
e264d29d | 821 | } |
c7ba218d | 822 | |
8a661aea AF |
823 | static const TypeInfo sun4u_type = { |
824 | .name = MACHINE_TYPE_NAME("sun4u"), | |
825 | .parent = TYPE_MACHINE, | |
826 | .class_init = sun4u_class_init, | |
0a1d5c45 MCA |
827 | .interfaces = (InterfaceInfo[]) { |
828 | { TYPE_FW_PATH_PROVIDER }, | |
829 | { } | |
830 | }, | |
8a661aea | 831 | }; |
e87231d4 | 832 | |
8a661aea | 833 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 834 | { |
8a661aea AF |
835 | MachineClass *mc = MACHINE_CLASS(oc); |
836 | ||
e264d29d EH |
837 | mc->desc = "Sun4v platform"; |
838 | mc->init = sun4v_init; | |
2059839b | 839 | mc->block_default_type = IF_IDE; |
e264d29d EH |
840 | mc->max_cpus = 1; /* XXX for now */ |
841 | mc->default_boot_order = "c"; | |
58530461 | 842 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); |
9aed808e | 843 | mc->default_display = "std"; |
e264d29d EH |
844 | } |
845 | ||
8a661aea AF |
846 | static const TypeInfo sun4v_type = { |
847 | .name = MACHINE_TYPE_NAME("sun4v"), | |
848 | .parent = TYPE_MACHINE, | |
849 | .class_init = sun4v_class_init, | |
850 | }; | |
e264d29d | 851 | |
83f7d43a AF |
852 | static void sun4u_register_types(void) |
853 | { | |
25c5d5ac | 854 | type_register_static(&power_info); |
83f7d43a AF |
855 | type_register_static(&ebus_info); |
856 | type_register_static(&prom_info); | |
857 | type_register_static(&ram_info); | |
83f7d43a | 858 | |
8a661aea AF |
859 | type_register_static(&sun4u_type); |
860 | type_register_static(&sun4v_type); | |
8a661aea AF |
861 | } |
862 | ||
83f7d43a | 863 | type_init(sun4u_register_types) |