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7c1c69bc CLG |
1 | /* |
2 | * ASPEED AST2400 SMC Controller (SPI Flash Only) | |
3 | * | |
4 | * Copyright (C) 2016 IBM Corp. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
26 | #include "hw/sysbus.h" | |
27 | #include "sysemu/sysemu.h" | |
28 | #include "qemu/log.h" | |
29 | #include "include/qemu/error-report.h" | |
30 | #include "exec/address-spaces.h" | |
31 | ||
32 | #include "hw/ssi/aspeed_smc.h" | |
33 | ||
34 | /* CE Type Setting Register */ | |
35 | #define R_CONF (0x00 / 4) | |
36 | #define CONF_LEGACY_DISABLE (1 << 31) | |
37 | #define CONF_ENABLE_W4 20 | |
38 | #define CONF_ENABLE_W3 19 | |
39 | #define CONF_ENABLE_W2 18 | |
40 | #define CONF_ENABLE_W1 17 | |
41 | #define CONF_ENABLE_W0 16 | |
0707b34d CLG |
42 | #define CONF_FLASH_TYPE4 8 |
43 | #define CONF_FLASH_TYPE3 6 | |
44 | #define CONF_FLASH_TYPE2 4 | |
45 | #define CONF_FLASH_TYPE1 2 | |
46 | #define CONF_FLASH_TYPE0 0 | |
47 | #define CONF_FLASH_TYPE_NOR 0x0 | |
48 | #define CONF_FLASH_TYPE_NAND 0x1 | |
49 | #define CONF_FLASH_TYPE_SPI 0x2 | |
7c1c69bc CLG |
50 | |
51 | /* CE Control Register */ | |
52 | #define R_CE_CTRL (0x04 / 4) | |
53 | #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ | |
54 | #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ | |
55 | #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ | |
56 | #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ | |
57 | #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ | |
58 | ||
59 | /* Interrupt Control and Status Register */ | |
60 | #define R_INTR_CTRL (0x08 / 4) | |
61 | #define INTR_CTRL_DMA_STATUS (1 << 11) | |
62 | #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) | |
63 | #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) | |
64 | #define INTR_CTRL_DMA_EN (1 << 3) | |
65 | #define INTR_CTRL_CMD_ABORT_EN (1 << 2) | |
66 | #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) | |
67 | ||
68 | /* CEx Control Register */ | |
69 | #define R_CTRL0 (0x10 / 4) | |
70 | #define CTRL_CMD_SHIFT 16 | |
71 | #define CTRL_CMD_MASK 0xff | |
72 | #define CTRL_CE_STOP_ACTIVE (1 << 2) | |
73 | #define CTRL_CMD_MODE_MASK 0x3 | |
74 | #define CTRL_READMODE 0x0 | |
75 | #define CTRL_FREADMODE 0x1 | |
76 | #define CTRL_WRITEMODE 0x2 | |
77 | #define CTRL_USERMODE 0x3 | |
78 | #define R_CTRL1 (0x14 / 4) | |
79 | #define R_CTRL2 (0x18 / 4) | |
80 | #define R_CTRL3 (0x1C / 4) | |
81 | #define R_CTRL4 (0x20 / 4) | |
82 | ||
83 | /* CEx Segment Address Register */ | |
84 | #define R_SEG_ADDR0 (0x30 / 4) | |
a03cb1da CLG |
85 | #define SEG_END_SHIFT 24 /* 8MB units */ |
86 | #define SEG_END_MASK 0xff | |
7c1c69bc | 87 | #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ |
a03cb1da | 88 | #define SEG_START_MASK 0xff |
7c1c69bc CLG |
89 | #define R_SEG_ADDR1 (0x34 / 4) |
90 | #define R_SEG_ADDR2 (0x38 / 4) | |
91 | #define R_SEG_ADDR3 (0x3C / 4) | |
92 | #define R_SEG_ADDR4 (0x40 / 4) | |
93 | ||
94 | /* Misc Control Register #1 */ | |
95 | #define R_MISC_CTRL1 (0x50 / 4) | |
96 | ||
97 | /* Misc Control Register #2 */ | |
98 | #define R_MISC_CTRL2 (0x54 / 4) | |
99 | ||
100 | /* DMA Control/Status Register */ | |
101 | #define R_DMA_CTRL (0x80 / 4) | |
102 | #define DMA_CTRL_DELAY_MASK 0xf | |
103 | #define DMA_CTRL_DELAY_SHIFT 8 | |
104 | #define DMA_CTRL_FREQ_MASK 0xf | |
105 | #define DMA_CTRL_FREQ_SHIFT 4 | |
106 | #define DMA_CTRL_MODE (1 << 3) | |
107 | #define DMA_CTRL_CKSUM (1 << 2) | |
108 | #define DMA_CTRL_DIR (1 << 1) | |
109 | #define DMA_CTRL_EN (1 << 0) | |
110 | ||
111 | /* DMA Flash Side Address */ | |
112 | #define R_DMA_FLASH_ADDR (0x84 / 4) | |
113 | ||
114 | /* DMA DRAM Side Address */ | |
115 | #define R_DMA_DRAM_ADDR (0x88 / 4) | |
116 | ||
117 | /* DMA Length Register */ | |
118 | #define R_DMA_LEN (0x8C / 4) | |
119 | ||
120 | /* Checksum Calculation Result */ | |
121 | #define R_DMA_CHECKSUM (0x90 / 4) | |
122 | ||
123 | /* Misc Control Register #2 */ | |
124 | #define R_TIMINGS (0x94 / 4) | |
125 | ||
126 | /* SPI controller registers and bits */ | |
127 | #define R_SPI_CONF (0x00 / 4) | |
128 | #define SPI_CONF_ENABLE_W0 0 | |
129 | #define R_SPI_CTRL0 (0x4 / 4) | |
130 | #define R_SPI_MISC_CTRL (0x10 / 4) | |
131 | #define R_SPI_TIMINGS (0x14 / 4) | |
132 | ||
dcb83444 CLG |
133 | #define ASPEED_SOC_SMC_FLASH_BASE 0x10000000 |
134 | #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000 | |
135 | #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 | |
6dc52326 | 136 | #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000 |
dcb83444 | 137 | |
924ed163 CLG |
138 | /* |
139 | * Default segments mapping addresses and size for each slave per | |
140 | * controller. These can be changed when board is initialized with the | |
a03cb1da | 141 | * Segment Address Registers. |
924ed163 CLG |
142 | */ |
143 | static const AspeedSegments aspeed_segments_legacy[] = { | |
144 | { 0x10000000, 32 * 1024 * 1024 }, | |
145 | }; | |
146 | ||
147 | static const AspeedSegments aspeed_segments_fmc[] = { | |
6dc52326 | 148 | { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */ |
924ed163 CLG |
149 | { 0x24000000, 32 * 1024 * 1024 }, |
150 | { 0x26000000, 32 * 1024 * 1024 }, | |
151 | { 0x28000000, 32 * 1024 * 1024 }, | |
152 | { 0x2A000000, 32 * 1024 * 1024 } | |
153 | }; | |
154 | ||
155 | static const AspeedSegments aspeed_segments_spi[] = { | |
156 | { 0x30000000, 64 * 1024 * 1024 }, | |
157 | }; | |
158 | ||
6dc52326 CLG |
159 | static const AspeedSegments aspeed_segments_ast2500_fmc[] = { |
160 | { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */ | |
161 | { 0x28000000, 32 * 1024 * 1024 }, | |
162 | { 0x2A000000, 32 * 1024 * 1024 }, | |
163 | }; | |
164 | ||
165 | static const AspeedSegments aspeed_segments_ast2500_spi1[] = { | |
166 | { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */ | |
167 | { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */ | |
168 | }; | |
169 | ||
170 | static const AspeedSegments aspeed_segments_ast2500_spi2[] = { | |
171 | { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */ | |
172 | { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */ | |
173 | }; | |
174 | ||
7c1c69bc CLG |
175 | static const AspeedSMCController controllers[] = { |
176 | { "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, | |
dcb83444 CLG |
177 | CONF_ENABLE_W0, 5, aspeed_segments_legacy, |
178 | ASPEED_SOC_SMC_FLASH_BASE, 0x6000000 }, | |
7c1c69bc | 179 | { "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, |
dcb83444 CLG |
180 | CONF_ENABLE_W0, 5, aspeed_segments_fmc, |
181 | ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 }, | |
7c1c69bc | 182 | { "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS, |
dcb83444 CLG |
183 | SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, |
184 | ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 }, | |
6dc52326 CLG |
185 | { "aspeed.smc.ast2500-fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, |
186 | CONF_ENABLE_W0, 3, aspeed_segments_ast2500_fmc, | |
187 | ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 }, | |
188 | { "aspeed.smc.ast2500-spi1", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, | |
189 | CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi1, | |
190 | ASPEED_SOC_SPI_FLASH_BASE, 0x8000000 }, | |
191 | { "aspeed.smc.ast2500-spi2", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, | |
192 | CONF_ENABLE_W0, 2, aspeed_segments_ast2500_spi2, | |
193 | ASPEED_SOC_SPI2_FLASH_BASE, 0x8000000 }, | |
924ed163 CLG |
194 | }; |
195 | ||
a03cb1da CLG |
196 | /* |
197 | * The Segment Register uses a 8MB unit to encode the start address | |
198 | * and the end address of the mapping window of a flash SPI slave : | |
199 | * | |
200 | * | byte 1 | byte 2 | byte 3 | byte 4 | | |
201 | * +--------+--------+--------+--------+ | |
202 | * | end | start | 0 | 0 | | |
203 | * | |
204 | */ | |
205 | static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg) | |
206 | { | |
207 | uint32_t reg = 0; | |
208 | reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; | |
209 | reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; | |
210 | return reg; | |
211 | } | |
212 | ||
213 | static inline void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg) | |
214 | { | |
215 | seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; | |
216 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; | |
217 | } | |
218 | ||
219 | static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, | |
220 | const AspeedSegments *new, | |
221 | int cs) | |
222 | { | |
223 | AspeedSegments seg; | |
224 | int i; | |
225 | ||
226 | for (i = 0; i < s->ctrl->max_slaves; i++) { | |
227 | if (i == cs) { | |
228 | continue; | |
229 | } | |
230 | ||
231 | aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + i], &seg); | |
232 | ||
233 | if (new->addr + new->size > seg.addr && | |
234 | new->addr < seg.addr + seg.size) { | |
235 | qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment CS%d [ 0x%" | |
236 | HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " | |
237 | "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", | |
238 | s->ctrl->name, cs, new->addr, new->addr + new->size, | |
239 | i, seg.addr, seg.addr + seg.size); | |
240 | return true; | |
241 | } | |
242 | } | |
243 | return false; | |
244 | } | |
245 | ||
246 | static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, | |
247 | uint64_t new) | |
248 | { | |
249 | AspeedSMCFlash *fl = &s->flashes[cs]; | |
250 | AspeedSegments seg; | |
251 | ||
252 | aspeed_smc_reg_to_segment(new, &seg); | |
253 | ||
254 | /* The start address of CS0 is read-only */ | |
255 | if (cs == 0 && seg.addr != s->ctrl->flash_window_base) { | |
256 | qemu_log_mask(LOG_GUEST_ERROR, | |
257 | "%s: Tried to change CS0 start address to 0x%" | |
258 | HWADDR_PRIx "\n", s->ctrl->name, seg.addr); | |
0584d3c3 CLG |
259 | seg.addr = s->ctrl->flash_window_base; |
260 | new = aspeed_smc_segment_to_reg(&seg); | |
a03cb1da CLG |
261 | } |
262 | ||
263 | /* | |
264 | * The end address of the AST2500 spi controllers is also | |
265 | * read-only. | |
266 | */ | |
267 | if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 || | |
268 | s->ctrl->segments == aspeed_segments_ast2500_spi2) && | |
269 | cs == s->ctrl->max_slaves && | |
270 | seg.addr + seg.size != s->ctrl->segments[cs].addr + | |
271 | s->ctrl->segments[cs].size) { | |
272 | qemu_log_mask(LOG_GUEST_ERROR, | |
273 | "%s: Tried to change CS%d end address to 0x%" | |
0584d3c3 CLG |
274 | HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size); |
275 | seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size - | |
276 | seg.addr; | |
277 | new = aspeed_smc_segment_to_reg(&seg); | |
a03cb1da CLG |
278 | } |
279 | ||
280 | /* Keep the segment in the overall flash window */ | |
281 | if (seg.addr + seg.size <= s->ctrl->flash_window_base || | |
282 | seg.addr > s->ctrl->flash_window_base + s->ctrl->flash_window_size) { | |
283 | qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is invalid : " | |
284 | "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", | |
285 | s->ctrl->name, cs, seg.addr, seg.addr + seg.size); | |
286 | return; | |
287 | } | |
288 | ||
289 | /* Check start address vs. alignment */ | |
0584d3c3 | 290 | if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { |
a03cb1da CLG |
291 | qemu_log_mask(LOG_GUEST_ERROR, "%s: new segment for CS%d is not " |
292 | "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", | |
293 | s->ctrl->name, cs, seg.addr, seg.addr + seg.size); | |
294 | } | |
295 | ||
0584d3c3 CLG |
296 | /* And segments should not overlap (in the specs) */ |
297 | aspeed_smc_flash_overlap(s, &seg, cs); | |
a03cb1da CLG |
298 | |
299 | /* All should be fine now to move the region */ | |
300 | memory_region_transaction_begin(); | |
301 | memory_region_set_size(&fl->mmio, seg.size); | |
302 | memory_region_set_address(&fl->mmio, seg.addr - s->ctrl->flash_window_base); | |
303 | memory_region_set_enabled(&fl->mmio, true); | |
304 | memory_region_transaction_commit(); | |
305 | ||
306 | s->regs[R_SEG_ADDR0 + cs] = new; | |
307 | } | |
308 | ||
924ed163 CLG |
309 | static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, |
310 | unsigned size) | |
311 | { | |
312 | qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u" | |
313 | PRIx64 "\n", __func__, addr, size); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, | |
318 | uint64_t data, unsigned size) | |
319 | { | |
320 | qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%" | |
321 | PRIx64 "\n", __func__, addr, size, data); | |
322 | } | |
323 | ||
324 | static const MemoryRegionOps aspeed_smc_flash_default_ops = { | |
325 | .read = aspeed_smc_flash_default_read, | |
326 | .write = aspeed_smc_flash_default_write, | |
327 | .endianness = DEVICE_LITTLE_ENDIAN, | |
328 | .valid = { | |
329 | .min_access_size = 1, | |
330 | .max_access_size = 4, | |
331 | }, | |
332 | }; | |
333 | ||
f248a9db | 334 | static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl) |
924ed163 | 335 | { |
f248a9db CLG |
336 | const AspeedSMCState *s = fl->controller; |
337 | ||
338 | return s->regs[s->r_ctrl0 + fl->id] & CTRL_CMD_MODE_MASK; | |
924ed163 CLG |
339 | } |
340 | ||
f248a9db | 341 | static inline bool aspeed_smc_is_usermode(const AspeedSMCFlash *fl) |
924ed163 | 342 | { |
f248a9db | 343 | return aspeed_smc_flash_mode(fl) == CTRL_USERMODE; |
924ed163 CLG |
344 | } |
345 | ||
f248a9db | 346 | static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl) |
924ed163 | 347 | { |
f248a9db CLG |
348 | const AspeedSMCState *s = fl->controller; |
349 | ||
350 | return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->id)); | |
924ed163 CLG |
351 | } |
352 | ||
353 | static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) | |
354 | { | |
355 | AspeedSMCFlash *fl = opaque; | |
356 | const AspeedSMCState *s = fl->controller; | |
357 | uint64_t ret = 0; | |
358 | int i; | |
359 | ||
f248a9db | 360 | if (aspeed_smc_is_usermode(fl)) { |
924ed163 CLG |
361 | for (i = 0; i < size; i++) { |
362 | ret |= ssi_transfer(s->spi, 0x0) << (8 * i); | |
363 | } | |
364 | } else { | |
365 | qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n", | |
366 | __func__); | |
367 | ret = -1; | |
368 | } | |
369 | ||
370 | return ret; | |
371 | } | |
372 | ||
373 | static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, | |
374 | unsigned size) | |
375 | { | |
376 | AspeedSMCFlash *fl = opaque; | |
377 | const AspeedSMCState *s = fl->controller; | |
378 | int i; | |
379 | ||
f248a9db | 380 | if (!aspeed_smc_is_writable(fl)) { |
924ed163 CLG |
381 | qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%" |
382 | HWADDR_PRIx "\n", __func__, addr); | |
383 | return; | |
384 | } | |
385 | ||
f248a9db | 386 | if (!aspeed_smc_is_usermode(fl)) { |
924ed163 CLG |
387 | qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n", |
388 | __func__); | |
389 | return; | |
390 | } | |
391 | ||
392 | for (i = 0; i < size; i++) { | |
393 | ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); | |
394 | } | |
395 | } | |
396 | ||
397 | static const MemoryRegionOps aspeed_smc_flash_ops = { | |
398 | .read = aspeed_smc_flash_read, | |
399 | .write = aspeed_smc_flash_write, | |
400 | .endianness = DEVICE_LITTLE_ENDIAN, | |
401 | .valid = { | |
402 | .min_access_size = 1, | |
403 | .max_access_size = 4, | |
404 | }, | |
7c1c69bc CLG |
405 | }; |
406 | ||
f248a9db | 407 | static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl) |
7c1c69bc | 408 | { |
f248a9db CLG |
409 | const AspeedSMCState *s = fl->controller; |
410 | ||
411 | return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE; | |
7c1c69bc CLG |
412 | } |
413 | ||
f248a9db | 414 | static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl) |
7c1c69bc | 415 | { |
f248a9db | 416 | const AspeedSMCState *s = fl->controller; |
7c1c69bc | 417 | |
f248a9db | 418 | qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); |
7c1c69bc CLG |
419 | } |
420 | ||
421 | static void aspeed_smc_reset(DeviceState *d) | |
422 | { | |
423 | AspeedSMCState *s = ASPEED_SMC(d); | |
424 | int i; | |
425 | ||
426 | memset(s->regs, 0, sizeof s->regs); | |
427 | ||
2e1f0502 CLG |
428 | /* Pretend DMA is done (u-boot initialization) */ |
429 | s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS; | |
430 | ||
7c1c69bc CLG |
431 | /* Unselect all slaves */ |
432 | for (i = 0; i < s->num_cs; ++i) { | |
433 | s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; | |
1d247bd0 | 434 | qemu_set_irq(s->cs_lines[i], true); |
7c1c69bc CLG |
435 | } |
436 | ||
a03cb1da CLG |
437 | /* setup default segment register values for all */ |
438 | for (i = 0; i < s->ctrl->max_slaves; ++i) { | |
439 | s->regs[R_SEG_ADDR0 + i] = | |
440 | aspeed_smc_segment_to_reg(&s->ctrl->segments[i]); | |
441 | } | |
0707b34d CLG |
442 | |
443 | /* HW strapping for AST2500 FMC controllers */ | |
444 | if (s->ctrl->segments == aspeed_segments_ast2500_fmc) { | |
445 | /* flash type is fixed to SPI for CE0 and CE1 */ | |
446 | s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); | |
447 | s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1); | |
448 | ||
449 | /* 4BYTE mode is autodetected for CE0. Let's force it to 1 for | |
450 | * now */ | |
451 | s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0)); | |
452 | } | |
453 | ||
454 | /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the | |
455 | * configuration of the palmetto-bmc machine */ | |
456 | if (s->ctrl->segments == aspeed_segments_fmc) { | |
457 | s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); | |
458 | ||
459 | s->regs[s->r_ce_ctrl] |= (1 << (CTRL_EXTENDED0)); | |
460 | } | |
7c1c69bc CLG |
461 | } |
462 | ||
7c1c69bc CLG |
463 | static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) |
464 | { | |
465 | AspeedSMCState *s = ASPEED_SMC(opaque); | |
466 | ||
467 | addr >>= 2; | |
468 | ||
469 | if (addr >= ARRAY_SIZE(s->regs)) { | |
470 | qemu_log_mask(LOG_GUEST_ERROR, | |
471 | "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", | |
472 | __func__, addr); | |
473 | return 0; | |
474 | } | |
475 | ||
97c2ed5d CLG |
476 | if (addr == s->r_conf || |
477 | addr == s->r_timings || | |
478 | addr == s->r_ce_ctrl || | |
2e1f0502 | 479 | addr == R_INTR_CTRL || |
a03cb1da | 480 | (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || |
97c2ed5d CLG |
481 | (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) { |
482 | return s->regs[addr]; | |
483 | } else { | |
7c1c69bc | 484 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |
97c2ed5d | 485 | __func__, addr); |
7c1c69bc CLG |
486 | return 0; |
487 | } | |
7c1c69bc CLG |
488 | } |
489 | ||
490 | static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, | |
491 | unsigned int size) | |
492 | { | |
493 | AspeedSMCState *s = ASPEED_SMC(opaque); | |
494 | uint32_t value = data; | |
495 | ||
496 | addr >>= 2; | |
497 | ||
498 | if (addr >= ARRAY_SIZE(s->regs)) { | |
499 | qemu_log_mask(LOG_GUEST_ERROR, | |
500 | "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", | |
501 | __func__, addr); | |
502 | return; | |
503 | } | |
504 | ||
97c2ed5d CLG |
505 | if (addr == s->r_conf || |
506 | addr == s->r_timings || | |
507 | addr == s->r_ce_ctrl) { | |
508 | s->regs[addr] = value; | |
509 | } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { | |
f248a9db | 510 | int cs = addr - s->r_ctrl0; |
97c2ed5d | 511 | s->regs[addr] = value; |
f248a9db | 512 | aspeed_smc_flash_update_cs(&s->flashes[cs]); |
a03cb1da CLG |
513 | } else if (addr >= R_SEG_ADDR0 && |
514 | addr < R_SEG_ADDR0 + s->ctrl->max_slaves) { | |
515 | int cs = addr - R_SEG_ADDR0; | |
516 | ||
517 | if (value != s->regs[R_SEG_ADDR0 + cs]) { | |
518 | aspeed_smc_flash_set_segment(s, cs, value); | |
519 | } | |
97c2ed5d | 520 | } else { |
7c1c69bc CLG |
521 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |
522 | __func__, addr); | |
523 | return; | |
524 | } | |
7c1c69bc CLG |
525 | } |
526 | ||
527 | static const MemoryRegionOps aspeed_smc_ops = { | |
528 | .read = aspeed_smc_read, | |
529 | .write = aspeed_smc_write, | |
530 | .endianness = DEVICE_LITTLE_ENDIAN, | |
531 | .valid.unaligned = true, | |
532 | }; | |
533 | ||
534 | static void aspeed_smc_realize(DeviceState *dev, Error **errp) | |
535 | { | |
536 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
537 | AspeedSMCState *s = ASPEED_SMC(dev); | |
538 | AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s); | |
539 | int i; | |
924ed163 CLG |
540 | char name[32]; |
541 | hwaddr offset = 0; | |
7c1c69bc CLG |
542 | |
543 | s->ctrl = mc->ctrl; | |
544 | ||
545 | /* keep a copy under AspeedSMCState to speed up accesses */ | |
546 | s->r_conf = s->ctrl->r_conf; | |
547 | s->r_ce_ctrl = s->ctrl->r_ce_ctrl; | |
548 | s->r_ctrl0 = s->ctrl->r_ctrl0; | |
549 | s->r_timings = s->ctrl->r_timings; | |
550 | s->conf_enable_w0 = s->ctrl->conf_enable_w0; | |
551 | ||
552 | /* Enforce some real HW limits */ | |
553 | if (s->num_cs > s->ctrl->max_slaves) { | |
554 | qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n", | |
555 | __func__, s->ctrl->max_slaves); | |
556 | s->num_cs = s->ctrl->max_slaves; | |
557 | } | |
558 | ||
559 | s->spi = ssi_create_bus(dev, "spi"); | |
560 | ||
561 | /* Setup cs_lines for slaves */ | |
562 | sysbus_init_irq(sbd, &s->irq); | |
563 | s->cs_lines = g_new0(qemu_irq, s->num_cs); | |
564 | ssi_auto_connect_slaves(dev, s->cs_lines, s->spi); | |
565 | ||
566 | for (i = 0; i < s->num_cs; ++i) { | |
567 | sysbus_init_irq(sbd, &s->cs_lines[i]); | |
568 | } | |
569 | ||
2da95fd8 | 570 | /* The memory region for the controller registers */ |
7c1c69bc CLG |
571 | memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, |
572 | s->ctrl->name, ASPEED_SMC_R_MAX * 4); | |
573 | sysbus_init_mmio(sbd, &s->mmio); | |
924ed163 CLG |
574 | |
575 | /* | |
2da95fd8 CLG |
576 | * The container memory region representing the address space |
577 | * window in which the flash modules are mapped. The size and | |
578 | * address depends on the SoC model and controller type. | |
924ed163 CLG |
579 | */ |
580 | snprintf(name, sizeof(name), "%s.flash", s->ctrl->name); | |
581 | ||
582 | memory_region_init_io(&s->mmio_flash, OBJECT(s), | |
583 | &aspeed_smc_flash_default_ops, s, name, | |
dcb83444 | 584 | s->ctrl->flash_window_size); |
924ed163 CLG |
585 | sysbus_init_mmio(sbd, &s->mmio_flash); |
586 | ||
2da95fd8 | 587 | s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves); |
924ed163 | 588 | |
2da95fd8 CLG |
589 | /* |
590 | * Let's create a sub memory region for each possible slave. All | |
591 | * have a configurable memory segment in the overall flash mapping | |
592 | * window of the controller but, there is not necessarily a flash | |
593 | * module behind to handle the memory accesses. This depends on | |
594 | * the board configuration. | |
595 | */ | |
596 | for (i = 0; i < s->ctrl->max_slaves; ++i) { | |
924ed163 CLG |
597 | AspeedSMCFlash *fl = &s->flashes[i]; |
598 | ||
599 | snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i); | |
600 | ||
601 | fl->id = i; | |
602 | fl->controller = s; | |
603 | fl->size = s->ctrl->segments[i].size; | |
604 | memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops, | |
605 | fl, name, fl->size); | |
606 | memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); | |
607 | offset += fl->size; | |
608 | } | |
7c1c69bc CLG |
609 | } |
610 | ||
611 | static const VMStateDescription vmstate_aspeed_smc = { | |
612 | .name = "aspeed.smc", | |
613 | .version_id = 1, | |
614 | .minimum_version_id = 1, | |
615 | .fields = (VMStateField[]) { | |
616 | VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), | |
617 | VMSTATE_END_OF_LIST() | |
618 | } | |
619 | }; | |
620 | ||
621 | static Property aspeed_smc_properties[] = { | |
622 | DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), | |
623 | DEFINE_PROP_END_OF_LIST(), | |
624 | }; | |
625 | ||
626 | static void aspeed_smc_class_init(ObjectClass *klass, void *data) | |
627 | { | |
628 | DeviceClass *dc = DEVICE_CLASS(klass); | |
629 | AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass); | |
630 | ||
631 | dc->realize = aspeed_smc_realize; | |
632 | dc->reset = aspeed_smc_reset; | |
633 | dc->props = aspeed_smc_properties; | |
634 | dc->vmsd = &vmstate_aspeed_smc; | |
635 | mc->ctrl = data; | |
636 | } | |
637 | ||
638 | static const TypeInfo aspeed_smc_info = { | |
639 | .name = TYPE_ASPEED_SMC, | |
640 | .parent = TYPE_SYS_BUS_DEVICE, | |
641 | .instance_size = sizeof(AspeedSMCState), | |
642 | .class_size = sizeof(AspeedSMCClass), | |
643 | .abstract = true, | |
644 | }; | |
645 | ||
646 | static void aspeed_smc_register_types(void) | |
647 | { | |
648 | int i; | |
649 | ||
650 | type_register_static(&aspeed_smc_info); | |
651 | for (i = 0; i < ARRAY_SIZE(controllers); ++i) { | |
652 | TypeInfo ti = { | |
653 | .name = controllers[i].name, | |
654 | .parent = TYPE_ASPEED_SMC, | |
655 | .class_init = aspeed_smc_class_init, | |
656 | .class_data = (void *)&controllers[i], | |
657 | }; | |
658 | type_register(&ti); | |
659 | } | |
660 | } | |
661 | ||
662 | type_init(aspeed_smc_register_types) |