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Commit | Line | Data |
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420557e8 | 1 | /* |
6f7e9aec | 2 | * QEMU TCX Frame buffer |
5fafdf24 | 3 | * |
6f7e9aec | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "sun4m.h" | |
26 | #include "console.h" | |
94470844 | 27 | #include "pixel_ops.h" |
420557e8 | 28 | |
420557e8 FB |
29 | #define MAXX 1024 |
30 | #define MAXY 768 | |
6f7e9aec | 31 | #define TCX_DAC_NREGS 16 |
8508b89e BS |
32 | #define TCX_THC_NREGS_8 0x081c |
33 | #define TCX_THC_NREGS_24 0x1000 | |
34 | #define TCX_TEC_NREGS 0x1000 | |
420557e8 | 35 | |
420557e8 | 36 | typedef struct TCXState { |
5dcb6b91 | 37 | target_phys_addr_t addr; |
420557e8 | 38 | DisplayState *ds; |
c60e08d9 | 39 | QEMUConsole *console; |
8d5f07fa | 40 | uint8_t *vram; |
eee0b836 BS |
41 | uint32_t *vram24, *cplane; |
42 | ram_addr_t vram_offset, vram24_offset, cplane_offset; | |
43 | uint16_t width, height, depth; | |
e80cfcfc | 44 | uint8_t r[256], g[256], b[256]; |
21206a10 | 45 | uint32_t palette[256]; |
6f7e9aec | 46 | uint8_t dac_index, dac_state; |
420557e8 FB |
47 | } TCXState; |
48 | ||
95219897 | 49 | static void tcx_screen_dump(void *opaque, const char *filename); |
eee0b836 | 50 | static void tcx24_screen_dump(void *opaque, const char *filename); |
97e7df27 BS |
51 | static void tcx_invalidate_display(void *opaque); |
52 | static void tcx24_invalidate_display(void *opaque); | |
95219897 | 53 | |
21206a10 FB |
54 | static void update_palette_entries(TCXState *s, int start, int end) |
55 | { | |
56 | int i; | |
57 | for(i = start; i < end; i++) { | |
0e1f5a0c | 58 | switch(ds_get_bits_per_pixel(s->ds)) { |
21206a10 FB |
59 | default: |
60 | case 8: | |
61 | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); | |
62 | break; | |
63 | case 15: | |
8927bcfd | 64 | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
21206a10 FB |
65 | break; |
66 | case 16: | |
8927bcfd | 67 | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
21206a10 FB |
68 | break; |
69 | case 32: | |
8927bcfd | 70 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
21206a10 FB |
71 | break; |
72 | } | |
73 | } | |
97e7df27 BS |
74 | if (s->depth == 24) |
75 | tcx24_invalidate_display(s); | |
76 | else | |
77 | tcx_invalidate_display(s); | |
21206a10 FB |
78 | } |
79 | ||
5fafdf24 | 80 | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
f930d07e | 81 | const uint8_t *s, int width) |
420557e8 | 82 | { |
e80cfcfc FB |
83 | int x; |
84 | uint8_t val; | |
8bdc2159 | 85 | uint32_t *p = (uint32_t *)d; |
e80cfcfc FB |
86 | |
87 | for(x = 0; x < width; x++) { | |
f930d07e | 88 | val = *s++; |
8bdc2159 | 89 | *p++ = s1->palette[val]; |
e80cfcfc | 90 | } |
420557e8 FB |
91 | } |
92 | ||
5fafdf24 | 93 | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
f930d07e | 94 | const uint8_t *s, int width) |
e80cfcfc FB |
95 | { |
96 | int x; | |
97 | uint8_t val; | |
8bdc2159 | 98 | uint16_t *p = (uint16_t *)d; |
8d5f07fa | 99 | |
e80cfcfc | 100 | for(x = 0; x < width; x++) { |
f930d07e | 101 | val = *s++; |
8bdc2159 | 102 | *p++ = s1->palette[val]; |
e80cfcfc FB |
103 | } |
104 | } | |
105 | ||
5fafdf24 | 106 | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
f930d07e | 107 | const uint8_t *s, int width) |
420557e8 | 108 | { |
e80cfcfc FB |
109 | int x; |
110 | uint8_t val; | |
111 | ||
112 | for(x = 0; x < width; x++) { | |
f930d07e | 113 | val = *s++; |
21206a10 | 114 | *d++ = s1->palette[val]; |
420557e8 | 115 | } |
420557e8 FB |
116 | } |
117 | ||
688ea2eb BS |
118 | /* |
119 | XXX Could be much more optimal: | |
120 | * detect if line/page/whole screen is in 24 bit mode | |
121 | * if destination is also BGR, use memcpy | |
122 | */ | |
eee0b836 BS |
123 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
124 | const uint8_t *s, int width, | |
125 | const uint32_t *cplane, | |
126 | const uint32_t *s24) | |
127 | { | |
8927bcfd | 128 | int x, r, g, b; |
688ea2eb | 129 | uint8_t val, *p8; |
eee0b836 BS |
130 | uint32_t *p = (uint32_t *)d; |
131 | uint32_t dval; | |
132 | ||
133 | for(x = 0; x < width; x++, s++, s24++) { | |
688ea2eb BS |
134 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
135 | // 24-bit direct, BGR order | |
136 | p8 = (uint8_t *)s24; | |
137 | p8++; | |
138 | b = *p8++; | |
139 | g = *p8++; | |
140 | r = *p8++; | |
8927bcfd | 141 | dval = rgb_to_pixel32(r, g, b); |
eee0b836 BS |
142 | } else { |
143 | val = *s; | |
144 | dval = s1->palette[val]; | |
145 | } | |
146 | *p++ = dval; | |
147 | } | |
148 | } | |
149 | ||
22548760 | 150 | static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
eee0b836 BS |
151 | ram_addr_t cpage) |
152 | { | |
153 | int ret; | |
154 | unsigned int off; | |
155 | ||
156 | ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); | |
157 | for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { | |
158 | ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); | |
159 | ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); | |
160 | } | |
161 | return ret; | |
162 | } | |
163 | ||
164 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, | |
165 | ram_addr_t page_max, ram_addr_t page24, | |
166 | ram_addr_t cpage) | |
167 | { | |
168 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, | |
169 | VGA_DIRTY_FLAG); | |
170 | page_min -= ts->vram_offset; | |
171 | page_max -= ts->vram_offset; | |
172 | cpu_physical_memory_reset_dirty(page24 + page_min * 4, | |
173 | page24 + page_max * 4 + TARGET_PAGE_SIZE, | |
174 | VGA_DIRTY_FLAG); | |
175 | cpu_physical_memory_reset_dirty(cpage + page_min * 4, | |
176 | cpage + page_max * 4 + TARGET_PAGE_SIZE, | |
177 | VGA_DIRTY_FLAG); | |
178 | } | |
179 | ||
e80cfcfc FB |
180 | /* Fixed line length 1024 allows us to do nice tricks not possible on |
181 | VGA... */ | |
95219897 | 182 | static void tcx_update_display(void *opaque) |
420557e8 | 183 | { |
e80cfcfc | 184 | TCXState *ts = opaque; |
550be127 FB |
185 | ram_addr_t page, page_min, page_max; |
186 | int y, y_start, dd, ds; | |
e80cfcfc | 187 | uint8_t *d, *s; |
b3ceef24 | 188 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
e80cfcfc | 189 | |
0e1f5a0c | 190 | if (ds_get_bits_per_pixel(ts->ds) == 0) |
f930d07e | 191 | return; |
6f7e9aec | 192 | page = ts->vram_offset; |
e80cfcfc | 193 | y_start = -1; |
550be127 FB |
194 | page_min = 0xffffffff; |
195 | page_max = 0; | |
0e1f5a0c | 196 | d = ds_get_data(ts->ds); |
6f7e9aec | 197 | s = ts->vram; |
0e1f5a0c | 198 | dd = ds_get_linesize(ts->ds); |
e80cfcfc FB |
199 | ds = 1024; |
200 | ||
0e1f5a0c | 201 | switch (ds_get_bits_per_pixel(ts->ds)) { |
e80cfcfc | 202 | case 32: |
f930d07e BS |
203 | f = tcx_draw_line32; |
204 | break; | |
21206a10 FB |
205 | case 15: |
206 | case 16: | |
f930d07e BS |
207 | f = tcx_draw_line16; |
208 | break; | |
e80cfcfc FB |
209 | default: |
210 | case 8: | |
f930d07e BS |
211 | f = tcx_draw_line8; |
212 | break; | |
e80cfcfc | 213 | case 0: |
f930d07e | 214 | return; |
e80cfcfc | 215 | } |
3b46e624 | 216 | |
6f7e9aec | 217 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
f930d07e BS |
218 | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { |
219 | if (y_start < 0) | |
e80cfcfc FB |
220 | y_start = y; |
221 | if (page < page_min) | |
222 | page_min = page; | |
223 | if (page > page_max) | |
224 | page_max = page; | |
f930d07e BS |
225 | f(ts, d, s, ts->width); |
226 | d += dd; | |
227 | s += ds; | |
228 | f(ts, d, s, ts->width); | |
229 | d += dd; | |
230 | s += ds; | |
231 | f(ts, d, s, ts->width); | |
232 | d += dd; | |
233 | s += ds; | |
234 | f(ts, d, s, ts->width); | |
235 | d += dd; | |
236 | s += ds; | |
237 | } else { | |
e80cfcfc FB |
238 | if (y_start >= 0) { |
239 | /* flush to display */ | |
5fafdf24 | 240 | dpy_update(ts->ds, 0, y_start, |
6f7e9aec | 241 | ts->width, y - y_start); |
e80cfcfc FB |
242 | y_start = -1; |
243 | } | |
f930d07e BS |
244 | d += dd * 4; |
245 | s += ds * 4; | |
246 | } | |
e80cfcfc FB |
247 | } |
248 | if (y_start >= 0) { | |
f930d07e BS |
249 | /* flush to display */ |
250 | dpy_update(ts->ds, 0, y_start, | |
251 | ts->width, y - y_start); | |
e80cfcfc FB |
252 | } |
253 | /* reset modified pages */ | |
550be127 | 254 | if (page_min <= page_max) { |
0a962c02 FB |
255 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
256 | VGA_DIRTY_FLAG); | |
e80cfcfc | 257 | } |
420557e8 FB |
258 | } |
259 | ||
eee0b836 BS |
260 | static void tcx24_update_display(void *opaque) |
261 | { | |
262 | TCXState *ts = opaque; | |
263 | ram_addr_t page, page_min, page_max, cpage, page24; | |
264 | int y, y_start, dd, ds; | |
265 | uint8_t *d, *s; | |
266 | uint32_t *cptr, *s24; | |
267 | ||
0e1f5a0c | 268 | if (ds_get_bits_per_pixel(ts->ds) != 32) |
eee0b836 BS |
269 | return; |
270 | page = ts->vram_offset; | |
271 | page24 = ts->vram24_offset; | |
272 | cpage = ts->cplane_offset; | |
273 | y_start = -1; | |
274 | page_min = 0xffffffff; | |
275 | page_max = 0; | |
0e1f5a0c | 276 | d = ds_get_data(ts->ds); |
eee0b836 BS |
277 | s = ts->vram; |
278 | s24 = ts->vram24; | |
279 | cptr = ts->cplane; | |
0e1f5a0c | 280 | dd = ds_get_linesize(ts->ds); |
eee0b836 BS |
281 | ds = 1024; |
282 | ||
283 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, | |
284 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { | |
22548760 | 285 | if (check_dirty(page, page24, cpage)) { |
eee0b836 BS |
286 | if (y_start < 0) |
287 | y_start = y; | |
288 | if (page < page_min) | |
289 | page_min = page; | |
290 | if (page > page_max) | |
291 | page_max = page; | |
292 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
293 | d += dd; | |
294 | s += ds; | |
295 | cptr += ds; | |
296 | s24 += ds; | |
297 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
298 | d += dd; | |
299 | s += ds; | |
300 | cptr += ds; | |
301 | s24 += ds; | |
302 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
303 | d += dd; | |
304 | s += ds; | |
305 | cptr += ds; | |
306 | s24 += ds; | |
307 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
308 | d += dd; | |
309 | s += ds; | |
310 | cptr += ds; | |
311 | s24 += ds; | |
312 | } else { | |
313 | if (y_start >= 0) { | |
314 | /* flush to display */ | |
315 | dpy_update(ts->ds, 0, y_start, | |
316 | ts->width, y - y_start); | |
317 | y_start = -1; | |
318 | } | |
319 | d += dd * 4; | |
320 | s += ds * 4; | |
321 | cptr += ds * 4; | |
322 | s24 += ds * 4; | |
323 | } | |
324 | } | |
325 | if (y_start >= 0) { | |
326 | /* flush to display */ | |
327 | dpy_update(ts->ds, 0, y_start, | |
328 | ts->width, y - y_start); | |
329 | } | |
330 | /* reset modified pages */ | |
331 | if (page_min <= page_max) { | |
332 | reset_dirty(ts, page_min, page_max, page24, cpage); | |
333 | } | |
334 | } | |
335 | ||
95219897 | 336 | static void tcx_invalidate_display(void *opaque) |
420557e8 | 337 | { |
e80cfcfc FB |
338 | TCXState *s = opaque; |
339 | int i; | |
340 | ||
341 | for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { | |
f930d07e | 342 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
e80cfcfc | 343 | } |
420557e8 FB |
344 | } |
345 | ||
eee0b836 BS |
346 | static void tcx24_invalidate_display(void *opaque) |
347 | { | |
348 | TCXState *s = opaque; | |
349 | int i; | |
350 | ||
351 | tcx_invalidate_display(s); | |
352 | for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { | |
353 | cpu_physical_memory_set_dirty(s->vram24_offset + i); | |
354 | cpu_physical_memory_set_dirty(s->cplane_offset + i); | |
355 | } | |
356 | } | |
357 | ||
e80cfcfc | 358 | static void tcx_save(QEMUFile *f, void *opaque) |
420557e8 FB |
359 | { |
360 | TCXState *s = opaque; | |
3b46e624 | 361 | |
b6c4f71f BS |
362 | qemu_put_be16s(f, &s->height); |
363 | qemu_put_be16s(f, &s->width); | |
364 | qemu_put_be16s(f, &s->depth); | |
e80cfcfc FB |
365 | qemu_put_buffer(f, s->r, 256); |
366 | qemu_put_buffer(f, s->g, 256); | |
367 | qemu_put_buffer(f, s->b, 256); | |
6f7e9aec FB |
368 | qemu_put_8s(f, &s->dac_index); |
369 | qemu_put_8s(f, &s->dac_state); | |
420557e8 FB |
370 | } |
371 | ||
e80cfcfc | 372 | static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
420557e8 | 373 | { |
e80cfcfc | 374 | TCXState *s = opaque; |
fda77c2d BS |
375 | uint32_t dummy; |
376 | ||
377 | if (version_id != 3 && version_id != 4) | |
e80cfcfc FB |
378 | return -EINVAL; |
379 | ||
fda77c2d | 380 | if (version_id == 3) { |
b6c4f71f BS |
381 | qemu_get_be32s(f, &dummy); |
382 | qemu_get_be32s(f, &dummy); | |
383 | qemu_get_be32s(f, &dummy); | |
fda77c2d | 384 | } |
b6c4f71f BS |
385 | qemu_get_be16s(f, &s->height); |
386 | qemu_get_be16s(f, &s->width); | |
387 | qemu_get_be16s(f, &s->depth); | |
e80cfcfc FB |
388 | qemu_get_buffer(f, s->r, 256); |
389 | qemu_get_buffer(f, s->g, 256); | |
390 | qemu_get_buffer(f, s->b, 256); | |
6f7e9aec FB |
391 | qemu_get_8s(f, &s->dac_index); |
392 | qemu_get_8s(f, &s->dac_state); | |
21206a10 | 393 | update_palette_entries(s, 0, 256); |
97e7df27 BS |
394 | if (s->depth == 24) |
395 | tcx24_invalidate_display(s); | |
396 | else | |
397 | tcx_invalidate_display(s); | |
5425a216 | 398 | |
e80cfcfc | 399 | return 0; |
420557e8 FB |
400 | } |
401 | ||
e80cfcfc | 402 | static void tcx_reset(void *opaque) |
420557e8 | 403 | { |
e80cfcfc FB |
404 | TCXState *s = opaque; |
405 | ||
406 | /* Initialize palette */ | |
407 | memset(s->r, 0, 256); | |
408 | memset(s->g, 0, 256); | |
409 | memset(s->b, 0, 256); | |
410 | s->r[255] = s->g[255] = s->b[255] = 255; | |
21206a10 | 411 | update_palette_entries(s, 0, 256); |
e80cfcfc | 412 | memset(s->vram, 0, MAXX*MAXY); |
eee0b836 BS |
413 | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
414 | MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); | |
6f7e9aec FB |
415 | s->dac_index = 0; |
416 | s->dac_state = 0; | |
417 | } | |
418 | ||
419 | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) | |
420 | { | |
421 | return 0; | |
422 | } | |
423 | ||
424 | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
425 | { | |
426 | TCXState *s = opaque; | |
6f7e9aec | 427 | |
e64d7d59 | 428 | switch (addr) { |
6f7e9aec | 429 | case 0: |
f930d07e BS |
430 | s->dac_index = val >> 24; |
431 | s->dac_state = 0; | |
432 | break; | |
e64d7d59 | 433 | case 4: |
f930d07e BS |
434 | switch (s->dac_state) { |
435 | case 0: | |
436 | s->r[s->dac_index] = val >> 24; | |
21206a10 | 437 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
f930d07e BS |
438 | s->dac_state++; |
439 | break; | |
440 | case 1: | |
441 | s->g[s->dac_index] = val >> 24; | |
21206a10 | 442 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
f930d07e BS |
443 | s->dac_state++; |
444 | break; | |
445 | case 2: | |
446 | s->b[s->dac_index] = val >> 24; | |
21206a10 | 447 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
5c8cdbf8 | 448 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
f930d07e BS |
449 | default: |
450 | s->dac_state = 0; | |
451 | break; | |
452 | } | |
453 | break; | |
6f7e9aec | 454 | default: |
f930d07e | 455 | break; |
6f7e9aec FB |
456 | } |
457 | return; | |
420557e8 FB |
458 | } |
459 | ||
6f7e9aec | 460 | static CPUReadMemoryFunc *tcx_dac_read[3] = { |
7c560456 BS |
461 | NULL, |
462 | NULL, | |
6f7e9aec FB |
463 | tcx_dac_readl, |
464 | }; | |
465 | ||
466 | static CPUWriteMemoryFunc *tcx_dac_write[3] = { | |
7c560456 BS |
467 | NULL, |
468 | NULL, | |
6f7e9aec FB |
469 | tcx_dac_writel, |
470 | }; | |
471 | ||
8508b89e BS |
472 | static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
473 | { | |
474 | return 0; | |
475 | } | |
476 | ||
477 | static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, | |
478 | uint32_t val) | |
479 | { | |
480 | } | |
481 | ||
482 | static CPUReadMemoryFunc *tcx_dummy_read[3] = { | |
7c560456 BS |
483 | NULL, |
484 | NULL, | |
8508b89e BS |
485 | tcx_dummy_readl, |
486 | }; | |
487 | ||
488 | static CPUWriteMemoryFunc *tcx_dummy_write[3] = { | |
7c560456 BS |
489 | NULL, |
490 | NULL, | |
8508b89e BS |
491 | tcx_dummy_writel, |
492 | }; | |
493 | ||
5dcb6b91 | 494 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base, |
eee0b836 BS |
495 | unsigned long vram_offset, int vram_size, int width, int height, |
496 | int depth) | |
420557e8 FB |
497 | { |
498 | TCXState *s; | |
8508b89e | 499 | int io_memory, dummy_memory; |
eee0b836 | 500 | int size; |
420557e8 FB |
501 | |
502 | s = qemu_mallocz(sizeof(TCXState)); | |
503 | if (!s) | |
95219897 | 504 | return; |
420557e8 | 505 | s->ds = ds; |
8d5f07fa | 506 | s->addr = addr; |
e80cfcfc | 507 | s->vram_offset = vram_offset; |
6f7e9aec FB |
508 | s->width = width; |
509 | s->height = height; | |
eee0b836 BS |
510 | s->depth = depth; |
511 | ||
512 | // 8-bit plane | |
513 | s->vram = vram_base; | |
514 | size = vram_size; | |
5dcb6b91 | 515 | cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset); |
eee0b836 BS |
516 | vram_offset += size; |
517 | vram_base += size; | |
e80cfcfc | 518 | |
6f7e9aec | 519 | io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s); |
77f193da BS |
520 | cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, |
521 | io_memory); | |
eee0b836 | 522 | |
8508b89e BS |
523 | dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write, |
524 | s); | |
5dcb6b91 | 525 | cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS, |
8508b89e | 526 | dummy_memory); |
eee0b836 BS |
527 | if (depth == 24) { |
528 | // 24-bit plane | |
529 | size = vram_size * 4; | |
530 | s->vram24 = (uint32_t *)vram_base; | |
531 | s->vram24_offset = vram_offset; | |
5dcb6b91 | 532 | cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset); |
eee0b836 BS |
533 | vram_offset += size; |
534 | vram_base += size; | |
535 | ||
536 | // Control plane | |
537 | size = vram_size * 4; | |
538 | s->cplane = (uint32_t *)vram_base; | |
539 | s->cplane_offset = vram_offset; | |
5dcb6b91 | 540 | cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset); |
c60e08d9 PB |
541 | s->console = graphic_console_init(s->ds, tcx24_update_display, |
542 | tcx24_invalidate_display, | |
543 | tcx24_screen_dump, NULL, s); | |
eee0b836 | 544 | } else { |
5dcb6b91 | 545 | cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8, |
8508b89e | 546 | dummy_memory); |
c60e08d9 PB |
547 | s->console = graphic_console_init(s->ds, tcx_update_display, |
548 | tcx_invalidate_display, | |
549 | tcx_screen_dump, NULL, s); | |
eee0b836 | 550 | } |
f96f4c9d | 551 | // NetBSD writes here even with 8-bit display |
5dcb6b91 | 552 | cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24, |
f96f4c9d | 553 | dummy_memory); |
e80cfcfc | 554 | |
fda77c2d | 555 | register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
e80cfcfc FB |
556 | qemu_register_reset(tcx_reset, s); |
557 | tcx_reset(s); | |
c60e08d9 | 558 | qemu_console_resize(s->console, width, height); |
420557e8 FB |
559 | } |
560 | ||
95219897 | 561 | static void tcx_screen_dump(void *opaque, const char *filename) |
8d5f07fa | 562 | { |
e80cfcfc | 563 | TCXState *s = opaque; |
8d5f07fa | 564 | FILE *f; |
e80cfcfc | 565 | uint8_t *d, *d1, v; |
8d5f07fa FB |
566 | int y, x; |
567 | ||
568 | f = fopen(filename, "wb"); | |
569 | if (!f) | |
e80cfcfc | 570 | return; |
6f7e9aec FB |
571 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
572 | d1 = s->vram; | |
573 | for(y = 0; y < s->height; y++) { | |
8d5f07fa | 574 | d = d1; |
6f7e9aec | 575 | for(x = 0; x < s->width; x++) { |
8d5f07fa | 576 | v = *d; |
e80cfcfc FB |
577 | fputc(s->r[v], f); |
578 | fputc(s->g[v], f); | |
579 | fputc(s->b[v], f); | |
8d5f07fa FB |
580 | d++; |
581 | } | |
e80cfcfc | 582 | d1 += MAXX; |
8d5f07fa FB |
583 | } |
584 | fclose(f); | |
585 | return; | |
586 | } | |
587 | ||
eee0b836 BS |
588 | static void tcx24_screen_dump(void *opaque, const char *filename) |
589 | { | |
590 | TCXState *s = opaque; | |
591 | FILE *f; | |
592 | uint8_t *d, *d1, v; | |
593 | uint32_t *s24, *cptr, dval; | |
594 | int y, x; | |
8d5f07fa | 595 | |
eee0b836 BS |
596 | f = fopen(filename, "wb"); |
597 | if (!f) | |
598 | return; | |
599 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); | |
600 | d1 = s->vram; | |
601 | s24 = s->vram24; | |
602 | cptr = s->cplane; | |
603 | for(y = 0; y < s->height; y++) { | |
604 | d = d1; | |
605 | for(x = 0; x < s->width; x++, d++, s24++) { | |
606 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct | |
607 | dval = *s24 & 0x00ffffff; | |
608 | fputc((dval >> 16) & 0xff, f); | |
609 | fputc((dval >> 8) & 0xff, f); | |
610 | fputc(dval & 0xff, f); | |
611 | } else { | |
612 | v = *d; | |
613 | fputc(s->r[v], f); | |
614 | fputc(s->g[v], f); | |
615 | fputc(s->b[v], f); | |
616 | } | |
617 | } | |
618 | d1 += MAXX; | |
619 | } | |
620 | fclose(f); | |
621 | return; | |
622 | } |