[qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
} UNINState;

/* Don't know if this matches real hardware, but it agrees with OHW.  */
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return (irq_num + (pci_dev->devfn >> 3)) & 3;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    qemu_set_irq(pic[irq_num + 8], level);
}

static void pci_unin_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;

    pci_device_save(d, f);
}

static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;

    if (version_id != 1)
        return -EINVAL;

    return pci_device_load(d, f);
}

static void pci_unin_reset(void *opaque)
{
}

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}

static int pci_dec_21154_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth bridge */
    s = FROM_SYSBUS(UNINState, dev);

    // XXX: s = &pci_bridge[2];
    pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, 11 << 3, 4);

#if 0
    pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
    dev = qdev_create(NULL, "uni-north-pci");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int dec_21154_pci_host_init(PCIDevice *d)
{
    /* pci-to-pci bridge */
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
    d->config[0x08] = 0x05; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x20; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type

    d->config[0x18] = 0x01; // primary_bus
    d->config[0x19] = 0x02; // secondary_bus
    d->config[0x1A] = 0x02; // subordinate_bus
    d->config[0x1B] = 0x20; // secondary_latency_timer
    d->config[0x1C] = 0x11; // io_base
    d->config[0x1D] = 0x01; // io_limit
    d->config[0x20] = 0x00; // memory_base
    d->config[0x21] = 0x80;
    d->config[0x22] = 0x00; // memory_limit
    d->config[0x23] = 0x80;
    d->config[0x24] = 0x01; // prefetchable_memory_base
    d->config[0x25] = 0x80;
    d->config[0x26] = 0xF1; // prefectchable_memory_limit
    d->config[0x27] = 0x7F;
    // d->config[0x34] = 0xdc // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
};

static PCIDeviceInfo dec_21154_pci_host_info = {
    .qdev.name = "dec-21154",
    .qdev.size = sizeof(PCIDevice),
    .init      = dec_21154_pci_host_init,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("uni-north", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("dec-21154", sizeof(UNINState),
                        pci_dec_21154_init_device);
    pci_qdev_register(&dec_21154_pci_host_info);
    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("uni-north-pci", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
2e29bd04 BS	39	typedef struct UNINState {
	40	SysBusDevice busdev;
	41	PCIHostState host_state;
	42	} UNINState;
502a5395	43
d2b59317 PB	44	/* Don't know if this matches real hardware, but it agrees with OHW. */
d2b59317 PB	45	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	46	{
d2b59317 PB	47	return (irq_num + (pci_dev->devfn >> 3)) & 3;
	48	}
	49
5d4e84c8	50	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	51	{
5d4e84c8 JQ	52	qemu_irq *pic = opaque;
5d4e84c8 JQ	53
d537cf6c	54	qemu_set_irq(pic[irq_num + 8], level);
502a5395 PB	55	}
502a5395 PB	56
f3902383 BS	57	static void pci_unin_save(QEMUFile* f, void *opaque)
	58	{
	59	PCIDevice *d = opaque;
	60
	61	pci_device_save(d, f);
	62	}
	63
	64	static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
	65	{
	66	PCIDevice *d = opaque;
	67
	68	if (version_id != 1)
	69	return -EINVAL;
	70
	71	return pci_device_load(d, f);
	72	}
	73
	74	static void pci_unin_reset(void *opaque)
	75	{
	76	}
	77
81a322d4	78	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	79	{
502a5395 PB	80	UNINState *s;
502a5395 PB	81	int pci_mem_config, pci_mem_data;
	82
	83	/* Use values found on a real PowerMac */
	84	/* Uninorth main bus */
2e29bd04	85	s = FROM_SYSBUS(UNINState, dev);
502a5395	86
f08b32fe IY	87	pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
f08b32fe IY	88	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
2e29bd04 BS	89	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	90	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	91
	92	register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);
	93	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	94	return 0;
2e29bd04 BS	95	}
2e29bd04 BS	96
81a322d4	97	static int pci_dec_21154_init_device(SysBusDevice *dev)
2e29bd04 BS	98	{
	99	UNINState *s;
	100	int pci_mem_config, pci_mem_data;
	101
	102	/* Uninorth bridge */
	103	s = FROM_SYSBUS(UNINState, dev);
	104
	105	// XXX: s = &pci_bridge[2];
f08b32fe IY	106	pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
f08b32fe IY	107	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
2e29bd04 BS	108	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	109	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	110	return 0;
2e29bd04 BS	111	}
2e29bd04 BS	112
81a322d4	113	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	114	{
	115	UNINState *s;
	116	int pci_mem_config, pci_mem_data;
	117
	118	/* Uninorth AGP bus */
	119	s = FROM_SYSBUS(UNINState, dev);
	120
f08b32fe IY	121	pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
f08b32fe IY	122	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
2e29bd04 BS	123	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	124	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	125	return 0;
2e29bd04 BS	126	}
2e29bd04 BS	127
81a322d4	128	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	129	{
	130	UNINState *s;
	131	int pci_mem_config, pci_mem_data;
	132
	133	/* Uninorth internal bus */
	134	s = FROM_SYSBUS(UNINState, dev);
	135
f08b32fe IY	136	pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
f08b32fe IY	137	pci_mem_data = pci_host_data_register_mmio(&s->host_state);
2e29bd04 BS	138	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	139	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	140	return 0;
2e29bd04 BS	141	}
	142
	143	PCIBus pci_pmac_init(qemu_irq pic)
	144	{
	145	DeviceState *dev;
	146	SysBusDevice *s;
	147	UNINState *d;
	148
	149	/* Use values found on a real PowerMac */
	150	/* Uninorth main bus */
99917a99	151	dev = qdev_create(NULL, "uni-north");
e23a1b33	152	qdev_init_nofail(dev);
2e29bd04 BS	153	s = sysbus_from_qdev(dev);
2e29bd04 BS	154	d = FROM_SYSBUS(UNINState, s);
cdd0935c	155	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04 BS	156	pci_unin_set_irq, pci_unin_map_irq,
	157	pic, 11 << 3, 4);
	158
60398748	159	#if 0
99917a99	160	pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
60398748	161	#endif
2e29bd04 BS	162
	163	sysbus_mmio_map(s, 0, 0xf2800000);
	164	sysbus_mmio_map(s, 1, 0xf2c00000);
	165
	166	/* DEC 21154 bridge */
	167	#if 0
	168	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
72fbd9f9	169	pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
2e29bd04 BS	170	#endif
	171
	172	/* Uninorth AGP bus */
99917a99 MA	173	pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
99917a99 MA	174	dev = qdev_create(NULL, "uni-north-agp");
d27d06f2 BS	175	qdev_init_nofail(dev);
	176	s = sysbus_from_qdev(dev);
	177	sysbus_mmio_map(s, 0, 0xf0800000);
	178	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	179
	180	/* Uninorth internal bus */
	181	#if 0
	182	/* XXX: not needed for now */
99917a99 MA	183	pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
99917a99 MA	184	dev = qdev_create(NULL, "uni-north-pci");
d27d06f2 BS	185	qdev_init_nofail(dev);
	186	s = sysbus_from_qdev(dev);
	187	sysbus_mmio_map(s, 0, 0xf4800000);
	188	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	189	#endif
	190
	191	return d->host_state.bus;
	192	}
	193
81a322d4	194	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	195	{
deb54399	196	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	197	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
502a5395	198	d->config[0x08] = 0x00; // revision
173a543b	199	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	200	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	201	d->config[0x0D] = 0x10; // latency_timer
6407f373	202	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	203	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	204	return 0;
2e29bd04	205	}
502a5395	206
81a322d4	207	static int dec_21154_pci_host_init(PCIDevice *d)
2e29bd04	208	{
502a5395	209	/* pci-to-pci bridge */
4ebcf884 BS	210	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
4ebcf884 BS	211	pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
502a5395	212	d->config[0x08] = 0x05; // revision
173a543b	213	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
502a5395 PB	214	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	215	d->config[0x0D] = 0x20; // latency_timer
6407f373	216	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
502a5395 PB	217
	218	d->config[0x18] = 0x01; // primary_bus
	219	d->config[0x19] = 0x02; // secondary_bus
	220	d->config[0x1A] = 0x02; // subordinate_bus
	221	d->config[0x1B] = 0x20; // secondary_latency_timer
	222	d->config[0x1C] = 0x11; // io_base
	223	d->config[0x1D] = 0x01; // io_limit
	224	d->config[0x20] = 0x00; // memory_base
	225	d->config[0x21] = 0x80;
	226	d->config[0x22] = 0x00; // memory_limit
	227	d->config[0x23] = 0x80;
	228	d->config[0x24] = 0x01; // prefetchable_memory_base
	229	d->config[0x25] = 0x80;
	230	d->config[0x26] = 0xF1; // prefectchable_memory_limit
	231	d->config[0x27] = 0x7F;
	232	// d->config[0x34] = 0xdc // capabilities_pointer
81a322d4	233	return 0;
2e29bd04	234	}
502a5395	235
81a322d4	236	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	237	{
deb54399 AL	238	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
deb54399 AL	239	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
502a5395	240	d->config[0x08] = 0x00; // revision
173a543b	241	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	242	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	243	d->config[0x0D] = 0x10; // latency_timer
6407f373	244	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	245	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	246	return 0;
2e29bd04	247	}
502a5395	248
81a322d4	249	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	250	{
deb54399	251	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	252	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
502a5395	253	d->config[0x08] = 0x00; // revision
173a543b	254	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	255	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	256	d->config[0x0D] = 0x10; // latency_timer
6407f373	257	d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
502a5395	258	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	259	return 0;
2e29bd04 BS	260	}
	261
	262	static PCIDeviceInfo unin_main_pci_host_info = {
99917a99	263	.qdev.name = "uni-north",
2e29bd04 BS	264	.qdev.size = sizeof(PCIDevice),
	265	.init = unin_main_pci_host_init,
	266	};
	267
	268	static PCIDeviceInfo dec_21154_pci_host_info = {
72fbd9f9	269	.qdev.name = "dec-21154",
2e29bd04 BS	270	.qdev.size = sizeof(PCIDevice),
	271	.init = dec_21154_pci_host_init,
	272	};
f3902383	273
2e29bd04	274	static PCIDeviceInfo unin_agp_pci_host_info = {
99917a99	275	.qdev.name = "uni-north-agp",
2e29bd04 BS	276	.qdev.size = sizeof(PCIDevice),
	277	.init = unin_agp_pci_host_init,
	278	};
	279
	280	static PCIDeviceInfo unin_internal_pci_host_info = {
99917a99	281	.qdev.name = "uni-north-pci",
2e29bd04 BS	282	.qdev.size = sizeof(PCIDevice),
	283	.init = unin_internal_pci_host_init,
	284	};
	285
	286	static void unin_register_devices(void)
	287	{
99917a99	288	sysbus_register_dev("uni-north", sizeof(UNINState),
2e29bd04 BS	289	pci_unin_main_init_device);
2e29bd04 BS	290	pci_qdev_register(&unin_main_pci_host_info);
72fbd9f9	291	sysbus_register_dev("dec-21154", sizeof(UNINState),
2e29bd04 BS	292	pci_dec_21154_init_device);
2e29bd04 BS	293	pci_qdev_register(&dec_21154_pci_host_info);
99917a99	294	sysbus_register_dev("uni-north-agp", sizeof(UNINState),
2e29bd04 BS	295	pci_unin_agp_init_device);
2e29bd04 BS	296	pci_qdev_register(&unin_agp_pci_host_info);
99917a99	297	sysbus_register_dev("uni-north-pci", sizeof(UNINState),
2e29bd04 BS	298	pci_unin_internal_init_device);
2e29bd04 BS	299	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	300	}
2e29bd04 BS	301
2e29bd04 BS	302	device_init(unin_register_devices)