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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
c15d61b2 HG |
5 | * Copyright(c) 2011-2012 Red Hat, Inc. |
6 | * | |
7 | * Red Hat Authors: | |
8 | * Gerd Hoffmann <kraxel@redhat.com> | |
9 | * Hans de Goede <hdegoede@redhat.com> | |
94527ead GH |
10 | * |
11 | * EHCI project was started by Mark Burkley, with contributions by | |
12 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
13 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
14 | * | |
15 | * | |
16 | * This library is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU Lesser General Public | |
18 | * License as published by the Free Software Foundation; either | |
19 | * version 2 of the License, or(at your option) any later version. | |
20 | * | |
21 | * This library is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
24 | * Lesser General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
28 | */ |
29 | ||
f1ae32a1 | 30 | #include "hw/hw.h" |
94527ead | 31 | #include "qemu-timer.h" |
f1ae32a1 GH |
32 | #include "hw/usb.h" |
33 | #include "hw/pci.h" | |
94527ead | 34 | #include "monitor.h" |
439a97cc | 35 | #include "trace.h" |
0ce668bc | 36 | #include "dma.h" |
94527ead GH |
37 | |
38 | #define EHCI_DEBUG 0 | |
94527ead | 39 | |
26d53979 | 40 | #if EHCI_DEBUG |
94527ead GH |
41 | #define DPRINTF printf |
42 | #else | |
43 | #define DPRINTF(...) | |
44 | #endif | |
45 | ||
94527ead GH |
46 | /* internal processing - reset HC to try and recover */ |
47 | #define USB_RET_PROCERR (-99) | |
48 | ||
49 | #define MMIO_SIZE 0x1000 | |
50 | ||
51 | /* Capability Registers Base Address - section 2.2 */ | |
52 | #define CAPREGBASE 0x0000 | |
53 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
54 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
55 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
56 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
57 | #define EECP HCCPARAMS + 1 | |
58 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
59 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
60 | ||
61 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
62 | ||
63 | #define USBCMD OPREGBASE + 0x0000 | |
64 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
65 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
66 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
67 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
68 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
69 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
70 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
71 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
72 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
73 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
74 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
75 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
76 | ||
77 | #define USBSTS OPREGBASE + 0x0004 | |
78 | #define USBSTS_RO_MASK 0x0000003f | |
79 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
80 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
81 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
82 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
83 | #define USBSTS_HSE (1 << 4) // Host System Error | |
84 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
85 | #define USBSTS_HALT (1 << 12) // HC Halted | |
86 | #define USBSTS_REC (1 << 13) // Reclamation | |
87 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
88 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
89 | ||
90 | /* | |
91 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
92 | * so no need to redefine here. | |
93 | */ | |
94 | #define USBINTR OPREGBASE + 0x0008 | |
95 | #define USBINTR_MASK 0x0000003f | |
96 | ||
97 | #define FRINDEX OPREGBASE + 0x000c | |
98 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
99 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
100 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
101 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
102 | ||
103 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
104 | ||
105 | #define PORTSC (OPREGBASE + 0x0044) | |
106 | #define PORTSC_BEGIN PORTSC | |
107 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
108 | /* | |
c44fd61c | 109 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
110 | * written to us by software |
111 | */ | |
a0a3167a | 112 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
113 | #define PORTSC_RWC_MASK 0x0000002a |
114 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
115 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
116 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
117 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
118 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
119 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
120 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
121 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
122 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
123 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
124 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
125 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
126 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
127 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
128 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
129 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
130 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
131 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
132 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
133 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
134 | ||
135 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 136 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
137 | |
138 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
5cc194ca | 139 | #define NB_PORTS 6 // Number of downstream ports |
94527ead | 140 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
94527ead | 141 | #define MAX_QH 100 // Max allowable queue heads in a chain |
349b4e90 | 142 | #define MIN_FR_PER_TICK 3 // Min frames to process when catching up |
94527ead GH |
143 | |
144 | /* Internal periodic / asynchronous schedule state machine states | |
145 | */ | |
146 | typedef enum { | |
147 | EST_INACTIVE = 1000, | |
148 | EST_ACTIVE, | |
149 | EST_EXECUTING, | |
150 | EST_SLEEPING, | |
151 | /* The following states are internal to the state machine function | |
152 | */ | |
153 | EST_WAITLISTHEAD, | |
154 | EST_FETCHENTRY, | |
155 | EST_FETCHQH, | |
156 | EST_FETCHITD, | |
2fe80192 | 157 | EST_FETCHSITD, |
94527ead GH |
158 | EST_ADVANCEQUEUE, |
159 | EST_FETCHQTD, | |
160 | EST_EXECUTE, | |
161 | EST_WRITEBACK, | |
162 | EST_HORIZONTALQH | |
163 | } EHCI_STATES; | |
164 | ||
165 | /* macros for accessing fields within next link pointer entry */ | |
166 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
167 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
168 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
169 | ||
170 | /* link pointer types */ | |
171 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
172 | #define NLPTR_TYPE_QH 1 // queue head | |
173 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
174 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
175 | ||
176 | ||
177 | /* EHCI spec version 1.0 Section 3.3 | |
178 | */ | |
179 | typedef struct EHCIitd { | |
180 | uint32_t next; | |
181 | ||
182 | uint32_t transact[8]; | |
183 | #define ITD_XACT_ACTIVE (1 << 31) | |
184 | #define ITD_XACT_DBERROR (1 << 30) | |
185 | #define ITD_XACT_BABBLE (1 << 29) | |
186 | #define ITD_XACT_XACTERR (1 << 28) | |
187 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
188 | #define ITD_XACT_LENGTH_SH 16 | |
189 | #define ITD_XACT_IOC (1 << 15) | |
190 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
191 | #define ITD_XACT_PGSEL_SH 12 | |
192 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
193 | ||
194 | uint32_t bufptr[7]; | |
195 | #define ITD_BUFPTR_MASK 0xfffff000 | |
196 | #define ITD_BUFPTR_SH 12 | |
197 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
198 | #define ITD_BUFPTR_EP_SH 8 | |
199 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
200 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
201 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
202 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
203 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
204 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 205 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
206 | } EHCIitd; |
207 | ||
208 | /* EHCI spec version 1.0 Section 3.4 | |
209 | */ | |
210 | typedef struct EHCIsitd { | |
211 | uint32_t next; // Standard next link pointer | |
212 | uint32_t epchar; | |
213 | #define SITD_EPCHAR_IO (1 << 31) | |
214 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
215 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
216 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
217 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
218 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
219 | #define SITD_EPCHAR_EPNUM_SH 8 | |
220 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
221 | ||
222 | uint32_t uframe; | |
223 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
224 | #define SITD_UFRAME_CMASK_SH 8 | |
225 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
226 | ||
227 | uint32_t results; | |
228 | #define SITD_RESULTS_IOC (1 << 31) | |
229 | #define SITD_RESULTS_PGSEL (1 << 30) | |
230 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
231 | #define SITD_RESULTS_TYBYTES_SH 16 | |
232 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
233 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
234 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
235 | #define SITD_RESULTS_ERR (1 << 6) | |
236 | #define SITD_RESULTS_DBERR (1 << 5) | |
237 | #define SITD_RESULTS_BABBLE (1 << 4) | |
238 | #define SITD_RESULTS_XACTERR (1 << 3) | |
239 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
240 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
241 | ||
242 | uint32_t bufptr[2]; | |
243 | #define SITD_BUFPTR_MASK 0xfffff000 | |
244 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
245 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
246 | #define SITD_BUFPTR_TPOS_SH 3 | |
247 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
248 | ||
249 | uint32_t backptr; // Standard next link pointer | |
250 | } EHCIsitd; | |
251 | ||
252 | /* EHCI spec version 1.0 Section 3.5 | |
253 | */ | |
254 | typedef struct EHCIqtd { | |
255 | uint32_t next; // Standard next link pointer | |
256 | uint32_t altnext; // Standard next link pointer | |
257 | uint32_t token; | |
258 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
259 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
260 | #define QTD_TOKEN_TBYTES_SH 16 | |
261 | #define QTD_TOKEN_IOC (1 << 15) | |
262 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
263 | #define QTD_TOKEN_CPAGE_SH 12 | |
264 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
265 | #define QTD_TOKEN_CERR_SH 10 | |
266 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
267 | #define QTD_TOKEN_PID_SH 8 | |
268 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
269 | #define QTD_TOKEN_HALT (1 << 6) | |
270 | #define QTD_TOKEN_DBERR (1 << 5) | |
271 | #define QTD_TOKEN_BABBLE (1 << 4) | |
272 | #define QTD_TOKEN_XACTERR (1 << 3) | |
273 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
274 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
275 | #define QTD_TOKEN_PING (1 << 0) | |
276 | ||
277 | uint32_t bufptr[5]; // Standard buffer pointer | |
278 | #define QTD_BUFPTR_MASK 0xfffff000 | |
0ce668bc | 279 | #define QTD_BUFPTR_SH 12 |
94527ead GH |
280 | } EHCIqtd; |
281 | ||
282 | /* EHCI spec version 1.0 Section 3.6 | |
283 | */ | |
284 | typedef struct EHCIqh { | |
285 | uint32_t next; // Standard next link pointer | |
286 | ||
287 | /* endpoint characteristics */ | |
288 | uint32_t epchar; | |
289 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
290 | #define QH_EPCHAR_RL_SH 28 | |
291 | #define QH_EPCHAR_C (1 << 27) | |
292 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
293 | #define QH_EPCHAR_MPLEN_SH 16 | |
294 | #define QH_EPCHAR_H (1 << 15) | |
295 | #define QH_EPCHAR_DTC (1 << 14) | |
296 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
297 | #define QH_EPCHAR_EPS_SH 12 | |
298 | #define EHCI_QH_EPS_FULL 0 | |
299 | #define EHCI_QH_EPS_LOW 1 | |
300 | #define EHCI_QH_EPS_HIGH 2 | |
301 | #define EHCI_QH_EPS_RESERVED 3 | |
302 | ||
303 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
304 | #define QH_EPCHAR_EP_SH 8 | |
305 | #define QH_EPCHAR_I (1 << 7) | |
306 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
307 | #define QH_EPCHAR_DEVADDR_SH 0 | |
308 | ||
309 | /* endpoint capabilities */ | |
310 | uint32_t epcap; | |
311 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
312 | #define QH_EPCAP_MULT_SH 30 | |
313 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
314 | #define QH_EPCAP_PORTNUM_SH 23 | |
315 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
316 | #define QH_EPCAP_HUBADDR_SH 16 | |
317 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
318 | #define QH_EPCAP_CMASK_SH 8 | |
319 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
320 | #define QH_EPCAP_SMASK_SH 0 | |
321 | ||
322 | uint32_t current_qtd; // Standard next link pointer | |
323 | uint32_t next_qtd; // Standard next link pointer | |
324 | uint32_t altnext_qtd; | |
325 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
326 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
327 | ||
328 | uint32_t token; // Same as QTD token | |
329 | uint32_t bufptr[5]; // Standard buffer pointer | |
330 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
331 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
332 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
333 | #define BUFPTR_SBYTES_SH 5 | |
334 | } EHCIqh; | |
335 | ||
336 | /* EHCI spec version 1.0 Section 3.7 | |
337 | */ | |
338 | typedef struct EHCIfstn { | |
339 | uint32_t next; // Standard next link pointer | |
340 | uint32_t backptr; // Standard next link pointer | |
341 | } EHCIfstn; | |
342 | ||
eb36a88e | 343 | typedef struct EHCIPacket EHCIPacket; |
0122f472 GH |
344 | typedef struct EHCIQueue EHCIQueue; |
345 | typedef struct EHCIState EHCIState; | |
346 | ||
347 | enum async_state { | |
348 | EHCI_ASYNC_NONE = 0, | |
2f7ba473 | 349 | EHCI_ASYNC_INITIALIZED, |
0122f472 GH |
350 | EHCI_ASYNC_INFLIGHT, |
351 | EHCI_ASYNC_FINISHED, | |
352 | }; | |
353 | ||
eb36a88e GH |
354 | struct EHCIPacket { |
355 | EHCIQueue *queue; | |
356 | QTAILQ_ENTRY(EHCIPacket) next; | |
357 | ||
358 | EHCIqtd qtd; /* copy of current QTD (being worked on) */ | |
359 | uint32_t qtdaddr; /* address QTD read from */ | |
360 | ||
361 | USBPacket packet; | |
362 | QEMUSGList sgl; | |
363 | int pid; | |
364 | uint32_t tbytes; | |
365 | enum async_state async; | |
366 | int usb_status; | |
367 | }; | |
368 | ||
0122f472 GH |
369 | struct EHCIQueue { |
370 | EHCIState *ehci; | |
8ac6d699 | 371 | QTAILQ_ENTRY(EHCIQueue) next; |
adddecb1 GH |
372 | uint32_t seen; |
373 | uint64_t ts; | |
ae0138a8 | 374 | int async; |
0122f472 GH |
375 | |
376 | /* cached data from guest - needs to be flushed | |
377 | * when guest removes an entry (doorbell, handshake sequence) | |
378 | */ | |
eb36a88e GH |
379 | EHCIqh qh; /* copy of current QH (being worked on) */ |
380 | uint32_t qhaddr; /* address QH read from */ | |
381 | uint32_t qtdaddr; /* address QTD read from */ | |
e59928b3 | 382 | USBDevice *dev; |
eb36a88e | 383 | QTAILQ_HEAD(, EHCIPacket) packets; |
0122f472 GH |
384 | }; |
385 | ||
df5d5c5c HG |
386 | typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; |
387 | ||
0122f472 | 388 | struct EHCIState { |
94527ead | 389 | PCIDevice dev; |
0122f472 | 390 | USBBus bus; |
94527ead | 391 | qemu_irq irq; |
e57964f5 | 392 | MemoryRegion mem; |
1f97f6c9 GH |
393 | MemoryRegion mem_caps; |
394 | MemoryRegion mem_opreg; | |
395 | MemoryRegion mem_ports; | |
a0a3167a | 396 | int companion_count; |
16a2dee6 GH |
397 | |
398 | /* properties */ | |
16a2dee6 GH |
399 | uint32_t maxframes; |
400 | ||
94527ead GH |
401 | /* |
402 | * EHCI spec version 1.0 Section 2.3 | |
403 | * Host Controller Operational Registers | |
404 | */ | |
1f97f6c9 | 405 | uint8_t caps[OPREGBASE]; |
94527ead | 406 | union { |
1f97f6c9 | 407 | uint32_t opreg[(PORTSC_BEGIN-OPREGBASE)/sizeof(uint32_t)]; |
94527ead | 408 | struct { |
94527ead GH |
409 | uint32_t usbcmd; |
410 | uint32_t usbsts; | |
411 | uint32_t usbintr; | |
412 | uint32_t frindex; | |
413 | uint32_t ctrldssegment; | |
414 | uint32_t periodiclistbase; | |
415 | uint32_t asynclistaddr; | |
416 | uint32_t notused[9]; | |
417 | uint32_t configflag; | |
94527ead GH |
418 | }; |
419 | }; | |
1f97f6c9 | 420 | uint32_t portsc[NB_PORTS]; |
0122f472 | 421 | |
94527ead GH |
422 | /* |
423 | * Internal states, shadow registers, etc | |
424 | */ | |
94527ead | 425 | QEMUTimer *frame_timer; |
0fb3e299 | 426 | QEMUBH *async_bh; |
9a773408 GH |
427 | uint32_t astate; /* Current state in asynchronous schedule */ |
428 | uint32_t pstate; /* Current state in periodic schedule */ | |
94527ead | 429 | USBPort ports[NB_PORTS]; |
a0a3167a | 430 | USBPort *companion_ports[NB_PORTS]; |
94527ead | 431 | uint32_t usbsts_pending; |
7efc17af | 432 | uint32_t usbsts_frindex; |
df5d5c5c HG |
433 | EHCIQueueHead aqueues; |
434 | EHCIQueueHead pqueues; | |
94527ead | 435 | |
9a773408 GH |
436 | /* which address to look at next */ |
437 | uint32_t a_fetch_addr; | |
438 | uint32_t p_fetch_addr; | |
94527ead | 439 | |
0122f472 | 440 | USBPacket ipacket; |
0ce668bc | 441 | QEMUSGList isgl; |
0122f472 | 442 | |
adddecb1 | 443 | uint64_t last_run_ns; |
3a215326 | 444 | uint32_t async_stepdown; |
0122f472 | 445 | }; |
94527ead GH |
446 | |
447 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 448 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
449 | |
450 | /* nifty macros from Arnon's EHCI version */ | |
451 | #define get_field(data, field) \ | |
452 | (((data) & field##_MASK) >> field##_SH) | |
453 | ||
454 | #define set_field(data, newval, field) do { \ | |
455 | uint32_t val = *data; \ | |
456 | val &= ~ field##_MASK; \ | |
457 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
458 | *data = val; \ | |
459 | } while(0) | |
460 | ||
26d53979 | 461 | static const char *ehci_state_names[] = { |
aac882e7 GH |
462 | [EST_INACTIVE] = "INACTIVE", |
463 | [EST_ACTIVE] = "ACTIVE", | |
464 | [EST_EXECUTING] = "EXECUTING", | |
465 | [EST_SLEEPING] = "SLEEPING", | |
466 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
467 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
468 | [EST_FETCHQH] = "FETCH QH", | |
469 | [EST_FETCHITD] = "FETCH ITD", | |
470 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
471 | [EST_FETCHQTD] = "FETCH QTD", | |
472 | [EST_EXECUTE] = "EXECUTE", | |
473 | [EST_WRITEBACK] = "WRITEBACK", | |
474 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
475 | }; |
476 | ||
477 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
478 | [USBCMD] = "USBCMD", |
479 | [USBSTS] = "USBSTS", | |
480 | [USBINTR] = "USBINTR", | |
481 | [FRINDEX] = "FRINDEX", | |
482 | [PERIODICLISTBASE] = "P-LIST BASE", | |
483 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
aac882e7 | 484 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 485 | }; |
94527ead | 486 | |
a8cf10d5 HG |
487 | static int ehci_state_executing(EHCIQueue *q); |
488 | static int ehci_state_writeback(EHCIQueue *q); | |
489 | ||
26d53979 | 490 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 491 | { |
26d53979 GH |
492 | if (nr < len && n[nr] != NULL) { |
493 | return n[nr]; | |
94527ead | 494 | } else { |
26d53979 | 495 | return "unknown"; |
94527ead GH |
496 | } |
497 | } | |
94527ead | 498 | |
26d53979 GH |
499 | static const char *state2str(uint32_t state) |
500 | { | |
501 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
502 | } | |
503 | ||
504 | static const char *addr2str(target_phys_addr_t addr) | |
505 | { | |
1f97f6c9 GH |
506 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), |
507 | addr + OPREGBASE); | |
26d53979 GH |
508 | } |
509 | ||
439a97cc GH |
510 | static void ehci_trace_usbsts(uint32_t mask, int state) |
511 | { | |
512 | /* interrupts */ | |
513 | if (mask & USBSTS_INT) { | |
514 | trace_usb_ehci_usbsts("INT", state); | |
515 | } | |
516 | if (mask & USBSTS_ERRINT) { | |
517 | trace_usb_ehci_usbsts("ERRINT", state); | |
518 | } | |
519 | if (mask & USBSTS_PCD) { | |
520 | trace_usb_ehci_usbsts("PCD", state); | |
521 | } | |
522 | if (mask & USBSTS_FLR) { | |
523 | trace_usb_ehci_usbsts("FLR", state); | |
524 | } | |
525 | if (mask & USBSTS_HSE) { | |
526 | trace_usb_ehci_usbsts("HSE", state); | |
527 | } | |
528 | if (mask & USBSTS_IAA) { | |
529 | trace_usb_ehci_usbsts("IAA", state); | |
530 | } | |
531 | ||
532 | /* status */ | |
533 | if (mask & USBSTS_HALT) { | |
534 | trace_usb_ehci_usbsts("HALT", state); | |
535 | } | |
536 | if (mask & USBSTS_REC) { | |
537 | trace_usb_ehci_usbsts("REC", state); | |
538 | } | |
539 | if (mask & USBSTS_PSS) { | |
540 | trace_usb_ehci_usbsts("PSS", state); | |
541 | } | |
542 | if (mask & USBSTS_ASS) { | |
543 | trace_usb_ehci_usbsts("ASS", state); | |
544 | } | |
545 | } | |
546 | ||
547 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
548 | { | |
549 | if ((s->usbsts & mask) == mask) { | |
550 | return; | |
551 | } | |
552 | ehci_trace_usbsts(mask, 1); | |
553 | s->usbsts |= mask; | |
554 | } | |
555 | ||
556 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
557 | { | |
558 | if ((s->usbsts & mask) == 0) { | |
559 | return; | |
560 | } | |
561 | ehci_trace_usbsts(mask, 0); | |
562 | s->usbsts &= ~mask; | |
563 | } | |
94527ead | 564 | |
7efc17af GH |
565 | /* update irq line */ |
566 | static inline void ehci_update_irq(EHCIState *s) | |
94527ead GH |
567 | { |
568 | int level = 0; | |
569 | ||
94527ead GH |
570 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { |
571 | level = 1; | |
572 | } | |
573 | ||
7efc17af | 574 | trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); |
94527ead GH |
575 | qemu_set_irq(s->irq, level); |
576 | } | |
577 | ||
7efc17af GH |
578 | /* flag interrupt condition */ |
579 | static inline void ehci_raise_irq(EHCIState *s, int intr) | |
94527ead | 580 | { |
6d3b6d3d GH |
581 | if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) { |
582 | s->usbsts |= intr; | |
583 | ehci_update_irq(s); | |
584 | } else { | |
585 | s->usbsts_pending |= intr; | |
586 | } | |
94527ead GH |
587 | } |
588 | ||
7efc17af GH |
589 | /* |
590 | * Commit pending interrupts (added via ehci_raise_irq), | |
591 | * at the rate allowed by "Interrupt Threshold Control". | |
592 | */ | |
593 | static inline void ehci_commit_irq(EHCIState *s) | |
94527ead | 594 | { |
7efc17af GH |
595 | uint32_t itc; |
596 | ||
94527ead GH |
597 | if (!s->usbsts_pending) { |
598 | return; | |
599 | } | |
7efc17af GH |
600 | if (s->usbsts_frindex > s->frindex) { |
601 | return; | |
602 | } | |
603 | ||
604 | itc = (s->usbcmd >> 16) & 0xff; | |
605 | s->usbsts |= s->usbsts_pending; | |
94527ead | 606 | s->usbsts_pending = 0; |
7efc17af GH |
607 | s->usbsts_frindex = s->frindex + itc; |
608 | ehci_update_irq(s); | |
94527ead GH |
609 | } |
610 | ||
daf25307 GH |
611 | static void ehci_update_halt(EHCIState *s) |
612 | { | |
613 | if (s->usbcmd & USBCMD_RUNSTOP) { | |
614 | ehci_clear_usbsts(s, USBSTS_HALT); | |
615 | } else { | |
616 | if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { | |
617 | ehci_set_usbsts(s, USBSTS_HALT); | |
618 | } | |
619 | } | |
620 | } | |
621 | ||
26d53979 GH |
622 | static void ehci_set_state(EHCIState *s, int async, int state) |
623 | { | |
624 | if (async) { | |
625 | trace_usb_ehci_state("async", state2str(state)); | |
626 | s->astate = state; | |
b53f685d GH |
627 | if (s->astate == EST_INACTIVE) { |
628 | ehci_clear_usbsts(s, USBSTS_ASS); | |
daf25307 | 629 | ehci_update_halt(s); |
b53f685d GH |
630 | } else { |
631 | ehci_set_usbsts(s, USBSTS_ASS); | |
632 | } | |
26d53979 GH |
633 | } else { |
634 | trace_usb_ehci_state("periodic", state2str(state)); | |
635 | s->pstate = state; | |
b53f685d GH |
636 | if (s->pstate == EST_INACTIVE) { |
637 | ehci_clear_usbsts(s, USBSTS_PSS); | |
daf25307 | 638 | ehci_update_halt(s); |
b53f685d GH |
639 | } else { |
640 | ehci_set_usbsts(s, USBSTS_PSS); | |
641 | } | |
26d53979 GH |
642 | } |
643 | } | |
644 | ||
645 | static int ehci_get_state(EHCIState *s, int async) | |
646 | { | |
647 | return async ? s->astate : s->pstate; | |
648 | } | |
649 | ||
0122f472 GH |
650 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
651 | { | |
652 | if (async) { | |
653 | s->a_fetch_addr = addr; | |
654 | } else { | |
655 | s->p_fetch_addr = addr; | |
656 | } | |
657 | } | |
658 | ||
659 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
660 | { | |
661 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
662 | } | |
663 | ||
8ac6d699 | 664 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 665 | { |
025b168c GH |
666 | /* need three here due to argument count limits */ |
667 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
668 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
669 | trace_usb_ehci_qh_fields(addr, | |
670 | get_field(qh->epchar, QH_EPCHAR_RL), | |
671 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
672 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
673 | get_field(qh->epchar, QH_EPCHAR_EP), | |
674 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
675 | trace_usb_ehci_qh_bits(addr, | |
676 | (bool)(qh->epchar & QH_EPCHAR_C), | |
677 | (bool)(qh->epchar & QH_EPCHAR_H), | |
678 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
679 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
680 | } |
681 | ||
8ac6d699 | 682 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 683 | { |
025b168c GH |
684 | /* need three here due to argument count limits */ |
685 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
686 | trace_usb_ehci_qtd_fields(addr, | |
687 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
688 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
689 | get_field(qtd->token, QTD_TOKEN_CERR), | |
690 | get_field(qtd->token, QTD_TOKEN_PID)); | |
691 | trace_usb_ehci_qtd_bits(addr, | |
692 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
693 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
694 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
695 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
696 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
697 | } |
698 | ||
699 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
700 | { | |
e654887f GH |
701 | trace_usb_ehci_itd(addr, itd->next, |
702 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
703 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
704 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
705 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
706 | } |
707 | ||
2fe80192 GH |
708 | static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
709 | EHCIsitd *sitd) | |
710 | { | |
711 | trace_usb_ehci_sitd(addr, sitd->next, | |
712 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
713 | } | |
714 | ||
62fc5e69 GH |
715 | static void ehci_trace_guest_bug(EHCIState *s, const char *message) |
716 | { | |
717 | trace_usb_ehci_guest_bug(message); | |
718 | fprintf(stderr, "ehci warning: %s\n", message); | |
719 | } | |
720 | ||
ec807d12 GH |
721 | static inline bool ehci_enabled(EHCIState *s) |
722 | { | |
723 | return s->usbcmd & USBCMD_RUNSTOP; | |
724 | } | |
725 | ||
726 | static inline bool ehci_async_enabled(EHCIState *s) | |
727 | { | |
728 | return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); | |
729 | } | |
730 | ||
731 | static inline bool ehci_periodic_enabled(EHCIState *s) | |
732 | { | |
733 | return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); | |
734 | } | |
735 | ||
eb36a88e GH |
736 | /* packet management */ |
737 | ||
738 | static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) | |
739 | { | |
740 | EHCIPacket *p; | |
741 | ||
eb36a88e GH |
742 | p = g_new0(EHCIPacket, 1); |
743 | p->queue = q; | |
744 | usb_packet_init(&p->packet); | |
745 | QTAILQ_INSERT_TAIL(&q->packets, p, next); | |
746 | trace_usb_ehci_packet_action(p->queue, p, "alloc"); | |
747 | return p; | |
748 | } | |
749 | ||
750 | static void ehci_free_packet(EHCIPacket *p) | |
751 | { | |
a8cf10d5 HG |
752 | if (p->async == EHCI_ASYNC_FINISHED) { |
753 | int state = ehci_get_state(p->queue->ehci, p->queue->async); | |
754 | /* This is a normal, but rare condition (cancel racing completion) */ | |
755 | fprintf(stderr, "EHCI: Warning packet completed but not processed\n"); | |
756 | ehci_state_executing(p->queue); | |
757 | ehci_state_writeback(p->queue); | |
758 | ehci_set_state(p->queue->ehci, p->queue->async, state); | |
759 | /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */ | |
760 | return; | |
761 | } | |
4a6cdb48 | 762 | trace_usb_ehci_packet_action(p->queue, p, "free"); |
2f7ba473 HG |
763 | if (p->async == EHCI_ASYNC_INITIALIZED) { |
764 | usb_packet_unmap(&p->packet, &p->sgl); | |
765 | qemu_sglist_destroy(&p->sgl); | |
766 | } | |
4a6cdb48 GH |
767 | if (p->async == EHCI_ASYNC_INFLIGHT) { |
768 | usb_cancel_packet(&p->packet); | |
769 | usb_packet_unmap(&p->packet, &p->sgl); | |
770 | qemu_sglist_destroy(&p->sgl); | |
771 | } | |
eb36a88e GH |
772 | QTAILQ_REMOVE(&p->queue->packets, p, next); |
773 | usb_packet_cleanup(&p->packet); | |
774 | g_free(p); | |
775 | } | |
776 | ||
8ac6d699 GH |
777 | /* queue management */ |
778 | ||
8f6d5e26 | 779 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
8ac6d699 | 780 | { |
df5d5c5c | 781 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
782 | EHCIQueue *q; |
783 | ||
7267c094 | 784 | q = g_malloc0(sizeof(*q)); |
8ac6d699 | 785 | q->ehci = ehci; |
8f6d5e26 | 786 | q->qhaddr = addr; |
ae0138a8 | 787 | q->async = async; |
eb36a88e | 788 | QTAILQ_INIT(&q->packets); |
df5d5c5c | 789 | QTAILQ_INSERT_HEAD(head, q, next); |
8ac6d699 GH |
790 | trace_usb_ehci_queue_action(q, "alloc"); |
791 | return q; | |
792 | } | |
793 | ||
62fc5e69 | 794 | static int ehci_cancel_queue(EHCIQueue *q) |
c7cdca3b GH |
795 | { |
796 | EHCIPacket *p; | |
62fc5e69 | 797 | int packets = 0; |
c7cdca3b GH |
798 | |
799 | p = QTAILQ_FIRST(&q->packets); | |
800 | if (p == NULL) { | |
62fc5e69 | 801 | return 0; |
c7cdca3b GH |
802 | } |
803 | ||
804 | trace_usb_ehci_queue_action(q, "cancel"); | |
805 | do { | |
806 | ehci_free_packet(p); | |
62fc5e69 | 807 | packets++; |
c7cdca3b | 808 | } while ((p = QTAILQ_FIRST(&q->packets)) != NULL); |
62fc5e69 | 809 | return packets; |
c7cdca3b GH |
810 | } |
811 | ||
62fc5e69 | 812 | static int ehci_reset_queue(EHCIQueue *q) |
712fc762 | 813 | { |
62fc5e69 GH |
814 | int packets; |
815 | ||
712fc762 | 816 | trace_usb_ehci_queue_action(q, "reset"); |
62fc5e69 | 817 | packets = ehci_cancel_queue(q); |
712fc762 HG |
818 | q->dev = NULL; |
819 | q->qtdaddr = 0; | |
62fc5e69 | 820 | return packets; |
712fc762 HG |
821 | } |
822 | ||
0154d330 | 823 | static void ehci_free_queue(EHCIQueue *q, const char *warn) |
8ac6d699 | 824 | { |
ae0138a8 | 825 | EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
0154d330 | 826 | int cancelled; |
eb36a88e | 827 | |
8ac6d699 | 828 | trace_usb_ehci_queue_action(q, "free"); |
0154d330 HG |
829 | cancelled = ehci_cancel_queue(q); |
830 | if (warn && cancelled > 0) { | |
831 | ehci_trace_guest_bug(q->ehci, warn); | |
832 | } | |
df5d5c5c | 833 | QTAILQ_REMOVE(head, q, next); |
7267c094 | 834 | g_free(q); |
8ac6d699 GH |
835 | } |
836 | ||
df5d5c5c HG |
837 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, |
838 | int async) | |
8ac6d699 | 839 | { |
df5d5c5c | 840 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
841 | EHCIQueue *q; |
842 | ||
df5d5c5c | 843 | QTAILQ_FOREACH(q, head, next) { |
8ac6d699 GH |
844 | if (addr == q->qhaddr) { |
845 | return q; | |
846 | } | |
847 | } | |
848 | return NULL; | |
849 | } | |
850 | ||
a37d5e52 | 851 | static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush) |
8ac6d699 | 852 | { |
df5d5c5c | 853 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
0154d330 | 854 | const char *warn = (async && !flush) ? "guest unlinked busy QH" : NULL; |
3a215326 | 855 | uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4; |
8ac6d699 GH |
856 | EHCIQueue *q, *tmp; |
857 | ||
df5d5c5c | 858 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
8ac6d699 GH |
859 | if (q->seen) { |
860 | q->seen = 0; | |
adddecb1 | 861 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
862 | continue; |
863 | } | |
a37d5e52 | 864 | if (!flush && ehci->last_run_ns < q->ts + maxage) { |
8ac6d699 GH |
865 | continue; |
866 | } | |
0154d330 | 867 | ehci_free_queue(q, warn); |
8ac6d699 GH |
868 | } |
869 | } | |
870 | ||
df5d5c5c | 871 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
07771f6f | 872 | { |
df5d5c5c | 873 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
07771f6f GH |
874 | EHCIQueue *q, *tmp; |
875 | ||
df5d5c5c | 876 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
e59928b3 | 877 | if (q->dev != dev) { |
07771f6f GH |
878 | continue; |
879 | } | |
0154d330 | 880 | ehci_free_queue(q, NULL); |
07771f6f GH |
881 | } |
882 | } | |
883 | ||
df5d5c5c | 884 | static void ehci_queues_rip_all(EHCIState *ehci, int async) |
8ac6d699 | 885 | { |
df5d5c5c | 886 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
0154d330 | 887 | const char *warn = async ? "guest stopped busy async schedule" : NULL; |
8ac6d699 GH |
888 | EHCIQueue *q, *tmp; |
889 | ||
df5d5c5c | 890 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
0154d330 | 891 | ehci_free_queue(q, warn); |
8ac6d699 GH |
892 | } |
893 | } | |
894 | ||
94527ead GH |
895 | /* Attach or detach a device on root hub */ |
896 | ||
897 | static void ehci_attach(USBPort *port) | |
898 | { | |
899 | EHCIState *s = port->opaque; | |
900 | uint32_t *portsc = &s->portsc[port->index]; | |
30e9d412 | 901 | const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
94527ead | 902 | |
30e9d412 | 903 | trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); |
94527ead | 904 | |
a0a3167a HG |
905 | if (*portsc & PORTSC_POWNER) { |
906 | USBPort *companion = s->companion_ports[port->index]; | |
907 | companion->dev = port->dev; | |
908 | companion->ops->attach(companion); | |
909 | return; | |
910 | } | |
911 | ||
94527ead GH |
912 | *portsc |= PORTSC_CONNECT; |
913 | *portsc |= PORTSC_CSC; | |
914 | ||
7efc17af GH |
915 | ehci_raise_irq(s, USBSTS_PCD); |
916 | ehci_commit_irq(s); | |
94527ead GH |
917 | } |
918 | ||
919 | static void ehci_detach(USBPort *port) | |
920 | { | |
921 | EHCIState *s = port->opaque; | |
922 | uint32_t *portsc = &s->portsc[port->index]; | |
30e9d412 | 923 | const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; |
94527ead | 924 | |
30e9d412 | 925 | trace_usb_ehci_port_detach(port->index, owner); |
94527ead | 926 | |
a0a3167a HG |
927 | if (*portsc & PORTSC_POWNER) { |
928 | USBPort *companion = s->companion_ports[port->index]; | |
929 | companion->ops->detach(companion); | |
930 | companion->dev = NULL; | |
f76e1d81 HG |
931 | /* |
932 | * EHCI spec 4.2.2: "When a disconnect occurs... On the event, | |
933 | * the port ownership is returned immediately to the EHCI controller." | |
934 | */ | |
935 | *portsc &= ~PORTSC_POWNER; | |
a0a3167a HG |
936 | return; |
937 | } | |
938 | ||
df5d5c5c HG |
939 | ehci_queues_rip_device(s, port->dev, 0); |
940 | ehci_queues_rip_device(s, port->dev, 1); | |
4706ab6c | 941 | |
fbd97532 | 942 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
943 | *portsc |= PORTSC_CSC; |
944 | ||
7efc17af GH |
945 | ehci_raise_irq(s, USBSTS_PCD); |
946 | ehci_commit_irq(s); | |
94527ead GH |
947 | } |
948 | ||
4706ab6c HG |
949 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
950 | { | |
951 | EHCIState *s = port->opaque; | |
a0a3167a HG |
952 | uint32_t portsc = s->portsc[port->index]; |
953 | ||
954 | if (portsc & PORTSC_POWNER) { | |
955 | USBPort *companion = s->companion_ports[port->index]; | |
956 | companion->ops->child_detach(companion, child); | |
a0a3167a HG |
957 | return; |
958 | } | |
4706ab6c | 959 | |
df5d5c5c HG |
960 | ehci_queues_rip_device(s, child, 0); |
961 | ehci_queues_rip_device(s, child, 1); | |
4706ab6c HG |
962 | } |
963 | ||
a0a3167a HG |
964 | static void ehci_wakeup(USBPort *port) |
965 | { | |
966 | EHCIState *s = port->opaque; | |
967 | uint32_t portsc = s->portsc[port->index]; | |
968 | ||
969 | if (portsc & PORTSC_POWNER) { | |
970 | USBPort *companion = s->companion_ports[port->index]; | |
971 | if (companion->ops->wakeup) { | |
972 | companion->ops->wakeup(companion); | |
973 | } | |
37952117 | 974 | return; |
a0a3167a | 975 | } |
37952117 HG |
976 | |
977 | qemu_bh_schedule(s->async_bh); | |
a0a3167a HG |
978 | } |
979 | ||
980 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
981 | uint32_t portcount, uint32_t firstport) | |
982 | { | |
983 | EHCIState *s = container_of(bus, EHCIState, bus); | |
984 | uint32_t i; | |
985 | ||
986 | if (firstport + portcount > NB_PORTS) { | |
987 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
988 | "firstport on masterbus"); | |
989 | error_printf_unless_qmp( | |
990 | "firstport value of %u makes companion take ports %u - %u, which " | |
991 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
992 | firstport + portcount - 1, NB_PORTS - 1); | |
993 | return -1; | |
994 | } | |
995 | ||
996 | for (i = 0; i < portcount; i++) { | |
997 | if (s->companion_ports[firstport + i]) { | |
998 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
999 | "an USB masterbus"); | |
1000 | error_printf_unless_qmp( | |
1001 | "port %u on masterbus %s already has a companion assigned\n", | |
1002 | firstport + i, bus->qbus.name); | |
1003 | return -1; | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | for (i = 0; i < portcount; i++) { | |
1008 | s->companion_ports[firstport + i] = ports[i]; | |
1009 | s->ports[firstport + i].speedmask |= | |
1010 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
1011 | /* Ensure devs attached before the initial reset go to the companion */ | |
1012 | s->portsc[firstport + i] = PORTSC_POWNER; | |
1013 | } | |
1014 | ||
1015 | s->companion_count++; | |
1f97f6c9 | 1016 | s->caps[0x05] = (s->companion_count << 4) | portcount; |
a0a3167a HG |
1017 | |
1018 | return 0; | |
1019 | } | |
1020 | ||
828143c6 GH |
1021 | static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) |
1022 | { | |
1023 | USBDevice *dev; | |
1024 | USBPort *port; | |
1025 | int i; | |
1026 | ||
1027 | for (i = 0; i < NB_PORTS; i++) { | |
1028 | port = &ehci->ports[i]; | |
1029 | if (!(ehci->portsc[i] & PORTSC_PED)) { | |
1030 | DPRINTF("Port %d not enabled\n", i); | |
1031 | continue; | |
1032 | } | |
1033 | dev = usb_find_device(port, addr); | |
1034 | if (dev != NULL) { | |
1035 | return dev; | |
1036 | } | |
1037 | } | |
1038 | return NULL; | |
1039 | } | |
1040 | ||
94527ead GH |
1041 | /* 4.1 host controller initialization */ |
1042 | static void ehci_reset(void *opaque) | |
1043 | { | |
1044 | EHCIState *s = opaque; | |
94527ead | 1045 | int i; |
a0a3167a | 1046 | USBDevice *devs[NB_PORTS]; |
94527ead | 1047 | |
439a97cc | 1048 | trace_usb_ehci_reset(); |
94527ead | 1049 | |
a0a3167a HG |
1050 | /* |
1051 | * Do the detach before touching portsc, so that it correctly gets send to | |
1052 | * us or to our companion based on PORTSC_POWNER before the reset. | |
1053 | */ | |
1054 | for(i = 0; i < NB_PORTS; i++) { | |
1055 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
1056 | if (devs[i] && devs[i]->attached) { |
1057 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
1058 | } |
1059 | } | |
1060 | ||
1f97f6c9 GH |
1061 | memset(&s->opreg, 0x00, sizeof(s->opreg)); |
1062 | memset(&s->portsc, 0x00, sizeof(s->portsc)); | |
94527ead GH |
1063 | |
1064 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
1065 | s->usbsts = USBSTS_HALT; | |
7efc17af GH |
1066 | s->usbsts_pending = 0; |
1067 | s->usbsts_frindex = 0; | |
94527ead GH |
1068 | |
1069 | s->astate = EST_INACTIVE; | |
1070 | s->pstate = EST_INACTIVE; | |
94527ead GH |
1071 | |
1072 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
1073 | if (s->companion_ports[i]) { |
1074 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
1075 | } else { | |
1076 | s->portsc[i] = PORTSC_PPOWER; | |
1077 | } | |
891fb2cd GH |
1078 | if (devs[i] && devs[i]->attached) { |
1079 | usb_attach(&s->ports[i]); | |
d28f4e2d | 1080 | usb_device_reset(devs[i]); |
94527ead GH |
1081 | } |
1082 | } | |
df5d5c5c HG |
1083 | ehci_queues_rip_all(s, 0); |
1084 | ehci_queues_rip_all(s, 1); | |
81d37739 | 1085 | qemu_del_timer(s->frame_timer); |
0fb3e299 | 1086 | qemu_bh_cancel(s->async_bh); |
94527ead GH |
1087 | } |
1088 | ||
1f97f6c9 GH |
1089 | static uint64_t ehci_caps_read(void *ptr, target_phys_addr_t addr, |
1090 | unsigned size) | |
94527ead GH |
1091 | { |
1092 | EHCIState *s = ptr; | |
1f97f6c9 | 1093 | return s->caps[addr]; |
94527ead GH |
1094 | } |
1095 | ||
1f97f6c9 GH |
1096 | static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr, |
1097 | unsigned size) | |
94527ead GH |
1098 | { |
1099 | EHCIState *s = ptr; | |
1100 | uint32_t val; | |
1101 | ||
1f97f6c9 GH |
1102 | val = s->opreg[addr >> 2]; |
1103 | trace_usb_ehci_opreg_read(addr + OPREGBASE, addr2str(addr), val); | |
94527ead GH |
1104 | return val; |
1105 | } | |
1106 | ||
1f97f6c9 GH |
1107 | static uint64_t ehci_port_read(void *ptr, target_phys_addr_t addr, |
1108 | unsigned size) | |
94527ead GH |
1109 | { |
1110 | EHCIState *s = ptr; | |
1111 | uint32_t val; | |
1112 | ||
1f97f6c9 GH |
1113 | val = s->portsc[addr >> 2]; |
1114 | trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val); | |
94527ead GH |
1115 | return val; |
1116 | } | |
1117 | ||
a0a3167a HG |
1118 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
1119 | { | |
1120 | USBDevice *dev = s->ports[port].dev; | |
1121 | uint32_t *portsc = &s->portsc[port]; | |
1122 | uint32_t orig; | |
1123 | ||
1124 | if (s->companion_ports[port] == NULL) | |
1125 | return; | |
1126 | ||
1127 | owner = owner & PORTSC_POWNER; | |
1128 | orig = *portsc & PORTSC_POWNER; | |
1129 | ||
1130 | if (!(owner ^ orig)) { | |
1131 | return; | |
1132 | } | |
1133 | ||
891fb2cd GH |
1134 | if (dev && dev->attached) { |
1135 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
1136 | } |
1137 | ||
1138 | *portsc &= ~PORTSC_POWNER; | |
1139 | *portsc |= owner; | |
1140 | ||
891fb2cd GH |
1141 | if (dev && dev->attached) { |
1142 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
1143 | } |
1144 | } | |
1145 | ||
1f97f6c9 GH |
1146 | static void ehci_port_write(void *ptr, target_phys_addr_t addr, |
1147 | uint64_t val, unsigned size) | |
94527ead | 1148 | { |
1f97f6c9 GH |
1149 | EHCIState *s = ptr; |
1150 | int port = addr >> 2; | |
94527ead | 1151 | uint32_t *portsc = &s->portsc[port]; |
1f97f6c9 | 1152 | uint32_t old = *portsc; |
94527ead GH |
1153 | USBDevice *dev = s->ports[port].dev; |
1154 | ||
1f97f6c9 GH |
1155 | trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val); |
1156 | ||
fbd97532 HG |
1157 | /* Clear rwc bits */ |
1158 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
1159 | /* The guest may clear, but not set the PED bit */ | |
1160 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
1161 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
1162 | handle_port_owner_write(s, port, val); | |
1163 | /* And finally apply RO_MASK */ | |
94527ead GH |
1164 | val &= PORTSC_RO_MASK; |
1165 | ||
94527ead | 1166 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 1167 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
1168 | } |
1169 | ||
1170 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 1171 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 1172 | if (dev && dev->attached) { |
d28f4e2d | 1173 | usb_port_reset(&s->ports[port]); |
94527ead GH |
1174 | *portsc &= ~PORTSC_CSC; |
1175 | } | |
1176 | ||
fbd97532 HG |
1177 | /* |
1178 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 1179 | * to SW that this port has a high speed device attached |
94527ead | 1180 | */ |
891fb2cd | 1181 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
1182 | val |= PORTSC_PED; |
1183 | } | |
94527ead GH |
1184 | } |
1185 | ||
1186 | *portsc &= ~PORTSC_RO_MASK; | |
1187 | *portsc |= val; | |
1f97f6c9 | 1188 | trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old); |
94527ead GH |
1189 | } |
1190 | ||
1f97f6c9 GH |
1191 | static void ehci_opreg_write(void *ptr, target_phys_addr_t addr, |
1192 | uint64_t val, unsigned size) | |
94527ead GH |
1193 | { |
1194 | EHCIState *s = ptr; | |
1f97f6c9 | 1195 | uint32_t *mmio = s->opreg + (addr >> 2); |
c4f8e211 | 1196 | uint32_t old = *mmio; |
94527ead | 1197 | int i; |
439a97cc | 1198 | |
1f97f6c9 | 1199 | trace_usb_ehci_opreg_write(addr + OPREGBASE, addr2str(addr), val); |
94527ead | 1200 | |
1f97f6c9 | 1201 | switch (addr + OPREGBASE) { |
94527ead | 1202 | case USBCMD: |
7046530c GH |
1203 | if (val & USBCMD_HCRESET) { |
1204 | ehci_reset(s); | |
1205 | val = s->usbcmd; | |
1206 | break; | |
1207 | } | |
1208 | ||
47d073cc HG |
1209 | /* not supporting dynamic frame list size at the moment */ |
1210 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1211 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1f97f6c9 | 1212 | (int)val & USBCMD_FLS); |
47d073cc HG |
1213 | val &= ~USBCMD_FLS; |
1214 | } | |
1215 | ||
a1c3e4b8 HG |
1216 | if (val & USBCMD_IAAD) { |
1217 | /* | |
1218 | * Process IAAD immediately, otherwise the Linux IAAD watchdog may | |
1219 | * trigger and re-use a qh without us seeing the unlink. | |
1220 | */ | |
1221 | s->async_stepdown = 0; | |
1222 | qemu_bh_schedule(s->async_bh); | |
d294ad63 | 1223 | trace_usb_ehci_doorbell_ring(); |
a1c3e4b8 HG |
1224 | } |
1225 | ||
daf25307 GH |
1226 | if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != |
1227 | ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { | |
3a215326 | 1228 | if (s->pstate == EST_INACTIVE) { |
daf25307 GH |
1229 | SET_LAST_RUN_CLOCK(s); |
1230 | } | |
47d073cc | 1231 | s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */ |
daf25307 | 1232 | ehci_update_halt(s); |
3a215326 GH |
1233 | s->async_stepdown = 0; |
1234 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); | |
94527ead | 1235 | } |
94527ead GH |
1236 | break; |
1237 | ||
94527ead | 1238 | case USBSTS: |
a31f0531 JM |
1239 | val &= USBSTS_RO_MASK; // bits 6 through 31 are RO |
1240 | ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC | |
439a97cc | 1241 | val = s->usbsts; |
7efc17af | 1242 | ehci_update_irq(s); |
94527ead GH |
1243 | break; |
1244 | ||
94527ead GH |
1245 | case USBINTR: |
1246 | val &= USBINTR_MASK; | |
94527ead GH |
1247 | break; |
1248 | ||
8a771f77 HG |
1249 | case FRINDEX: |
1250 | val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ | |
1251 | break; | |
1252 | ||
94527ead | 1253 | case CONFIGFLAG: |
94527ead GH |
1254 | val &= 0x1; |
1255 | if (val) { | |
1256 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 1257 | handle_port_owner_write(s, i, 0); |
94527ead GH |
1258 | } |
1259 | break; | |
1260 | ||
1261 | case PERIODICLISTBASE: | |
ec807d12 | 1262 | if (ehci_periodic_enabled(s)) { |
94527ead GH |
1263 | fprintf(stderr, |
1264 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1265 | " is enabled and HC is enabled\n"); | |
1266 | } | |
94527ead GH |
1267 | break; |
1268 | ||
1269 | case ASYNCLISTADDR: | |
ec807d12 | 1270 | if (ehci_async_enabled(s)) { |
94527ead GH |
1271 | fprintf(stderr, |
1272 | "ehci: ASYNC list address register set while async schedule\n" | |
1273 | " is enabled and HC is enabled\n"); | |
1274 | } | |
94527ead GH |
1275 | break; |
1276 | } | |
1277 | ||
c4f8e211 | 1278 | *mmio = val; |
1f97f6c9 | 1279 | trace_usb_ehci_opreg_change(addr + OPREGBASE, addr2str(addr), *mmio, old); |
94527ead GH |
1280 | } |
1281 | ||
1282 | ||
1283 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1284 | ||
1285 | /* Get an array of dwords from main memory */ | |
68d55358 DG |
1286 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1287 | uint32_t *buf, int num) | |
94527ead GH |
1288 | { |
1289 | int i; | |
1290 | ||
1291 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
4bf80119 | 1292 | pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); |
94527ead GH |
1293 | *buf = le32_to_cpu(*buf); |
1294 | } | |
1295 | ||
1296 | return 1; | |
1297 | } | |
1298 | ||
1299 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1300 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1301 | uint32_t *buf, int num) | |
94527ead GH |
1302 | { |
1303 | int i; | |
1304 | ||
1305 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1306 | uint32_t tmp = cpu_to_le32(*buf); | |
4bf80119 | 1307 | pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); |
94527ead GH |
1308 | } |
1309 | ||
1310 | return 1; | |
1311 | } | |
1312 | ||
a5e0139a GH |
1313 | /* |
1314 | * Write the qh back to guest physical memory. This step isn't | |
1315 | * in the EHCI spec but we need to do it since we don't share | |
1316 | * physical memory with our guest VM. | |
1317 | * | |
1318 | * The first three dwords are read-only for the EHCI, so skip them | |
1319 | * when writing back the qh. | |
1320 | */ | |
1321 | static void ehci_flush_qh(EHCIQueue *q) | |
1322 | { | |
1323 | uint32_t *qh = (uint32_t *) &q->qh; | |
1324 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1325 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1326 | ||
1327 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); | |
1328 | } | |
1329 | ||
94527ead GH |
1330 | // 4.10.2 |
1331 | ||
0122f472 | 1332 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead | 1333 | { |
eb36a88e | 1334 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead GH |
1335 | int i; |
1336 | int dtoggle; | |
1337 | int ping; | |
1338 | int eps; | |
1339 | int reload; | |
1340 | ||
eb36a88e GH |
1341 | assert(p != NULL); |
1342 | assert(p->qtdaddr == q->qtdaddr); | |
1343 | ||
94527ead GH |
1344 | // remember values in fields to preserve in qh after overlay |
1345 | ||
0122f472 GH |
1346 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1347 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1348 | |
eb36a88e GH |
1349 | q->qh.current_qtd = p->qtdaddr; |
1350 | q->qh.next_qtd = p->qtd.next; | |
1351 | q->qh.altnext_qtd = p->qtd.altnext; | |
1352 | q->qh.token = p->qtd.token; | |
94527ead GH |
1353 | |
1354 | ||
0122f472 | 1355 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1356 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1357 | q->qh.token &= ~QTD_TOKEN_PING; |
1358 | q->qh.token |= ping; | |
94527ead GH |
1359 | } |
1360 | ||
0122f472 GH |
1361 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1362 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1363 | |
1364 | for (i = 0; i < 5; i++) { | |
eb36a88e | 1365 | q->qh.bufptr[i] = p->qtd.bufptr[i]; |
94527ead GH |
1366 | } |
1367 | ||
0122f472 | 1368 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1369 | // preserve QH DT bit |
0122f472 GH |
1370 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1371 | q->qh.token |= dtoggle; | |
94527ead GH |
1372 | } |
1373 | ||
0122f472 GH |
1374 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1375 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1376 | |
a5e0139a | 1377 | ehci_flush_qh(q); |
94527ead GH |
1378 | |
1379 | return 0; | |
1380 | } | |
1381 | ||
eb36a88e | 1382 | static int ehci_init_transfer(EHCIPacket *p) |
94527ead | 1383 | { |
0ce668bc | 1384 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1385 | dma_addr_t page; |
94527ead | 1386 | |
eb36a88e GH |
1387 | cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1388 | bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); | |
1389 | offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; | |
1390 | pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); | |
94527ead | 1391 | |
0ce668bc GH |
1392 | while (bytes > 0) { |
1393 | if (cpage > 4) { | |
1394 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1395 | return USB_RET_PROCERR; | |
1396 | } | |
94527ead | 1397 | |
eb36a88e | 1398 | page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
0ce668bc GH |
1399 | page += offset; |
1400 | plen = bytes; | |
1401 | if (plen > 4096 - offset) { | |
1402 | plen = 4096 - offset; | |
1403 | offset = 0; | |
1404 | cpage++; | |
94527ead GH |
1405 | } |
1406 | ||
eb36a88e | 1407 | qemu_sglist_add(&p->sgl, page, plen); |
0ce668bc GH |
1408 | bytes -= plen; |
1409 | } | |
1410 | return 0; | |
1411 | } | |
94527ead | 1412 | |
0ce668bc GH |
1413 | static void ehci_finish_transfer(EHCIQueue *q, int status) |
1414 | { | |
1415 | uint32_t cpage, offset; | |
94527ead | 1416 | |
0ce668bc GH |
1417 | if (status > 0) { |
1418 | /* update cpage & offset */ | |
1419 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1420 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1421 | |
0ce668bc GH |
1422 | offset += status; |
1423 | cpage += offset >> QTD_BUFPTR_SH; | |
1424 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1425 | |
0ce668bc GH |
1426 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1427 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1428 | q->qh.bufptr[0] |= offset; | |
1429 | } | |
94527ead GH |
1430 | } |
1431 | ||
d47e59b8 | 1432 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1433 | { |
eb36a88e | 1434 | EHCIPacket *p; |
a0a3167a HG |
1435 | EHCIState *s = port->opaque; |
1436 | uint32_t portsc = s->portsc[port->index]; | |
1437 | ||
1438 | if (portsc & PORTSC_POWNER) { | |
1439 | USBPort *companion = s->companion_ports[port->index]; | |
1440 | companion->ops->complete(companion, packet); | |
1441 | return; | |
1442 | } | |
94527ead | 1443 | |
eb36a88e GH |
1444 | p = container_of(packet, EHCIPacket, packet); |
1445 | trace_usb_ehci_packet_action(p->queue, p, "wakeup"); | |
1446 | assert(p->async == EHCI_ASYNC_INFLIGHT); | |
1447 | p->async = EHCI_ASYNC_FINISHED; | |
1448 | p->usb_status = packet->result; | |
ae710b99 GH |
1449 | |
1450 | if (p->queue->async) { | |
1451 | qemu_bh_schedule(p->queue->ehci->async_bh); | |
1452 | } | |
94527ead GH |
1453 | } |
1454 | ||
0122f472 | 1455 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead | 1456 | { |
eb36a88e GH |
1457 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1458 | ||
1459 | assert(p != NULL); | |
1460 | assert(p->qtdaddr == q->qtdaddr); | |
2f7ba473 HG |
1461 | assert(p->async == EHCI_ASYNC_INITIALIZED || |
1462 | p->async == EHCI_ASYNC_FINISHED); | |
94527ead GH |
1463 | |
1464 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1465 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1466 | |
eb36a88e GH |
1467 | if (p->usb_status < 0) { |
1468 | switch (p->usb_status) { | |
d61000a8 | 1469 | case USB_RET_IOERROR: |
94527ead | 1470 | case USB_RET_NODEV: |
d2bd525f | 1471 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
dd54cfe0 | 1472 | set_field(&q->qh.token, 0, QTD_TOKEN_CERR); |
7efc17af | 1473 | ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1474 | break; |
1475 | case USB_RET_STALL: | |
0122f472 | 1476 | q->qh.token |= QTD_TOKEN_HALT; |
7efc17af | 1477 | ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1478 | break; |
1479 | case USB_RET_NAK: | |
553a6a59 HG |
1480 | set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); |
1481 | return; /* We're not done yet with this transaction */ | |
94527ead | 1482 | case USB_RET_BABBLE: |
d2bd525f | 1483 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
7efc17af | 1484 | ehci_raise_irq(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1485 | break; |
1486 | default: | |
0122f472 | 1487 | /* should not be triggerable */ |
eb36a88e | 1488 | fprintf(stderr, "USB invalid response %d\n", p->usb_status); |
0122f472 | 1489 | assert(0); |
94527ead GH |
1490 | break; |
1491 | } | |
1492 | } else { | |
94527ead GH |
1493 | // TODO check 4.12 for splits |
1494 | ||
eb36a88e GH |
1495 | if (p->tbytes && p->pid == USB_TOKEN_IN) { |
1496 | p->tbytes -= p->usb_status; | |
94527ead | 1497 | } else { |
eb36a88e | 1498 | p->tbytes = 0; |
94527ead GH |
1499 | } |
1500 | ||
eb36a88e GH |
1501 | DPRINTF("updating tbytes to %d\n", p->tbytes); |
1502 | set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); | |
94527ead | 1503 | } |
eb36a88e | 1504 | ehci_finish_transfer(q, p->usb_status); |
e2f89926 | 1505 | usb_packet_unmap(&p->packet, &p->sgl); |
eb36a88e | 1506 | qemu_sglist_destroy(&p->sgl); |
2f7ba473 | 1507 | p->async = EHCI_ASYNC_NONE; |
94527ead | 1508 | |
0122f472 GH |
1509 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1510 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1511 | |
553a6a59 | 1512 | if (q->qh.token & QTD_TOKEN_IOC) { |
7efc17af | 1513 | ehci_raise_irq(q->ehci, USBSTS_INT); |
94527ead | 1514 | } |
94527ead GH |
1515 | } |
1516 | ||
1517 | // 4.10.3 | |
1518 | ||
773dc9cd | 1519 | static int ehci_execute(EHCIPacket *p, const char *action) |
94527ead | 1520 | { |
079d0b7f | 1521 | USBEndpoint *ep; |
94527ead | 1522 | int ret; |
94527ead | 1523 | int endp; |
94527ead | 1524 | |
2f7ba473 HG |
1525 | assert(p->async == EHCI_ASYNC_NONE || |
1526 | p->async == EHCI_ASYNC_INITIALIZED); | |
1527 | ||
4224558f GH |
1528 | if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { |
1529 | fprintf(stderr, "Attempting to execute inactive qtd\n"); | |
94527ead GH |
1530 | return USB_RET_PROCERR; |
1531 | } | |
1532 | ||
4224558f | 1533 | p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
eb36a88e | 1534 | if (p->tbytes > BUFF_SIZE) { |
0154d330 HG |
1535 | ehci_trace_guest_bug(p->queue->ehci, |
1536 | "guest requested more bytes than allowed"); | |
94527ead GH |
1537 | return USB_RET_PROCERR; |
1538 | } | |
1539 | ||
4224558f | 1540 | p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
eb36a88e GH |
1541 | switch (p->pid) { |
1542 | case 0: | |
1543 | p->pid = USB_TOKEN_OUT; | |
1544 | break; | |
1545 | case 1: | |
1546 | p->pid = USB_TOKEN_IN; | |
1547 | break; | |
1548 | case 2: | |
1549 | p->pid = USB_TOKEN_SETUP; | |
1550 | break; | |
1551 | default: | |
1552 | fprintf(stderr, "bad token\n"); | |
1553 | break; | |
94527ead GH |
1554 | } |
1555 | ||
4224558f | 1556 | endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
e59928b3 | 1557 | ep = usb_ep_get(p->queue->dev, p->pid, endp); |
94527ead | 1558 | |
2f7ba473 HG |
1559 | if (p->async == EHCI_ASYNC_NONE) { |
1560 | if (ehci_init_transfer(p) != 0) { | |
1561 | return USB_RET_PROCERR; | |
1562 | } | |
1563 | ||
1564 | usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr); | |
1565 | usb_packet_map(&p->packet, &p->sgl); | |
1566 | p->async = EHCI_ASYNC_INITIALIZED; | |
1567 | } | |
0ce668bc | 1568 | |
773dc9cd | 1569 | trace_usb_ehci_packet_action(p->queue, p, action); |
e59928b3 | 1570 | ret = usb_handle_packet(p->queue->dev, &p->packet); |
828143c6 GH |
1571 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " |
1572 | "(total %d) endp %x ret %d\n", | |
1573 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, | |
1574 | q->packet.iov.size, q->tbytes, endp, ret); | |
94527ead GH |
1575 | |
1576 | if (ret > BUFF_SIZE) { | |
1577 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1578 | return USB_RET_PROCERR; | |
1579 | } | |
1580 | ||
94527ead GH |
1581 | return ret; |
1582 | } | |
1583 | ||
1584 | /* 4.7.2 | |
1585 | */ | |
1586 | ||
1587 | static int ehci_process_itd(EHCIState *ehci, | |
e983395d GH |
1588 | EHCIitd *itd, |
1589 | uint32_t addr) | |
94527ead | 1590 | { |
94527ead | 1591 | USBDevice *dev; |
079d0b7f | 1592 | USBEndpoint *ep; |
94527ead | 1593 | int ret; |
828143c6 | 1594 | uint32_t i, len, pid, dir, devaddr, endp; |
e654887f | 1595 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead GH |
1596 | |
1597 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1598 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1599 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1600 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1601 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1602 | |
1603 | for(i = 0; i < 8; i++) { | |
1604 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1605 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1606 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1607 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1608 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1609 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1610 | ||
1611 | if (len > max * mult) { | |
1612 | len = max * mult; | |
1613 | } | |
94527ead GH |
1614 | |
1615 | if (len > BUFF_SIZE) { | |
1616 | return USB_RET_PROCERR; | |
1617 | } | |
1618 | ||
68d55358 | 1619 | pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); |
e654887f GH |
1620 | if (off + len > 4096) { |
1621 | /* transfer crosses page border */ | |
0ce668bc GH |
1622 | uint32_t len2 = off + len - 4096; |
1623 | uint32_t len1 = len - len2; | |
1624 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1625 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1626 | } else { |
0ce668bc | 1627 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1628 | } |
94527ead | 1629 | |
0ce668bc | 1630 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1631 | |
079d0b7f GH |
1632 | dev = ehci_find_device(ehci, devaddr); |
1633 | ep = usb_ep_get(dev, pid, endp); | |
7ce86aa1 | 1634 | if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { |
e983395d | 1635 | usb_packet_setup(&ehci->ipacket, pid, ep, addr); |
aa0568ff GH |
1636 | usb_packet_map(&ehci->ipacket, &ehci->isgl); |
1637 | ret = usb_handle_packet(dev, &ehci->ipacket); | |
1638 | assert(ret != USB_RET_ASYNC); | |
e2f89926 | 1639 | usb_packet_unmap(&ehci->ipacket, &ehci->isgl); |
aa0568ff GH |
1640 | } else { |
1641 | DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); | |
1642 | ret = USB_RET_NAK; | |
1643 | } | |
0ce668bc GH |
1644 | qemu_sglist_destroy(&ehci->isgl); |
1645 | ||
5eafd438 | 1646 | if (ret < 0) { |
df787185 HG |
1647 | switch (ret) { |
1648 | default: | |
1649 | fprintf(stderr, "Unexpected iso usb result: %d\n", ret); | |
1650 | /* Fall through */ | |
d61000a8 | 1651 | case USB_RET_IOERROR: |
df787185 HG |
1652 | case USB_RET_NODEV: |
1653 | /* 3.3.2: XACTERR is only allowed on IN transactions */ | |
1654 | if (dir) { | |
1655 | itd->transact[i] |= ITD_XACT_XACTERR; | |
7efc17af | 1656 | ehci_raise_irq(ehci, USBSTS_ERRINT); |
df787185 HG |
1657 | } |
1658 | break; | |
1659 | case USB_RET_BABBLE: | |
1660 | itd->transact[i] |= ITD_XACT_BABBLE; | |
7efc17af | 1661 | ehci_raise_irq(ehci, USBSTS_ERRINT); |
df787185 | 1662 | break; |
5eafd438 HG |
1663 | case USB_RET_NAK: |
1664 | /* no data for us, so do a zero-length transfer */ | |
1665 | ret = 0; | |
1666 | break; | |
1667 | } | |
1668 | } | |
1669 | if (ret >= 0) { | |
1670 | if (!dir) { | |
1671 | /* OUT */ | |
1672 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1673 | } else { | |
1674 | /* IN */ | |
1675 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
94527ead GH |
1676 | } |
1677 | } | |
df787185 | 1678 | if (itd->transact[i] & ITD_XACT_IOC) { |
7efc17af | 1679 | ehci_raise_irq(ehci, USBSTS_INT); |
df787185 | 1680 | } |
e654887f | 1681 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1682 | } |
1683 | } | |
1684 | return 0; | |
1685 | } | |
1686 | ||
cd665715 | 1687 | |
94527ead GH |
1688 | /* This state is the entry point for asynchronous schedule |
1689 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1690 | */ | |
26d53979 | 1691 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1692 | { |
0122f472 | 1693 | EHCIqh qh; |
94527ead GH |
1694 | int i = 0; |
1695 | int again = 0; | |
1696 | uint32_t entry = ehci->asynclistaddr; | |
1697 | ||
1698 | /* set reclamation flag at start event (4.8.6) */ | |
1699 | if (async) { | |
439a97cc | 1700 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1701 | } |
1702 | ||
a37d5e52 | 1703 | ehci_queues_rip_unused(ehci, async, 0); |
8ac6d699 | 1704 | |
94527ead GH |
1705 | /* Find the head of the list (4.9.1.1) */ |
1706 | for(i = 0; i < MAX_QH; i++) { | |
68d55358 DG |
1707 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1708 | sizeof(EHCIqh) >> 2); | |
8ac6d699 | 1709 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1710 | |
0122f472 | 1711 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1712 | if (async) { |
1713 | entry |= (NLPTR_TYPE_QH << 1); | |
1714 | } | |
1715 | ||
0122f472 | 1716 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1717 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1718 | again = 1; |
1719 | goto out; | |
1720 | } | |
1721 | ||
0122f472 | 1722 | entry = qh.next; |
94527ead | 1723 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1724 | break; |
1725 | } | |
1726 | } | |
1727 | ||
1728 | /* no head found for list. */ | |
1729 | ||
26d53979 | 1730 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1731 | |
1732 | out: | |
1733 | return again; | |
1734 | } | |
1735 | ||
1736 | ||
1737 | /* This state is the entry point for periodic schedule processing as | |
1738 | * well as being a continuation state for async processing. | |
1739 | */ | |
26d53979 | 1740 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1741 | { |
1742 | int again = 0; | |
0122f472 | 1743 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1744 | |
2a5ff735 | 1745 | if (NLPTR_TBIT(entry)) { |
26d53979 | 1746 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1747 | goto out; |
1748 | } | |
1749 | ||
1750 | /* section 4.8, only QH in async schedule */ | |
1751 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1752 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1753 | return -1; | |
1754 | } | |
1755 | ||
1756 | switch (NLPTR_TYPE_GET(entry)) { | |
1757 | case NLPTR_TYPE_QH: | |
26d53979 | 1758 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1759 | again = 1; |
1760 | break; | |
1761 | ||
1762 | case NLPTR_TYPE_ITD: | |
26d53979 | 1763 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1764 | again = 1; |
1765 | break; | |
1766 | ||
2fe80192 GH |
1767 | case NLPTR_TYPE_STITD: |
1768 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1769 | again = 1; | |
1770 | break; | |
1771 | ||
94527ead | 1772 | default: |
2fe80192 | 1773 | /* TODO: handle FSTN type */ |
94527ead GH |
1774 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1775 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1776 | return -1; | |
1777 | } | |
1778 | ||
1779 | out: | |
1780 | return again; | |
1781 | } | |
1782 | ||
0122f472 | 1783 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1784 | { |
eb36a88e | 1785 | EHCIPacket *p; |
712fc762 | 1786 | uint32_t entry, devaddr, endp; |
0122f472 | 1787 | EHCIQueue *q; |
712fc762 | 1788 | EHCIqh qh; |
94527ead | 1789 | |
0122f472 | 1790 | entry = ehci_get_fetch_addr(ehci, async); |
df5d5c5c | 1791 | q = ehci_find_queue_by_qh(ehci, entry, async); |
8ac6d699 | 1792 | if (NULL == q) { |
8f6d5e26 | 1793 | q = ehci_alloc_queue(ehci, entry, async); |
8ac6d699 | 1794 | } |
eb36a88e | 1795 | p = QTAILQ_FIRST(&q->packets); |
8ac6d699 | 1796 | |
8f6d5e26 | 1797 | q->seen++; |
8ac6d699 GH |
1798 | if (q->seen > 1) { |
1799 | /* we are going in circles -- stop processing */ | |
1800 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1801 | q = NULL; | |
1802 | goto out; | |
1803 | } | |
94527ead | 1804 | |
68d55358 | 1805 | get_dwords(ehci, NLPTR_GET(q->qhaddr), |
712fc762 HG |
1806 | (uint32_t *) &qh, sizeof(EHCIqh) >> 2); |
1807 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); | |
1808 | ||
1809 | /* | |
1810 | * The overlay area of the qh should never be changed by the guest, | |
1811 | * except when idle, in which case the reset is a nop. | |
1812 | */ | |
1813 | devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR); | |
1814 | endp = get_field(qh.epchar, QH_EPCHAR_EP); | |
1815 | if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) || | |
1816 | (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || | |
1817 | (memcmp(&qh.current_qtd, &q->qh.current_qtd, | |
1818 | 9 * sizeof(uint32_t)) != 0) || | |
1819 | (q->dev != NULL && q->dev->addr != devaddr)) { | |
62fc5e69 GH |
1820 | if (ehci_reset_queue(q) > 0) { |
1821 | ehci_trace_guest_bug(ehci, "guest updated active QH"); | |
1822 | } | |
712fc762 HG |
1823 | p = NULL; |
1824 | } | |
1825 | q->qh = qh; | |
1826 | ||
e59928b3 GH |
1827 | if (q->dev == NULL) { |
1828 | q->dev = ehci_find_device(q->ehci, devaddr); | |
1829 | } | |
1830 | ||
eb36a88e | 1831 | if (p && p->async == EHCI_ASYNC_FINISHED) { |
8ac6d699 | 1832 | /* I/O finished -- continue processing queue */ |
773dc9cd | 1833 | trace_usb_ehci_packet_action(p->queue, p, "complete"); |
8ac6d699 GH |
1834 | ehci_set_state(ehci, async, EST_EXECUTING); |
1835 | goto out; | |
1836 | } | |
0122f472 GH |
1837 | |
1838 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1839 | |
1840 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1841 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1842 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1843 | } else { |
1844 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1845 | " - done processing\n", q->qhaddr); |
26d53979 | 1846 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1847 | q = NULL; |
94527ead GH |
1848 | goto out; |
1849 | } | |
1850 | } | |
1851 | ||
1852 | #if EHCI_DEBUG | |
0122f472 | 1853 | if (q->qhaddr != q->qh.next) { |
94527ead | 1854 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1855 | q->qhaddr, |
1856 | q->qh.epchar & QH_EPCHAR_H, | |
1857 | q->qh.token & QTD_TOKEN_HALT, | |
1858 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1859 | q->qh.next); | |
94527ead GH |
1860 | } |
1861 | #endif | |
1862 | ||
0122f472 | 1863 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1864 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1865 | |
2a5ff735 HG |
1866 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1867 | (NLPTR_TBIT(q->qh.current_qtd) == 0)) { | |
0122f472 | 1868 | q->qtdaddr = q->qh.current_qtd; |
26d53979 | 1869 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1870 | |
1871 | } else { | |
1872 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1873 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1874 | } |
1875 | ||
1876 | out: | |
0122f472 | 1877 | return q; |
94527ead GH |
1878 | } |
1879 | ||
26d53979 | 1880 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1881 | { |
0122f472 | 1882 | uint32_t entry; |
94527ead GH |
1883 | EHCIitd itd; |
1884 | ||
0122f472 GH |
1885 | assert(!async); |
1886 | entry = ehci_get_fetch_addr(ehci, async); | |
1887 | ||
68d55358 | 1888 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1889 | sizeof(EHCIitd) >> 2); |
0122f472 | 1890 | ehci_trace_itd(ehci, entry, &itd); |
94527ead | 1891 | |
e983395d | 1892 | if (ehci_process_itd(ehci, &itd, entry) != 0) { |
94527ead GH |
1893 | return -1; |
1894 | } | |
1895 | ||
68d55358 DG |
1896 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1897 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1898 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1899 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1900 | |
1901 | return 1; | |
1902 | } | |
1903 | ||
2fe80192 GH |
1904 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1905 | { | |
1906 | uint32_t entry; | |
1907 | EHCIsitd sitd; | |
1908 | ||
1909 | assert(!async); | |
1910 | entry = ehci_get_fetch_addr(ehci, async); | |
1911 | ||
68d55358 | 1912 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
2fe80192 GH |
1913 | sizeof(EHCIsitd) >> 2); |
1914 | ehci_trace_sitd(ehci, entry, &sitd); | |
1915 | ||
1916 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1917 | /* siTD is not active, nothing to do */; | |
1918 | } else { | |
1919 | /* TODO: split transfers are not implemented */ | |
1920 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1921 | } | |
1922 | ||
1923 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1924 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1925 | return 1; | |
1926 | } | |
1927 | ||
94527ead | 1928 | /* Section 4.10.2 - paragraph 3 */ |
ae0138a8 | 1929 | static int ehci_state_advqueue(EHCIQueue *q) |
94527ead GH |
1930 | { |
1931 | #if 0 | |
1932 | /* TO-DO: 4.10.2 - paragraph 2 | |
1933 | * if I-bit is set to 1 and QH is not active | |
1934 | * go to horizontal QH | |
1935 | */ | |
1936 | if (I-bit set) { | |
26d53979 | 1937 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1938 | goto out; |
1939 | } | |
1940 | #endif | |
1941 | ||
1942 | /* | |
1943 | * want data and alt-next qTD is valid | |
1944 | */ | |
0122f472 | 1945 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
0122f472 GH |
1946 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { |
1947 | q->qtdaddr = q->qh.altnext_qtd; | |
ae0138a8 | 1948 | ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
94527ead GH |
1949 | |
1950 | /* | |
1951 | * next qTD is valid | |
1952 | */ | |
2a5ff735 | 1953 | } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
0122f472 | 1954 | q->qtdaddr = q->qh.next_qtd; |
ae0138a8 | 1955 | ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
94527ead GH |
1956 | |
1957 | /* | |
1958 | * no valid qTD, try next QH | |
1959 | */ | |
1960 | } else { | |
ae0138a8 | 1961 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead GH |
1962 | } |
1963 | ||
1964 | return 1; | |
1965 | } | |
1966 | ||
1967 | /* Section 4.10.2 - paragraph 4 */ | |
ae0138a8 | 1968 | static int ehci_state_fetchqtd(EHCIQueue *q) |
94527ead | 1969 | { |
eb36a88e GH |
1970 | EHCIqtd qtd; |
1971 | EHCIPacket *p; | |
94527ead GH |
1972 | int again = 0; |
1973 | ||
eb36a88e | 1974 | get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
68d55358 | 1975 | sizeof(EHCIqtd) >> 2); |
eb36a88e | 1976 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
94527ead | 1977 | |
773dc9cd | 1978 | p = QTAILQ_FIRST(&q->packets); |
773dc9cd | 1979 | if (p != NULL) { |
287fd3f1 GH |
1980 | if (p->qtdaddr != q->qtdaddr || |
1981 | (!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) || | |
1982 | (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) || | |
1983 | p->qtd.bufptr[0] != qtd.bufptr[0]) { | |
287fd3f1 | 1984 | ehci_cancel_queue(q); |
62fc5e69 | 1985 | ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD"); |
287fd3f1 GH |
1986 | p = NULL; |
1987 | } else { | |
1988 | p->qtd = qtd; | |
1989 | ehci_qh_do_overlay(q); | |
1990 | } | |
1991 | } | |
1992 | ||
1993 | if (!(qtd.token & QTD_TOKEN_ACTIVE)) { | |
1994 | if (p != NULL) { | |
1995 | /* transfer canceled by guest (clear active) */ | |
1996 | ehci_cancel_queue(q); | |
1997 | p = NULL; | |
1998 | } | |
1999 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); | |
2000 | again = 1; | |
2001 | } else if (p != NULL) { | |
adf47834 HG |
2002 | switch (p->async) { |
2003 | case EHCI_ASYNC_NONE: | |
2f7ba473 HG |
2004 | /* Should never happen packet should at least be initialized */ |
2005 | assert(0); | |
2006 | break; | |
2007 | case EHCI_ASYNC_INITIALIZED: | |
adf47834 | 2008 | /* Previously nacked packet (likely interrupt ep) */ |
2f7ba473 HG |
2009 | ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
2010 | break; | |
adf47834 | 2011 | case EHCI_ASYNC_INFLIGHT: |
2f7ba473 | 2012 | /* Unfinished async handled packet, go horizontal */ |
ae0138a8 | 2013 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
adf47834 HG |
2014 | break; |
2015 | case EHCI_ASYNC_FINISHED: | |
77c3d592 HG |
2016 | /* |
2017 | * We get here when advqueue moves to a packet which is already | |
2018 | * finished, which can happen with packets queued up by fill_queue | |
2019 | */ | |
ae0138a8 | 2020 | ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
adf47834 | 2021 | break; |
773dc9cd GH |
2022 | } |
2023 | again = 1; | |
287fd3f1 | 2024 | } else { |
eb36a88e GH |
2025 | p = ehci_alloc_packet(q); |
2026 | p->qtdaddr = q->qtdaddr; | |
2027 | p->qtd = qtd; | |
ae0138a8 | 2028 | ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
94527ead | 2029 | again = 1; |
94527ead GH |
2030 | } |
2031 | ||
2032 | return again; | |
2033 | } | |
2034 | ||
ae0138a8 | 2035 | static int ehci_state_horizqh(EHCIQueue *q) |
94527ead GH |
2036 | { |
2037 | int again = 0; | |
2038 | ||
ae0138a8 GH |
2039 | if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { |
2040 | ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); | |
2041 | ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); | |
94527ead GH |
2042 | again = 1; |
2043 | } else { | |
ae0138a8 | 2044 | ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
94527ead GH |
2045 | } |
2046 | ||
2047 | return again; | |
2048 | } | |
2049 | ||
e2ab86fe | 2050 | static int ehci_fill_queue(EHCIPacket *p) |
773dc9cd GH |
2051 | { |
2052 | EHCIQueue *q = p->queue; | |
2053 | EHCIqtd qtd = p->qtd; | |
2054 | uint32_t qtdaddr; | |
2055 | ||
2056 | for (;;) { | |
2057 | if (NLPTR_TBIT(qtd.altnext) == 0) { | |
2058 | break; | |
2059 | } | |
2060 | if (NLPTR_TBIT(qtd.next) != 0) { | |
2061 | break; | |
2062 | } | |
2063 | qtdaddr = qtd.next; | |
2064 | get_dwords(q->ehci, NLPTR_GET(qtdaddr), | |
2065 | (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); | |
2066 | ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); | |
2067 | if (!(qtd.token & QTD_TOKEN_ACTIVE)) { | |
2068 | break; | |
2069 | } | |
2070 | p = ehci_alloc_packet(q); | |
2071 | p->qtdaddr = qtdaddr; | |
2072 | p->qtd = qtd; | |
2073 | p->usb_status = ehci_execute(p, "queue"); | |
e2ab86fe HG |
2074 | if (p->usb_status == USB_RET_PROCERR) { |
2075 | break; | |
2076 | } | |
df6839c7 | 2077 | assert(p->usb_status == USB_RET_ASYNC); |
773dc9cd GH |
2078 | p->async = EHCI_ASYNC_INFLIGHT; |
2079 | } | |
e2ab86fe | 2080 | return p->usb_status; |
773dc9cd GH |
2081 | } |
2082 | ||
ae0138a8 | 2083 | static int ehci_state_execute(EHCIQueue *q) |
94527ead | 2084 | { |
eb36a88e | 2085 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 2086 | int again = 0; |
94527ead | 2087 | |
eb36a88e GH |
2088 | assert(p != NULL); |
2089 | assert(p->qtdaddr == q->qtdaddr); | |
2090 | ||
0122f472 | 2091 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
2092 | return -1; |
2093 | } | |
2094 | ||
94527ead GH |
2095 | // TODO verify enough time remains in the uframe as in 4.4.1.1 |
2096 | // TODO write back ptr to async list when done or out of time | |
2097 | // TODO Windows does not seem to ever set the MULT field | |
2098 | ||
ae0138a8 | 2099 | if (!q->async) { |
0122f472 | 2100 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 2101 | if (!transactCtr) { |
ae0138a8 | 2102 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead GH |
2103 | again = 1; |
2104 | goto out; | |
2105 | } | |
2106 | } | |
2107 | ||
ae0138a8 | 2108 | if (q->async) { |
0122f472 | 2109 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
2110 | } |
2111 | ||
773dc9cd | 2112 | p->usb_status = ehci_execute(p, "process"); |
eb36a88e | 2113 | if (p->usb_status == USB_RET_PROCERR) { |
94527ead GH |
2114 | again = -1; |
2115 | goto out; | |
2116 | } | |
eb36a88e | 2117 | if (p->usb_status == USB_RET_ASYNC) { |
8ac6d699 | 2118 | ehci_flush_qh(q); |
773dc9cd | 2119 | trace_usb_ehci_packet_action(p->queue, p, "async"); |
eb36a88e | 2120 | p->async = EHCI_ASYNC_INFLIGHT; |
ae0138a8 | 2121 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
e2ab86fe | 2122 | again = (ehci_fill_queue(p) == USB_RET_PROCERR) ? -1 : 1; |
8ac6d699 | 2123 | goto out; |
94527ead GH |
2124 | } |
2125 | ||
ae0138a8 | 2126 | ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
8ac6d699 GH |
2127 | again = 1; |
2128 | ||
94527ead GH |
2129 | out: |
2130 | return again; | |
2131 | } | |
2132 | ||
ae0138a8 | 2133 | static int ehci_state_executing(EHCIQueue *q) |
94527ead | 2134 | { |
eb36a88e | 2135 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 2136 | |
eb36a88e GH |
2137 | assert(p != NULL); |
2138 | assert(p->qtdaddr == q->qtdaddr); | |
2139 | ||
0122f472 | 2140 | ehci_execute_complete(q); |
94527ead GH |
2141 | |
2142 | // 4.10.3 | |
ae0138a8 | 2143 | if (!q->async) { |
0122f472 | 2144 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 2145 | transactCtr--; |
0122f472 | 2146 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
2147 | // 4.10.3, bottom of page 82, should exit this state when transaction |
2148 | // counter decrements to 0 | |
2149 | } | |
2150 | ||
94527ead | 2151 | /* 4.10.5 */ |
eb36a88e | 2152 | if (p->usb_status == USB_RET_NAK) { |
ae0138a8 | 2153 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead | 2154 | } else { |
ae0138a8 | 2155 | ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
94527ead GH |
2156 | } |
2157 | ||
8ac6d699 | 2158 | ehci_flush_qh(q); |
574ef171 | 2159 | return 1; |
94527ead GH |
2160 | } |
2161 | ||
2162 | ||
ae0138a8 | 2163 | static int ehci_state_writeback(EHCIQueue *q) |
94527ead | 2164 | { |
eb36a88e | 2165 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
4ed1c57a | 2166 | uint32_t *qtd, addr; |
94527ead GH |
2167 | int again = 0; |
2168 | ||
2169 | /* Write back the QTD from the QH area */ | |
eb36a88e GH |
2170 | assert(p != NULL); |
2171 | assert(p->qtdaddr == q->qtdaddr); | |
2172 | ||
2173 | ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); | |
4ed1c57a GH |
2174 | qtd = (uint32_t *) &q->qh.next_qtd; |
2175 | addr = NLPTR_GET(p->qtdaddr); | |
2176 | put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); | |
eb36a88e | 2177 | ehci_free_packet(p); |
94527ead | 2178 | |
d2bd525f GH |
2179 | /* |
2180 | * EHCI specs say go horizontal here. | |
2181 | * | |
2182 | * We can also advance the queue here for performance reasons. We | |
2183 | * need to take care to only take that shortcut in case we've | |
2184 | * processed the qtd just written back without errors, i.e. halt | |
2185 | * bit is clear. | |
94527ead | 2186 | */ |
d2bd525f | 2187 | if (q->qh.token & QTD_TOKEN_HALT) { |
0132b4b6 HG |
2188 | /* |
2189 | * We should not do any further processing on a halted queue! | |
2190 | * This is esp. important for bulk endpoints with pipelining enabled | |
2191 | * (redirection to a real USB device), where we must cancel all the | |
2192 | * transfers after this one so that: | |
2193 | * 1) If they've completed already, they are not processed further | |
2194 | * causing more stalls, originating from the same failed transfer | |
2195 | * 2) If still in flight, they are cancelled before the guest does | |
2196 | * a clear stall, otherwise the guest and device can loose sync! | |
2197 | */ | |
2198 | while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { | |
2199 | ehci_free_packet(p); | |
2200 | } | |
ae0138a8 | 2201 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
d2bd525f GH |
2202 | again = 1; |
2203 | } else { | |
ae0138a8 | 2204 | ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
94527ead | 2205 | again = 1; |
d2bd525f | 2206 | } |
94527ead GH |
2207 | return again; |
2208 | } | |
2209 | ||
2210 | /* | |
2211 | * This is the state machine that is common to both async and periodic | |
2212 | */ | |
2213 | ||
ae0138a8 | 2214 | static void ehci_advance_state(EHCIState *ehci, int async) |
94527ead | 2215 | { |
0122f472 | 2216 | EHCIQueue *q = NULL; |
94527ead | 2217 | int again; |
94527ead GH |
2218 | |
2219 | do { | |
26d53979 | 2220 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2221 | case EST_WAITLISTHEAD: |
26d53979 | 2222 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
2223 | break; |
2224 | ||
2225 | case EST_FETCHENTRY: | |
26d53979 | 2226 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
2227 | break; |
2228 | ||
2229 | case EST_FETCHQH: | |
0122f472 | 2230 | q = ehci_state_fetchqh(ehci, async); |
ae0138a8 GH |
2231 | if (q != NULL) { |
2232 | assert(q->async == async); | |
2233 | again = 1; | |
2234 | } else { | |
2235 | again = 0; | |
2236 | } | |
94527ead GH |
2237 | break; |
2238 | ||
2239 | case EST_FETCHITD: | |
26d53979 | 2240 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
2241 | break; |
2242 | ||
2fe80192 GH |
2243 | case EST_FETCHSITD: |
2244 | again = ehci_state_fetchsitd(ehci, async); | |
2245 | break; | |
2246 | ||
94527ead | 2247 | case EST_ADVANCEQUEUE: |
ae0138a8 | 2248 | again = ehci_state_advqueue(q); |
94527ead GH |
2249 | break; |
2250 | ||
2251 | case EST_FETCHQTD: | |
ae0138a8 | 2252 | again = ehci_state_fetchqtd(q); |
94527ead GH |
2253 | break; |
2254 | ||
2255 | case EST_HORIZONTALQH: | |
ae0138a8 | 2256 | again = ehci_state_horizqh(q); |
94527ead GH |
2257 | break; |
2258 | ||
2259 | case EST_EXECUTE: | |
ae0138a8 | 2260 | again = ehci_state_execute(q); |
3a215326 GH |
2261 | if (async) { |
2262 | ehci->async_stepdown = 0; | |
2263 | } | |
94527ead GH |
2264 | break; |
2265 | ||
2266 | case EST_EXECUTING: | |
8ac6d699 | 2267 | assert(q != NULL); |
3a215326 GH |
2268 | if (async) { |
2269 | ehci->async_stepdown = 0; | |
2270 | } | |
ae0138a8 | 2271 | again = ehci_state_executing(q); |
94527ead GH |
2272 | break; |
2273 | ||
2274 | case EST_WRITEBACK: | |
b2467216 | 2275 | assert(q != NULL); |
ae0138a8 | 2276 | again = ehci_state_writeback(q); |
94527ead GH |
2277 | break; |
2278 | ||
2279 | default: | |
2280 | fprintf(stderr, "Bad state!\n"); | |
2281 | again = -1; | |
8ac6d699 | 2282 | assert(0); |
94527ead GH |
2283 | break; |
2284 | } | |
2285 | ||
2286 | if (again < 0) { | |
2287 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2288 | ehci_reset(ehci); | |
2289 | again = 0; | |
2290 | } | |
2291 | } | |
2292 | while (again); | |
94527ead GH |
2293 | } |
2294 | ||
2295 | static void ehci_advance_async_state(EHCIState *ehci) | |
2296 | { | |
df5d5c5c | 2297 | const int async = 1; |
94527ead | 2298 | |
26d53979 | 2299 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2300 | case EST_INACTIVE: |
ec807d12 | 2301 | if (!ehci_async_enabled(ehci)) { |
94527ead GH |
2302 | break; |
2303 | } | |
26d53979 | 2304 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2305 | // No break, fall through to ACTIVE |
2306 | ||
2307 | case EST_ACTIVE: | |
ec807d12 | 2308 | if (!ehci_async_enabled(ehci)) { |
e850c2b4 | 2309 | ehci_queues_rip_all(ehci, async); |
26d53979 | 2310 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2311 | break; |
2312 | } | |
2313 | ||
4be23939 | 2314 | /* make sure guest has acknowledged the doorbell interrupt */ |
94527ead GH |
2315 | /* TO-DO: is this really needed? */ |
2316 | if (ehci->usbsts & USBSTS_IAA) { | |
2317 | DPRINTF("IAA status bit still set.\n"); | |
2318 | break; | |
2319 | } | |
2320 | ||
94527ead GH |
2321 | /* check that address register has been set */ |
2322 | if (ehci->asynclistaddr == 0) { | |
2323 | break; | |
2324 | } | |
2325 | ||
26d53979 | 2326 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2327 | ehci_advance_state(ehci, async); |
4be23939 HG |
2328 | |
2329 | /* If the doorbell is set, the guest wants to make a change to the | |
2330 | * schedule. The host controller needs to release cached data. | |
2331 | * (section 4.8.2) | |
2332 | */ | |
2333 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2334 | /* Remove all unseen qhs from the async qhs queue */ | |
a37d5e52 | 2335 | ehci_queues_rip_unused(ehci, async, 1); |
d294ad63 | 2336 | trace_usb_ehci_doorbell_ack(); |
4be23939 | 2337 | ehci->usbcmd &= ~USBCMD_IAAD; |
7efc17af | 2338 | ehci_raise_irq(ehci, USBSTS_IAA); |
4be23939 | 2339 | } |
94527ead GH |
2340 | break; |
2341 | ||
2342 | default: | |
2343 | /* this should only be due to a developer mistake */ | |
2344 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2345 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2346 | assert(0); |
94527ead GH |
2347 | } |
2348 | } | |
2349 | ||
2350 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2351 | { | |
2352 | uint32_t entry; | |
2353 | uint32_t list; | |
df5d5c5c | 2354 | const int async = 0; |
94527ead GH |
2355 | |
2356 | // 4.6 | |
2357 | ||
26d53979 | 2358 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2359 | case EST_INACTIVE: |
ec807d12 | 2360 | if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
26d53979 | 2361 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2362 | // No break, fall through to ACTIVE |
2363 | } else | |
2364 | break; | |
2365 | ||
2366 | case EST_ACTIVE: | |
ec807d12 | 2367 | if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
e850c2b4 | 2368 | ehci_queues_rip_all(ehci, async); |
26d53979 | 2369 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2370 | break; |
2371 | } | |
2372 | ||
2373 | list = ehci->periodiclistbase & 0xfffff000; | |
2374 | /* check that register has been set */ | |
2375 | if (list == 0) { | |
2376 | break; | |
2377 | } | |
2378 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2379 | ||
4bf80119 | 2380 | pci_dma_read(&ehci->dev, list, &entry, sizeof entry); |
94527ead GH |
2381 | entry = le32_to_cpu(entry); |
2382 | ||
2383 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2384 | ehci->frindex / 8, list, entry); | |
0122f472 | 2385 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2386 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2387 | ehci_advance_state(ehci, async); | |
a37d5e52 | 2388 | ehci_queues_rip_unused(ehci, async, 0); |
94527ead GH |
2389 | break; |
2390 | ||
94527ead GH |
2391 | default: |
2392 | /* this should only be due to a developer mistake */ | |
2393 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2394 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2395 | assert(0); |
94527ead GH |
2396 | } |
2397 | } | |
2398 | ||
6ceced0b GH |
2399 | static void ehci_update_frindex(EHCIState *ehci, int frames) |
2400 | { | |
2401 | int i; | |
2402 | ||
2403 | if (!ehci_enabled(ehci)) { | |
2404 | return; | |
2405 | } | |
2406 | ||
2407 | for (i = 0; i < frames; i++) { | |
2408 | ehci->frindex += 8; | |
2409 | ||
2410 | if (ehci->frindex == 0x00002000) { | |
7efc17af | 2411 | ehci_raise_irq(ehci, USBSTS_FLR); |
6ceced0b GH |
2412 | } |
2413 | ||
2414 | if (ehci->frindex == 0x00004000) { | |
7efc17af | 2415 | ehci_raise_irq(ehci, USBSTS_FLR); |
6ceced0b | 2416 | ehci->frindex = 0; |
29ecaa26 | 2417 | if (ehci->usbsts_frindex >= 0x00004000) { |
7efc17af GH |
2418 | ehci->usbsts_frindex -= 0x00004000; |
2419 | } else { | |
2420 | ehci->usbsts_frindex = 0; | |
2421 | } | |
6ceced0b GH |
2422 | } |
2423 | } | |
2424 | } | |
2425 | ||
94527ead GH |
2426 | static void ehci_frame_timer(void *opaque) |
2427 | { | |
2428 | EHCIState *ehci = opaque; | |
7efc17af | 2429 | int need_timer = 0; |
94527ead | 2430 | int64_t expire_time, t_now; |
adddecb1 | 2431 | uint64_t ns_elapsed; |
f020ed36 | 2432 | int frames, skipped_frames; |
94527ead | 2433 | int i; |
94527ead | 2434 | |
94527ead | 2435 | t_now = qemu_get_clock_ns(vm_clock); |
adddecb1 GH |
2436 | ns_elapsed = t_now - ehci->last_run_ns; |
2437 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead | 2438 | |
3a215326 | 2439 | if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { |
7efc17af | 2440 | need_timer++; |
afb7a0b8 | 2441 | ehci->async_stepdown = 0; |
94527ead | 2442 | |
f020ed36 GH |
2443 | if (frames > ehci->maxframes) { |
2444 | skipped_frames = frames - ehci->maxframes; | |
2445 | ehci_update_frindex(ehci, skipped_frames); | |
2446 | ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; | |
2447 | frames -= skipped_frames; | |
2448 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2449 | } | |
2450 | ||
3a215326 | 2451 | for (i = 0; i < frames; i++) { |
349b4e90 HG |
2452 | /* |
2453 | * If we're running behind schedule, we should not catch up | |
2454 | * too fast, as that will make some guests unhappy: | |
2455 | * 1) We must process a minimum of MIN_FR_PER_TICK frames, | |
2456 | * otherwise we will never catch up | |
2457 | * 2) Process frames until the guest has requested an irq (IOC) | |
2458 | */ | |
2459 | if (i >= MIN_FR_PER_TICK) { | |
2460 | ehci_commit_irq(ehci); | |
2461 | if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) { | |
2462 | break; | |
2463 | } | |
2464 | } | |
3a215326 | 2465 | ehci_update_frindex(ehci, 1); |
f020ed36 | 2466 | ehci_advance_periodic_state(ehci); |
3a215326 GH |
2467 | ehci->last_run_ns += FRAME_TIMER_NS; |
2468 | } | |
2469 | } else { | |
2470 | if (ehci->async_stepdown < ehci->maxframes / 2) { | |
2471 | ehci->async_stepdown++; | |
2472 | } | |
3a215326 GH |
2473 | ehci_update_frindex(ehci, frames); |
2474 | ehci->last_run_ns += FRAME_TIMER_NS * frames; | |
94527ead GH |
2475 | } |
2476 | ||
94527ead GH |
2477 | /* Async is not inside loop since it executes everything it can once |
2478 | * called | |
2479 | */ | |
3a215326 | 2480 | if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) { |
7efc17af | 2481 | need_timer++; |
afb7a0b8 | 2482 | ehci_advance_async_state(ehci); |
3a215326 | 2483 | } |
94527ead | 2484 | |
7efc17af GH |
2485 | ehci_commit_irq(ehci); |
2486 | if (ehci->usbsts_pending) { | |
2487 | need_timer++; | |
2488 | ehci->async_stepdown = 0; | |
daf25307 | 2489 | } |
f0ad01f9 | 2490 | |
7efc17af | 2491 | if (need_timer) { |
afb7a0b8 GH |
2492 | expire_time = t_now + (get_ticks_per_sec() |
2493 | * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ); | |
7efc17af GH |
2494 | qemu_mod_timer(ehci->frame_timer, expire_time); |
2495 | } | |
94527ead GH |
2496 | } |
2497 | ||
0fb3e299 GH |
2498 | static void ehci_async_bh(void *opaque) |
2499 | { | |
2500 | EHCIState *ehci = opaque; | |
2501 | ehci_advance_async_state(ehci); | |
2502 | } | |
94527ead | 2503 | |
1f97f6c9 GH |
2504 | static const MemoryRegionOps ehci_mmio_caps_ops = { |
2505 | .read = ehci_caps_read, | |
2506 | .valid.min_access_size = 1, | |
2507 | .valid.max_access_size = 4, | |
2508 | .impl.min_access_size = 1, | |
2509 | .impl.max_access_size = 1, | |
2510 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2511 | }; | |
2512 | ||
2513 | static const MemoryRegionOps ehci_mmio_opreg_ops = { | |
2514 | .read = ehci_opreg_read, | |
2515 | .write = ehci_opreg_write, | |
2516 | .valid.min_access_size = 4, | |
2517 | .valid.max_access_size = 4, | |
2518 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2519 | }; | |
2520 | ||
2521 | static const MemoryRegionOps ehci_mmio_port_ops = { | |
2522 | .read = ehci_port_read, | |
2523 | .write = ehci_port_write, | |
2524 | .valid.min_access_size = 4, | |
2525 | .valid.max_access_size = 4, | |
e57964f5 | 2526 | .endianness = DEVICE_LITTLE_ENDIAN, |
94527ead GH |
2527 | }; |
2528 | ||
94527ead GH |
2529 | static int usb_ehci_initfn(PCIDevice *dev); |
2530 | ||
2531 | static USBPortOps ehci_port_ops = { | |
2532 | .attach = ehci_attach, | |
2533 | .detach = ehci_detach, | |
4706ab6c | 2534 | .child_detach = ehci_child_detach, |
a0a3167a | 2535 | .wakeup = ehci_wakeup, |
94527ead GH |
2536 | .complete = ehci_async_complete_packet, |
2537 | }; | |
2538 | ||
07771f6f | 2539 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2540 | .register_companion = ehci_register_companion, |
07771f6f GH |
2541 | }; |
2542 | ||
9a773408 GH |
2543 | static int usb_ehci_post_load(void *opaque, int version_id) |
2544 | { | |
2545 | EHCIState *s = opaque; | |
2546 | int i; | |
2547 | ||
2548 | for (i = 0; i < NB_PORTS; i++) { | |
2549 | USBPort *companion = s->companion_ports[i]; | |
2550 | if (companion == NULL) { | |
2551 | continue; | |
2552 | } | |
2553 | if (s->portsc[i] & PORTSC_POWNER) { | |
2554 | companion->dev = s->ports[i].dev; | |
2555 | } else { | |
2556 | companion->dev = NULL; | |
2557 | } | |
2558 | } | |
2559 | ||
2560 | return 0; | |
2561 | } | |
2562 | ||
9490fb06 | 2563 | static const VMStateDescription vmstate_ehci = { |
9a773408 | 2564 | .name = "ehci", |
6d3b6d3d GH |
2565 | .version_id = 2, |
2566 | .minimum_version_id = 1, | |
9a773408 GH |
2567 | .post_load = usb_ehci_post_load, |
2568 | .fields = (VMStateField[]) { | |
2569 | VMSTATE_PCI_DEVICE(dev, EHCIState), | |
2570 | /* mmio registers */ | |
2571 | VMSTATE_UINT32(usbcmd, EHCIState), | |
2572 | VMSTATE_UINT32(usbsts, EHCIState), | |
6d3b6d3d GH |
2573 | VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2), |
2574 | VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2), | |
9a773408 GH |
2575 | VMSTATE_UINT32(usbintr, EHCIState), |
2576 | VMSTATE_UINT32(frindex, EHCIState), | |
2577 | VMSTATE_UINT32(ctrldssegment, EHCIState), | |
2578 | VMSTATE_UINT32(periodiclistbase, EHCIState), | |
2579 | VMSTATE_UINT32(asynclistaddr, EHCIState), | |
2580 | VMSTATE_UINT32(configflag, EHCIState), | |
2581 | VMSTATE_UINT32(portsc[0], EHCIState), | |
2582 | VMSTATE_UINT32(portsc[1], EHCIState), | |
2583 | VMSTATE_UINT32(portsc[2], EHCIState), | |
2584 | VMSTATE_UINT32(portsc[3], EHCIState), | |
2585 | VMSTATE_UINT32(portsc[4], EHCIState), | |
2586 | VMSTATE_UINT32(portsc[5], EHCIState), | |
2587 | /* frame timer */ | |
2588 | VMSTATE_TIMER(frame_timer, EHCIState), | |
2589 | VMSTATE_UINT64(last_run_ns, EHCIState), | |
2590 | VMSTATE_UINT32(async_stepdown, EHCIState), | |
2591 | /* schedule state */ | |
2592 | VMSTATE_UINT32(astate, EHCIState), | |
2593 | VMSTATE_UINT32(pstate, EHCIState), | |
2594 | VMSTATE_UINT32(a_fetch_addr, EHCIState), | |
2595 | VMSTATE_UINT32(p_fetch_addr, EHCIState), | |
2596 | VMSTATE_END_OF_LIST() | |
2597 | } | |
9490fb06 GH |
2598 | }; |
2599 | ||
3028376e | 2600 | static Property ehci_properties[] = { |
3028376e GH |
2601 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), |
2602 | DEFINE_PROP_END_OF_LIST(), | |
2603 | }; | |
2604 | ||
40021f08 AL |
2605 | static void ehci_class_init(ObjectClass *klass, void *data) |
2606 | { | |
39bffca2 | 2607 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2608 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2609 | ||
2610 | k->init = usb_ehci_initfn; | |
2611 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2612 | k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ | |
2613 | k->revision = 0x10; | |
2614 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2615 | dc->vmsd = &vmstate_ehci; |
2616 | dc->props = ehci_properties; | |
40021f08 AL |
2617 | } |
2618 | ||
39bffca2 AL |
2619 | static TypeInfo ehci_info = { |
2620 | .name = "usb-ehci", | |
2621 | .parent = TYPE_PCI_DEVICE, | |
2622 | .instance_size = sizeof(EHCIState), | |
2623 | .class_init = ehci_class_init, | |
e855761c AL |
2624 | }; |
2625 | ||
40021f08 AL |
2626 | static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2627 | { | |
39bffca2 | 2628 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2629 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2630 | ||
2631 | k->init = usb_ehci_initfn; | |
2632 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2633 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; | |
2634 | k->revision = 0x03; | |
2635 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2636 | dc->vmsd = &vmstate_ehci; |
2637 | dc->props = ehci_properties; | |
40021f08 AL |
2638 | } |
2639 | ||
39bffca2 AL |
2640 | static TypeInfo ich9_ehci_info = { |
2641 | .name = "ich9-usb-ehci1", | |
2642 | .parent = TYPE_PCI_DEVICE, | |
2643 | .instance_size = sizeof(EHCIState), | |
2644 | .class_init = ich9_ehci_class_init, | |
94527ead GH |
2645 | }; |
2646 | ||
2647 | static int usb_ehci_initfn(PCIDevice *dev) | |
2648 | { | |
2649 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2650 | uint8_t *pci_conf = s->dev.config; | |
2651 | int i; | |
2652 | ||
94527ead | 2653 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2654 | |
2655 | /* capabilities pointer */ | |
2656 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2657 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2658 | ||
817e0b6f | 2659 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
94527ead GH |
2660 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); |
2661 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2662 | ||
2663 | // pci_conf[0x50] = 0x01; // power management caps | |
2664 | ||
4001f22f | 2665 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2666 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2667 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2668 | ||
2669 | pci_conf[0x64] = 0x00; | |
2670 | pci_conf[0x65] = 0x00; | |
2671 | pci_conf[0x66] = 0x00; | |
2672 | pci_conf[0x67] = 0x00; | |
2673 | pci_conf[0x68] = 0x01; | |
2674 | pci_conf[0x69] = 0x00; | |
2675 | pci_conf[0x6a] = 0x00; | |
2676 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2677 | pci_conf[0x6c] = 0x00; | |
2678 | pci_conf[0x6d] = 0x00; | |
2679 | pci_conf[0x6e] = 0x00; | |
2680 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2681 | ||
1f97f6c9 GH |
2682 | /* 2.2 host controller interface version */ |
2683 | s->caps[0x00] = (uint8_t) OPREGBASE; | |
2684 | s->caps[0x01] = 0x00; | |
2685 | s->caps[0x02] = 0x00; | |
2686 | s->caps[0x03] = 0x01; /* HC version */ | |
2687 | s->caps[0x04] = NB_PORTS; /* Number of downstream ports */ | |
2688 | s->caps[0x05] = 0x00; /* No companion ports at present */ | |
2689 | s->caps[0x06] = 0x00; | |
2690 | s->caps[0x07] = 0x00; | |
2691 | s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ | |
2692 | s->caps[0x09] = 0x68; /* EECP */ | |
2693 | s->caps[0x0a] = 0x00; | |
2694 | s->caps[0x0b] = 0x00; | |
94527ead GH |
2695 | |
2696 | s->irq = s->dev.irq[3]; | |
2697 | ||
07771f6f | 2698 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2699 | for(i = 0; i < NB_PORTS; i++) { |
2700 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2701 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2702 | s->ports[i].dev = 0; |
2703 | } | |
2704 | ||
2705 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
0fb3e299 | 2706 | s->async_bh = qemu_bh_new(ehci_async_bh, s); |
df5d5c5c HG |
2707 | QTAILQ_INIT(&s->aqueues); |
2708 | QTAILQ_INIT(&s->pqueues); | |
7341ea07 | 2709 | usb_packet_init(&s->ipacket); |
94527ead GH |
2710 | |
2711 | qemu_register_reset(ehci_reset, s); | |
2712 | ||
1f97f6c9 GH |
2713 | memory_region_init(&s->mem, "ehci", MMIO_SIZE); |
2714 | memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, | |
2715 | "capabilities", OPREGBASE); | |
2716 | memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, | |
2717 | "operational", PORTSC_BEGIN - OPREGBASE); | |
2718 | memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, | |
2719 | "ports", PORTSC_END - PORTSC_BEGIN); | |
2720 | ||
2721 | memory_region_add_subregion(&s->mem, 0, &s->mem_caps); | |
2722 | memory_region_add_subregion(&s->mem, OPREGBASE, &s->mem_opreg); | |
2723 | memory_region_add_subregion(&s->mem, PORTSC_BEGIN, &s->mem_ports); | |
2724 | ||
e824b2cc | 2725 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); |
94527ead | 2726 | |
94527ead GH |
2727 | return 0; |
2728 | } | |
2729 | ||
83f7d43a | 2730 | static void ehci_register_types(void) |
94527ead | 2731 | { |
39bffca2 AL |
2732 | type_register_static(&ehci_info); |
2733 | type_register_static(&ich9_ehci_info); | |
94527ead | 2734 | } |
83f7d43a AF |
2735 | |
2736 | type_init(ehci_register_types) | |
94527ead GH |
2737 | |
2738 | /* | |
2739 | * vim: expandtab ts=4 | |
2740 | */ |