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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
23 | */ |
24 | ||
f1ae32a1 | 25 | #include "hw/hw.h" |
94527ead | 26 | #include "qemu-timer.h" |
f1ae32a1 GH |
27 | #include "hw/usb.h" |
28 | #include "hw/pci.h" | |
94527ead | 29 | #include "monitor.h" |
439a97cc | 30 | #include "trace.h" |
0ce668bc | 31 | #include "dma.h" |
94527ead GH |
32 | |
33 | #define EHCI_DEBUG 0 | |
94527ead | 34 | |
26d53979 | 35 | #if EHCI_DEBUG |
94527ead GH |
36 | #define DPRINTF printf |
37 | #else | |
38 | #define DPRINTF(...) | |
39 | #endif | |
40 | ||
94527ead GH |
41 | /* internal processing - reset HC to try and recover */ |
42 | #define USB_RET_PROCERR (-99) | |
43 | ||
44 | #define MMIO_SIZE 0x1000 | |
45 | ||
46 | /* Capability Registers Base Address - section 2.2 */ | |
47 | #define CAPREGBASE 0x0000 | |
48 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
49 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
50 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
51 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
52 | #define EECP HCCPARAMS + 1 | |
53 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
54 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
55 | ||
56 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
57 | ||
58 | #define USBCMD OPREGBASE + 0x0000 | |
59 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
60 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
61 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
62 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
63 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
64 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
65 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
66 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
67 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
68 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
69 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
70 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
71 | ||
72 | #define USBSTS OPREGBASE + 0x0004 | |
73 | #define USBSTS_RO_MASK 0x0000003f | |
74 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
75 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
76 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
77 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
78 | #define USBSTS_HSE (1 << 4) // Host System Error | |
79 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
80 | #define USBSTS_HALT (1 << 12) // HC Halted | |
81 | #define USBSTS_REC (1 << 13) // Reclamation | |
82 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
83 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
84 | ||
85 | /* | |
86 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
87 | * so no need to redefine here. | |
88 | */ | |
89 | #define USBINTR OPREGBASE + 0x0008 | |
90 | #define USBINTR_MASK 0x0000003f | |
91 | ||
92 | #define FRINDEX OPREGBASE + 0x000c | |
93 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
94 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
95 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
96 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
97 | ||
98 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
99 | ||
100 | #define PORTSC (OPREGBASE + 0x0044) | |
101 | #define PORTSC_BEGIN PORTSC | |
102 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
103 | /* | |
c44fd61c | 104 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
105 | * written to us by software |
106 | */ | |
a0a3167a | 107 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
108 | #define PORTSC_RWC_MASK 0x0000002a |
109 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
110 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
111 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
112 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
113 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
114 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
115 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
116 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
117 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
118 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
119 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
120 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
121 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
122 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
123 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
124 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
125 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
126 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
127 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
128 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
129 | ||
130 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 131 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
132 | |
133 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
5cc194ca | 134 | #define NB_PORTS 6 // Number of downstream ports |
94527ead | 135 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
94527ead GH |
136 | #define MAX_QH 100 // Max allowable queue heads in a chain |
137 | ||
138 | /* Internal periodic / asynchronous schedule state machine states | |
139 | */ | |
140 | typedef enum { | |
141 | EST_INACTIVE = 1000, | |
142 | EST_ACTIVE, | |
143 | EST_EXECUTING, | |
144 | EST_SLEEPING, | |
145 | /* The following states are internal to the state machine function | |
146 | */ | |
147 | EST_WAITLISTHEAD, | |
148 | EST_FETCHENTRY, | |
149 | EST_FETCHQH, | |
150 | EST_FETCHITD, | |
2fe80192 | 151 | EST_FETCHSITD, |
94527ead GH |
152 | EST_ADVANCEQUEUE, |
153 | EST_FETCHQTD, | |
154 | EST_EXECUTE, | |
155 | EST_WRITEBACK, | |
156 | EST_HORIZONTALQH | |
157 | } EHCI_STATES; | |
158 | ||
159 | /* macros for accessing fields within next link pointer entry */ | |
160 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
161 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
162 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
163 | ||
164 | /* link pointer types */ | |
165 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
166 | #define NLPTR_TYPE_QH 1 // queue head | |
167 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
168 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
169 | ||
170 | ||
171 | /* EHCI spec version 1.0 Section 3.3 | |
172 | */ | |
173 | typedef struct EHCIitd { | |
174 | uint32_t next; | |
175 | ||
176 | uint32_t transact[8]; | |
177 | #define ITD_XACT_ACTIVE (1 << 31) | |
178 | #define ITD_XACT_DBERROR (1 << 30) | |
179 | #define ITD_XACT_BABBLE (1 << 29) | |
180 | #define ITD_XACT_XACTERR (1 << 28) | |
181 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
182 | #define ITD_XACT_LENGTH_SH 16 | |
183 | #define ITD_XACT_IOC (1 << 15) | |
184 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
185 | #define ITD_XACT_PGSEL_SH 12 | |
186 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
187 | ||
188 | uint32_t bufptr[7]; | |
189 | #define ITD_BUFPTR_MASK 0xfffff000 | |
190 | #define ITD_BUFPTR_SH 12 | |
191 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
192 | #define ITD_BUFPTR_EP_SH 8 | |
193 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
194 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
195 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
196 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
197 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
198 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 199 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
200 | } EHCIitd; |
201 | ||
202 | /* EHCI spec version 1.0 Section 3.4 | |
203 | */ | |
204 | typedef struct EHCIsitd { | |
205 | uint32_t next; // Standard next link pointer | |
206 | uint32_t epchar; | |
207 | #define SITD_EPCHAR_IO (1 << 31) | |
208 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
209 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
210 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
211 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
212 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
213 | #define SITD_EPCHAR_EPNUM_SH 8 | |
214 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
215 | ||
216 | uint32_t uframe; | |
217 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
218 | #define SITD_UFRAME_CMASK_SH 8 | |
219 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
220 | ||
221 | uint32_t results; | |
222 | #define SITD_RESULTS_IOC (1 << 31) | |
223 | #define SITD_RESULTS_PGSEL (1 << 30) | |
224 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
225 | #define SITD_RESULTS_TYBYTES_SH 16 | |
226 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
227 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
228 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
229 | #define SITD_RESULTS_ERR (1 << 6) | |
230 | #define SITD_RESULTS_DBERR (1 << 5) | |
231 | #define SITD_RESULTS_BABBLE (1 << 4) | |
232 | #define SITD_RESULTS_XACTERR (1 << 3) | |
233 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
234 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
235 | ||
236 | uint32_t bufptr[2]; | |
237 | #define SITD_BUFPTR_MASK 0xfffff000 | |
238 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
239 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
240 | #define SITD_BUFPTR_TPOS_SH 3 | |
241 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
242 | ||
243 | uint32_t backptr; // Standard next link pointer | |
244 | } EHCIsitd; | |
245 | ||
246 | /* EHCI spec version 1.0 Section 3.5 | |
247 | */ | |
248 | typedef struct EHCIqtd { | |
249 | uint32_t next; // Standard next link pointer | |
250 | uint32_t altnext; // Standard next link pointer | |
251 | uint32_t token; | |
252 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
253 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
254 | #define QTD_TOKEN_TBYTES_SH 16 | |
255 | #define QTD_TOKEN_IOC (1 << 15) | |
256 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
257 | #define QTD_TOKEN_CPAGE_SH 12 | |
258 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
259 | #define QTD_TOKEN_CERR_SH 10 | |
260 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
261 | #define QTD_TOKEN_PID_SH 8 | |
262 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
263 | #define QTD_TOKEN_HALT (1 << 6) | |
264 | #define QTD_TOKEN_DBERR (1 << 5) | |
265 | #define QTD_TOKEN_BABBLE (1 << 4) | |
266 | #define QTD_TOKEN_XACTERR (1 << 3) | |
267 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
268 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
269 | #define QTD_TOKEN_PING (1 << 0) | |
270 | ||
271 | uint32_t bufptr[5]; // Standard buffer pointer | |
272 | #define QTD_BUFPTR_MASK 0xfffff000 | |
0ce668bc | 273 | #define QTD_BUFPTR_SH 12 |
94527ead GH |
274 | } EHCIqtd; |
275 | ||
276 | /* EHCI spec version 1.0 Section 3.6 | |
277 | */ | |
278 | typedef struct EHCIqh { | |
279 | uint32_t next; // Standard next link pointer | |
280 | ||
281 | /* endpoint characteristics */ | |
282 | uint32_t epchar; | |
283 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
284 | #define QH_EPCHAR_RL_SH 28 | |
285 | #define QH_EPCHAR_C (1 << 27) | |
286 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
287 | #define QH_EPCHAR_MPLEN_SH 16 | |
288 | #define QH_EPCHAR_H (1 << 15) | |
289 | #define QH_EPCHAR_DTC (1 << 14) | |
290 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
291 | #define QH_EPCHAR_EPS_SH 12 | |
292 | #define EHCI_QH_EPS_FULL 0 | |
293 | #define EHCI_QH_EPS_LOW 1 | |
294 | #define EHCI_QH_EPS_HIGH 2 | |
295 | #define EHCI_QH_EPS_RESERVED 3 | |
296 | ||
297 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
298 | #define QH_EPCHAR_EP_SH 8 | |
299 | #define QH_EPCHAR_I (1 << 7) | |
300 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
301 | #define QH_EPCHAR_DEVADDR_SH 0 | |
302 | ||
303 | /* endpoint capabilities */ | |
304 | uint32_t epcap; | |
305 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
306 | #define QH_EPCAP_MULT_SH 30 | |
307 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
308 | #define QH_EPCAP_PORTNUM_SH 23 | |
309 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
310 | #define QH_EPCAP_HUBADDR_SH 16 | |
311 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
312 | #define QH_EPCAP_CMASK_SH 8 | |
313 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
314 | #define QH_EPCAP_SMASK_SH 0 | |
315 | ||
316 | uint32_t current_qtd; // Standard next link pointer | |
317 | uint32_t next_qtd; // Standard next link pointer | |
318 | uint32_t altnext_qtd; | |
319 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
320 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
321 | ||
322 | uint32_t token; // Same as QTD token | |
323 | uint32_t bufptr[5]; // Standard buffer pointer | |
324 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
325 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
326 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
327 | #define BUFPTR_SBYTES_SH 5 | |
328 | } EHCIqh; | |
329 | ||
330 | /* EHCI spec version 1.0 Section 3.7 | |
331 | */ | |
332 | typedef struct EHCIfstn { | |
333 | uint32_t next; // Standard next link pointer | |
334 | uint32_t backptr; // Standard next link pointer | |
335 | } EHCIfstn; | |
336 | ||
eb36a88e | 337 | typedef struct EHCIPacket EHCIPacket; |
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
eb36a88e GH |
347 | struct EHCIPacket { |
348 | EHCIQueue *queue; | |
349 | QTAILQ_ENTRY(EHCIPacket) next; | |
350 | ||
351 | EHCIqtd qtd; /* copy of current QTD (being worked on) */ | |
352 | uint32_t qtdaddr; /* address QTD read from */ | |
353 | ||
354 | USBPacket packet; | |
355 | QEMUSGList sgl; | |
356 | int pid; | |
357 | uint32_t tbytes; | |
358 | enum async_state async; | |
359 | int usb_status; | |
360 | }; | |
361 | ||
0122f472 GH |
362 | struct EHCIQueue { |
363 | EHCIState *ehci; | |
8ac6d699 | 364 | QTAILQ_ENTRY(EHCIQueue) next; |
adddecb1 GH |
365 | uint32_t seen; |
366 | uint64_t ts; | |
ae0138a8 | 367 | int async; |
0122f472 GH |
368 | |
369 | /* cached data from guest - needs to be flushed | |
370 | * when guest removes an entry (doorbell, handshake sequence) | |
371 | */ | |
eb36a88e GH |
372 | EHCIqh qh; /* copy of current QH (being worked on) */ |
373 | uint32_t qhaddr; /* address QH read from */ | |
374 | uint32_t qtdaddr; /* address QTD read from */ | |
e59928b3 | 375 | USBDevice *dev; |
eb36a88e | 376 | QTAILQ_HEAD(, EHCIPacket) packets; |
0122f472 GH |
377 | }; |
378 | ||
df5d5c5c HG |
379 | typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; |
380 | ||
0122f472 | 381 | struct EHCIState { |
94527ead | 382 | PCIDevice dev; |
0122f472 | 383 | USBBus bus; |
94527ead | 384 | qemu_irq irq; |
e57964f5 | 385 | MemoryRegion mem; |
a0a3167a | 386 | int companion_count; |
16a2dee6 GH |
387 | |
388 | /* properties */ | |
389 | uint32_t freq; | |
390 | uint32_t maxframes; | |
391 | ||
94527ead GH |
392 | /* |
393 | * EHCI spec version 1.0 Section 2.3 | |
394 | * Host Controller Operational Registers | |
395 | */ | |
396 | union { | |
397 | uint8_t mmio[MMIO_SIZE]; | |
398 | struct { | |
399 | uint8_t cap[OPREGBASE]; | |
400 | uint32_t usbcmd; | |
401 | uint32_t usbsts; | |
402 | uint32_t usbintr; | |
403 | uint32_t frindex; | |
404 | uint32_t ctrldssegment; | |
405 | uint32_t periodiclistbase; | |
406 | uint32_t asynclistaddr; | |
407 | uint32_t notused[9]; | |
408 | uint32_t configflag; | |
409 | uint32_t portsc[NB_PORTS]; | |
410 | }; | |
411 | }; | |
0122f472 | 412 | |
94527ead GH |
413 | /* |
414 | * Internal states, shadow registers, etc | |
415 | */ | |
94527ead | 416 | QEMUTimer *frame_timer; |
0fb3e299 | 417 | QEMUBH *async_bh; |
94527ead GH |
418 | int astate; // Current state in asynchronous schedule |
419 | int pstate; // Current state in periodic schedule | |
420 | USBPort ports[NB_PORTS]; | |
a0a3167a | 421 | USBPort *companion_ports[NB_PORTS]; |
94527ead | 422 | uint32_t usbsts_pending; |
df5d5c5c HG |
423 | EHCIQueueHead aqueues; |
424 | EHCIQueueHead pqueues; | |
94527ead | 425 | |
0122f472 GH |
426 | uint32_t a_fetch_addr; // which address to look at next |
427 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 428 | |
0122f472 | 429 | USBPacket ipacket; |
0ce668bc | 430 | QEMUSGList isgl; |
0122f472 | 431 | |
adddecb1 | 432 | uint64_t last_run_ns; |
0122f472 | 433 | }; |
94527ead GH |
434 | |
435 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 436 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
437 | |
438 | /* nifty macros from Arnon's EHCI version */ | |
439 | #define get_field(data, field) \ | |
440 | (((data) & field##_MASK) >> field##_SH) | |
441 | ||
442 | #define set_field(data, newval, field) do { \ | |
443 | uint32_t val = *data; \ | |
444 | val &= ~ field##_MASK; \ | |
445 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
446 | *data = val; \ | |
447 | } while(0) | |
448 | ||
26d53979 | 449 | static const char *ehci_state_names[] = { |
aac882e7 GH |
450 | [EST_INACTIVE] = "INACTIVE", |
451 | [EST_ACTIVE] = "ACTIVE", | |
452 | [EST_EXECUTING] = "EXECUTING", | |
453 | [EST_SLEEPING] = "SLEEPING", | |
454 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
455 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
456 | [EST_FETCHQH] = "FETCH QH", | |
457 | [EST_FETCHITD] = "FETCH ITD", | |
458 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
459 | [EST_FETCHQTD] = "FETCH QTD", | |
460 | [EST_EXECUTE] = "EXECUTE", | |
461 | [EST_WRITEBACK] = "WRITEBACK", | |
462 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
463 | }; |
464 | ||
465 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
466 | [CAPLENGTH] = "CAPLENGTH", |
467 | [HCIVERSION] = "HCIVERSION", | |
468 | [HCSPARAMS] = "HCSPARAMS", | |
469 | [HCCPARAMS] = "HCCPARAMS", | |
470 | [USBCMD] = "USBCMD", | |
471 | [USBSTS] = "USBSTS", | |
472 | [USBINTR] = "USBINTR", | |
473 | [FRINDEX] = "FRINDEX", | |
474 | [PERIODICLISTBASE] = "P-LIST BASE", | |
475 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
476 | [PORTSC_BEGIN] = "PORTSC #0", | |
477 | [PORTSC_BEGIN + 4] = "PORTSC #1", | |
478 | [PORTSC_BEGIN + 8] = "PORTSC #2", | |
479 | [PORTSC_BEGIN + 12] = "PORTSC #3", | |
335b8d20 GH |
480 | [PORTSC_BEGIN + 16] = "PORTSC #4", |
481 | [PORTSC_BEGIN + 20] = "PORTSC #5", | |
aac882e7 | 482 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 483 | }; |
94527ead | 484 | |
26d53979 | 485 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 486 | { |
26d53979 GH |
487 | if (nr < len && n[nr] != NULL) { |
488 | return n[nr]; | |
94527ead | 489 | } else { |
26d53979 | 490 | return "unknown"; |
94527ead GH |
491 | } |
492 | } | |
94527ead | 493 | |
26d53979 GH |
494 | static const char *state2str(uint32_t state) |
495 | { | |
496 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
497 | } | |
498 | ||
499 | static const char *addr2str(target_phys_addr_t addr) | |
500 | { | |
501 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
502 | } | |
503 | ||
439a97cc GH |
504 | static void ehci_trace_usbsts(uint32_t mask, int state) |
505 | { | |
506 | /* interrupts */ | |
507 | if (mask & USBSTS_INT) { | |
508 | trace_usb_ehci_usbsts("INT", state); | |
509 | } | |
510 | if (mask & USBSTS_ERRINT) { | |
511 | trace_usb_ehci_usbsts("ERRINT", state); | |
512 | } | |
513 | if (mask & USBSTS_PCD) { | |
514 | trace_usb_ehci_usbsts("PCD", state); | |
515 | } | |
516 | if (mask & USBSTS_FLR) { | |
517 | trace_usb_ehci_usbsts("FLR", state); | |
518 | } | |
519 | if (mask & USBSTS_HSE) { | |
520 | trace_usb_ehci_usbsts("HSE", state); | |
521 | } | |
522 | if (mask & USBSTS_IAA) { | |
523 | trace_usb_ehci_usbsts("IAA", state); | |
524 | } | |
525 | ||
526 | /* status */ | |
527 | if (mask & USBSTS_HALT) { | |
528 | trace_usb_ehci_usbsts("HALT", state); | |
529 | } | |
530 | if (mask & USBSTS_REC) { | |
531 | trace_usb_ehci_usbsts("REC", state); | |
532 | } | |
533 | if (mask & USBSTS_PSS) { | |
534 | trace_usb_ehci_usbsts("PSS", state); | |
535 | } | |
536 | if (mask & USBSTS_ASS) { | |
537 | trace_usb_ehci_usbsts("ASS", state); | |
538 | } | |
539 | } | |
540 | ||
541 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
542 | { | |
543 | if ((s->usbsts & mask) == mask) { | |
544 | return; | |
545 | } | |
546 | ehci_trace_usbsts(mask, 1); | |
547 | s->usbsts |= mask; | |
548 | } | |
549 | ||
550 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
551 | { | |
552 | if ((s->usbsts & mask) == 0) { | |
553 | return; | |
554 | } | |
555 | ehci_trace_usbsts(mask, 0); | |
556 | s->usbsts &= ~mask; | |
557 | } | |
94527ead GH |
558 | |
559 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
560 | { | |
561 | int level = 0; | |
562 | ||
563 | // TODO honour interrupt threshold requests | |
564 | ||
439a97cc | 565 | ehci_set_usbsts(s, intr); |
94527ead GH |
566 | |
567 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
568 | level = 1; | |
569 | } | |
570 | ||
571 | qemu_set_irq(s->irq, level); | |
572 | } | |
573 | ||
574 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
575 | { | |
576 | s->usbsts_pending |= intr; | |
577 | } | |
578 | ||
579 | static inline void ehci_commit_interrupt(EHCIState *s) | |
580 | { | |
581 | if (!s->usbsts_pending) { | |
582 | return; | |
583 | } | |
584 | ehci_set_interrupt(s, s->usbsts_pending); | |
585 | s->usbsts_pending = 0; | |
586 | } | |
587 | ||
daf25307 GH |
588 | static void ehci_update_halt(EHCIState *s) |
589 | { | |
590 | if (s->usbcmd & USBCMD_RUNSTOP) { | |
591 | ehci_clear_usbsts(s, USBSTS_HALT); | |
592 | } else { | |
593 | if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { | |
594 | ehci_set_usbsts(s, USBSTS_HALT); | |
595 | } | |
596 | } | |
597 | } | |
598 | ||
26d53979 GH |
599 | static void ehci_set_state(EHCIState *s, int async, int state) |
600 | { | |
601 | if (async) { | |
602 | trace_usb_ehci_state("async", state2str(state)); | |
603 | s->astate = state; | |
b53f685d GH |
604 | if (s->astate == EST_INACTIVE) { |
605 | ehci_clear_usbsts(s, USBSTS_ASS); | |
daf25307 | 606 | ehci_update_halt(s); |
b53f685d GH |
607 | } else { |
608 | ehci_set_usbsts(s, USBSTS_ASS); | |
609 | } | |
26d53979 GH |
610 | } else { |
611 | trace_usb_ehci_state("periodic", state2str(state)); | |
612 | s->pstate = state; | |
b53f685d GH |
613 | if (s->pstate == EST_INACTIVE) { |
614 | ehci_clear_usbsts(s, USBSTS_PSS); | |
daf25307 | 615 | ehci_update_halt(s); |
b53f685d GH |
616 | } else { |
617 | ehci_set_usbsts(s, USBSTS_PSS); | |
618 | } | |
26d53979 GH |
619 | } |
620 | } | |
621 | ||
622 | static int ehci_get_state(EHCIState *s, int async) | |
623 | { | |
624 | return async ? s->astate : s->pstate; | |
625 | } | |
626 | ||
0122f472 GH |
627 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
628 | { | |
629 | if (async) { | |
630 | s->a_fetch_addr = addr; | |
631 | } else { | |
632 | s->p_fetch_addr = addr; | |
633 | } | |
634 | } | |
635 | ||
636 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
637 | { | |
638 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
639 | } | |
640 | ||
8ac6d699 | 641 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 642 | { |
025b168c GH |
643 | /* need three here due to argument count limits */ |
644 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
645 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
646 | trace_usb_ehci_qh_fields(addr, | |
647 | get_field(qh->epchar, QH_EPCHAR_RL), | |
648 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
649 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
650 | get_field(qh->epchar, QH_EPCHAR_EP), | |
651 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
652 | trace_usb_ehci_qh_bits(addr, | |
653 | (bool)(qh->epchar & QH_EPCHAR_C), | |
654 | (bool)(qh->epchar & QH_EPCHAR_H), | |
655 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
656 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
657 | } |
658 | ||
8ac6d699 | 659 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 660 | { |
025b168c GH |
661 | /* need three here due to argument count limits */ |
662 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
663 | trace_usb_ehci_qtd_fields(addr, | |
664 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
665 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
666 | get_field(qtd->token, QTD_TOKEN_CERR), | |
667 | get_field(qtd->token, QTD_TOKEN_PID)); | |
668 | trace_usb_ehci_qtd_bits(addr, | |
669 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
670 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
671 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
672 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
673 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
674 | } |
675 | ||
676 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
677 | { | |
e654887f GH |
678 | trace_usb_ehci_itd(addr, itd->next, |
679 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
680 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
681 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
682 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
683 | } |
684 | ||
2fe80192 GH |
685 | static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
686 | EHCIsitd *sitd) | |
687 | { | |
688 | trace_usb_ehci_sitd(addr, sitd->next, | |
689 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
690 | } | |
691 | ||
ec807d12 GH |
692 | static inline bool ehci_enabled(EHCIState *s) |
693 | { | |
694 | return s->usbcmd & USBCMD_RUNSTOP; | |
695 | } | |
696 | ||
697 | static inline bool ehci_async_enabled(EHCIState *s) | |
698 | { | |
699 | return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); | |
700 | } | |
701 | ||
702 | static inline bool ehci_periodic_enabled(EHCIState *s) | |
703 | { | |
704 | return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); | |
705 | } | |
706 | ||
eb36a88e GH |
707 | /* packet management */ |
708 | ||
709 | static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) | |
710 | { | |
711 | EHCIPacket *p; | |
712 | ||
eb36a88e GH |
713 | p = g_new0(EHCIPacket, 1); |
714 | p->queue = q; | |
715 | usb_packet_init(&p->packet); | |
716 | QTAILQ_INSERT_TAIL(&q->packets, p, next); | |
717 | trace_usb_ehci_packet_action(p->queue, p, "alloc"); | |
718 | return p; | |
719 | } | |
720 | ||
721 | static void ehci_free_packet(EHCIPacket *p) | |
722 | { | |
723 | trace_usb_ehci_packet_action(p->queue, p, "free"); | |
724 | if (p->async == EHCI_ASYNC_INFLIGHT) { | |
725 | usb_cancel_packet(&p->packet); | |
726 | } | |
727 | QTAILQ_REMOVE(&p->queue->packets, p, next); | |
728 | usb_packet_cleanup(&p->packet); | |
729 | g_free(p); | |
730 | } | |
731 | ||
8ac6d699 GH |
732 | /* queue management */ |
733 | ||
8f6d5e26 | 734 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) |
8ac6d699 | 735 | { |
df5d5c5c | 736 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
737 | EHCIQueue *q; |
738 | ||
7267c094 | 739 | q = g_malloc0(sizeof(*q)); |
8ac6d699 | 740 | q->ehci = ehci; |
8f6d5e26 | 741 | q->qhaddr = addr; |
ae0138a8 | 742 | q->async = async; |
eb36a88e | 743 | QTAILQ_INIT(&q->packets); |
df5d5c5c | 744 | QTAILQ_INSERT_HEAD(head, q, next); |
8ac6d699 GH |
745 | trace_usb_ehci_queue_action(q, "alloc"); |
746 | return q; | |
747 | } | |
748 | ||
ae0138a8 | 749 | static void ehci_free_queue(EHCIQueue *q) |
8ac6d699 | 750 | { |
ae0138a8 | 751 | EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; |
eb36a88e GH |
752 | EHCIPacket *p; |
753 | ||
8ac6d699 | 754 | trace_usb_ehci_queue_action(q, "free"); |
eb36a88e GH |
755 | while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { |
756 | ehci_free_packet(p); | |
8ac6d699 | 757 | } |
df5d5c5c | 758 | QTAILQ_REMOVE(head, q, next); |
7267c094 | 759 | g_free(q); |
8ac6d699 GH |
760 | } |
761 | ||
df5d5c5c HG |
762 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, |
763 | int async) | |
8ac6d699 | 764 | { |
df5d5c5c | 765 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
766 | EHCIQueue *q; |
767 | ||
df5d5c5c | 768 | QTAILQ_FOREACH(q, head, next) { |
8ac6d699 GH |
769 | if (addr == q->qhaddr) { |
770 | return q; | |
771 | } | |
772 | } | |
773 | return NULL; | |
774 | } | |
775 | ||
4be23939 | 776 | static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush) |
8ac6d699 | 777 | { |
df5d5c5c | 778 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
779 | EHCIQueue *q, *tmp; |
780 | ||
df5d5c5c | 781 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
8ac6d699 GH |
782 | if (q->seen) { |
783 | q->seen = 0; | |
adddecb1 | 784 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
785 | continue; |
786 | } | |
4be23939 | 787 | if (!flush && ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
788 | /* allow 0.25 sec idle */ |
789 | continue; | |
790 | } | |
ae0138a8 | 791 | ehci_free_queue(q); |
8ac6d699 GH |
792 | } |
793 | } | |
794 | ||
df5d5c5c | 795 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
07771f6f | 796 | { |
df5d5c5c | 797 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
07771f6f GH |
798 | EHCIQueue *q, *tmp; |
799 | ||
df5d5c5c | 800 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
e59928b3 | 801 | if (q->dev != dev) { |
07771f6f GH |
802 | continue; |
803 | } | |
ae0138a8 | 804 | ehci_free_queue(q); |
07771f6f GH |
805 | } |
806 | } | |
807 | ||
df5d5c5c | 808 | static void ehci_queues_rip_all(EHCIState *ehci, int async) |
8ac6d699 | 809 | { |
df5d5c5c | 810 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
811 | EHCIQueue *q, *tmp; |
812 | ||
df5d5c5c | 813 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
ae0138a8 | 814 | ehci_free_queue(q); |
8ac6d699 GH |
815 | } |
816 | } | |
817 | ||
94527ead GH |
818 | /* Attach or detach a device on root hub */ |
819 | ||
820 | static void ehci_attach(USBPort *port) | |
821 | { | |
822 | EHCIState *s = port->opaque; | |
823 | uint32_t *portsc = &s->portsc[port->index]; | |
824 | ||
dcbd0b5c | 825 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead | 826 | |
a0a3167a HG |
827 | if (*portsc & PORTSC_POWNER) { |
828 | USBPort *companion = s->companion_ports[port->index]; | |
829 | companion->dev = port->dev; | |
830 | companion->ops->attach(companion); | |
831 | return; | |
832 | } | |
833 | ||
94527ead GH |
834 | *portsc |= PORTSC_CONNECT; |
835 | *portsc |= PORTSC_CSC; | |
836 | ||
a0a3167a | 837 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
838 | } |
839 | ||
840 | static void ehci_detach(USBPort *port) | |
841 | { | |
842 | EHCIState *s = port->opaque; | |
843 | uint32_t *portsc = &s->portsc[port->index]; | |
844 | ||
dcbd0b5c | 845 | trace_usb_ehci_port_detach(port->index); |
94527ead | 846 | |
a0a3167a HG |
847 | if (*portsc & PORTSC_POWNER) { |
848 | USBPort *companion = s->companion_ports[port->index]; | |
849 | companion->ops->detach(companion); | |
850 | companion->dev = NULL; | |
f76e1d81 HG |
851 | /* |
852 | * EHCI spec 4.2.2: "When a disconnect occurs... On the event, | |
853 | * the port ownership is returned immediately to the EHCI controller." | |
854 | */ | |
855 | *portsc &= ~PORTSC_POWNER; | |
a0a3167a HG |
856 | return; |
857 | } | |
858 | ||
df5d5c5c HG |
859 | ehci_queues_rip_device(s, port->dev, 0); |
860 | ehci_queues_rip_device(s, port->dev, 1); | |
4706ab6c | 861 | |
fbd97532 | 862 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
863 | *portsc |= PORTSC_CSC; |
864 | ||
a0a3167a | 865 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
866 | } |
867 | ||
4706ab6c HG |
868 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
869 | { | |
870 | EHCIState *s = port->opaque; | |
a0a3167a HG |
871 | uint32_t portsc = s->portsc[port->index]; |
872 | ||
873 | if (portsc & PORTSC_POWNER) { | |
874 | USBPort *companion = s->companion_ports[port->index]; | |
875 | companion->ops->child_detach(companion, child); | |
a0a3167a HG |
876 | return; |
877 | } | |
4706ab6c | 878 | |
df5d5c5c HG |
879 | ehci_queues_rip_device(s, child, 0); |
880 | ehci_queues_rip_device(s, child, 1); | |
4706ab6c HG |
881 | } |
882 | ||
a0a3167a HG |
883 | static void ehci_wakeup(USBPort *port) |
884 | { | |
885 | EHCIState *s = port->opaque; | |
886 | uint32_t portsc = s->portsc[port->index]; | |
887 | ||
888 | if (portsc & PORTSC_POWNER) { | |
889 | USBPort *companion = s->companion_ports[port->index]; | |
890 | if (companion->ops->wakeup) { | |
891 | companion->ops->wakeup(companion); | |
0f588df8 GH |
892 | } else { |
893 | qemu_bh_schedule(s->async_bh); | |
a0a3167a HG |
894 | } |
895 | } | |
896 | } | |
897 | ||
898 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
899 | uint32_t portcount, uint32_t firstport) | |
900 | { | |
901 | EHCIState *s = container_of(bus, EHCIState, bus); | |
902 | uint32_t i; | |
903 | ||
904 | if (firstport + portcount > NB_PORTS) { | |
905 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
906 | "firstport on masterbus"); | |
907 | error_printf_unless_qmp( | |
908 | "firstport value of %u makes companion take ports %u - %u, which " | |
909 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
910 | firstport + portcount - 1, NB_PORTS - 1); | |
911 | return -1; | |
912 | } | |
913 | ||
914 | for (i = 0; i < portcount; i++) { | |
915 | if (s->companion_ports[firstport + i]) { | |
916 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
917 | "an USB masterbus"); | |
918 | error_printf_unless_qmp( | |
919 | "port %u on masterbus %s already has a companion assigned\n", | |
920 | firstport + i, bus->qbus.name); | |
921 | return -1; | |
922 | } | |
923 | } | |
924 | ||
925 | for (i = 0; i < portcount; i++) { | |
926 | s->companion_ports[firstport + i] = ports[i]; | |
927 | s->ports[firstport + i].speedmask |= | |
928 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
929 | /* Ensure devs attached before the initial reset go to the companion */ | |
930 | s->portsc[firstport + i] = PORTSC_POWNER; | |
931 | } | |
932 | ||
933 | s->companion_count++; | |
934 | s->mmio[0x05] = (s->companion_count << 4) | portcount; | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
828143c6 GH |
939 | static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) |
940 | { | |
941 | USBDevice *dev; | |
942 | USBPort *port; | |
943 | int i; | |
944 | ||
945 | for (i = 0; i < NB_PORTS; i++) { | |
946 | port = &ehci->ports[i]; | |
947 | if (!(ehci->portsc[i] & PORTSC_PED)) { | |
948 | DPRINTF("Port %d not enabled\n", i); | |
949 | continue; | |
950 | } | |
951 | dev = usb_find_device(port, addr); | |
952 | if (dev != NULL) { | |
953 | return dev; | |
954 | } | |
955 | } | |
956 | return NULL; | |
957 | } | |
958 | ||
94527ead GH |
959 | /* 4.1 host controller initialization */ |
960 | static void ehci_reset(void *opaque) | |
961 | { | |
962 | EHCIState *s = opaque; | |
94527ead | 963 | int i; |
a0a3167a | 964 | USBDevice *devs[NB_PORTS]; |
94527ead | 965 | |
439a97cc | 966 | trace_usb_ehci_reset(); |
94527ead | 967 | |
a0a3167a HG |
968 | /* |
969 | * Do the detach before touching portsc, so that it correctly gets send to | |
970 | * us or to our companion based on PORTSC_POWNER before the reset. | |
971 | */ | |
972 | for(i = 0; i < NB_PORTS; i++) { | |
973 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
974 | if (devs[i] && devs[i]->attached) { |
975 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
976 | } |
977 | } | |
978 | ||
94527ead GH |
979 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); |
980 | ||
981 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
982 | s->usbsts = USBSTS_HALT; | |
983 | ||
984 | s->astate = EST_INACTIVE; | |
985 | s->pstate = EST_INACTIVE; | |
94527ead GH |
986 | |
987 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
988 | if (s->companion_ports[i]) { |
989 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
990 | } else { | |
991 | s->portsc[i] = PORTSC_PPOWER; | |
992 | } | |
891fb2cd GH |
993 | if (devs[i] && devs[i]->attached) { |
994 | usb_attach(&s->ports[i]); | |
d28f4e2d | 995 | usb_device_reset(devs[i]); |
94527ead GH |
996 | } |
997 | } | |
df5d5c5c HG |
998 | ehci_queues_rip_all(s, 0); |
999 | ehci_queues_rip_all(s, 1); | |
81d37739 | 1000 | qemu_del_timer(s->frame_timer); |
0fb3e299 | 1001 | qemu_bh_cancel(s->async_bh); |
94527ead GH |
1002 | } |
1003 | ||
1004 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
1005 | { | |
1006 | EHCIState *s = ptr; | |
1007 | uint32_t val; | |
1008 | ||
1009 | val = s->mmio[addr]; | |
1010 | ||
1011 | return val; | |
1012 | } | |
1013 | ||
1014 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
1015 | { | |
1016 | EHCIState *s = ptr; | |
1017 | uint32_t val; | |
1018 | ||
1019 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
1020 | ||
1021 | return val; | |
1022 | } | |
1023 | ||
1024 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
1025 | { | |
1026 | EHCIState *s = ptr; | |
1027 | uint32_t val; | |
1028 | ||
1029 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
1030 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
1031 | ||
439a97cc | 1032 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
1033 | return val; |
1034 | } | |
1035 | ||
1036 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1037 | { | |
1038 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
1039 | exit(1); | |
1040 | } | |
1041 | ||
1042 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1043 | { | |
1044 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
1045 | exit(1); | |
1046 | } | |
1047 | ||
a0a3167a HG |
1048 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
1049 | { | |
1050 | USBDevice *dev = s->ports[port].dev; | |
1051 | uint32_t *portsc = &s->portsc[port]; | |
1052 | uint32_t orig; | |
1053 | ||
1054 | if (s->companion_ports[port] == NULL) | |
1055 | return; | |
1056 | ||
1057 | owner = owner & PORTSC_POWNER; | |
1058 | orig = *portsc & PORTSC_POWNER; | |
1059 | ||
1060 | if (!(owner ^ orig)) { | |
1061 | return; | |
1062 | } | |
1063 | ||
891fb2cd GH |
1064 | if (dev && dev->attached) { |
1065 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
1066 | } |
1067 | ||
1068 | *portsc &= ~PORTSC_POWNER; | |
1069 | *portsc |= owner; | |
1070 | ||
891fb2cd GH |
1071 | if (dev && dev->attached) { |
1072 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
1073 | } |
1074 | } | |
1075 | ||
94527ead GH |
1076 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) |
1077 | { | |
1078 | uint32_t *portsc = &s->portsc[port]; | |
94527ead GH |
1079 | USBDevice *dev = s->ports[port].dev; |
1080 | ||
fbd97532 HG |
1081 | /* Clear rwc bits */ |
1082 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
1083 | /* The guest may clear, but not set the PED bit */ | |
1084 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
1085 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
1086 | handle_port_owner_write(s, port, val); | |
1087 | /* And finally apply RO_MASK */ | |
94527ead GH |
1088 | val &= PORTSC_RO_MASK; |
1089 | ||
94527ead | 1090 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 1091 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
1092 | } |
1093 | ||
1094 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 1095 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 1096 | if (dev && dev->attached) { |
d28f4e2d | 1097 | usb_port_reset(&s->ports[port]); |
94527ead GH |
1098 | *portsc &= ~PORTSC_CSC; |
1099 | } | |
1100 | ||
fbd97532 HG |
1101 | /* |
1102 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 1103 | * to SW that this port has a high speed device attached |
94527ead | 1104 | */ |
891fb2cd | 1105 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
1106 | val |= PORTSC_PED; |
1107 | } | |
94527ead GH |
1108 | } |
1109 | ||
1110 | *portsc &= ~PORTSC_RO_MASK; | |
1111 | *portsc |= val; | |
94527ead GH |
1112 | } |
1113 | ||
1114 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1115 | { | |
1116 | EHCIState *s = ptr; | |
c4f8e211 GH |
1117 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
1118 | uint32_t old = *mmio; | |
94527ead | 1119 | int i; |
439a97cc | 1120 | |
c4f8e211 | 1121 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
1122 | |
1123 | /* Only aligned reads are allowed on OHCI */ | |
1124 | if (addr & 3) { | |
1125 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
1126 | TARGET_FMT_plx "\n", addr); | |
1127 | return; | |
1128 | } | |
1129 | ||
1130 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
1131 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 1132 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
1133 | return; |
1134 | } | |
1135 | ||
1136 | if (addr < OPREGBASE) { | |
1137 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
1138 | TARGET_FMT_plx "\n", addr); | |
1139 | return; | |
1140 | } | |
1141 | ||
1142 | ||
1143 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
1144 | switch(addr) { |
1145 | case USBCMD: | |
7046530c GH |
1146 | if (val & USBCMD_HCRESET) { |
1147 | ehci_reset(s); | |
1148 | val = s->usbcmd; | |
1149 | break; | |
1150 | } | |
1151 | ||
daf25307 GH |
1152 | if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != |
1153 | ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { | |
1154 | if (!ehci_enabled(s)) { | |
1155 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); | |
1156 | SET_LAST_RUN_CLOCK(s); | |
1157 | } | |
1158 | ehci_update_halt(s); | |
94527ead GH |
1159 | } |
1160 | ||
94527ead GH |
1161 | /* not supporting dynamic frame list size at the moment */ |
1162 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1163 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1164 | val & USBCMD_FLS); | |
1165 | val &= ~USBCMD_FLS; | |
1166 | } | |
94527ead GH |
1167 | break; |
1168 | ||
94527ead | 1169 | case USBSTS: |
a31f0531 JM |
1170 | val &= USBSTS_RO_MASK; // bits 6 through 31 are RO |
1171 | ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC | |
439a97cc | 1172 | val = s->usbsts; |
94527ead GH |
1173 | ehci_set_interrupt(s, 0); |
1174 | break; | |
1175 | ||
94527ead GH |
1176 | case USBINTR: |
1177 | val &= USBINTR_MASK; | |
94527ead GH |
1178 | break; |
1179 | ||
8a771f77 HG |
1180 | case FRINDEX: |
1181 | val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ | |
1182 | break; | |
1183 | ||
94527ead | 1184 | case CONFIGFLAG: |
94527ead GH |
1185 | val &= 0x1; |
1186 | if (val) { | |
1187 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 1188 | handle_port_owner_write(s, i, 0); |
94527ead GH |
1189 | } |
1190 | break; | |
1191 | ||
1192 | case PERIODICLISTBASE: | |
ec807d12 | 1193 | if (ehci_periodic_enabled(s)) { |
94527ead GH |
1194 | fprintf(stderr, |
1195 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1196 | " is enabled and HC is enabled\n"); | |
1197 | } | |
94527ead GH |
1198 | break; |
1199 | ||
1200 | case ASYNCLISTADDR: | |
ec807d12 | 1201 | if (ehci_async_enabled(s)) { |
94527ead GH |
1202 | fprintf(stderr, |
1203 | "ehci: ASYNC list address register set while async schedule\n" | |
1204 | " is enabled and HC is enabled\n"); | |
1205 | } | |
94527ead GH |
1206 | break; |
1207 | } | |
1208 | ||
c4f8e211 GH |
1209 | *mmio = val; |
1210 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
1211 | } |
1212 | ||
1213 | ||
1214 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1215 | ||
1216 | /* Get an array of dwords from main memory */ | |
68d55358 DG |
1217 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1218 | uint32_t *buf, int num) | |
94527ead GH |
1219 | { |
1220 | int i; | |
1221 | ||
1222 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
4bf80119 | 1223 | pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); |
94527ead GH |
1224 | *buf = le32_to_cpu(*buf); |
1225 | } | |
1226 | ||
1227 | return 1; | |
1228 | } | |
1229 | ||
1230 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1231 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1232 | uint32_t *buf, int num) | |
94527ead GH |
1233 | { |
1234 | int i; | |
1235 | ||
1236 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1237 | uint32_t tmp = cpu_to_le32(*buf); | |
4bf80119 | 1238 | pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); |
94527ead GH |
1239 | } |
1240 | ||
1241 | return 1; | |
1242 | } | |
1243 | ||
1244 | // 4.10.2 | |
1245 | ||
0122f472 | 1246 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead | 1247 | { |
eb36a88e | 1248 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead GH |
1249 | int i; |
1250 | int dtoggle; | |
1251 | int ping; | |
1252 | int eps; | |
1253 | int reload; | |
1254 | ||
eb36a88e GH |
1255 | assert(p != NULL); |
1256 | assert(p->qtdaddr == q->qtdaddr); | |
1257 | ||
94527ead GH |
1258 | // remember values in fields to preserve in qh after overlay |
1259 | ||
0122f472 GH |
1260 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1261 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1262 | |
eb36a88e GH |
1263 | q->qh.current_qtd = p->qtdaddr; |
1264 | q->qh.next_qtd = p->qtd.next; | |
1265 | q->qh.altnext_qtd = p->qtd.altnext; | |
1266 | q->qh.token = p->qtd.token; | |
94527ead GH |
1267 | |
1268 | ||
0122f472 | 1269 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1270 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1271 | q->qh.token &= ~QTD_TOKEN_PING; |
1272 | q->qh.token |= ping; | |
94527ead GH |
1273 | } |
1274 | ||
0122f472 GH |
1275 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1276 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1277 | |
1278 | for (i = 0; i < 5; i++) { | |
eb36a88e | 1279 | q->qh.bufptr[i] = p->qtd.bufptr[i]; |
94527ead GH |
1280 | } |
1281 | ||
0122f472 | 1282 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1283 | // preserve QH DT bit |
0122f472 GH |
1284 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1285 | q->qh.token |= dtoggle; | |
94527ead GH |
1286 | } |
1287 | ||
0122f472 GH |
1288 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1289 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1290 | |
68d55358 DG |
1291 | put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, |
1292 | sizeof(EHCIqh) >> 2); | |
94527ead GH |
1293 | |
1294 | return 0; | |
1295 | } | |
1296 | ||
eb36a88e | 1297 | static int ehci_init_transfer(EHCIPacket *p) |
94527ead | 1298 | { |
0ce668bc | 1299 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1300 | dma_addr_t page; |
94527ead | 1301 | |
eb36a88e GH |
1302 | cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1303 | bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); | |
1304 | offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; | |
1305 | pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); | |
94527ead | 1306 | |
0ce668bc GH |
1307 | while (bytes > 0) { |
1308 | if (cpage > 4) { | |
1309 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1310 | return USB_RET_PROCERR; | |
1311 | } | |
94527ead | 1312 | |
eb36a88e | 1313 | page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
0ce668bc GH |
1314 | page += offset; |
1315 | plen = bytes; | |
1316 | if (plen > 4096 - offset) { | |
1317 | plen = 4096 - offset; | |
1318 | offset = 0; | |
1319 | cpage++; | |
94527ead GH |
1320 | } |
1321 | ||
eb36a88e | 1322 | qemu_sglist_add(&p->sgl, page, plen); |
0ce668bc GH |
1323 | bytes -= plen; |
1324 | } | |
1325 | return 0; | |
1326 | } | |
94527ead | 1327 | |
0ce668bc GH |
1328 | static void ehci_finish_transfer(EHCIQueue *q, int status) |
1329 | { | |
1330 | uint32_t cpage, offset; | |
94527ead | 1331 | |
0ce668bc GH |
1332 | if (status > 0) { |
1333 | /* update cpage & offset */ | |
1334 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1335 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1336 | |
0ce668bc GH |
1337 | offset += status; |
1338 | cpage += offset >> QTD_BUFPTR_SH; | |
1339 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1340 | |
0ce668bc GH |
1341 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1342 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1343 | q->qh.bufptr[0] |= offset; | |
1344 | } | |
94527ead GH |
1345 | } |
1346 | ||
d47e59b8 | 1347 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1348 | { |
eb36a88e | 1349 | EHCIPacket *p; |
a0a3167a HG |
1350 | EHCIState *s = port->opaque; |
1351 | uint32_t portsc = s->portsc[port->index]; | |
1352 | ||
1353 | if (portsc & PORTSC_POWNER) { | |
1354 | USBPort *companion = s->companion_ports[port->index]; | |
1355 | companion->ops->complete(companion, packet); | |
1356 | return; | |
1357 | } | |
94527ead | 1358 | |
eb36a88e GH |
1359 | p = container_of(packet, EHCIPacket, packet); |
1360 | trace_usb_ehci_packet_action(p->queue, p, "wakeup"); | |
1361 | assert(p->async == EHCI_ASYNC_INFLIGHT); | |
1362 | p->async = EHCI_ASYNC_FINISHED; | |
1363 | p->usb_status = packet->result; | |
ae710b99 GH |
1364 | |
1365 | if (p->queue->async) { | |
1366 | qemu_bh_schedule(p->queue->ehci->async_bh); | |
1367 | } | |
94527ead GH |
1368 | } |
1369 | ||
0122f472 | 1370 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead | 1371 | { |
eb36a88e GH |
1372 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1373 | ||
1374 | assert(p != NULL); | |
1375 | assert(p->qtdaddr == q->qtdaddr); | |
1376 | assert(p->async != EHCI_ASYNC_INFLIGHT); | |
1377 | p->async = EHCI_ASYNC_NONE; | |
94527ead GH |
1378 | |
1379 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1380 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1381 | |
eb36a88e GH |
1382 | if (p->usb_status < 0) { |
1383 | switch (p->usb_status) { | |
d61000a8 | 1384 | case USB_RET_IOERROR: |
94527ead | 1385 | case USB_RET_NODEV: |
d2bd525f | 1386 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
dd54cfe0 | 1387 | set_field(&q->qh.token, 0, QTD_TOKEN_CERR); |
d2bd525f | 1388 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1389 | break; |
1390 | case USB_RET_STALL: | |
0122f472 GH |
1391 | q->qh.token |= QTD_TOKEN_HALT; |
1392 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1393 | break; |
1394 | case USB_RET_NAK: | |
553a6a59 HG |
1395 | set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); |
1396 | return; /* We're not done yet with this transaction */ | |
94527ead | 1397 | case USB_RET_BABBLE: |
d2bd525f | 1398 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1399 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1400 | break; |
1401 | default: | |
0122f472 | 1402 | /* should not be triggerable */ |
eb36a88e | 1403 | fprintf(stderr, "USB invalid response %d\n", p->usb_status); |
0122f472 | 1404 | assert(0); |
94527ead GH |
1405 | break; |
1406 | } | |
eb36a88e GH |
1407 | } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) { |
1408 | p->usb_status = USB_RET_BABBLE; | |
dd54cfe0 HG |
1409 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
1410 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead | 1411 | } else { |
94527ead GH |
1412 | // TODO check 4.12 for splits |
1413 | ||
eb36a88e GH |
1414 | if (p->tbytes && p->pid == USB_TOKEN_IN) { |
1415 | p->tbytes -= p->usb_status; | |
94527ead | 1416 | } else { |
eb36a88e | 1417 | p->tbytes = 0; |
94527ead GH |
1418 | } |
1419 | ||
eb36a88e GH |
1420 | DPRINTF("updating tbytes to %d\n", p->tbytes); |
1421 | set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); | |
94527ead | 1422 | } |
eb36a88e GH |
1423 | ehci_finish_transfer(q, p->usb_status); |
1424 | qemu_sglist_destroy(&p->sgl); | |
1425 | usb_packet_unmap(&p->packet); | |
94527ead | 1426 | |
0122f472 GH |
1427 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1428 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1429 | |
553a6a59 | 1430 | if (q->qh.token & QTD_TOKEN_IOC) { |
0122f472 | 1431 | ehci_record_interrupt(q->ehci, USBSTS_INT); |
94527ead | 1432 | } |
94527ead GH |
1433 | } |
1434 | ||
1435 | // 4.10.3 | |
1436 | ||
773dc9cd | 1437 | static int ehci_execute(EHCIPacket *p, const char *action) |
94527ead | 1438 | { |
079d0b7f | 1439 | USBEndpoint *ep; |
94527ead | 1440 | int ret; |
94527ead | 1441 | int endp; |
94527ead | 1442 | |
4224558f GH |
1443 | if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { |
1444 | fprintf(stderr, "Attempting to execute inactive qtd\n"); | |
94527ead GH |
1445 | return USB_RET_PROCERR; |
1446 | } | |
1447 | ||
4224558f | 1448 | p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
eb36a88e | 1449 | if (p->tbytes > BUFF_SIZE) { |
94527ead GH |
1450 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1451 | return USB_RET_PROCERR; | |
1452 | } | |
1453 | ||
4224558f | 1454 | p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
eb36a88e GH |
1455 | switch (p->pid) { |
1456 | case 0: | |
1457 | p->pid = USB_TOKEN_OUT; | |
1458 | break; | |
1459 | case 1: | |
1460 | p->pid = USB_TOKEN_IN; | |
1461 | break; | |
1462 | case 2: | |
1463 | p->pid = USB_TOKEN_SETUP; | |
1464 | break; | |
1465 | default: | |
1466 | fprintf(stderr, "bad token\n"); | |
1467 | break; | |
94527ead GH |
1468 | } |
1469 | ||
eb36a88e | 1470 | if (ehci_init_transfer(p) != 0) { |
94527ead GH |
1471 | return USB_RET_PROCERR; |
1472 | } | |
1473 | ||
4224558f | 1474 | endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); |
e59928b3 | 1475 | ep = usb_ep_get(p->queue->dev, p->pid, endp); |
94527ead | 1476 | |
eb36a88e GH |
1477 | usb_packet_setup(&p->packet, p->pid, ep); |
1478 | usb_packet_map(&p->packet, &p->sgl); | |
0ce668bc | 1479 | |
773dc9cd | 1480 | trace_usb_ehci_packet_action(p->queue, p, action); |
e59928b3 | 1481 | ret = usb_handle_packet(p->queue->dev, &p->packet); |
828143c6 GH |
1482 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " |
1483 | "(total %d) endp %x ret %d\n", | |
1484 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, | |
1485 | q->packet.iov.size, q->tbytes, endp, ret); | |
94527ead GH |
1486 | |
1487 | if (ret > BUFF_SIZE) { | |
1488 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1489 | return USB_RET_PROCERR; | |
1490 | } | |
1491 | ||
94527ead GH |
1492 | return ret; |
1493 | } | |
1494 | ||
1495 | /* 4.7.2 | |
1496 | */ | |
1497 | ||
1498 | static int ehci_process_itd(EHCIState *ehci, | |
1499 | EHCIitd *itd) | |
1500 | { | |
94527ead | 1501 | USBDevice *dev; |
079d0b7f | 1502 | USBEndpoint *ep; |
94527ead | 1503 | int ret; |
828143c6 | 1504 | uint32_t i, len, pid, dir, devaddr, endp; |
e654887f | 1505 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead GH |
1506 | |
1507 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1508 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1509 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1510 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1511 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1512 | |
1513 | for(i = 0; i < 8; i++) { | |
1514 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1515 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1516 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1517 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1518 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1519 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1520 | ||
1521 | if (len > max * mult) { | |
1522 | len = max * mult; | |
1523 | } | |
94527ead GH |
1524 | |
1525 | if (len > BUFF_SIZE) { | |
1526 | return USB_RET_PROCERR; | |
1527 | } | |
1528 | ||
68d55358 | 1529 | pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); |
e654887f GH |
1530 | if (off + len > 4096) { |
1531 | /* transfer crosses page border */ | |
0ce668bc GH |
1532 | uint32_t len2 = off + len - 4096; |
1533 | uint32_t len1 = len - len2; | |
1534 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1535 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1536 | } else { |
0ce668bc | 1537 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1538 | } |
94527ead | 1539 | |
0ce668bc | 1540 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1541 | |
079d0b7f GH |
1542 | dev = ehci_find_device(ehci, devaddr); |
1543 | ep = usb_ep_get(dev, pid, endp); | |
aa0568ff GH |
1544 | if (ep->type == USB_ENDPOINT_XFER_ISOC) { |
1545 | usb_packet_setup(&ehci->ipacket, pid, ep); | |
1546 | usb_packet_map(&ehci->ipacket, &ehci->isgl); | |
1547 | ret = usb_handle_packet(dev, &ehci->ipacket); | |
1548 | assert(ret != USB_RET_ASYNC); | |
1549 | usb_packet_unmap(&ehci->ipacket); | |
1550 | } else { | |
1551 | DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); | |
1552 | ret = USB_RET_NAK; | |
1553 | } | |
0ce668bc GH |
1554 | qemu_sglist_destroy(&ehci->isgl); |
1555 | ||
5eafd438 | 1556 | if (ret < 0) { |
df787185 HG |
1557 | switch (ret) { |
1558 | default: | |
1559 | fprintf(stderr, "Unexpected iso usb result: %d\n", ret); | |
1560 | /* Fall through */ | |
d61000a8 | 1561 | case USB_RET_IOERROR: |
df787185 HG |
1562 | case USB_RET_NODEV: |
1563 | /* 3.3.2: XACTERR is only allowed on IN transactions */ | |
1564 | if (dir) { | |
1565 | itd->transact[i] |= ITD_XACT_XACTERR; | |
1566 | ehci_record_interrupt(ehci, USBSTS_ERRINT); | |
1567 | } | |
1568 | break; | |
1569 | case USB_RET_BABBLE: | |
1570 | itd->transact[i] |= ITD_XACT_BABBLE; | |
1571 | ehci_record_interrupt(ehci, USBSTS_ERRINT); | |
1572 | break; | |
5eafd438 HG |
1573 | case USB_RET_NAK: |
1574 | /* no data for us, so do a zero-length transfer */ | |
1575 | ret = 0; | |
1576 | break; | |
1577 | } | |
1578 | } | |
1579 | if (ret >= 0) { | |
1580 | if (!dir) { | |
1581 | /* OUT */ | |
1582 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1583 | } else { | |
1584 | /* IN */ | |
1585 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
94527ead GH |
1586 | } |
1587 | } | |
df787185 HG |
1588 | if (itd->transact[i] & ITD_XACT_IOC) { |
1589 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1590 | } | |
e654887f | 1591 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1592 | } |
1593 | } | |
1594 | return 0; | |
1595 | } | |
1596 | ||
cd665715 GH |
1597 | |
1598 | /* | |
1599 | * Write the qh back to guest physical memory. This step isn't | |
1600 | * in the EHCI spec but we need to do it since we don't share | |
1601 | * physical memory with our guest VM. | |
1602 | * | |
1603 | * The first three dwords are read-only for the EHCI, so skip them | |
1604 | * when writing back the qh. | |
1605 | */ | |
1606 | static void ehci_flush_qh(EHCIQueue *q) | |
1607 | { | |
1608 | uint32_t *qh = (uint32_t *) &q->qh; | |
1609 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1610 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1611 | ||
1612 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); | |
1613 | } | |
1614 | ||
94527ead GH |
1615 | /* This state is the entry point for asynchronous schedule |
1616 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1617 | */ | |
26d53979 | 1618 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1619 | { |
0122f472 | 1620 | EHCIqh qh; |
94527ead GH |
1621 | int i = 0; |
1622 | int again = 0; | |
1623 | uint32_t entry = ehci->asynclistaddr; | |
1624 | ||
1625 | /* set reclamation flag at start event (4.8.6) */ | |
1626 | if (async) { | |
439a97cc | 1627 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1628 | } |
1629 | ||
4be23939 | 1630 | ehci_queues_rip_unused(ehci, async, 0); |
8ac6d699 | 1631 | |
94527ead GH |
1632 | /* Find the head of the list (4.9.1.1) */ |
1633 | for(i = 0; i < MAX_QH; i++) { | |
68d55358 DG |
1634 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1635 | sizeof(EHCIqh) >> 2); | |
8ac6d699 | 1636 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1637 | |
0122f472 | 1638 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1639 | if (async) { |
1640 | entry |= (NLPTR_TYPE_QH << 1); | |
1641 | } | |
1642 | ||
0122f472 | 1643 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1644 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1645 | again = 1; |
1646 | goto out; | |
1647 | } | |
1648 | ||
0122f472 | 1649 | entry = qh.next; |
94527ead | 1650 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1651 | break; |
1652 | } | |
1653 | } | |
1654 | ||
1655 | /* no head found for list. */ | |
1656 | ||
26d53979 | 1657 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1658 | |
1659 | out: | |
1660 | return again; | |
1661 | } | |
1662 | ||
1663 | ||
1664 | /* This state is the entry point for periodic schedule processing as | |
1665 | * well as being a continuation state for async processing. | |
1666 | */ | |
26d53979 | 1667 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1668 | { |
1669 | int again = 0; | |
0122f472 | 1670 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1671 | |
2a5ff735 | 1672 | if (NLPTR_TBIT(entry)) { |
26d53979 | 1673 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1674 | goto out; |
1675 | } | |
1676 | ||
1677 | /* section 4.8, only QH in async schedule */ | |
1678 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1679 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1680 | return -1; | |
1681 | } | |
1682 | ||
1683 | switch (NLPTR_TYPE_GET(entry)) { | |
1684 | case NLPTR_TYPE_QH: | |
26d53979 | 1685 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1686 | again = 1; |
1687 | break; | |
1688 | ||
1689 | case NLPTR_TYPE_ITD: | |
26d53979 | 1690 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1691 | again = 1; |
1692 | break; | |
1693 | ||
2fe80192 GH |
1694 | case NLPTR_TYPE_STITD: |
1695 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1696 | again = 1; | |
1697 | break; | |
1698 | ||
94527ead | 1699 | default: |
2fe80192 | 1700 | /* TODO: handle FSTN type */ |
94527ead GH |
1701 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1702 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1703 | return -1; | |
1704 | } | |
1705 | ||
1706 | out: | |
1707 | return again; | |
1708 | } | |
1709 | ||
0122f472 | 1710 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1711 | { |
eb36a88e | 1712 | EHCIPacket *p; |
e59928b3 | 1713 | uint32_t entry, devaddr; |
0122f472 | 1714 | EHCIQueue *q; |
94527ead | 1715 | |
0122f472 | 1716 | entry = ehci_get_fetch_addr(ehci, async); |
df5d5c5c | 1717 | q = ehci_find_queue_by_qh(ehci, entry, async); |
8ac6d699 | 1718 | if (NULL == q) { |
8f6d5e26 | 1719 | q = ehci_alloc_queue(ehci, entry, async); |
8ac6d699 | 1720 | } |
eb36a88e | 1721 | p = QTAILQ_FIRST(&q->packets); |
8ac6d699 | 1722 | |
8f6d5e26 | 1723 | q->seen++; |
8ac6d699 GH |
1724 | if (q->seen > 1) { |
1725 | /* we are going in circles -- stop processing */ | |
1726 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1727 | q = NULL; | |
1728 | goto out; | |
1729 | } | |
94527ead | 1730 | |
68d55358 DG |
1731 | get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1732 | (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
8ac6d699 GH |
1733 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1734 | ||
e59928b3 GH |
1735 | devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); |
1736 | if (q->dev != NULL && q->dev->addr != devaddr) { | |
1737 | if (!QTAILQ_EMPTY(&q->packets)) { | |
1738 | /* should not happen (guest bug) */ | |
1739 | while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { | |
1740 | ehci_free_packet(p); | |
1741 | } | |
1742 | } | |
1743 | q->dev = NULL; | |
1744 | } | |
1745 | if (q->dev == NULL) { | |
1746 | q->dev = ehci_find_device(q->ehci, devaddr); | |
1747 | } | |
1748 | ||
eb36a88e | 1749 | if (p && p->async == EHCI_ASYNC_INFLIGHT) { |
8ac6d699 GH |
1750 | /* I/O still in progress -- skip queue */ |
1751 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1752 | goto out; | |
1753 | } | |
eb36a88e | 1754 | if (p && p->async == EHCI_ASYNC_FINISHED) { |
8ac6d699 | 1755 | /* I/O finished -- continue processing queue */ |
773dc9cd | 1756 | trace_usb_ehci_packet_action(p->queue, p, "complete"); |
8ac6d699 GH |
1757 | ehci_set_state(ehci, async, EST_EXECUTING); |
1758 | goto out; | |
1759 | } | |
0122f472 GH |
1760 | |
1761 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1762 | |
1763 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1764 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1765 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1766 | } else { |
1767 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1768 | " - done processing\n", q->qhaddr); |
26d53979 | 1769 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1770 | q = NULL; |
94527ead GH |
1771 | goto out; |
1772 | } | |
1773 | } | |
1774 | ||
1775 | #if EHCI_DEBUG | |
0122f472 | 1776 | if (q->qhaddr != q->qh.next) { |
94527ead | 1777 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1778 | q->qhaddr, |
1779 | q->qh.epchar & QH_EPCHAR_H, | |
1780 | q->qh.token & QTD_TOKEN_HALT, | |
1781 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1782 | q->qh.next); | |
94527ead GH |
1783 | } |
1784 | #endif | |
1785 | ||
0122f472 | 1786 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1787 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1788 | |
2a5ff735 HG |
1789 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1790 | (NLPTR_TBIT(q->qh.current_qtd) == 0)) { | |
0122f472 | 1791 | q->qtdaddr = q->qh.current_qtd; |
26d53979 | 1792 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1793 | |
1794 | } else { | |
1795 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1796 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1797 | } |
1798 | ||
1799 | out: | |
0122f472 | 1800 | return q; |
94527ead GH |
1801 | } |
1802 | ||
26d53979 | 1803 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1804 | { |
0122f472 | 1805 | uint32_t entry; |
94527ead GH |
1806 | EHCIitd itd; |
1807 | ||
0122f472 GH |
1808 | assert(!async); |
1809 | entry = ehci_get_fetch_addr(ehci, async); | |
1810 | ||
68d55358 | 1811 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1812 | sizeof(EHCIitd) >> 2); |
0122f472 | 1813 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1814 | |
1815 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1816 | return -1; | |
1817 | } | |
1818 | ||
68d55358 DG |
1819 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1820 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1821 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1822 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1823 | |
1824 | return 1; | |
1825 | } | |
1826 | ||
2fe80192 GH |
1827 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1828 | { | |
1829 | uint32_t entry; | |
1830 | EHCIsitd sitd; | |
1831 | ||
1832 | assert(!async); | |
1833 | entry = ehci_get_fetch_addr(ehci, async); | |
1834 | ||
68d55358 | 1835 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
2fe80192 GH |
1836 | sizeof(EHCIsitd) >> 2); |
1837 | ehci_trace_sitd(ehci, entry, &sitd); | |
1838 | ||
1839 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1840 | /* siTD is not active, nothing to do */; | |
1841 | } else { | |
1842 | /* TODO: split transfers are not implemented */ | |
1843 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1844 | } | |
1845 | ||
1846 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1847 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1848 | return 1; | |
1849 | } | |
1850 | ||
94527ead | 1851 | /* Section 4.10.2 - paragraph 3 */ |
ae0138a8 | 1852 | static int ehci_state_advqueue(EHCIQueue *q) |
94527ead GH |
1853 | { |
1854 | #if 0 | |
1855 | /* TO-DO: 4.10.2 - paragraph 2 | |
1856 | * if I-bit is set to 1 and QH is not active | |
1857 | * go to horizontal QH | |
1858 | */ | |
1859 | if (I-bit set) { | |
26d53979 | 1860 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1861 | goto out; |
1862 | } | |
1863 | #endif | |
1864 | ||
1865 | /* | |
1866 | * want data and alt-next qTD is valid | |
1867 | */ | |
0122f472 | 1868 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
0122f472 GH |
1869 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { |
1870 | q->qtdaddr = q->qh.altnext_qtd; | |
ae0138a8 | 1871 | ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
94527ead GH |
1872 | |
1873 | /* | |
1874 | * next qTD is valid | |
1875 | */ | |
2a5ff735 | 1876 | } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
0122f472 | 1877 | q->qtdaddr = q->qh.next_qtd; |
ae0138a8 | 1878 | ehci_set_state(q->ehci, q->async, EST_FETCHQTD); |
94527ead GH |
1879 | |
1880 | /* | |
1881 | * no valid qTD, try next QH | |
1882 | */ | |
1883 | } else { | |
ae0138a8 | 1884 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead GH |
1885 | } |
1886 | ||
1887 | return 1; | |
1888 | } | |
1889 | ||
1890 | /* Section 4.10.2 - paragraph 4 */ | |
ae0138a8 | 1891 | static int ehci_state_fetchqtd(EHCIQueue *q) |
94527ead | 1892 | { |
eb36a88e GH |
1893 | EHCIqtd qtd; |
1894 | EHCIPacket *p; | |
94527ead GH |
1895 | int again = 0; |
1896 | ||
eb36a88e | 1897 | get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
68d55358 | 1898 | sizeof(EHCIqtd) >> 2); |
eb36a88e | 1899 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
94527ead | 1900 | |
773dc9cd GH |
1901 | p = QTAILQ_FIRST(&q->packets); |
1902 | while (p != NULL && p->qtdaddr != q->qtdaddr) { | |
1903 | /* should not happen (guest bug) */ | |
1904 | ehci_free_packet(p); | |
1905 | p = QTAILQ_FIRST(&q->packets); | |
1906 | } | |
1907 | if (p != NULL) { | |
1908 | ehci_qh_do_overlay(q); | |
1909 | ehci_flush_qh(q); | |
1910 | if (p->async == EHCI_ASYNC_INFLIGHT) { | |
ae0138a8 | 1911 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
773dc9cd | 1912 | } else { |
ae0138a8 | 1913 | ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
773dc9cd GH |
1914 | } |
1915 | again = 1; | |
1916 | } else if (qtd.token & QTD_TOKEN_ACTIVE) { | |
eb36a88e GH |
1917 | p = ehci_alloc_packet(q); |
1918 | p->qtdaddr = q->qtdaddr; | |
1919 | p->qtd = qtd; | |
ae0138a8 | 1920 | ehci_set_state(q->ehci, q->async, EST_EXECUTE); |
94527ead GH |
1921 | again = 1; |
1922 | } else { | |
ae0138a8 | 1923 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead GH |
1924 | again = 1; |
1925 | } | |
1926 | ||
1927 | return again; | |
1928 | } | |
1929 | ||
ae0138a8 | 1930 | static int ehci_state_horizqh(EHCIQueue *q) |
94527ead GH |
1931 | { |
1932 | int again = 0; | |
1933 | ||
ae0138a8 GH |
1934 | if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { |
1935 | ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); | |
1936 | ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); | |
94527ead GH |
1937 | again = 1; |
1938 | } else { | |
ae0138a8 | 1939 | ehci_set_state(q->ehci, q->async, EST_ACTIVE); |
94527ead GH |
1940 | } |
1941 | ||
1942 | return again; | |
1943 | } | |
1944 | ||
ae0138a8 | 1945 | static void ehci_fill_queue(EHCIPacket *p) |
773dc9cd GH |
1946 | { |
1947 | EHCIQueue *q = p->queue; | |
1948 | EHCIqtd qtd = p->qtd; | |
1949 | uint32_t qtdaddr; | |
1950 | ||
1951 | for (;;) { | |
1952 | if (NLPTR_TBIT(qtd.altnext) == 0) { | |
1953 | break; | |
1954 | } | |
1955 | if (NLPTR_TBIT(qtd.next) != 0) { | |
1956 | break; | |
1957 | } | |
1958 | qtdaddr = qtd.next; | |
1959 | get_dwords(q->ehci, NLPTR_GET(qtdaddr), | |
1960 | (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); | |
1961 | ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); | |
1962 | if (!(qtd.token & QTD_TOKEN_ACTIVE)) { | |
1963 | break; | |
1964 | } | |
1965 | p = ehci_alloc_packet(q); | |
1966 | p->qtdaddr = qtdaddr; | |
1967 | p->qtd = qtd; | |
1968 | p->usb_status = ehci_execute(p, "queue"); | |
1969 | assert(p->usb_status = USB_RET_ASYNC); | |
1970 | p->async = EHCI_ASYNC_INFLIGHT; | |
1971 | } | |
1972 | } | |
1973 | ||
ae0138a8 | 1974 | static int ehci_state_execute(EHCIQueue *q) |
94527ead | 1975 | { |
eb36a88e | 1976 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 1977 | int again = 0; |
94527ead | 1978 | |
eb36a88e GH |
1979 | assert(p != NULL); |
1980 | assert(p->qtdaddr == q->qtdaddr); | |
1981 | ||
0122f472 | 1982 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1983 | return -1; |
1984 | } | |
1985 | ||
94527ead GH |
1986 | // TODO verify enough time remains in the uframe as in 4.4.1.1 |
1987 | // TODO write back ptr to async list when done or out of time | |
1988 | // TODO Windows does not seem to ever set the MULT field | |
1989 | ||
ae0138a8 | 1990 | if (!q->async) { |
0122f472 | 1991 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1992 | if (!transactCtr) { |
ae0138a8 | 1993 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead GH |
1994 | again = 1; |
1995 | goto out; | |
1996 | } | |
1997 | } | |
1998 | ||
ae0138a8 | 1999 | if (q->async) { |
0122f472 | 2000 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
2001 | } |
2002 | ||
773dc9cd | 2003 | p->usb_status = ehci_execute(p, "process"); |
eb36a88e | 2004 | if (p->usb_status == USB_RET_PROCERR) { |
94527ead GH |
2005 | again = -1; |
2006 | goto out; | |
2007 | } | |
eb36a88e | 2008 | if (p->usb_status == USB_RET_ASYNC) { |
8ac6d699 | 2009 | ehci_flush_qh(q); |
773dc9cd | 2010 | trace_usb_ehci_packet_action(p->queue, p, "async"); |
eb36a88e | 2011 | p->async = EHCI_ASYNC_INFLIGHT; |
ae0138a8 | 2012 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead | 2013 | again = 1; |
ae0138a8 | 2014 | ehci_fill_queue(p); |
8ac6d699 | 2015 | goto out; |
94527ead GH |
2016 | } |
2017 | ||
ae0138a8 | 2018 | ehci_set_state(q->ehci, q->async, EST_EXECUTING); |
8ac6d699 GH |
2019 | again = 1; |
2020 | ||
94527ead GH |
2021 | out: |
2022 | return again; | |
2023 | } | |
2024 | ||
ae0138a8 | 2025 | static int ehci_state_executing(EHCIQueue *q) |
94527ead | 2026 | { |
eb36a88e | 2027 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 2028 | int again = 0; |
94527ead | 2029 | |
eb36a88e GH |
2030 | assert(p != NULL); |
2031 | assert(p->qtdaddr == q->qtdaddr); | |
2032 | ||
0122f472 | 2033 | ehci_execute_complete(q); |
eb36a88e | 2034 | if (p->usb_status == USB_RET_ASYNC) { |
94527ead GH |
2035 | goto out; |
2036 | } | |
eb36a88e | 2037 | if (p->usb_status == USB_RET_PROCERR) { |
94527ead GH |
2038 | again = -1; |
2039 | goto out; | |
2040 | } | |
2041 | ||
2042 | // 4.10.3 | |
ae0138a8 | 2043 | if (!q->async) { |
0122f472 | 2044 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 2045 | transactCtr--; |
0122f472 | 2046 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
2047 | // 4.10.3, bottom of page 82, should exit this state when transaction |
2048 | // counter decrements to 0 | |
2049 | } | |
2050 | ||
94527ead | 2051 | /* 4.10.5 */ |
eb36a88e | 2052 | if (p->usb_status == USB_RET_NAK) { |
ae0138a8 | 2053 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
94527ead | 2054 | } else { |
ae0138a8 | 2055 | ehci_set_state(q->ehci, q->async, EST_WRITEBACK); |
94527ead GH |
2056 | } |
2057 | ||
2058 | again = 1; | |
2059 | ||
2060 | out: | |
8ac6d699 | 2061 | ehci_flush_qh(q); |
94527ead GH |
2062 | return again; |
2063 | } | |
2064 | ||
2065 | ||
ae0138a8 | 2066 | static int ehci_state_writeback(EHCIQueue *q) |
94527ead | 2067 | { |
eb36a88e | 2068 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead GH |
2069 | int again = 0; |
2070 | ||
2071 | /* Write back the QTD from the QH area */ | |
eb36a88e GH |
2072 | assert(p != NULL); |
2073 | assert(p->qtdaddr == q->qtdaddr); | |
2074 | ||
2075 | ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); | |
2076 | put_dwords(q->ehci, NLPTR_GET(p->qtdaddr), (uint32_t *) &q->qh.next_qtd, | |
68d55358 | 2077 | sizeof(EHCIqtd) >> 2); |
eb36a88e | 2078 | ehci_free_packet(p); |
94527ead | 2079 | |
d2bd525f GH |
2080 | /* |
2081 | * EHCI specs say go horizontal here. | |
2082 | * | |
2083 | * We can also advance the queue here for performance reasons. We | |
2084 | * need to take care to only take that shortcut in case we've | |
2085 | * processed the qtd just written back without errors, i.e. halt | |
2086 | * bit is clear. | |
94527ead | 2087 | */ |
d2bd525f | 2088 | if (q->qh.token & QTD_TOKEN_HALT) { |
ae0138a8 | 2089 | ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); |
d2bd525f GH |
2090 | again = 1; |
2091 | } else { | |
ae0138a8 | 2092 | ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); |
94527ead | 2093 | again = 1; |
d2bd525f | 2094 | } |
94527ead GH |
2095 | return again; |
2096 | } | |
2097 | ||
2098 | /* | |
2099 | * This is the state machine that is common to both async and periodic | |
2100 | */ | |
2101 | ||
ae0138a8 | 2102 | static void ehci_advance_state(EHCIState *ehci, int async) |
94527ead | 2103 | { |
0122f472 | 2104 | EHCIQueue *q = NULL; |
94527ead | 2105 | int again; |
94527ead GH |
2106 | |
2107 | do { | |
26d53979 | 2108 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2109 | case EST_WAITLISTHEAD: |
26d53979 | 2110 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
2111 | break; |
2112 | ||
2113 | case EST_FETCHENTRY: | |
26d53979 | 2114 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
2115 | break; |
2116 | ||
2117 | case EST_FETCHQH: | |
0122f472 | 2118 | q = ehci_state_fetchqh(ehci, async); |
ae0138a8 GH |
2119 | if (q != NULL) { |
2120 | assert(q->async == async); | |
2121 | again = 1; | |
2122 | } else { | |
2123 | again = 0; | |
2124 | } | |
94527ead GH |
2125 | break; |
2126 | ||
2127 | case EST_FETCHITD: | |
26d53979 | 2128 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
2129 | break; |
2130 | ||
2fe80192 GH |
2131 | case EST_FETCHSITD: |
2132 | again = ehci_state_fetchsitd(ehci, async); | |
2133 | break; | |
2134 | ||
94527ead | 2135 | case EST_ADVANCEQUEUE: |
ae0138a8 | 2136 | again = ehci_state_advqueue(q); |
94527ead GH |
2137 | break; |
2138 | ||
2139 | case EST_FETCHQTD: | |
ae0138a8 | 2140 | again = ehci_state_fetchqtd(q); |
94527ead GH |
2141 | break; |
2142 | ||
2143 | case EST_HORIZONTALQH: | |
ae0138a8 | 2144 | again = ehci_state_horizqh(q); |
94527ead GH |
2145 | break; |
2146 | ||
2147 | case EST_EXECUTE: | |
ae0138a8 | 2148 | again = ehci_state_execute(q); |
94527ead GH |
2149 | break; |
2150 | ||
2151 | case EST_EXECUTING: | |
8ac6d699 | 2152 | assert(q != NULL); |
ae0138a8 | 2153 | again = ehci_state_executing(q); |
94527ead GH |
2154 | break; |
2155 | ||
2156 | case EST_WRITEBACK: | |
b2467216 | 2157 | assert(q != NULL); |
ae0138a8 | 2158 | again = ehci_state_writeback(q); |
94527ead GH |
2159 | break; |
2160 | ||
2161 | default: | |
2162 | fprintf(stderr, "Bad state!\n"); | |
2163 | again = -1; | |
8ac6d699 | 2164 | assert(0); |
94527ead GH |
2165 | break; |
2166 | } | |
2167 | ||
2168 | if (again < 0) { | |
2169 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2170 | ehci_reset(ehci); | |
2171 | again = 0; | |
2172 | } | |
2173 | } | |
2174 | while (again); | |
2175 | ||
2176 | ehci_commit_interrupt(ehci); | |
94527ead GH |
2177 | } |
2178 | ||
2179 | static void ehci_advance_async_state(EHCIState *ehci) | |
2180 | { | |
df5d5c5c | 2181 | const int async = 1; |
94527ead | 2182 | |
26d53979 | 2183 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2184 | case EST_INACTIVE: |
ec807d12 | 2185 | if (!ehci_async_enabled(ehci)) { |
94527ead GH |
2186 | break; |
2187 | } | |
26d53979 | 2188 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2189 | // No break, fall through to ACTIVE |
2190 | ||
2191 | case EST_ACTIVE: | |
ec807d12 | 2192 | if (!ehci_async_enabled(ehci)) { |
e850c2b4 | 2193 | ehci_queues_rip_all(ehci, async); |
26d53979 | 2194 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2195 | break; |
2196 | } | |
2197 | ||
4be23939 | 2198 | /* make sure guest has acknowledged the doorbell interrupt */ |
94527ead GH |
2199 | /* TO-DO: is this really needed? */ |
2200 | if (ehci->usbsts & USBSTS_IAA) { | |
2201 | DPRINTF("IAA status bit still set.\n"); | |
2202 | break; | |
2203 | } | |
2204 | ||
94527ead GH |
2205 | /* check that address register has been set */ |
2206 | if (ehci->asynclistaddr == 0) { | |
2207 | break; | |
2208 | } | |
2209 | ||
26d53979 | 2210 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2211 | ehci_advance_state(ehci, async); |
4be23939 HG |
2212 | |
2213 | /* If the doorbell is set, the guest wants to make a change to the | |
2214 | * schedule. The host controller needs to release cached data. | |
2215 | * (section 4.8.2) | |
2216 | */ | |
2217 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2218 | /* Remove all unseen qhs from the async qhs queue */ | |
2219 | ehci_queues_rip_unused(ehci, async, 1); | |
2220 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
2221 | ehci->usbcmd &= ~USBCMD_IAAD; | |
2222 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
2223 | } | |
94527ead GH |
2224 | break; |
2225 | ||
2226 | default: | |
2227 | /* this should only be due to a developer mistake */ | |
2228 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2229 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2230 | assert(0); |
94527ead GH |
2231 | } |
2232 | } | |
2233 | ||
2234 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2235 | { | |
2236 | uint32_t entry; | |
2237 | uint32_t list; | |
df5d5c5c | 2238 | const int async = 0; |
94527ead GH |
2239 | |
2240 | // 4.6 | |
2241 | ||
26d53979 | 2242 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2243 | case EST_INACTIVE: |
ec807d12 | 2244 | if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { |
26d53979 | 2245 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2246 | // No break, fall through to ACTIVE |
2247 | } else | |
2248 | break; | |
2249 | ||
2250 | case EST_ACTIVE: | |
ec807d12 | 2251 | if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { |
e850c2b4 | 2252 | ehci_queues_rip_all(ehci, async); |
26d53979 | 2253 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2254 | break; |
2255 | } | |
2256 | ||
2257 | list = ehci->periodiclistbase & 0xfffff000; | |
2258 | /* check that register has been set */ | |
2259 | if (list == 0) { | |
2260 | break; | |
2261 | } | |
2262 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2263 | ||
4bf80119 | 2264 | pci_dma_read(&ehci->dev, list, &entry, sizeof entry); |
94527ead GH |
2265 | entry = le32_to_cpu(entry); |
2266 | ||
2267 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2268 | ehci->frindex / 8, list, entry); | |
0122f472 | 2269 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2270 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2271 | ehci_advance_state(ehci, async); | |
4be23939 | 2272 | ehci_queues_rip_unused(ehci, async, 0); |
94527ead GH |
2273 | break; |
2274 | ||
94527ead GH |
2275 | default: |
2276 | /* this should only be due to a developer mistake */ | |
2277 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2278 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2279 | assert(0); |
94527ead GH |
2280 | } |
2281 | } | |
2282 | ||
2283 | static void ehci_frame_timer(void *opaque) | |
2284 | { | |
2285 | EHCIState *ehci = opaque; | |
2286 | int64_t expire_time, t_now; | |
adddecb1 | 2287 | uint64_t ns_elapsed; |
94527ead | 2288 | int frames; |
94527ead GH |
2289 | int i; |
2290 | int skipped_frames = 0; | |
2291 | ||
94527ead | 2292 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2293 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2294 | |
adddecb1 GH |
2295 | ns_elapsed = t_now - ehci->last_run_ns; |
2296 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2297 | |
2298 | for (i = 0; i < frames; i++) { | |
daf25307 | 2299 | if (ehci_enabled(ehci)) { |
fcb70eca | 2300 | ehci->frindex += 8; |
94527ead | 2301 | |
58ea88d8 | 2302 | if (ehci->frindex == 0x00002000) { |
94527ead GH |
2303 | ehci_set_interrupt(ehci, USBSTS_FLR); |
2304 | } | |
2305 | ||
58ea88d8 HG |
2306 | if (ehci->frindex == 0x00004000) { |
2307 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2308 | ehci->frindex = 0; | |
2309 | } | |
94527ead GH |
2310 | } |
2311 | ||
16a2dee6 | 2312 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2313 | skipped_frames++; |
2314 | } else { | |
d0539307 | 2315 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2316 | } |
2317 | ||
adddecb1 | 2318 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2319 | } |
2320 | ||
2321 | #if 0 | |
2322 | if (skipped_frames) { | |
2323 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2324 | } | |
2325 | #endif | |
2326 | ||
2327 | /* Async is not inside loop since it executes everything it can once | |
2328 | * called | |
2329 | */ | |
0fb3e299 | 2330 | qemu_bh_schedule(ehci->async_bh); |
94527ead | 2331 | |
daf25307 GH |
2332 | if (ehci_enabled(ehci)) { |
2333 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2334 | } | |
94527ead GH |
2335 | } |
2336 | ||
0fb3e299 GH |
2337 | static void ehci_async_bh(void *opaque) |
2338 | { | |
2339 | EHCIState *ehci = opaque; | |
2340 | ehci_advance_async_state(ehci); | |
2341 | } | |
94527ead | 2342 | |
e57964f5 AK |
2343 | static const MemoryRegionOps ehci_mem_ops = { |
2344 | .old_mmio = { | |
2345 | .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, | |
2346 | .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, | |
2347 | }, | |
2348 | .endianness = DEVICE_LITTLE_ENDIAN, | |
94527ead GH |
2349 | }; |
2350 | ||
94527ead GH |
2351 | static int usb_ehci_initfn(PCIDevice *dev); |
2352 | ||
2353 | static USBPortOps ehci_port_ops = { | |
2354 | .attach = ehci_attach, | |
2355 | .detach = ehci_detach, | |
4706ab6c | 2356 | .child_detach = ehci_child_detach, |
a0a3167a | 2357 | .wakeup = ehci_wakeup, |
94527ead GH |
2358 | .complete = ehci_async_complete_packet, |
2359 | }; | |
2360 | ||
07771f6f | 2361 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2362 | .register_companion = ehci_register_companion, |
07771f6f GH |
2363 | }; |
2364 | ||
9490fb06 GH |
2365 | static const VMStateDescription vmstate_ehci = { |
2366 | .name = "ehci", | |
2367 | .unmigratable = 1, | |
2368 | }; | |
2369 | ||
3028376e GH |
2370 | static Property ehci_properties[] = { |
2371 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2372 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2373 | DEFINE_PROP_END_OF_LIST(), | |
2374 | }; | |
2375 | ||
40021f08 AL |
2376 | static void ehci_class_init(ObjectClass *klass, void *data) |
2377 | { | |
39bffca2 | 2378 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2379 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2380 | ||
2381 | k->init = usb_ehci_initfn; | |
2382 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2383 | k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ | |
2384 | k->revision = 0x10; | |
2385 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2386 | dc->vmsd = &vmstate_ehci; |
2387 | dc->props = ehci_properties; | |
40021f08 AL |
2388 | } |
2389 | ||
39bffca2 AL |
2390 | static TypeInfo ehci_info = { |
2391 | .name = "usb-ehci", | |
2392 | .parent = TYPE_PCI_DEVICE, | |
2393 | .instance_size = sizeof(EHCIState), | |
2394 | .class_init = ehci_class_init, | |
e855761c AL |
2395 | }; |
2396 | ||
40021f08 AL |
2397 | static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2398 | { | |
39bffca2 | 2399 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2400 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2401 | ||
2402 | k->init = usb_ehci_initfn; | |
2403 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2404 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; | |
2405 | k->revision = 0x03; | |
2406 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2407 | dc->vmsd = &vmstate_ehci; |
2408 | dc->props = ehci_properties; | |
40021f08 AL |
2409 | } |
2410 | ||
39bffca2 AL |
2411 | static TypeInfo ich9_ehci_info = { |
2412 | .name = "ich9-usb-ehci1", | |
2413 | .parent = TYPE_PCI_DEVICE, | |
2414 | .instance_size = sizeof(EHCIState), | |
2415 | .class_init = ich9_ehci_class_init, | |
94527ead GH |
2416 | }; |
2417 | ||
2418 | static int usb_ehci_initfn(PCIDevice *dev) | |
2419 | { | |
2420 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2421 | uint8_t *pci_conf = s->dev.config; | |
2422 | int i; | |
2423 | ||
94527ead | 2424 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2425 | |
2426 | /* capabilities pointer */ | |
2427 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2428 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2429 | ||
817e0b6f | 2430 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
94527ead GH |
2431 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); |
2432 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2433 | ||
2434 | // pci_conf[0x50] = 0x01; // power management caps | |
2435 | ||
4001f22f | 2436 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2437 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2438 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2439 | ||
2440 | pci_conf[0x64] = 0x00; | |
2441 | pci_conf[0x65] = 0x00; | |
2442 | pci_conf[0x66] = 0x00; | |
2443 | pci_conf[0x67] = 0x00; | |
2444 | pci_conf[0x68] = 0x01; | |
2445 | pci_conf[0x69] = 0x00; | |
2446 | pci_conf[0x6a] = 0x00; | |
2447 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2448 | pci_conf[0x6c] = 0x00; | |
2449 | pci_conf[0x6d] = 0x00; | |
2450 | pci_conf[0x6e] = 0x00; | |
2451 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2452 | ||
2453 | // 2.2 host controller interface version | |
2454 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2455 | s->mmio[0x01] = 0x00; | |
2456 | s->mmio[0x02] = 0x00; | |
2457 | s->mmio[0x03] = 0x01; // HC version | |
2458 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2459 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2460 | s->mmio[0x06] = 0x00; | |
2461 | s->mmio[0x07] = 0x00; | |
2462 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2463 | s->mmio[0x09] = 0x68; // EECP | |
2464 | s->mmio[0x0a] = 0x00; | |
2465 | s->mmio[0x0b] = 0x00; | |
2466 | ||
2467 | s->irq = s->dev.irq[3]; | |
2468 | ||
07771f6f | 2469 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2470 | for(i = 0; i < NB_PORTS; i++) { |
2471 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2472 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2473 | s->ports[i].dev = 0; |
2474 | } | |
2475 | ||
2476 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
0fb3e299 | 2477 | s->async_bh = qemu_bh_new(ehci_async_bh, s); |
df5d5c5c HG |
2478 | QTAILQ_INIT(&s->aqueues); |
2479 | QTAILQ_INIT(&s->pqueues); | |
94527ead GH |
2480 | |
2481 | qemu_register_reset(ehci_reset, s); | |
2482 | ||
e57964f5 | 2483 | memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); |
e824b2cc | 2484 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); |
94527ead | 2485 | |
94527ead GH |
2486 | return 0; |
2487 | } | |
2488 | ||
83f7d43a | 2489 | static void ehci_register_types(void) |
94527ead | 2490 | { |
39bffca2 AL |
2491 | type_register_static(&ehci_info); |
2492 | type_register_static(&ich9_ehci_info); | |
94527ead | 2493 | } |
83f7d43a AF |
2494 | |
2495 | type_init(ehci_register_types) | |
94527ead GH |
2496 | |
2497 | /* | |
2498 | * vim: expandtab ts=4 | |
2499 | */ |