]>
Commit | Line | Data |
---|---|---|
0d92ed30 PB |
1 | /* |
2 | * QEMU USB OHCI Emulation | |
3 | * Copyright (c) 2004 Gianni Tedesco | |
4 | * Copyright (c) 2006 CodeSourcery | |
e24ad6f1 | 5 | * Copyright (c) 2006 Openedhand Ltd. |
0d92ed30 PB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
0d92ed30 PB |
19 | * |
20 | * TODO: | |
21 | * o Isochronous transfers | |
22 | * o Allocate bandwidth in frames properly | |
23 | * o Disable timers when nothing needs to be done, or remove timer usage | |
24 | * all together. | |
25 | * o Handle unrecoverable errors properly | |
26 | * o BIOS work to boot from USB storage | |
27 | */ | |
28 | ||
87ecb68b PB |
29 | #include "hw.h" |
30 | #include "qemu-timer.h" | |
31 | #include "usb.h" | |
32 | #include "pci.h" | |
18e08a55 | 33 | #include "usb-ohci.h" |
61d3cf93 PB |
34 | #include "sysbus.h" |
35 | #include "qdev-addr.h" | |
0d92ed30 PB |
36 | |
37 | //#define DEBUG_OHCI | |
38 | /* Dump packet contents. */ | |
39 | //#define DEBUG_PACKET | |
7bfe5777 | 40 | //#define DEBUG_ISOCH |
0d92ed30 PB |
41 | /* This causes frames to occur 1000x slower */ |
42 | //#define OHCI_TIME_WARP 1 | |
43 | ||
44 | #ifdef DEBUG_OHCI | |
d0f2c4c6 | 45 | #define DPRINTF printf |
0d92ed30 | 46 | #else |
d0f2c4c6 | 47 | #define DPRINTF(...) |
0d92ed30 PB |
48 | #endif |
49 | ||
50 | /* Number of Downstream Ports on the root hub. */ | |
51 | ||
52 | #define OHCI_MAX_PORTS 15 | |
53 | ||
54 | static int64_t usb_frame_time; | |
55 | static int64_t usb_bit_time; | |
56 | ||
57 | typedef struct OHCIPort { | |
58 | USBPort port; | |
59 | uint32_t ctrl; | |
60 | } OHCIPort; | |
61 | ||
62 | typedef struct { | |
b2317837 | 63 | USBBus bus; |
d537cf6c | 64 | qemu_irq irq; |
0d92ed30 PB |
65 | int mem; |
66 | int num_ports; | |
e24ad6f1 | 67 | const char *name; |
0d92ed30 PB |
68 | |
69 | QEMUTimer *eof_timer; | |
70 | int64_t sof_time; | |
71 | ||
72 | /* OHCI state */ | |
73 | /* Control partition */ | |
74 | uint32_t ctl, status; | |
75 | uint32_t intr_status; | |
76 | uint32_t intr; | |
77 | ||
78 | /* memory pointer partition */ | |
79 | uint32_t hcca; | |
80 | uint32_t ctrl_head, ctrl_cur; | |
81 | uint32_t bulk_head, bulk_cur; | |
82 | uint32_t per_cur; | |
83 | uint32_t done; | |
84 | int done_count; | |
85 | ||
86 | /* Frame counter partition */ | |
87 | uint32_t fsmps:15; | |
88 | uint32_t fit:1; | |
89 | uint32_t fi:14; | |
90 | uint32_t frt:1; | |
91 | uint16_t frame_number; | |
92 | uint16_t padding; | |
93 | uint32_t pstart; | |
94 | uint32_t lst; | |
95 | ||
96 | /* Root Hub partition */ | |
97 | uint32_t rhdesc_a, rhdesc_b; | |
98 | uint32_t rhstatus; | |
99 | OHCIPort rhport[OHCI_MAX_PORTS]; | |
4d611c9a | 100 | |
e24ad6f1 PB |
101 | /* PXA27x Non-OHCI events */ |
102 | uint32_t hstatus; | |
103 | uint32_t hmask; | |
104 | uint32_t hreset; | |
105 | uint32_t htest; | |
106 | ||
ac611340 | 107 | /* SM501 local memory offset */ |
c227f099 | 108 | target_phys_addr_t localmem_base; |
ac611340 | 109 | |
4d611c9a PB |
110 | /* Active packets. */ |
111 | uint32_t old_ctl; | |
112 | USBPacket usb_packet; | |
113 | uint8_t usb_buf[8192]; | |
114 | uint32_t async_td; | |
115 | int async_complete; | |
116 | ||
0d92ed30 PB |
117 | } OHCIState; |
118 | ||
119 | /* Host Controller Communications Area */ | |
120 | struct ohci_hcca { | |
121 | uint32_t intr[32]; | |
122 | uint16_t frame, pad; | |
123 | uint32_t done; | |
124 | }; | |
125 | ||
73221b12 TS |
126 | static void ohci_bus_stop(OHCIState *ohci); |
127 | ||
0d92ed30 PB |
128 | /* Bitfields for the first word of an Endpoint Desciptor. */ |
129 | #define OHCI_ED_FA_SHIFT 0 | |
130 | #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) | |
131 | #define OHCI_ED_EN_SHIFT 7 | |
132 | #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) | |
133 | #define OHCI_ED_D_SHIFT 11 | |
134 | #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) | |
135 | #define OHCI_ED_S (1<<13) | |
136 | #define OHCI_ED_K (1<<14) | |
137 | #define OHCI_ED_F (1<<15) | |
7bfe5777 AZ |
138 | #define OHCI_ED_MPS_SHIFT 16 |
139 | #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) | |
0d92ed30 PB |
140 | |
141 | /* Flags in the head field of an Endpoint Desciptor. */ | |
142 | #define OHCI_ED_H 1 | |
143 | #define OHCI_ED_C 2 | |
144 | ||
145 | /* Bitfields for the first word of a Transfer Desciptor. */ | |
146 | #define OHCI_TD_R (1<<18) | |
147 | #define OHCI_TD_DP_SHIFT 19 | |
148 | #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) | |
149 | #define OHCI_TD_DI_SHIFT 21 | |
150 | #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) | |
151 | #define OHCI_TD_T0 (1<<24) | |
152 | #define OHCI_TD_T1 (1<<24) | |
153 | #define OHCI_TD_EC_SHIFT 26 | |
154 | #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) | |
155 | #define OHCI_TD_CC_SHIFT 28 | |
156 | #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) | |
157 | ||
7bfe5777 AZ |
158 | /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ |
159 | /* CC & DI - same as in the General Transfer Desciptor */ | |
160 | #define OHCI_TD_SF_SHIFT 0 | |
161 | #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) | |
162 | #define OHCI_TD_FC_SHIFT 24 | |
163 | #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) | |
164 | ||
165 | /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ | |
166 | #define OHCI_TD_PSW_CC_SHIFT 12 | |
167 | #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) | |
168 | #define OHCI_TD_PSW_SIZE_SHIFT 0 | |
169 | #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) | |
170 | ||
171 | #define OHCI_PAGE_MASK 0xfffff000 | |
172 | #define OHCI_OFFSET_MASK 0xfff | |
173 | ||
0d92ed30 PB |
174 | #define OHCI_DPTR_MASK 0xfffffff0 |
175 | ||
176 | #define OHCI_BM(val, field) \ | |
177 | (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) | |
178 | ||
179 | #define OHCI_SET_BM(val, field, newval) do { \ | |
180 | val &= ~OHCI_##field##_MASK; \ | |
181 | val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ | |
182 | } while(0) | |
183 | ||
184 | /* endpoint descriptor */ | |
185 | struct ohci_ed { | |
186 | uint32_t flags; | |
187 | uint32_t tail; | |
188 | uint32_t head; | |
189 | uint32_t next; | |
190 | }; | |
191 | ||
192 | /* General transfer descriptor */ | |
193 | struct ohci_td { | |
194 | uint32_t flags; | |
195 | uint32_t cbp; | |
196 | uint32_t next; | |
197 | uint32_t be; | |
198 | }; | |
199 | ||
7bfe5777 AZ |
200 | /* Isochronous transfer descriptor */ |
201 | struct ohci_iso_td { | |
202 | uint32_t flags; | |
203 | uint32_t bp; | |
204 | uint32_t next; | |
205 | uint32_t be; | |
206 | uint16_t offset[8]; | |
207 | }; | |
208 | ||
0d92ed30 PB |
209 | #define USB_HZ 12000000 |
210 | ||
211 | /* OHCI Local stuff */ | |
212 | #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) | |
213 | #define OHCI_CTL_PLE (1<<2) | |
214 | #define OHCI_CTL_IE (1<<3) | |
215 | #define OHCI_CTL_CLE (1<<4) | |
216 | #define OHCI_CTL_BLE (1<<5) | |
217 | #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) | |
218 | #define OHCI_USB_RESET 0x00 | |
219 | #define OHCI_USB_RESUME 0x40 | |
220 | #define OHCI_USB_OPERATIONAL 0x80 | |
221 | #define OHCI_USB_SUSPEND 0xc0 | |
222 | #define OHCI_CTL_IR (1<<8) | |
223 | #define OHCI_CTL_RWC (1<<9) | |
224 | #define OHCI_CTL_RWE (1<<10) | |
225 | ||
226 | #define OHCI_STATUS_HCR (1<<0) | |
227 | #define OHCI_STATUS_CLF (1<<1) | |
228 | #define OHCI_STATUS_BLF (1<<2) | |
229 | #define OHCI_STATUS_OCR (1<<3) | |
230 | #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) | |
231 | ||
232 | #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ | |
233 | #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ | |
234 | #define OHCI_INTR_SF (1<<2) /* Start of frame */ | |
235 | #define OHCI_INTR_RD (1<<3) /* Resume detect */ | |
236 | #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ | |
237 | #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ | |
238 | #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ | |
239 | #define OHCI_INTR_OC (1<<30) /* Ownership change */ | |
240 | #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ | |
241 | ||
242 | #define OHCI_HCCA_SIZE 0x100 | |
243 | #define OHCI_HCCA_MASK 0xffffff00 | |
244 | ||
245 | #define OHCI_EDPTR_MASK 0xfffffff0 | |
246 | ||
247 | #define OHCI_FMI_FI 0x00003fff | |
248 | #define OHCI_FMI_FSMPS 0xffff0000 | |
249 | #define OHCI_FMI_FIT 0x80000000 | |
250 | ||
251 | #define OHCI_FR_RT (1<<31) | |
252 | ||
253 | #define OHCI_LS_THRESH 0x628 | |
254 | ||
255 | #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ | |
256 | #define OHCI_RHA_PSM (1<<8) | |
257 | #define OHCI_RHA_NPS (1<<9) | |
258 | #define OHCI_RHA_DT (1<<10) | |
259 | #define OHCI_RHA_OCPM (1<<11) | |
260 | #define OHCI_RHA_NOCP (1<<12) | |
261 | #define OHCI_RHA_POTPGT_MASK 0xff000000 | |
262 | ||
263 | #define OHCI_RHS_LPS (1<<0) | |
264 | #define OHCI_RHS_OCI (1<<1) | |
265 | #define OHCI_RHS_DRWE (1<<15) | |
266 | #define OHCI_RHS_LPSC (1<<16) | |
267 | #define OHCI_RHS_OCIC (1<<17) | |
268 | #define OHCI_RHS_CRWE (1<<31) | |
269 | ||
270 | #define OHCI_PORT_CCS (1<<0) | |
271 | #define OHCI_PORT_PES (1<<1) | |
272 | #define OHCI_PORT_PSS (1<<2) | |
273 | #define OHCI_PORT_POCI (1<<3) | |
274 | #define OHCI_PORT_PRS (1<<4) | |
275 | #define OHCI_PORT_PPS (1<<8) | |
276 | #define OHCI_PORT_LSDA (1<<9) | |
277 | #define OHCI_PORT_CSC (1<<16) | |
278 | #define OHCI_PORT_PESC (1<<17) | |
279 | #define OHCI_PORT_PSSC (1<<18) | |
280 | #define OHCI_PORT_OCIC (1<<19) | |
281 | #define OHCI_PORT_PRSC (1<<20) | |
282 | #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ | |
283 | |OHCI_PORT_OCIC|OHCI_PORT_PRSC) | |
284 | ||
285 | #define OHCI_TD_DIR_SETUP 0x0 | |
286 | #define OHCI_TD_DIR_OUT 0x1 | |
287 | #define OHCI_TD_DIR_IN 0x2 | |
288 | #define OHCI_TD_DIR_RESERVED 0x3 | |
289 | ||
290 | #define OHCI_CC_NOERROR 0x0 | |
291 | #define OHCI_CC_CRC 0x1 | |
292 | #define OHCI_CC_BITSTUFFING 0x2 | |
293 | #define OHCI_CC_DATATOGGLEMISMATCH 0x3 | |
294 | #define OHCI_CC_STALL 0x4 | |
295 | #define OHCI_CC_DEVICENOTRESPONDING 0x5 | |
296 | #define OHCI_CC_PIDCHECKFAILURE 0x6 | |
297 | #define OHCI_CC_UNDEXPETEDPID 0x7 | |
298 | #define OHCI_CC_DATAOVERRUN 0x8 | |
299 | #define OHCI_CC_DATAUNDERRUN 0x9 | |
300 | #define OHCI_CC_BUFFEROVERRUN 0xc | |
301 | #define OHCI_CC_BUFFERUNDERRUN 0xd | |
302 | ||
e24ad6f1 PB |
303 | #define OHCI_HRESET_FSBIR (1 << 0) |
304 | ||
61064870 PB |
305 | /* Update IRQ levels */ |
306 | static inline void ohci_intr_update(OHCIState *ohci) | |
307 | { | |
308 | int level = 0; | |
309 | ||
310 | if ((ohci->intr & OHCI_INTR_MIE) && | |
311 | (ohci->intr_status & ohci->intr)) | |
312 | level = 1; | |
313 | ||
d537cf6c | 314 | qemu_set_irq(ohci->irq, level); |
61064870 PB |
315 | } |
316 | ||
317 | /* Set an interrupt */ | |
318 | static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) | |
319 | { | |
320 | ohci->intr_status |= intr; | |
321 | ohci_intr_update(ohci); | |
322 | } | |
323 | ||
324 | /* Attach or detach a device on a root hub port. */ | |
618c169b | 325 | static void ohci_attach(USBPort *port1) |
0d92ed30 PB |
326 | { |
327 | OHCIState *s = port1->opaque; | |
328 | OHCIPort *port = &s->rhport[port1->index]; | |
329 | ||
618c169b GH |
330 | /* set connect status */ |
331 | port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; | |
332 | ||
333 | /* update speed */ | |
334 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
335 | port->ctrl |= OHCI_PORT_LSDA; | |
0d92ed30 | 336 | } else { |
618c169b GH |
337 | port->ctrl &= ~OHCI_PORT_LSDA; |
338 | } | |
339 | ||
340 | /* notify of remote-wakeup */ | |
341 | if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { | |
342 | ohci_set_interrupt(s, OHCI_INTR_RD); | |
343 | } | |
344 | ||
345 | DPRINTF("usb-ohci: Attached port %d\n", port1->index); | |
346 | } | |
347 | ||
348 | static void ohci_detach(USBPort *port1) | |
349 | { | |
350 | OHCIState *s = port1->opaque; | |
351 | OHCIPort *port = &s->rhport[port1->index]; | |
352 | uint32_t old_state = port->ctrl; | |
353 | ||
354 | /* set connect status */ | |
355 | if (port->ctrl & OHCI_PORT_CCS) { | |
356 | port->ctrl &= ~OHCI_PORT_CCS; | |
357 | port->ctrl |= OHCI_PORT_CSC; | |
358 | } | |
359 | /* disable port */ | |
360 | if (port->ctrl & OHCI_PORT_PES) { | |
361 | port->ctrl &= ~OHCI_PORT_PES; | |
362 | port->ctrl |= OHCI_PORT_PESC; | |
0d92ed30 | 363 | } |
618c169b | 364 | DPRINTF("usb-ohci: Detached port %d\n", port1->index); |
61064870 PB |
365 | |
366 | if (old_state != port->ctrl) | |
367 | ohci_set_interrupt(s, OHCI_INTR_RHSC); | |
0d92ed30 PB |
368 | } |
369 | ||
370 | /* Reset the controller */ | |
73221b12 | 371 | static void ohci_reset(void *opaque) |
0d92ed30 | 372 | { |
73221b12 | 373 | OHCIState *ohci = opaque; |
0d92ed30 PB |
374 | OHCIPort *port; |
375 | int i; | |
376 | ||
73221b12 | 377 | ohci_bus_stop(ohci); |
0d92ed30 | 378 | ohci->ctl = 0; |
4d611c9a | 379 | ohci->old_ctl = 0; |
0d92ed30 PB |
380 | ohci->status = 0; |
381 | ohci->intr_status = 0; | |
382 | ohci->intr = OHCI_INTR_MIE; | |
383 | ||
384 | ohci->hcca = 0; | |
385 | ohci->ctrl_head = ohci->ctrl_cur = 0; | |
386 | ohci->bulk_head = ohci->bulk_cur = 0; | |
387 | ohci->per_cur = 0; | |
388 | ohci->done = 0; | |
389 | ohci->done_count = 7; | |
390 | ||
391 | /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? | |
392 | * I took the value linux sets ... | |
393 | */ | |
394 | ohci->fsmps = 0x2778; | |
395 | ohci->fi = 0x2edf; | |
396 | ohci->fit = 0; | |
397 | ohci->frt = 0; | |
398 | ohci->frame_number = 0; | |
399 | ohci->pstart = 0; | |
400 | ohci->lst = OHCI_LS_THRESH; | |
401 | ||
402 | ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; | |
403 | ohci->rhdesc_b = 0x0; /* Impl. specific */ | |
404 | ohci->rhstatus = 0; | |
405 | ||
406 | for (i = 0; i < ohci->num_ports; i++) | |
407 | { | |
408 | port = &ohci->rhport[i]; | |
409 | port->ctrl = 0; | |
618c169b GH |
410 | if (port->port.dev) { |
411 | usb_attach(&port->port, port->port.dev); | |
412 | } | |
0d92ed30 | 413 | } |
4d611c9a PB |
414 | if (ohci->async_td) { |
415 | usb_cancel_packet(&ohci->usb_packet); | |
416 | ohci->async_td = 0; | |
417 | } | |
d0f2c4c6 | 418 | DPRINTF("usb-ohci: Reset %s\n", ohci->name); |
0d92ed30 PB |
419 | } |
420 | ||
0d92ed30 | 421 | /* Get an array of dwords from main memory */ |
ac611340 AJ |
422 | static inline int get_dwords(OHCIState *ohci, |
423 | uint32_t addr, uint32_t *buf, int num) | |
0d92ed30 PB |
424 | { |
425 | int i; | |
426 | ||
ac611340 AJ |
427 | addr += ohci->localmem_base; |
428 | ||
0d92ed30 | 429 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
54f7b4a3 | 430 | cpu_physical_memory_read(addr, buf, sizeof(*buf)); |
0d92ed30 PB |
431 | *buf = le32_to_cpu(*buf); |
432 | } | |
433 | ||
434 | return 1; | |
435 | } | |
436 | ||
437 | /* Put an array of dwords in to main memory */ | |
ac611340 AJ |
438 | static inline int put_dwords(OHCIState *ohci, |
439 | uint32_t addr, uint32_t *buf, int num) | |
0d92ed30 PB |
440 | { |
441 | int i; | |
442 | ||
ac611340 AJ |
443 | addr += ohci->localmem_base; |
444 | ||
0d92ed30 PB |
445 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
446 | uint32_t tmp = cpu_to_le32(*buf); | |
54f7b4a3 | 447 | cpu_physical_memory_write(addr, &tmp, sizeof(tmp)); |
0d92ed30 PB |
448 | } |
449 | ||
450 | return 1; | |
451 | } | |
452 | ||
7bfe5777 | 453 | /* Get an array of words from main memory */ |
ac611340 AJ |
454 | static inline int get_words(OHCIState *ohci, |
455 | uint32_t addr, uint16_t *buf, int num) | |
7bfe5777 AZ |
456 | { |
457 | int i; | |
458 | ||
ac611340 AJ |
459 | addr += ohci->localmem_base; |
460 | ||
7bfe5777 | 461 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
54f7b4a3 | 462 | cpu_physical_memory_read(addr, buf, sizeof(*buf)); |
7bfe5777 AZ |
463 | *buf = le16_to_cpu(*buf); |
464 | } | |
465 | ||
466 | return 1; | |
467 | } | |
468 | ||
469 | /* Put an array of words in to main memory */ | |
ac611340 AJ |
470 | static inline int put_words(OHCIState *ohci, |
471 | uint32_t addr, uint16_t *buf, int num) | |
7bfe5777 AZ |
472 | { |
473 | int i; | |
474 | ||
ac611340 AJ |
475 | addr += ohci->localmem_base; |
476 | ||
7bfe5777 AZ |
477 | for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
478 | uint16_t tmp = cpu_to_le16(*buf); | |
54f7b4a3 | 479 | cpu_physical_memory_write(addr, &tmp, sizeof(tmp)); |
7bfe5777 AZ |
480 | } |
481 | ||
482 | return 1; | |
483 | } | |
484 | ||
ac611340 AJ |
485 | static inline int ohci_read_ed(OHCIState *ohci, |
486 | uint32_t addr, struct ohci_ed *ed) | |
0d92ed30 | 487 | { |
ac611340 | 488 | return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
0d92ed30 PB |
489 | } |
490 | ||
ac611340 AJ |
491 | static inline int ohci_read_td(OHCIState *ohci, |
492 | uint32_t addr, struct ohci_td *td) | |
0d92ed30 | 493 | { |
ac611340 | 494 | return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
0d92ed30 PB |
495 | } |
496 | ||
ac611340 AJ |
497 | static inline int ohci_read_iso_td(OHCIState *ohci, |
498 | uint32_t addr, struct ohci_iso_td *td) | |
7bfe5777 | 499 | { |
ac611340 AJ |
500 | return (get_dwords(ohci, addr, (uint32_t *)td, 4) && |
501 | get_words(ohci, addr + 16, td->offset, 8)); | |
7bfe5777 AZ |
502 | } |
503 | ||
ac611340 AJ |
504 | static inline int ohci_read_hcca(OHCIState *ohci, |
505 | uint32_t addr, struct ohci_hcca *hcca) | |
0d92ed30 | 506 | { |
54f7b4a3 | 507 | cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca)); |
ac611340 | 508 | return 1; |
0d92ed30 PB |
509 | } |
510 | ||
ac611340 AJ |
511 | static inline int ohci_put_ed(OHCIState *ohci, |
512 | uint32_t addr, struct ohci_ed *ed) | |
0d92ed30 | 513 | { |
ac611340 | 514 | return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
0d92ed30 PB |
515 | } |
516 | ||
ac611340 AJ |
517 | static inline int ohci_put_td(OHCIState *ohci, |
518 | uint32_t addr, struct ohci_td *td) | |
7bfe5777 | 519 | { |
ac611340 AJ |
520 | return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
521 | } | |
522 | ||
523 | static inline int ohci_put_iso_td(OHCIState *ohci, | |
524 | uint32_t addr, struct ohci_iso_td *td) | |
525 | { | |
526 | return (put_dwords(ohci, addr, (uint32_t *)td, 4) && | |
527 | put_words(ohci, addr + 16, td->offset, 8)); | |
528 | } | |
529 | ||
530 | static inline int ohci_put_hcca(OHCIState *ohci, | |
531 | uint32_t addr, struct ohci_hcca *hcca) | |
532 | { | |
54f7b4a3 | 533 | cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca)); |
ac611340 | 534 | return 1; |
7bfe5777 AZ |
535 | } |
536 | ||
0d92ed30 | 537 | /* Read/Write the contents of a TD from/to main memory. */ |
ac611340 AJ |
538 | static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td, |
539 | uint8_t *buf, int len, int write) | |
0d92ed30 PB |
540 | { |
541 | uint32_t ptr; | |
542 | uint32_t n; | |
543 | ||
544 | ptr = td->cbp; | |
545 | n = 0x1000 - (ptr & 0xfff); | |
546 | if (n > len) | |
547 | n = len; | |
ac611340 | 548 | cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write); |
0d92ed30 PB |
549 | if (n == len) |
550 | return; | |
551 | ptr = td->be & ~0xfffu; | |
e6f3e5e0 | 552 | buf += n; |
ac611340 | 553 | cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write); |
0d92ed30 PB |
554 | } |
555 | ||
7bfe5777 | 556 | /* Read/Write the contents of an ISO TD from/to main memory. */ |
ac611340 AJ |
557 | static void ohci_copy_iso_td(OHCIState *ohci, |
558 | uint32_t start_addr, uint32_t end_addr, | |
7bfe5777 AZ |
559 | uint8_t *buf, int len, int write) |
560 | { | |
561 | uint32_t ptr; | |
562 | uint32_t n; | |
4d611c9a | 563 | |
7bfe5777 AZ |
564 | ptr = start_addr; |
565 | n = 0x1000 - (ptr & 0xfff); | |
566 | if (n > len) | |
567 | n = len; | |
ac611340 | 568 | cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write); |
7bfe5777 AZ |
569 | if (n == len) |
570 | return; | |
571 | ptr = end_addr & ~0xfffu; | |
572 | buf += n; | |
ac611340 | 573 | cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write); |
7bfe5777 AZ |
574 | } |
575 | ||
576 | static void ohci_process_lists(OHCIState *ohci, int completion); | |
577 | ||
578 | static void ohci_async_complete_packet(USBPacket *packet, void *opaque) | |
4d611c9a PB |
579 | { |
580 | OHCIState *ohci = opaque; | |
581 | #ifdef DEBUG_PACKET | |
d0f2c4c6 | 582 | DPRINTF("Async packet complete\n"); |
4d611c9a PB |
583 | #endif |
584 | ohci->async_complete = 1; | |
7bfe5777 AZ |
585 | ohci_process_lists(ohci, 1); |
586 | } | |
587 | ||
588 | #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) | |
589 | ||
590 | static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, | |
591 | int completion) | |
592 | { | |
593 | int dir; | |
594 | size_t len = 0; | |
d4c4e6fd | 595 | #ifdef DEBUG_ISOCH |
7ccfb2eb | 596 | const char *str = NULL; |
d4c4e6fd | 597 | #endif |
7bfe5777 AZ |
598 | int pid; |
599 | int ret; | |
600 | int i; | |
601 | USBDevice *dev; | |
602 | struct ohci_iso_td iso_td; | |
603 | uint32_t addr; | |
604 | uint16_t starting_frame; | |
605 | int16_t relative_frame_number; | |
606 | int frame_count; | |
607 | uint32_t start_offset, next_offset, end_offset = 0; | |
608 | uint32_t start_addr, end_addr; | |
609 | ||
610 | addr = ed->head & OHCI_DPTR_MASK; | |
611 | ||
ac611340 | 612 | if (!ohci_read_iso_td(ohci, addr, &iso_td)) { |
7bfe5777 AZ |
613 | printf("usb-ohci: ISO_TD read error at %x\n", addr); |
614 | return 0; | |
615 | } | |
616 | ||
617 | starting_frame = OHCI_BM(iso_td.flags, TD_SF); | |
618 | frame_count = OHCI_BM(iso_td.flags, TD_FC); | |
619 | relative_frame_number = USUB(ohci->frame_number, starting_frame); | |
620 | ||
621 | #ifdef DEBUG_ISOCH | |
622 | printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n" | |
623 | "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n" | |
624 | "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n" | |
625 | "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n" | |
626 | "frame_number 0x%.8x starting_frame 0x%.8x\n" | |
627 | "frame_count 0x%.8x relative %d\n" | |
628 | "di 0x%.8x cc 0x%.8x\n", | |
629 | ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, | |
630 | iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, | |
631 | iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], | |
632 | iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], | |
633 | ohci->frame_number, starting_frame, | |
634 | frame_count, relative_frame_number, | |
635 | OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); | |
636 | #endif | |
637 | ||
638 | if (relative_frame_number < 0) { | |
d0f2c4c6 | 639 | DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number); |
7bfe5777 AZ |
640 | return 1; |
641 | } else if (relative_frame_number > frame_count) { | |
642 | /* ISO TD expired - retire the TD to the Done Queue and continue with | |
643 | the next ISO TD of the same ED */ | |
d0f2c4c6 | 644 | DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, |
7bfe5777 AZ |
645 | frame_count); |
646 | OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); | |
647 | ed->head &= ~OHCI_DPTR_MASK; | |
648 | ed->head |= (iso_td.next & OHCI_DPTR_MASK); | |
649 | iso_td.next = ohci->done; | |
650 | ohci->done = addr; | |
651 | i = OHCI_BM(iso_td.flags, TD_DI); | |
652 | if (i < ohci->done_count) | |
653 | ohci->done_count = i; | |
ac611340 | 654 | ohci_put_iso_td(ohci, addr, &iso_td); |
7bfe5777 AZ |
655 | return 0; |
656 | } | |
657 | ||
658 | dir = OHCI_BM(ed->flags, ED_D); | |
659 | switch (dir) { | |
660 | case OHCI_TD_DIR_IN: | |
d4c4e6fd | 661 | #ifdef DEBUG_ISOCH |
7bfe5777 | 662 | str = "in"; |
d4c4e6fd | 663 | #endif |
7bfe5777 AZ |
664 | pid = USB_TOKEN_IN; |
665 | break; | |
666 | case OHCI_TD_DIR_OUT: | |
d4c4e6fd | 667 | #ifdef DEBUG_ISOCH |
7bfe5777 | 668 | str = "out"; |
d4c4e6fd | 669 | #endif |
7bfe5777 AZ |
670 | pid = USB_TOKEN_OUT; |
671 | break; | |
672 | case OHCI_TD_DIR_SETUP: | |
d4c4e6fd | 673 | #ifdef DEBUG_ISOCH |
7bfe5777 | 674 | str = "setup"; |
d4c4e6fd | 675 | #endif |
7bfe5777 AZ |
676 | pid = USB_TOKEN_SETUP; |
677 | break; | |
678 | default: | |
679 | printf("usb-ohci: Bad direction %d\n", dir); | |
680 | return 1; | |
681 | } | |
682 | ||
683 | if (!iso_td.bp || !iso_td.be) { | |
684 | printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be); | |
685 | return 1; | |
686 | } | |
687 | ||
688 | start_offset = iso_td.offset[relative_frame_number]; | |
689 | next_offset = iso_td.offset[relative_frame_number + 1]; | |
690 | ||
691 | if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || | |
692 | ((relative_frame_number < frame_count) && | |
693 | !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { | |
694 | printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n", | |
695 | start_offset, next_offset); | |
696 | return 1; | |
697 | } | |
698 | ||
699 | if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { | |
700 | printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n", | |
701 | start_offset, next_offset); | |
702 | return 1; | |
703 | } | |
704 | ||
705 | if ((start_offset & 0x1000) == 0) { | |
706 | start_addr = (iso_td.bp & OHCI_PAGE_MASK) | | |
707 | (start_offset & OHCI_OFFSET_MASK); | |
708 | } else { | |
709 | start_addr = (iso_td.be & OHCI_PAGE_MASK) | | |
710 | (start_offset & OHCI_OFFSET_MASK); | |
711 | } | |
712 | ||
713 | if (relative_frame_number < frame_count) { | |
714 | end_offset = next_offset - 1; | |
715 | if ((end_offset & 0x1000) == 0) { | |
716 | end_addr = (iso_td.bp & OHCI_PAGE_MASK) | | |
717 | (end_offset & OHCI_OFFSET_MASK); | |
718 | } else { | |
719 | end_addr = (iso_td.be & OHCI_PAGE_MASK) | | |
720 | (end_offset & OHCI_OFFSET_MASK); | |
721 | } | |
722 | } else { | |
723 | /* Last packet in the ISO TD */ | |
724 | end_addr = iso_td.be; | |
725 | } | |
726 | ||
727 | if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { | |
728 | len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 | |
729 | - (start_addr & OHCI_OFFSET_MASK); | |
730 | } else { | |
731 | len = end_addr - start_addr + 1; | |
732 | } | |
733 | ||
734 | if (len && dir != OHCI_TD_DIR_IN) { | |
ac611340 | 735 | ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0); |
7bfe5777 AZ |
736 | } |
737 | ||
738 | if (completion) { | |
739 | ret = ohci->usb_packet.len; | |
740 | } else { | |
741 | ret = USB_RET_NODEV; | |
742 | for (i = 0; i < ohci->num_ports; i++) { | |
743 | dev = ohci->rhport[i].port.dev; | |
744 | if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) | |
745 | continue; | |
746 | ohci->usb_packet.pid = pid; | |
747 | ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); | |
748 | ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); | |
749 | ohci->usb_packet.data = ohci->usb_buf; | |
750 | ohci->usb_packet.len = len; | |
751 | ohci->usb_packet.complete_cb = ohci_async_complete_packet; | |
752 | ohci->usb_packet.complete_opaque = ohci; | |
806b6024 | 753 | ret = dev->info->handle_packet(dev, &ohci->usb_packet); |
7bfe5777 AZ |
754 | if (ret != USB_RET_NODEV) |
755 | break; | |
756 | } | |
757 | ||
758 | if (ret == USB_RET_ASYNC) { | |
759 | return 1; | |
760 | } | |
761 | } | |
762 | ||
763 | #ifdef DEBUG_ISOCH | |
764 | printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n", | |
765 | start_offset, end_offset, start_addr, end_addr, str, len, ret); | |
766 | #endif | |
767 | ||
768 | /* Writeback */ | |
769 | if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { | |
770 | /* IN transfer succeeded */ | |
ac611340 | 771 | ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1); |
7bfe5777 AZ |
772 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
773 | OHCI_CC_NOERROR); | |
774 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); | |
775 | } else if (dir == OHCI_TD_DIR_OUT && ret == len) { | |
776 | /* OUT transfer succeeded */ | |
777 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
778 | OHCI_CC_NOERROR); | |
779 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); | |
780 | } else { | |
87283515 | 781 | if (ret > (ssize_t) len) { |
7bfe5777 AZ |
782 | printf("usb-ohci: DataOverrun %d > %zu\n", ret, len); |
783 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
784 | OHCI_CC_DATAOVERRUN); | |
785 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
786 | len); | |
787 | } else if (ret >= 0) { | |
788 | printf("usb-ohci: DataUnderrun %d\n", ret); | |
789 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
790 | OHCI_CC_DATAUNDERRUN); | |
791 | } else { | |
792 | switch (ret) { | |
793 | case USB_RET_NODEV: | |
794 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
795 | OHCI_CC_DEVICENOTRESPONDING); | |
796 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
797 | 0); | |
798 | break; | |
799 | case USB_RET_NAK: | |
800 | case USB_RET_STALL: | |
801 | printf("usb-ohci: got NAK/STALL %d\n", ret); | |
802 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
803 | OHCI_CC_STALL); | |
804 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, | |
805 | 0); | |
806 | break; | |
807 | default: | |
808 | printf("usb-ohci: Bad device response %d\n", ret); | |
809 | OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, | |
810 | OHCI_CC_UNDEXPETEDPID); | |
811 | break; | |
812 | } | |
813 | } | |
814 | } | |
815 | ||
816 | if (relative_frame_number == frame_count) { | |
817 | /* Last data packet of ISO TD - retire the TD to the Done Queue */ | |
818 | OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); | |
819 | ed->head &= ~OHCI_DPTR_MASK; | |
820 | ed->head |= (iso_td.next & OHCI_DPTR_MASK); | |
821 | iso_td.next = ohci->done; | |
822 | ohci->done = addr; | |
823 | i = OHCI_BM(iso_td.flags, TD_DI); | |
824 | if (i < ohci->done_count) | |
825 | ohci->done_count = i; | |
826 | } | |
ac611340 | 827 | ohci_put_iso_td(ohci, addr, &iso_td); |
7bfe5777 | 828 | return 1; |
4d611c9a PB |
829 | } |
830 | ||
0d92ed30 PB |
831 | /* Service a transport descriptor. |
832 | Returns nonzero to terminate processing of this endpoint. */ | |
833 | ||
834 | static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) | |
835 | { | |
836 | int dir; | |
837 | size_t len = 0; | |
d4c4e6fd | 838 | #ifdef DEBUG_PACKET |
7ccfb2eb | 839 | const char *str = NULL; |
d4c4e6fd | 840 | #endif |
0d92ed30 PB |
841 | int pid; |
842 | int ret; | |
843 | int i; | |
844 | USBDevice *dev; | |
845 | struct ohci_td td; | |
846 | uint32_t addr; | |
847 | int flag_r; | |
4d611c9a | 848 | int completion; |
0d92ed30 PB |
849 | |
850 | addr = ed->head & OHCI_DPTR_MASK; | |
4d611c9a PB |
851 | /* See if this TD has already been submitted to the device. */ |
852 | completion = (addr == ohci->async_td); | |
853 | if (completion && !ohci->async_complete) { | |
854 | #ifdef DEBUG_PACKET | |
d0f2c4c6 | 855 | DPRINTF("Skipping async TD\n"); |
4d611c9a PB |
856 | #endif |
857 | return 1; | |
858 | } | |
ac611340 | 859 | if (!ohci_read_td(ohci, addr, &td)) { |
0d92ed30 PB |
860 | fprintf(stderr, "usb-ohci: TD read error at %x\n", addr); |
861 | return 0; | |
862 | } | |
863 | ||
864 | dir = OHCI_BM(ed->flags, ED_D); | |
865 | switch (dir) { | |
866 | case OHCI_TD_DIR_OUT: | |
867 | case OHCI_TD_DIR_IN: | |
868 | /* Same value. */ | |
869 | break; | |
870 | default: | |
871 | dir = OHCI_BM(td.flags, TD_DP); | |
872 | break; | |
873 | } | |
874 | ||
875 | switch (dir) { | |
876 | case OHCI_TD_DIR_IN: | |
d4c4e6fd | 877 | #ifdef DEBUG_PACKET |
0d92ed30 | 878 | str = "in"; |
d4c4e6fd | 879 | #endif |
0d92ed30 PB |
880 | pid = USB_TOKEN_IN; |
881 | break; | |
882 | case OHCI_TD_DIR_OUT: | |
d4c4e6fd | 883 | #ifdef DEBUG_PACKET |
0d92ed30 | 884 | str = "out"; |
d4c4e6fd | 885 | #endif |
0d92ed30 PB |
886 | pid = USB_TOKEN_OUT; |
887 | break; | |
888 | case OHCI_TD_DIR_SETUP: | |
d4c4e6fd | 889 | #ifdef DEBUG_PACKET |
0d92ed30 | 890 | str = "setup"; |
d4c4e6fd | 891 | #endif |
0d92ed30 PB |
892 | pid = USB_TOKEN_SETUP; |
893 | break; | |
894 | default: | |
895 | fprintf(stderr, "usb-ohci: Bad direction\n"); | |
896 | return 1; | |
897 | } | |
898 | if (td.cbp && td.be) { | |
e6f3e5e0 PB |
899 | if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
900 | len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); | |
901 | } else { | |
902 | len = (td.be - td.cbp) + 1; | |
903 | } | |
904 | ||
4d611c9a | 905 | if (len && dir != OHCI_TD_DIR_IN && !completion) { |
ac611340 | 906 | ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0); |
0d92ed30 PB |
907 | } |
908 | } | |
909 | ||
910 | flag_r = (td.flags & OHCI_TD_R) != 0; | |
911 | #ifdef DEBUG_PACKET | |
d0f2c4c6 | 912 | DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n", |
f3571b1a | 913 | addr, (int64_t)len, str, flag_r, td.cbp, td.be); |
0d92ed30 | 914 | |
87283515 | 915 | if (len > 0 && dir != OHCI_TD_DIR_IN) { |
d0f2c4c6 | 916 | DPRINTF(" data:"); |
0d92ed30 | 917 | for (i = 0; i < len; i++) |
4d611c9a | 918 | printf(" %.2x", ohci->usb_buf[i]); |
d0f2c4c6 | 919 | DPRINTF("\n"); |
0d92ed30 PB |
920 | } |
921 | #endif | |
4d611c9a PB |
922 | if (completion) { |
923 | ret = ohci->usb_packet.len; | |
924 | ohci->async_td = 0; | |
925 | ohci->async_complete = 0; | |
926 | } else { | |
927 | ret = USB_RET_NODEV; | |
928 | for (i = 0; i < ohci->num_ports; i++) { | |
929 | dev = ohci->rhport[i].port.dev; | |
930 | if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) | |
931 | continue; | |
932 | ||
933 | if (ohci->async_td) { | |
934 | /* ??? The hardware should allow one active packet per | |
935 | endpoint. We only allow one active packet per controller. | |
936 | This should be sufficient as long as devices respond in a | |
937 | timely manner. | |
938 | */ | |
0d92ed30 | 939 | #ifdef DEBUG_PACKET |
d0f2c4c6 | 940 | DPRINTF("Too many pending packets\n"); |
0d92ed30 | 941 | #endif |
4d611c9a PB |
942 | return 1; |
943 | } | |
944 | ohci->usb_packet.pid = pid; | |
945 | ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); | |
946 | ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); | |
947 | ohci->usb_packet.data = ohci->usb_buf; | |
948 | ohci->usb_packet.len = len; | |
949 | ohci->usb_packet.complete_cb = ohci_async_complete_packet; | |
950 | ohci->usb_packet.complete_opaque = ohci; | |
806b6024 | 951 | ret = dev->info->handle_packet(dev, &ohci->usb_packet); |
4d611c9a PB |
952 | if (ret != USB_RET_NODEV) |
953 | break; | |
954 | } | |
955 | #ifdef DEBUG_PACKET | |
d0f2c4c6 | 956 | DPRINTF("ret=%d\n", ret); |
4d611c9a PB |
957 | #endif |
958 | if (ret == USB_RET_ASYNC) { | |
959 | ohci->async_td = addr; | |
960 | return 1; | |
961 | } | |
962 | } | |
0d92ed30 PB |
963 | if (ret >= 0) { |
964 | if (dir == OHCI_TD_DIR_IN) { | |
ac611340 | 965 | ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1); |
0d92ed30 | 966 | #ifdef DEBUG_PACKET |
d0f2c4c6 | 967 | DPRINTF(" data:"); |
0d92ed30 | 968 | for (i = 0; i < ret; i++) |
4d611c9a | 969 | printf(" %.2x", ohci->usb_buf[i]); |
d0f2c4c6 | 970 | DPRINTF("\n"); |
0d92ed30 PB |
971 | #endif |
972 | } else { | |
973 | ret = len; | |
974 | } | |
975 | } | |
976 | ||
977 | /* Writeback */ | |
978 | if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { | |
979 | /* Transmission succeeded. */ | |
980 | if (ret == len) { | |
981 | td.cbp = 0; | |
982 | } else { | |
983 | td.cbp += ret; | |
984 | if ((td.cbp & 0xfff) + ret > 0xfff) { | |
985 | td.cbp &= 0xfff; | |
986 | td.cbp |= td.be & ~0xfff; | |
987 | } | |
988 | } | |
989 | td.flags |= OHCI_TD_T1; | |
990 | td.flags ^= OHCI_TD_T0; | |
991 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); | |
992 | OHCI_SET_BM(td.flags, TD_EC, 0); | |
993 | ||
994 | ed->head &= ~OHCI_ED_C; | |
995 | if (td.flags & OHCI_TD_T0) | |
996 | ed->head |= OHCI_ED_C; | |
997 | } else { | |
998 | if (ret >= 0) { | |
d0f2c4c6 | 999 | DPRINTF("usb-ohci: Underrun\n"); |
0d92ed30 PB |
1000 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
1001 | } else { | |
1002 | switch (ret) { | |
1003 | case USB_RET_NODEV: | |
1004 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); | |
1005 | case USB_RET_NAK: | |
d0f2c4c6 | 1006 | DPRINTF("usb-ohci: got NAK\n"); |
0d92ed30 PB |
1007 | return 1; |
1008 | case USB_RET_STALL: | |
d0f2c4c6 | 1009 | DPRINTF("usb-ohci: got STALL\n"); |
0d92ed30 PB |
1010 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
1011 | break; | |
1012 | case USB_RET_BABBLE: | |
d0f2c4c6 | 1013 | DPRINTF("usb-ohci: got BABBLE\n"); |
0d92ed30 PB |
1014 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
1015 | break; | |
1016 | default: | |
1017 | fprintf(stderr, "usb-ohci: Bad device response %d\n", ret); | |
1018 | OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); | |
1019 | OHCI_SET_BM(td.flags, TD_EC, 3); | |
1020 | break; | |
1021 | } | |
1022 | } | |
1023 | ed->head |= OHCI_ED_H; | |
1024 | } | |
1025 | ||
1026 | /* Retire this TD */ | |
1027 | ed->head &= ~OHCI_DPTR_MASK; | |
1028 | ed->head |= td.next & OHCI_DPTR_MASK; | |
1029 | td.next = ohci->done; | |
1030 | ohci->done = addr; | |
1031 | i = OHCI_BM(td.flags, TD_DI); | |
1032 | if (i < ohci->done_count) | |
1033 | ohci->done_count = i; | |
ac611340 | 1034 | ohci_put_td(ohci, addr, &td); |
0d92ed30 PB |
1035 | return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; |
1036 | } | |
1037 | ||
1038 | /* Service an endpoint list. Returns nonzero if active TD were found. */ | |
7bfe5777 | 1039 | static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) |
0d92ed30 PB |
1040 | { |
1041 | struct ohci_ed ed; | |
1042 | uint32_t next_ed; | |
1043 | uint32_t cur; | |
1044 | int active; | |
1045 | ||
1046 | active = 0; | |
1047 | ||
1048 | if (head == 0) | |
1049 | return 0; | |
1050 | ||
1051 | for (cur = head; cur; cur = next_ed) { | |
ac611340 | 1052 | if (!ohci_read_ed(ohci, cur, &ed)) { |
0d92ed30 PB |
1053 | fprintf(stderr, "usb-ohci: ED read error at %x\n", cur); |
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | next_ed = ed.next & OHCI_DPTR_MASK; | |
1058 | ||
4d611c9a PB |
1059 | if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { |
1060 | uint32_t addr; | |
1061 | /* Cancel pending packets for ED that have been paused. */ | |
1062 | addr = ed.head & OHCI_DPTR_MASK; | |
1063 | if (ohci->async_td && addr == ohci->async_td) { | |
1064 | usb_cancel_packet(&ohci->usb_packet); | |
1065 | ohci->async_td = 0; | |
1066 | } | |
0d92ed30 | 1067 | continue; |
4d611c9a | 1068 | } |
0d92ed30 | 1069 | |
0d92ed30 PB |
1070 | while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { |
1071 | #ifdef DEBUG_PACKET | |
d0f2c4c6 | 1072 | DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u " |
0d92ed30 PB |
1073 | "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur, |
1074 | OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), | |
1075 | OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, | |
1076 | (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, | |
1077 | OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0, | |
1078 | (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, | |
1079 | ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); | |
1080 | #endif | |
1081 | active = 1; | |
1082 | ||
7bfe5777 AZ |
1083 | if ((ed.flags & OHCI_ED_F) == 0) { |
1084 | if (ohci_service_td(ohci, &ed)) | |
1085 | break; | |
1086 | } else { | |
1087 | /* Handle isochronous endpoints */ | |
1088 | if (ohci_service_iso_td(ohci, &ed, completion)) | |
1089 | break; | |
1090 | } | |
0d92ed30 PB |
1091 | } |
1092 | ||
ac611340 | 1093 | ohci_put_ed(ohci, cur, &ed); |
0d92ed30 PB |
1094 | } |
1095 | ||
1096 | return active; | |
1097 | } | |
1098 | ||
1099 | /* Generate a SOF event, and set a timer for EOF */ | |
1100 | static void ohci_sof(OHCIState *ohci) | |
1101 | { | |
74475455 | 1102 | ohci->sof_time = qemu_get_clock_ns(vm_clock); |
0d92ed30 PB |
1103 | qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); |
1104 | ohci_set_interrupt(ohci, OHCI_INTR_SF); | |
1105 | } | |
1106 | ||
4d611c9a | 1107 | /* Process Control and Bulk lists. */ |
7bfe5777 | 1108 | static void ohci_process_lists(OHCIState *ohci, int completion) |
4d611c9a PB |
1109 | { |
1110 | if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { | |
6ad6135d BS |
1111 | if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { |
1112 | DPRINTF("usb-ohci: head %x, cur %x\n", | |
1113 | ohci->ctrl_head, ohci->ctrl_cur); | |
1114 | } | |
7bfe5777 | 1115 | if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { |
4d611c9a PB |
1116 | ohci->ctrl_cur = 0; |
1117 | ohci->status &= ~OHCI_STATUS_CLF; | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { | |
7bfe5777 | 1122 | if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { |
4d611c9a PB |
1123 | ohci->bulk_cur = 0; |
1124 | ohci->status &= ~OHCI_STATUS_BLF; | |
1125 | } | |
1126 | } | |
1127 | } | |
1128 | ||
0d92ed30 PB |
1129 | /* Do frame processing on frame boundary */ |
1130 | static void ohci_frame_boundary(void *opaque) | |
1131 | { | |
1132 | OHCIState *ohci = opaque; | |
1133 | struct ohci_hcca hcca; | |
1134 | ||
ac611340 | 1135 | ohci_read_hcca(ohci, ohci->hcca, &hcca); |
0d92ed30 PB |
1136 | |
1137 | /* Process all the lists at the end of the frame */ | |
1138 | if (ohci->ctl & OHCI_CTL_PLE) { | |
1139 | int n; | |
1140 | ||
1141 | n = ohci->frame_number & 0x1f; | |
7bfe5777 | 1142 | ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); |
0d92ed30 | 1143 | } |
0d92ed30 | 1144 | |
4d611c9a PB |
1145 | /* Cancel all pending packets if either of the lists has been disabled. */ |
1146 | if (ohci->async_td && | |
1147 | ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { | |
1148 | usb_cancel_packet(&ohci->usb_packet); | |
1149 | ohci->async_td = 0; | |
0d92ed30 | 1150 | } |
4d611c9a | 1151 | ohci->old_ctl = ohci->ctl; |
7bfe5777 | 1152 | ohci_process_lists(ohci, 0); |
0d92ed30 PB |
1153 | |
1154 | /* Frame boundary, so do EOF stuf here */ | |
1155 | ohci->frt = ohci->fit; | |
1156 | ||
1fa63e43 | 1157 | /* Increment frame number and take care of endianness. */ |
0d92ed30 | 1158 | ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
1fa63e43 | 1159 | hcca.frame = cpu_to_le16(ohci->frame_number); |
0d92ed30 PB |
1160 | |
1161 | if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { | |
1162 | if (!ohci->done) | |
1163 | abort(); | |
1164 | if (ohci->intr & ohci->intr_status) | |
1165 | ohci->done |= 1; | |
1166 | hcca.done = cpu_to_le32(ohci->done); | |
1167 | ohci->done = 0; | |
1168 | ohci->done_count = 7; | |
1169 | ohci_set_interrupt(ohci, OHCI_INTR_WD); | |
1170 | } | |
1171 | ||
1172 | if (ohci->done_count != 7 && ohci->done_count != 0) | |
1173 | ohci->done_count--; | |
1174 | ||
1175 | /* Do SOF stuff here */ | |
1176 | ohci_sof(ohci); | |
1177 | ||
1178 | /* Writeback HCCA */ | |
ac611340 | 1179 | ohci_put_hcca(ohci, ohci->hcca, &hcca); |
0d92ed30 PB |
1180 | } |
1181 | ||
1182 | /* Start sending SOF tokens across the USB bus, lists are processed in | |
1183 | * next frame | |
1184 | */ | |
1185 | static int ohci_bus_start(OHCIState *ohci) | |
1186 | { | |
74475455 | 1187 | ohci->eof_timer = qemu_new_timer_ns(vm_clock, |
0d92ed30 PB |
1188 | ohci_frame_boundary, |
1189 | ohci); | |
1190 | ||
1191 | if (ohci->eof_timer == NULL) { | |
74475455 | 1192 | fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name); |
0d92ed30 PB |
1193 | /* TODO: Signal unrecoverable error */ |
1194 | return 0; | |
1195 | } | |
1196 | ||
d0f2c4c6 | 1197 | DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name); |
0d92ed30 PB |
1198 | |
1199 | ohci_sof(ohci); | |
1200 | ||
1201 | return 1; | |
1202 | } | |
1203 | ||
1204 | /* Stop sending SOF tokens on the bus */ | |
1205 | static void ohci_bus_stop(OHCIState *ohci) | |
1206 | { | |
1207 | if (ohci->eof_timer) | |
1208 | qemu_del_timer(ohci->eof_timer); | |
73221b12 | 1209 | ohci->eof_timer = NULL; |
0d92ed30 PB |
1210 | } |
1211 | ||
1212 | /* Sets a flag in a port status register but only set it if the port is | |
1213 | * connected, if not set ConnectStatusChange flag. If flag is enabled | |
1214 | * return 1. | |
1215 | */ | |
1216 | static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) | |
1217 | { | |
1218 | int ret = 1; | |
1219 | ||
1220 | /* writing a 0 has no effect */ | |
1221 | if (val == 0) | |
1222 | return 0; | |
1223 | ||
1224 | /* If CurrentConnectStatus is cleared we set | |
1225 | * ConnectStatusChange | |
1226 | */ | |
1227 | if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { | |
1228 | ohci->rhport[i].ctrl |= OHCI_PORT_CSC; | |
1229 | if (ohci->rhstatus & OHCI_RHS_DRWE) { | |
1230 | /* TODO: CSC is a wakeup event */ | |
1231 | } | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | if (ohci->rhport[i].ctrl & val) | |
1236 | ret = 0; | |
1237 | ||
1238 | /* set the bit */ | |
1239 | ohci->rhport[i].ctrl |= val; | |
1240 | ||
1241 | return ret; | |
1242 | } | |
1243 | ||
1244 | /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ | |
1245 | static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) | |
1246 | { | |
1247 | val &= OHCI_FMI_FI; | |
1248 | ||
1249 | if (val != ohci->fi) { | |
d0f2c4c6 | 1250 | DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n", |
e24ad6f1 | 1251 | ohci->name, ohci->fi, ohci->fi); |
0d92ed30 PB |
1252 | } |
1253 | ||
1254 | ohci->fi = val; | |
1255 | } | |
1256 | ||
1257 | static void ohci_port_power(OHCIState *ohci, int i, int p) | |
1258 | { | |
1259 | if (p) { | |
1260 | ohci->rhport[i].ctrl |= OHCI_PORT_PPS; | |
1261 | } else { | |
1262 | ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| | |
1263 | OHCI_PORT_CCS| | |
1264 | OHCI_PORT_PSS| | |
1265 | OHCI_PORT_PRS); | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | /* Set HcControlRegister */ | |
1270 | static void ohci_set_ctl(OHCIState *ohci, uint32_t val) | |
1271 | { | |
1272 | uint32_t old_state; | |
1273 | uint32_t new_state; | |
1274 | ||
1275 | old_state = ohci->ctl & OHCI_CTL_HCFS; | |
1276 | ohci->ctl = val; | |
1277 | new_state = ohci->ctl & OHCI_CTL_HCFS; | |
1278 | ||
1279 | /* no state change */ | |
1280 | if (old_state == new_state) | |
1281 | return; | |
1282 | ||
1283 | switch (new_state) { | |
1284 | case OHCI_USB_OPERATIONAL: | |
1285 | ohci_bus_start(ohci); | |
1286 | break; | |
1287 | case OHCI_USB_SUSPEND: | |
1288 | ohci_bus_stop(ohci); | |
d0f2c4c6 | 1289 | DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name); |
0d92ed30 PB |
1290 | break; |
1291 | case OHCI_USB_RESUME: | |
d0f2c4c6 | 1292 | DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name); |
0d92ed30 PB |
1293 | break; |
1294 | case OHCI_USB_RESET: | |
73221b12 | 1295 | ohci_reset(ohci); |
d0f2c4c6 | 1296 | DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name); |
0d92ed30 PB |
1297 | break; |
1298 | } | |
1299 | } | |
1300 | ||
1301 | static uint32_t ohci_get_frame_remaining(OHCIState *ohci) | |
1302 | { | |
1303 | uint16_t fr; | |
1304 | int64_t tks; | |
1305 | ||
1306 | if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) | |
1307 | return (ohci->frt << 31); | |
1308 | ||
1309 | /* Being in USB operational state guarnatees sof_time was | |
1310 | * set already. | |
1311 | */ | |
74475455 | 1312 | tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time; |
0d92ed30 PB |
1313 | |
1314 | /* avoid muldiv if possible */ | |
1315 | if (tks >= usb_frame_time) | |
1316 | return (ohci->frt << 31); | |
1317 | ||
1318 | tks = muldiv64(1, tks, usb_bit_time); | |
1319 | fr = (uint16_t)(ohci->fi - tks); | |
1320 | ||
1321 | return (ohci->frt << 31) | fr; | |
1322 | } | |
1323 | ||
1324 | ||
1325 | /* Set root hub status */ | |
1326 | static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) | |
1327 | { | |
1328 | uint32_t old_state; | |
1329 | ||
1330 | old_state = ohci->rhstatus; | |
1331 | ||
1332 | /* write 1 to clear OCIC */ | |
1333 | if (val & OHCI_RHS_OCIC) | |
1334 | ohci->rhstatus &= ~OHCI_RHS_OCIC; | |
1335 | ||
1336 | if (val & OHCI_RHS_LPS) { | |
1337 | int i; | |
1338 | ||
1339 | for (i = 0; i < ohci->num_ports; i++) | |
1340 | ohci_port_power(ohci, i, 0); | |
d0f2c4c6 | 1341 | DPRINTF("usb-ohci: powered down all ports\n"); |
0d92ed30 PB |
1342 | } |
1343 | ||
1344 | if (val & OHCI_RHS_LPSC) { | |
1345 | int i; | |
1346 | ||
1347 | for (i = 0; i < ohci->num_ports; i++) | |
1348 | ohci_port_power(ohci, i, 1); | |
d0f2c4c6 | 1349 | DPRINTF("usb-ohci: powered up all ports\n"); |
0d92ed30 PB |
1350 | } |
1351 | ||
1352 | if (val & OHCI_RHS_DRWE) | |
1353 | ohci->rhstatus |= OHCI_RHS_DRWE; | |
1354 | ||
1355 | if (val & OHCI_RHS_CRWE) | |
1356 | ohci->rhstatus &= ~OHCI_RHS_DRWE; | |
1357 | ||
1358 | if (old_state != ohci->rhstatus) | |
1359 | ohci_set_interrupt(ohci, OHCI_INTR_RHSC); | |
1360 | } | |
1361 | ||
1362 | /* Set root hub port status */ | |
1363 | static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) | |
1364 | { | |
1365 | uint32_t old_state; | |
1366 | OHCIPort *port; | |
1367 | ||
1368 | port = &ohci->rhport[portnum]; | |
1369 | old_state = port->ctrl; | |
1370 | ||
1371 | /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ | |
1372 | if (val & OHCI_PORT_WTC) | |
1373 | port->ctrl &= ~(val & OHCI_PORT_WTC); | |
1374 | ||
1375 | if (val & OHCI_PORT_CCS) | |
1376 | port->ctrl &= ~OHCI_PORT_PES; | |
1377 | ||
1378 | ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); | |
1379 | ||
6ad6135d | 1380 | if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { |
d0f2c4c6 | 1381 | DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum); |
6ad6135d | 1382 | } |
0d92ed30 PB |
1383 | |
1384 | if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { | |
d0f2c4c6 | 1385 | DPRINTF("usb-ohci: port %d: RESET\n", portnum); |
4d611c9a | 1386 | usb_send_msg(port->port.dev, USB_MSG_RESET); |
0d92ed30 PB |
1387 | port->ctrl &= ~OHCI_PORT_PRS; |
1388 | /* ??? Should this also set OHCI_PORT_PESC. */ | |
1389 | port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; | |
1390 | } | |
1391 | ||
1392 | /* Invert order here to ensure in ambiguous case, device is | |
1393 | * powered up... | |
1394 | */ | |
1395 | if (val & OHCI_PORT_LSDA) | |
1396 | ohci_port_power(ohci, portnum, 0); | |
1397 | if (val & OHCI_PORT_PPS) | |
1398 | ohci_port_power(ohci, portnum, 1); | |
1399 | ||
1400 | if (old_state != port->ctrl) | |
1401 | ohci_set_interrupt(ohci, OHCI_INTR_RHSC); | |
1402 | ||
1403 | return; | |
1404 | } | |
1405 | ||
a67ba3b6 | 1406 | static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) |
0d92ed30 PB |
1407 | { |
1408 | OHCIState *ohci = ptr; | |
65e1d81b | 1409 | uint32_t retval; |
0d92ed30 | 1410 | |
09564574 PB |
1411 | addr &= 0xff; |
1412 | ||
0d92ed30 PB |
1413 | /* Only aligned reads are allowed on OHCI */ |
1414 | if (addr & 3) { | |
1415 | fprintf(stderr, "usb-ohci: Mis-aligned read\n"); | |
1416 | return 0xffffffff; | |
65e1d81b | 1417 | } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
0d92ed30 | 1418 | /* HcRhPortStatus */ |
65e1d81b AJ |
1419 | retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1420 | } else { | |
1421 | switch (addr >> 2) { | |
1422 | case 0: /* HcRevision */ | |
1423 | retval = 0x10; | |
1424 | break; | |
1425 | ||
1426 | case 1: /* HcControl */ | |
1427 | retval = ohci->ctl; | |
1428 | break; | |
1429 | ||
1430 | case 2: /* HcCommandStatus */ | |
1431 | retval = ohci->status; | |
1432 | break; | |
1433 | ||
1434 | case 3: /* HcInterruptStatus */ | |
1435 | retval = ohci->intr_status; | |
1436 | break; | |
1437 | ||
1438 | case 4: /* HcInterruptEnable */ | |
1439 | case 5: /* HcInterruptDisable */ | |
1440 | retval = ohci->intr; | |
1441 | break; | |
1442 | ||
1443 | case 6: /* HcHCCA */ | |
1444 | retval = ohci->hcca; | |
1445 | break; | |
1446 | ||
1447 | case 7: /* HcPeriodCurrentED */ | |
1448 | retval = ohci->per_cur; | |
1449 | break; | |
1450 | ||
1451 | case 8: /* HcControlHeadED */ | |
1452 | retval = ohci->ctrl_head; | |
1453 | break; | |
1454 | ||
1455 | case 9: /* HcControlCurrentED */ | |
1456 | retval = ohci->ctrl_cur; | |
1457 | break; | |
1458 | ||
1459 | case 10: /* HcBulkHeadED */ | |
1460 | retval = ohci->bulk_head; | |
1461 | break; | |
1462 | ||
1463 | case 11: /* HcBulkCurrentED */ | |
1464 | retval = ohci->bulk_cur; | |
1465 | break; | |
1466 | ||
1467 | case 12: /* HcDoneHead */ | |
1468 | retval = ohci->done; | |
1469 | break; | |
1470 | ||
1471 | case 13: /* HcFmInterretval */ | |
1472 | retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); | |
1473 | break; | |
1474 | ||
1475 | case 14: /* HcFmRemaining */ | |
1476 | retval = ohci_get_frame_remaining(ohci); | |
1477 | break; | |
1478 | ||
1479 | case 15: /* HcFmNumber */ | |
1480 | retval = ohci->frame_number; | |
1481 | break; | |
1482 | ||
1483 | case 16: /* HcPeriodicStart */ | |
1484 | retval = ohci->pstart; | |
1485 | break; | |
1486 | ||
1487 | case 17: /* HcLSThreshold */ | |
1488 | retval = ohci->lst; | |
1489 | break; | |
1490 | ||
1491 | case 18: /* HcRhDescriptorA */ | |
1492 | retval = ohci->rhdesc_a; | |
1493 | break; | |
1494 | ||
1495 | case 19: /* HcRhDescriptorB */ | |
1496 | retval = ohci->rhdesc_b; | |
1497 | break; | |
1498 | ||
1499 | case 20: /* HcRhStatus */ | |
1500 | retval = ohci->rhstatus; | |
1501 | break; | |
1502 | ||
1503 | /* PXA27x specific registers */ | |
1504 | case 24: /* HcStatus */ | |
1505 | retval = ohci->hstatus & ohci->hmask; | |
1506 | break; | |
1507 | ||
1508 | case 25: /* HcHReset */ | |
1509 | retval = ohci->hreset; | |
1510 | break; | |
1511 | ||
1512 | case 26: /* HcHInterruptEnable */ | |
1513 | retval = ohci->hmask; | |
1514 | break; | |
1515 | ||
1516 | case 27: /* HcHInterruptTest */ | |
1517 | retval = ohci->htest; | |
1518 | break; | |
1519 | ||
1520 | default: | |
1521 | fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); | |
1522 | retval = 0xffffffff; | |
1523 | } | |
0d92ed30 PB |
1524 | } |
1525 | ||
65e1d81b | 1526 | return retval; |
0d92ed30 PB |
1527 | } |
1528 | ||
a67ba3b6 | 1529 | static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) |
0d92ed30 PB |
1530 | { |
1531 | OHCIState *ohci = ptr; | |
1532 | ||
09564574 PB |
1533 | addr &= 0xff; |
1534 | ||
0d92ed30 PB |
1535 | /* Only aligned reads are allowed on OHCI */ |
1536 | if (addr & 3) { | |
1537 | fprintf(stderr, "usb-ohci: Mis-aligned write\n"); | |
1538 | return; | |
1539 | } | |
1540 | ||
1541 | if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { | |
1542 | /* HcRhPortStatus */ | |
1543 | ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); | |
1544 | return; | |
1545 | } | |
1546 | ||
1547 | switch (addr >> 2) { | |
1548 | case 1: /* HcControl */ | |
1549 | ohci_set_ctl(ohci, val); | |
1550 | break; | |
1551 | ||
1552 | case 2: /* HcCommandStatus */ | |
1553 | /* SOC is read-only */ | |
1554 | val = (val & ~OHCI_STATUS_SOC); | |
1555 | ||
1556 | /* Bits written as '0' remain unchanged in the register */ | |
1557 | ohci->status |= val; | |
1558 | ||
1559 | if (ohci->status & OHCI_STATUS_HCR) | |
1560 | ohci_reset(ohci); | |
1561 | break; | |
1562 | ||
1563 | case 3: /* HcInterruptStatus */ | |
1564 | ohci->intr_status &= ~val; | |
1565 | ohci_intr_update(ohci); | |
1566 | break; | |
1567 | ||
1568 | case 4: /* HcInterruptEnable */ | |
1569 | ohci->intr |= val; | |
1570 | ohci_intr_update(ohci); | |
1571 | break; | |
1572 | ||
1573 | case 5: /* HcInterruptDisable */ | |
1574 | ohci->intr &= ~val; | |
1575 | ohci_intr_update(ohci); | |
1576 | break; | |
1577 | ||
1578 | case 6: /* HcHCCA */ | |
1579 | ohci->hcca = val & OHCI_HCCA_MASK; | |
1580 | break; | |
1581 | ||
1582 | case 8: /* HcControlHeadED */ | |
1583 | ohci->ctrl_head = val & OHCI_EDPTR_MASK; | |
1584 | break; | |
1585 | ||
1586 | case 9: /* HcControlCurrentED */ | |
1587 | ohci->ctrl_cur = val & OHCI_EDPTR_MASK; | |
1588 | break; | |
1589 | ||
1590 | case 10: /* HcBulkHeadED */ | |
1591 | ohci->bulk_head = val & OHCI_EDPTR_MASK; | |
1592 | break; | |
1593 | ||
1594 | case 11: /* HcBulkCurrentED */ | |
1595 | ohci->bulk_cur = val & OHCI_EDPTR_MASK; | |
1596 | break; | |
1597 | ||
1598 | case 13: /* HcFmInterval */ | |
1599 | ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; | |
1600 | ohci->fit = (val & OHCI_FMI_FIT) >> 31; | |
1601 | ohci_set_frame_interval(ohci, val); | |
1602 | break; | |
1603 | ||
7bfe5777 AZ |
1604 | case 15: /* HcFmNumber */ |
1605 | break; | |
1606 | ||
0d92ed30 PB |
1607 | case 16: /* HcPeriodicStart */ |
1608 | ohci->pstart = val & 0xffff; | |
1609 | break; | |
1610 | ||
1611 | case 17: /* HcLSThreshold */ | |
1612 | ohci->lst = val & 0xffff; | |
1613 | break; | |
1614 | ||
1615 | case 18: /* HcRhDescriptorA */ | |
1616 | ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; | |
1617 | ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; | |
1618 | break; | |
1619 | ||
1620 | case 19: /* HcRhDescriptorB */ | |
1621 | break; | |
1622 | ||
1623 | case 20: /* HcRhStatus */ | |
1624 | ohci_set_hub_status(ohci, val); | |
1625 | break; | |
1626 | ||
e24ad6f1 PB |
1627 | /* PXA27x specific registers */ |
1628 | case 24: /* HcStatus */ | |
1629 | ohci->hstatus &= ~(val & ohci->hmask); | |
1630 | ||
1631 | case 25: /* HcHReset */ | |
1632 | ohci->hreset = val & ~OHCI_HRESET_FSBIR; | |
1633 | if (val & OHCI_HRESET_FSBIR) | |
1634 | ohci_reset(ohci); | |
1635 | break; | |
1636 | ||
1637 | case 26: /* HcHInterruptEnable */ | |
1638 | ohci->hmask = val; | |
1639 | break; | |
1640 | ||
1641 | case 27: /* HcHInterruptTest */ | |
1642 | ohci->htest = val; | |
1643 | break; | |
1644 | ||
0d92ed30 PB |
1645 | default: |
1646 | fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); | |
1647 | break; | |
1648 | } | |
1649 | } | |
1650 | ||
1651 | /* Only dword reads are defined on OHCI register space */ | |
a67ba3b6 PB |
1652 | static CPUReadMemoryFunc * const ohci_readfn[3]={ |
1653 | ohci_mem_read, | |
1654 | ohci_mem_read, | |
1655 | ohci_mem_read | |
0d92ed30 PB |
1656 | }; |
1657 | ||
1658 | /* Only dword writes are defined on OHCI register space */ | |
a67ba3b6 PB |
1659 | static CPUWriteMemoryFunc * const ohci_writefn[3]={ |
1660 | ohci_mem_write, | |
1661 | ohci_mem_write, | |
1662 | ohci_mem_write | |
0d92ed30 PB |
1663 | }; |
1664 | ||
0d86d2be GH |
1665 | static USBPortOps ohci_port_ops = { |
1666 | .attach = ohci_attach, | |
618c169b | 1667 | .detach = ohci_detach, |
0d86d2be GH |
1668 | }; |
1669 | ||
5b19d9a2 | 1670 | static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
61d3cf93 | 1671 | int num_ports, uint32_t localmem_base) |
0d92ed30 | 1672 | { |
0d92ed30 PB |
1673 | int i; |
1674 | ||
0d92ed30 | 1675 | if (usb_frame_time == 0) { |
eb38c52c | 1676 | #ifdef OHCI_TIME_WARP |
6ee093c9 JQ |
1677 | usb_frame_time = get_ticks_per_sec(); |
1678 | usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); | |
0d92ed30 | 1679 | #else |
6ee093c9 JQ |
1680 | usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); |
1681 | if (get_ticks_per_sec() >= USB_HZ) { | |
1682 | usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ); | |
0d92ed30 PB |
1683 | } else { |
1684 | usb_bit_time = 1; | |
1685 | } | |
1686 | #endif | |
d0f2c4c6 | 1687 | DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n", |
0d92ed30 PB |
1688 | usb_frame_time, usb_bit_time); |
1689 | } | |
1690 | ||
2507c12a | 1691 | ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci, |
34557491 | 1692 | DEVICE_LITTLE_ENDIAN); |
ac611340 | 1693 | ohci->localmem_base = localmem_base; |
e24ad6f1 | 1694 | |
61d3cf93 | 1695 | ohci->name = dev->info->name; |
e24ad6f1 | 1696 | |
b2317837 | 1697 | usb_bus_new(&ohci->bus, dev); |
e24ad6f1 PB |
1698 | ohci->num_ports = num_ports; |
1699 | for (i = 0; i < num_ports; i++) { | |
ace1318b | 1700 | usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, &ohci_port_ops, |
843d4e0c | 1701 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
c7a2196a | 1702 | usb_port_location(&ohci->rhport[i].port, NULL, i+1); |
e24ad6f1 PB |
1703 | } |
1704 | ||
1705 | ohci->async_td = 0; | |
a08d4367 | 1706 | qemu_register_reset(ohci_reset, ohci); |
e24ad6f1 PB |
1707 | } |
1708 | ||
1709 | typedef struct { | |
1710 | PCIDevice pci_dev; | |
1711 | OHCIState state; | |
1712 | } OHCIPCIState; | |
1713 | ||
5b19d9a2 | 1714 | static int usb_ohci_initfn_pci(struct PCIDevice *dev) |
e24ad6f1 | 1715 | { |
5b19d9a2 GH |
1716 | OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev); |
1717 | int num_ports = 3; | |
0d92ed30 | 1718 | |
d74dbb94 | 1719 | ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */ |
d74dbb94 MT |
1720 | /* TODO: RST# value should be 0. */ |
1721 | ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ | |
0d92ed30 | 1722 | |
61d3cf93 PB |
1723 | usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0); |
1724 | ohci->state.irq = ohci->pci_dev.irq[0]; | |
0d92ed30 | 1725 | |
d74dbb94 | 1726 | /* TODO: avoid cast below by using dev */ |
6e964ded | 1727 | pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem); |
5b19d9a2 GH |
1728 | return 0; |
1729 | } | |
1730 | ||
a67ba3b6 | 1731 | void usb_ohci_init_pci(struct PCIBus *bus, int devfn) |
5b19d9a2 | 1732 | { |
a67ba3b6 | 1733 | pci_create_simple(bus, devfn, "pci-ohci"); |
e24ad6f1 | 1734 | } |
0d92ed30 | 1735 | |
61d3cf93 PB |
1736 | typedef struct { |
1737 | SysBusDevice busdev; | |
1738 | OHCIState ohci; | |
1739 | uint32_t num_ports; | |
1740 | target_phys_addr_t dma_offset; | |
1741 | } OHCISysBusState; | |
ac611340 | 1742 | |
61d3cf93 | 1743 | static int ohci_init_pxa(SysBusDevice *dev) |
ac611340 | 1744 | { |
61d3cf93 | 1745 | OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev); |
ac611340 | 1746 | |
61d3cf93 PB |
1747 | usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset); |
1748 | sysbus_init_irq(dev, &s->ohci.irq); | |
1749 | sysbus_init_mmio(dev, 0x1000, s->ohci.mem); | |
ac611340 | 1750 | |
61d3cf93 | 1751 | return 0; |
ac611340 AJ |
1752 | } |
1753 | ||
61d3cf93 | 1754 | static PCIDeviceInfo ohci_pci_info = { |
556cd098 | 1755 | .qdev.name = "pci-ohci", |
5b19d9a2 GH |
1756 | .qdev.desc = "Apple USB Controller", |
1757 | .qdev.size = sizeof(OHCIPCIState), | |
1758 | .init = usb_ohci_initfn_pci, | |
a8eae585 IY |
1759 | .vendor_id = PCI_VENDOR_ID_APPLE, |
1760 | .device_id = PCI_DEVICE_ID_APPLE_IPID_USB, | |
1761 | .class_id = PCI_CLASS_SERIAL_USB, | |
5b19d9a2 GH |
1762 | }; |
1763 | ||
61d3cf93 PB |
1764 | static SysBusDeviceInfo ohci_sysbus_info = { |
1765 | .init = ohci_init_pxa, | |
1766 | .qdev.name = "sysbus-ohci", | |
1767 | .qdev.desc = "OHCI USB Controller", | |
1768 | .qdev.size = sizeof(OHCISysBusState), | |
1769 | .qdev.props = (Property[]) { | |
1770 | DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), | |
1771 | DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3), | |
1772 | DEFINE_PROP_END_OF_LIST(), | |
1773 | } | |
1774 | }; | |
1775 | ||
5b19d9a2 GH |
1776 | static void ohci_register(void) |
1777 | { | |
61d3cf93 PB |
1778 | pci_qdev_register(&ohci_pci_info); |
1779 | sysbus_register_withprop(&ohci_sysbus_info); | |
5b19d9a2 GH |
1780 | } |
1781 | device_init(ohci_register); |