]>
Commit | Line | Data |
---|---|---|
bb36d470 FB |
1 | /* |
2 | * USB UHCI controller emulation | |
5fafdf24 | 3 | * |
bb36d470 | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
54f254f9 AL |
6 | * Copyright (c) 2008 Max Krasnyansky |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
bb36d470 FB |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
87ecb68b PB |
28 | #include "hw.h" |
29 | #include "usb.h" | |
30 | #include "pci.h" | |
31 | #include "qemu-timer.h" | |
18e08a55 | 32 | #include "usb-uhci.h" |
bb36d470 FB |
33 | |
34 | //#define DEBUG | |
54f254f9 | 35 | //#define DEBUG_DUMP_DATA |
bb36d470 | 36 | |
96217e31 TS |
37 | #define UHCI_CMD_FGR (1 << 4) |
38 | #define UHCI_CMD_EGSM (1 << 3) | |
bb36d470 FB |
39 | #define UHCI_CMD_GRESET (1 << 2) |
40 | #define UHCI_CMD_HCRESET (1 << 1) | |
41 | #define UHCI_CMD_RS (1 << 0) | |
42 | ||
43 | #define UHCI_STS_HCHALTED (1 << 5) | |
44 | #define UHCI_STS_HCPERR (1 << 4) | |
45 | #define UHCI_STS_HSERR (1 << 3) | |
46 | #define UHCI_STS_RD (1 << 2) | |
47 | #define UHCI_STS_USBERR (1 << 1) | |
48 | #define UHCI_STS_USBINT (1 << 0) | |
49 | ||
50 | #define TD_CTRL_SPD (1 << 29) | |
51 | #define TD_CTRL_ERROR_SHIFT 27 | |
52 | #define TD_CTRL_IOS (1 << 25) | |
53 | #define TD_CTRL_IOC (1 << 24) | |
54 | #define TD_CTRL_ACTIVE (1 << 23) | |
55 | #define TD_CTRL_STALL (1 << 22) | |
56 | #define TD_CTRL_BABBLE (1 << 20) | |
57 | #define TD_CTRL_NAK (1 << 19) | |
58 | #define TD_CTRL_TIMEOUT (1 << 18) | |
59 | ||
9159f679 | 60 | #define UHCI_PORT_SUSPEND (1 << 12) |
bb36d470 FB |
61 | #define UHCI_PORT_RESET (1 << 9) |
62 | #define UHCI_PORT_LSDA (1 << 8) | |
9159f679 | 63 | #define UHCI_PORT_RD (1 << 6) |
bb36d470 FB |
64 | #define UHCI_PORT_ENC (1 << 3) |
65 | #define UHCI_PORT_EN (1 << 2) | |
66 | #define UHCI_PORT_CSC (1 << 1) | |
67 | #define UHCI_PORT_CCS (1 << 0) | |
68 | ||
9159f679 GH |
69 | #define UHCI_PORT_READ_ONLY (0x1bb) |
70 | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) | |
71 | ||
bb36d470 FB |
72 | #define FRAME_TIMER_FREQ 1000 |
73 | ||
74 | #define FRAME_MAX_LOOPS 100 | |
75 | ||
76 | #define NB_PORTS 2 | |
77 | ||
54f254f9 | 78 | #ifdef DEBUG |
d0f2c4c6 | 79 | #define DPRINTF printf |
54f254f9 | 80 | |
0bf9e31a | 81 | static const char *pid2str(int pid) |
54f254f9 AL |
82 | { |
83 | switch (pid) { | |
84 | case USB_TOKEN_SETUP: return "SETUP"; | |
85 | case USB_TOKEN_IN: return "IN"; | |
86 | case USB_TOKEN_OUT: return "OUT"; | |
87 | } | |
88 | return "?"; | |
89 | } | |
90 | ||
91 | #else | |
d0f2c4c6 | 92 | #define DPRINTF(...) |
54f254f9 AL |
93 | #endif |
94 | ||
95 | #ifdef DEBUG_DUMP_DATA | |
96 | static void dump_data(const uint8_t *data, int len) | |
97 | { | |
98 | int i; | |
99 | ||
100 | printf("uhci: data: "); | |
101 | for(i = 0; i < len; i++) | |
102 | printf(" %02x", data[i]); | |
103 | printf("\n"); | |
104 | } | |
105 | #else | |
106 | static void dump_data(const uint8_t *data, int len) {} | |
107 | #endif | |
108 | ||
7b5a44c5 GH |
109 | typedef struct UHCIState UHCIState; |
110 | ||
54f254f9 AL |
111 | /* |
112 | * Pending async transaction. | |
113 | * 'packet' must be the first field because completion | |
114 | * handler does "(UHCIAsync *) pkt" cast. | |
115 | */ | |
116 | typedef struct UHCIAsync { | |
117 | USBPacket packet; | |
7b5a44c5 | 118 | UHCIState *uhci; |
ddf6583f | 119 | QTAILQ_ENTRY(UHCIAsync) next; |
54f254f9 AL |
120 | uint32_t td; |
121 | uint32_t token; | |
122 | int8_t valid; | |
8e65b7c0 | 123 | uint8_t isoc; |
54f254f9 AL |
124 | uint8_t done; |
125 | uint8_t buffer[2048]; | |
126 | } UHCIAsync; | |
127 | ||
bb36d470 FB |
128 | typedef struct UHCIPort { |
129 | USBPort port; | |
130 | uint16_t ctrl; | |
bb36d470 FB |
131 | } UHCIPort; |
132 | ||
7b5a44c5 | 133 | struct UHCIState { |
bb36d470 | 134 | PCIDevice dev; |
b2317837 | 135 | USBBus bus; |
bb36d470 FB |
136 | uint16_t cmd; /* cmd register */ |
137 | uint16_t status; | |
138 | uint16_t intr; /* interrupt enable register */ | |
139 | uint16_t frnum; /* frame number */ | |
140 | uint32_t fl_base_addr; /* frame list base address */ | |
141 | uint8_t sof_timing; | |
142 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
8e65b7c0 | 143 | int64_t expire_time; |
bb36d470 FB |
144 | QEMUTimer *frame_timer; |
145 | UHCIPort ports[NB_PORTS]; | |
4d611c9a PB |
146 | |
147 | /* Interrupts that should be raised at the end of the current frame. */ | |
148 | uint32_t pending_int_mask; | |
54f254f9 AL |
149 | |
150 | /* Active packets */ | |
ddf6583f | 151 | QTAILQ_HEAD(,UHCIAsync) async_pending; |
64e58fe5 | 152 | uint8_t num_ports_vmstate; |
7b5a44c5 | 153 | }; |
bb36d470 FB |
154 | |
155 | typedef struct UHCI_TD { | |
156 | uint32_t link; | |
157 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
158 | uint32_t token; | |
159 | uint32_t buffer; | |
160 | } UHCI_TD; | |
161 | ||
162 | typedef struct UHCI_QH { | |
163 | uint32_t link; | |
164 | uint32_t el_link; | |
165 | } UHCI_QH; | |
166 | ||
54f254f9 AL |
167 | static UHCIAsync *uhci_async_alloc(UHCIState *s) |
168 | { | |
169 | UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync)); | |
487414f1 AL |
170 | |
171 | memset(&async->packet, 0, sizeof(async->packet)); | |
7b5a44c5 | 172 | async->uhci = s; |
487414f1 AL |
173 | async->valid = 0; |
174 | async->td = 0; | |
175 | async->token = 0; | |
176 | async->done = 0; | |
8e65b7c0 | 177 | async->isoc = 0; |
54f254f9 AL |
178 | |
179 | return async; | |
180 | } | |
181 | ||
182 | static void uhci_async_free(UHCIState *s, UHCIAsync *async) | |
183 | { | |
184 | qemu_free(async); | |
185 | } | |
186 | ||
187 | static void uhci_async_link(UHCIState *s, UHCIAsync *async) | |
188 | { | |
ddf6583f | 189 | QTAILQ_INSERT_HEAD(&s->async_pending, async, next); |
54f254f9 AL |
190 | } |
191 | ||
192 | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) | |
193 | { | |
ddf6583f | 194 | QTAILQ_REMOVE(&s->async_pending, async, next); |
54f254f9 AL |
195 | } |
196 | ||
197 | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) | |
198 | { | |
d0f2c4c6 | 199 | DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n", |
54f254f9 AL |
200 | async->td, async->token, async->done); |
201 | ||
202 | if (!async->done) | |
203 | usb_cancel_packet(&async->packet); | |
204 | uhci_async_free(s, async); | |
205 | } | |
206 | ||
207 | /* | |
208 | * Mark all outstanding async packets as invalid. | |
209 | * This is used for canceling them when TDs are removed by the HCD. | |
210 | */ | |
211 | static UHCIAsync *uhci_async_validate_begin(UHCIState *s) | |
212 | { | |
ddf6583f | 213 | UHCIAsync *async; |
54f254f9 | 214 | |
ddf6583f | 215 | QTAILQ_FOREACH(async, &s->async_pending, next) { |
54f254f9 | 216 | async->valid--; |
54f254f9 AL |
217 | } |
218 | return NULL; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Cancel async packets that are no longer valid | |
223 | */ | |
224 | static void uhci_async_validate_end(UHCIState *s) | |
225 | { | |
ddf6583f | 226 | UHCIAsync *curr, *n; |
54f254f9 | 227 | |
ddf6583f | 228 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
54f254f9 | 229 | if (curr->valid > 0) { |
54f254f9 AL |
230 | continue; |
231 | } | |
ddf6583f | 232 | uhci_async_unlink(s, curr); |
54f254f9 | 233 | uhci_async_cancel(s, curr); |
54f254f9 AL |
234 | } |
235 | } | |
236 | ||
07771f6f GH |
237 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
238 | { | |
239 | UHCIAsync *curr, *n; | |
240 | ||
241 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { | |
242 | if (curr->packet.owner != dev) { | |
243 | continue; | |
244 | } | |
245 | uhci_async_unlink(s, curr); | |
246 | uhci_async_cancel(s, curr); | |
247 | } | |
248 | } | |
249 | ||
54f254f9 AL |
250 | static void uhci_async_cancel_all(UHCIState *s) |
251 | { | |
ddf6583f | 252 | UHCIAsync *curr, *n; |
54f254f9 | 253 | |
ddf6583f GH |
254 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
255 | uhci_async_unlink(s, curr); | |
54f254f9 | 256 | uhci_async_cancel(s, curr); |
54f254f9 | 257 | } |
54f254f9 AL |
258 | } |
259 | ||
260 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token) | |
261 | { | |
ddf6583f | 262 | UHCIAsync *async; |
e8ee3c72 AJ |
263 | UHCIAsync *match = NULL; |
264 | int count = 0; | |
265 | ||
266 | /* | |
267 | * We're looking for the best match here. ie both td addr and token. | |
268 | * Otherwise we return last good match. ie just token. | |
269 | * It's ok to match just token because it identifies the transaction | |
270 | * rather well, token includes: device addr, endpoint, size, etc. | |
271 | * | |
272 | * Also since we queue async transactions in reverse order by returning | |
273 | * last good match we restores the order. | |
274 | * | |
275 | * It's expected that we wont have a ton of outstanding transactions. | |
276 | * If we ever do we'd want to optimize this algorithm. | |
277 | */ | |
54f254f9 | 278 | |
ddf6583f | 279 | QTAILQ_FOREACH(async, &s->async_pending, next) { |
e8ee3c72 AJ |
280 | if (async->token == token) { |
281 | /* Good match */ | |
282 | match = async; | |
283 | ||
284 | if (async->td == addr) { | |
285 | /* Best match */ | |
286 | break; | |
54f254f9 AL |
287 | } |
288 | } | |
e8ee3c72 | 289 | count++; |
54f254f9 | 290 | } |
e8ee3c72 AJ |
291 | |
292 | if (count > 64) | |
293 | fprintf(stderr, "uhci: warning lots of async transactions\n"); | |
294 | ||
295 | return match; | |
54f254f9 AL |
296 | } |
297 | ||
bb36d470 FB |
298 | static void uhci_update_irq(UHCIState *s) |
299 | { | |
300 | int level; | |
301 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
302 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
303 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
304 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
305 | (s->status & UHCI_STS_HSERR) || | |
306 | (s->status & UHCI_STS_HCPERR)) { | |
307 | level = 1; | |
308 | } else { | |
309 | level = 0; | |
310 | } | |
d537cf6c | 311 | qemu_set_irq(s->dev.irq[3], level); |
bb36d470 FB |
312 | } |
313 | ||
c8075ac3 | 314 | static void uhci_reset(void *opaque) |
bb36d470 | 315 | { |
c8075ac3 | 316 | UHCIState *s = opaque; |
bb36d470 FB |
317 | uint8_t *pci_conf; |
318 | int i; | |
319 | UHCIPort *port; | |
320 | ||
d0f2c4c6 | 321 | DPRINTF("uhci: full reset\n"); |
6f382b5e | 322 | |
bb36d470 FB |
323 | pci_conf = s->dev.config; |
324 | ||
325 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
326 | pci_conf[0x6b] = 0x00; | |
327 | s->cmd = 0; | |
328 | s->status = 0; | |
329 | s->status2 = 0; | |
330 | s->intr = 0; | |
331 | s->fl_base_addr = 0; | |
332 | s->sof_timing = 64; | |
54f254f9 | 333 | |
bb36d470 FB |
334 | for(i = 0; i < NB_PORTS; i++) { |
335 | port = &s->ports[i]; | |
336 | port->ctrl = 0x0080; | |
618c169b GH |
337 | if (port->port.dev) { |
338 | usb_attach(&port->port, port->port.dev); | |
339 | } | |
bb36d470 | 340 | } |
54f254f9 AL |
341 | |
342 | uhci_async_cancel_all(s); | |
bb36d470 FB |
343 | } |
344 | ||
817afc61 | 345 | static void uhci_pre_save(void *opaque) |
b9dc033c AZ |
346 | { |
347 | UHCIState *s = opaque; | |
b9dc033c | 348 | |
6f382b5e | 349 | uhci_async_cancel_all(s); |
b9dc033c AZ |
350 | } |
351 | ||
817afc61 JQ |
352 | static const VMStateDescription vmstate_uhci_port = { |
353 | .name = "uhci port", | |
354 | .version_id = 1, | |
355 | .minimum_version_id = 1, | |
356 | .minimum_version_id_old = 1, | |
357 | .fields = (VMStateField []) { | |
358 | VMSTATE_UINT16(ctrl, UHCIPort), | |
359 | VMSTATE_END_OF_LIST() | |
360 | } | |
361 | }; | |
362 | ||
363 | static const VMStateDescription vmstate_uhci = { | |
364 | .name = "uhci", | |
6881dd5f | 365 | .version_id = 2, |
817afc61 JQ |
366 | .minimum_version_id = 1, |
367 | .minimum_version_id_old = 1, | |
368 | .pre_save = uhci_pre_save, | |
369 | .fields = (VMStateField []) { | |
370 | VMSTATE_PCI_DEVICE(dev, UHCIState), | |
371 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), | |
372 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, | |
373 | vmstate_uhci_port, UHCIPort), | |
374 | VMSTATE_UINT16(cmd, UHCIState), | |
375 | VMSTATE_UINT16(status, UHCIState), | |
376 | VMSTATE_UINT16(intr, UHCIState), | |
377 | VMSTATE_UINT16(frnum, UHCIState), | |
378 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
379 | VMSTATE_UINT8(sof_timing, UHCIState), | |
380 | VMSTATE_UINT8(status2, UHCIState), | |
381 | VMSTATE_TIMER(frame_timer, UHCIState), | |
6881dd5f | 382 | VMSTATE_INT64_V(expire_time, UHCIState, 2), |
817afc61 JQ |
383 | VMSTATE_END_OF_LIST() |
384 | } | |
385 | }; | |
b9dc033c | 386 | |
bb36d470 FB |
387 | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
388 | { | |
389 | UHCIState *s = opaque; | |
3b46e624 | 390 | |
bb36d470 FB |
391 | addr &= 0x1f; |
392 | switch(addr) { | |
393 | case 0x0c: | |
394 | s->sof_timing = val; | |
395 | break; | |
396 | } | |
397 | } | |
398 | ||
399 | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) | |
400 | { | |
401 | UHCIState *s = opaque; | |
402 | uint32_t val; | |
403 | ||
404 | addr &= 0x1f; | |
405 | switch(addr) { | |
406 | case 0x0c: | |
407 | val = s->sof_timing; | |
d80cfb3f | 408 | break; |
bb36d470 FB |
409 | default: |
410 | val = 0xff; | |
411 | break; | |
412 | } | |
413 | return val; | |
414 | } | |
415 | ||
416 | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
417 | { | |
418 | UHCIState *s = opaque; | |
3b46e624 | 419 | |
bb36d470 | 420 | addr &= 0x1f; |
d0f2c4c6 | 421 | DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val); |
54f254f9 | 422 | |
bb36d470 FB |
423 | switch(addr) { |
424 | case 0x00: | |
425 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
426 | /* start frame processing */ | |
74475455 | 427 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
52328140 | 428 | s->status &= ~UHCI_STS_HCHALTED; |
467d409f | 429 | } else if (!(val & UHCI_CMD_RS)) { |
52328140 | 430 | s->status |= UHCI_STS_HCHALTED; |
bb36d470 FB |
431 | } |
432 | if (val & UHCI_CMD_GRESET) { | |
433 | UHCIPort *port; | |
434 | USBDevice *dev; | |
435 | int i; | |
436 | ||
437 | /* send reset on the USB bus */ | |
438 | for(i = 0; i < NB_PORTS; i++) { | |
439 | port = &s->ports[i]; | |
a594cfbf | 440 | dev = port->port.dev; |
bb36d470 | 441 | if (dev) { |
4d611c9a | 442 | usb_send_msg(dev, USB_MSG_RESET); |
bb36d470 FB |
443 | } |
444 | } | |
445 | uhci_reset(s); | |
446 | return; | |
447 | } | |
5e9ab4c4 | 448 | if (val & UHCI_CMD_HCRESET) { |
bb36d470 FB |
449 | uhci_reset(s); |
450 | return; | |
451 | } | |
452 | s->cmd = val; | |
453 | break; | |
454 | case 0x02: | |
455 | s->status &= ~val; | |
456 | /* XXX: the chip spec is not coherent, so we add a hidden | |
457 | register to distinguish between IOC and SPD */ | |
458 | if (val & UHCI_STS_USBINT) | |
459 | s->status2 = 0; | |
460 | uhci_update_irq(s); | |
461 | break; | |
462 | case 0x04: | |
463 | s->intr = val; | |
464 | uhci_update_irq(s); | |
465 | break; | |
466 | case 0x06: | |
467 | if (s->status & UHCI_STS_HCHALTED) | |
468 | s->frnum = val & 0x7ff; | |
469 | break; | |
470 | case 0x10 ... 0x1f: | |
471 | { | |
472 | UHCIPort *port; | |
473 | USBDevice *dev; | |
474 | int n; | |
475 | ||
476 | n = (addr >> 1) & 7; | |
477 | if (n >= NB_PORTS) | |
478 | return; | |
479 | port = &s->ports[n]; | |
a594cfbf | 480 | dev = port->port.dev; |
bb36d470 FB |
481 | if (dev) { |
482 | /* port reset */ | |
5fafdf24 | 483 | if ( (val & UHCI_PORT_RESET) && |
bb36d470 | 484 | !(port->ctrl & UHCI_PORT_RESET) ) { |
4d611c9a | 485 | usb_send_msg(dev, USB_MSG_RESET); |
bb36d470 FB |
486 | } |
487 | } | |
9159f679 GH |
488 | port->ctrl &= UHCI_PORT_READ_ONLY; |
489 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); | |
bb36d470 | 490 | /* some bits are reset when a '1' is written to them */ |
9159f679 | 491 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
bb36d470 FB |
492 | } |
493 | break; | |
494 | } | |
495 | } | |
496 | ||
497 | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) | |
498 | { | |
499 | UHCIState *s = opaque; | |
500 | uint32_t val; | |
501 | ||
502 | addr &= 0x1f; | |
503 | switch(addr) { | |
504 | case 0x00: | |
505 | val = s->cmd; | |
506 | break; | |
507 | case 0x02: | |
508 | val = s->status; | |
509 | break; | |
510 | case 0x04: | |
511 | val = s->intr; | |
512 | break; | |
513 | case 0x06: | |
514 | val = s->frnum; | |
515 | break; | |
516 | case 0x10 ... 0x1f: | |
517 | { | |
518 | UHCIPort *port; | |
519 | int n; | |
520 | n = (addr >> 1) & 7; | |
5fafdf24 | 521 | if (n >= NB_PORTS) |
bb36d470 FB |
522 | goto read_default; |
523 | port = &s->ports[n]; | |
524 | val = port->ctrl; | |
525 | } | |
526 | break; | |
527 | default: | |
528 | read_default: | |
529 | val = 0xff7f; /* disabled port */ | |
530 | break; | |
531 | } | |
54f254f9 | 532 | |
d0f2c4c6 | 533 | DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val); |
54f254f9 | 534 | |
bb36d470 FB |
535 | return val; |
536 | } | |
537 | ||
538 | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
539 | { | |
540 | UHCIState *s = opaque; | |
541 | ||
542 | addr &= 0x1f; | |
d0f2c4c6 | 543 | DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val); |
54f254f9 | 544 | |
bb36d470 FB |
545 | switch(addr) { |
546 | case 0x08: | |
547 | s->fl_base_addr = val & ~0xfff; | |
548 | break; | |
549 | } | |
550 | } | |
551 | ||
552 | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) | |
553 | { | |
554 | UHCIState *s = opaque; | |
555 | uint32_t val; | |
556 | ||
557 | addr &= 0x1f; | |
558 | switch(addr) { | |
559 | case 0x08: | |
560 | val = s->fl_base_addr; | |
561 | break; | |
562 | default: | |
563 | val = 0xffffffff; | |
564 | break; | |
565 | } | |
566 | return val; | |
567 | } | |
568 | ||
96217e31 TS |
569 | /* signal resume if controller suspended */ |
570 | static void uhci_resume (void *opaque) | |
571 | { | |
572 | UHCIState *s = (UHCIState *)opaque; | |
573 | ||
574 | if (!s) | |
575 | return; | |
576 | ||
577 | if (s->cmd & UHCI_CMD_EGSM) { | |
578 | s->cmd |= UHCI_CMD_FGR; | |
579 | s->status |= UHCI_STS_RD; | |
580 | uhci_update_irq(s); | |
581 | } | |
582 | } | |
583 | ||
618c169b | 584 | static void uhci_attach(USBPort *port1) |
bb36d470 FB |
585 | { |
586 | UHCIState *s = port1->opaque; | |
587 | UHCIPort *port = &s->ports[port1->index]; | |
588 | ||
618c169b GH |
589 | /* set connect status */ |
590 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
61064870 | 591 | |
618c169b GH |
592 | /* update speed */ |
593 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
594 | port->ctrl |= UHCI_PORT_LSDA; | |
bb36d470 | 595 | } else { |
618c169b GH |
596 | port->ctrl &= ~UHCI_PORT_LSDA; |
597 | } | |
96217e31 | 598 | |
618c169b GH |
599 | uhci_resume(s); |
600 | } | |
96217e31 | 601 | |
618c169b GH |
602 | static void uhci_detach(USBPort *port1) |
603 | { | |
604 | UHCIState *s = port1->opaque; | |
605 | UHCIPort *port = &s->ports[port1->index]; | |
606 | ||
607 | /* set connect status */ | |
608 | if (port->ctrl & UHCI_PORT_CCS) { | |
609 | port->ctrl &= ~UHCI_PORT_CCS; | |
610 | port->ctrl |= UHCI_PORT_CSC; | |
bb36d470 | 611 | } |
618c169b GH |
612 | /* disable port */ |
613 | if (port->ctrl & UHCI_PORT_EN) { | |
614 | port->ctrl &= ~UHCI_PORT_EN; | |
615 | port->ctrl |= UHCI_PORT_ENC; | |
616 | } | |
617 | ||
618 | uhci_resume(s); | |
bb36d470 FB |
619 | } |
620 | ||
9159f679 GH |
621 | static void uhci_wakeup(USBDevice *dev) |
622 | { | |
623 | USBBus *bus = usb_bus_from_device(dev); | |
624 | UHCIState *s = container_of(bus, UHCIState, bus); | |
625 | UHCIPort *port = s->ports + dev->port->index; | |
626 | ||
627 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
628 | port->ctrl |= UHCI_PORT_RD; | |
629 | uhci_resume(s); | |
630 | } | |
631 | } | |
632 | ||
4d611c9a | 633 | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
bb36d470 | 634 | { |
bb36d470 FB |
635 | int i, ret; |
636 | ||
d0f2c4c6 | 637 | DPRINTF("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n", |
54f254f9 | 638 | pid2str(p->pid), p->devaddr, p->devep, p->len); |
5d808245 | 639 | if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP) |
54f254f9 AL |
640 | dump_data(p->data, p->len); |
641 | ||
642 | ret = USB_RET_NODEV; | |
643 | for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { | |
644 | UHCIPort *port = &s->ports[i]; | |
645 | USBDevice *dev = port->port.dev; | |
646 | ||
647 | if (dev && (port->ctrl & UHCI_PORT_EN)) | |
53aa8c0e | 648 | ret = usb_handle_packet(dev, p); |
bb36d470 | 649 | } |
54f254f9 | 650 | |
d0f2c4c6 | 651 | DPRINTF("uhci: packet exit. ret %d len %d\n", ret, p->len); |
54f254f9 AL |
652 | if (p->pid == USB_TOKEN_IN && ret > 0) |
653 | dump_data(p->data, ret); | |
654 | ||
655 | return ret; | |
bb36d470 FB |
656 | } |
657 | ||
13a9a0d3 | 658 | static void uhci_async_complete(USBDevice *dev, USBPacket *packet); |
54f254f9 | 659 | static void uhci_process_frame(UHCIState *s); |
4d611c9a | 660 | |
bb36d470 FB |
661 | /* return -1 if fatal error (frame must be stopped) |
662 | 0 if TD successful | |
663 | 1 if TD unsuccessful or inactive | |
664 | */ | |
54f254f9 | 665 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
bb36d470 | 666 | { |
54f254f9 | 667 | int len = 0, max_len, err, ret; |
bb36d470 | 668 | uint8_t pid; |
bb36d470 | 669 | |
54f254f9 AL |
670 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
671 | pid = td->token & 0xff; | |
672 | ||
673 | ret = async->packet.len; | |
674 | ||
54f254f9 AL |
675 | if (td->ctrl & TD_CTRL_IOS) |
676 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
bb36d470 | 677 | |
54f254f9 AL |
678 | if (ret < 0) |
679 | goto out; | |
b9dc033c | 680 | |
54f254f9 AL |
681 | len = async->packet.len; |
682 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); | |
683 | ||
684 | /* The NAK bit may have been set by a previous frame, so clear it | |
685 | here. The docs are somewhat unclear, but win2k relies on this | |
686 | behavior. */ | |
687 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
5bd2c0d7 PB |
688 | if (td->ctrl & TD_CTRL_IOC) |
689 | *int_mask |= 0x01; | |
54f254f9 AL |
690 | |
691 | if (pid == USB_TOKEN_IN) { | |
692 | if (len > max_len) { | |
54f254f9 AL |
693 | ret = USB_RET_BABBLE; |
694 | goto out; | |
4d611c9a | 695 | } |
b9dc033c | 696 | |
54f254f9 AL |
697 | if (len > 0) { |
698 | /* write the data back */ | |
699 | cpu_physical_memory_write(td->buffer, async->buffer, len); | |
700 | } | |
701 | ||
702 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { | |
bb36d470 FB |
703 | *int_mask |= 0x02; |
704 | /* short packet: do not update QH */ | |
d0f2c4c6 | 705 | DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token); |
bb36d470 | 706 | return 1; |
bb36d470 | 707 | } |
54f254f9 AL |
708 | } |
709 | ||
710 | /* success */ | |
711 | return 0; | |
712 | ||
713 | out: | |
714 | switch(ret) { | |
715 | case USB_RET_STALL: | |
716 | td->ctrl |= TD_CTRL_STALL; | |
717 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a JV |
718 | s->status |= UHCI_STS_USBERR; |
719 | uhci_update_irq(s); | |
54f254f9 AL |
720 | return 1; |
721 | ||
722 | case USB_RET_BABBLE: | |
723 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
724 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a JV |
725 | s->status |= UHCI_STS_USBERR; |
726 | uhci_update_irq(s); | |
54f254f9 AL |
727 | /* frame interrupted */ |
728 | return -1; | |
729 | ||
730 | case USB_RET_NAK: | |
731 | td->ctrl |= TD_CTRL_NAK; | |
732 | if (pid == USB_TOKEN_SETUP) | |
733 | break; | |
734 | return 1; | |
735 | ||
736 | case USB_RET_NODEV: | |
737 | default: | |
738 | break; | |
739 | } | |
740 | ||
741 | /* Retry the TD if error count is not zero */ | |
742 | ||
743 | td->ctrl |= TD_CTRL_TIMEOUT; | |
744 | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; | |
745 | if (err != 0) { | |
746 | err--; | |
747 | if (err == 0) { | |
bb36d470 | 748 | td->ctrl &= ~TD_CTRL_ACTIVE; |
54f254f9 | 749 | s->status |= UHCI_STS_USBERR; |
5bd2c0d7 PB |
750 | if (td->ctrl & TD_CTRL_IOC) |
751 | *int_mask |= 0x01; | |
54f254f9 | 752 | uhci_update_irq(s); |
bb36d470 FB |
753 | } |
754 | } | |
54f254f9 AL |
755 | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | |
756 | (err << TD_CTRL_ERROR_SHIFT); | |
757 | return 1; | |
bb36d470 FB |
758 | } |
759 | ||
54f254f9 AL |
760 | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
761 | { | |
762 | UHCIAsync *async; | |
5d808245 | 763 | int len = 0, max_len; |
8e65b7c0 DA |
764 | uint8_t pid, isoc; |
765 | uint32_t token; | |
54f254f9 AL |
766 | |
767 | /* Is active ? */ | |
768 | if (!(td->ctrl & TD_CTRL_ACTIVE)) | |
769 | return 1; | |
770 | ||
8e65b7c0 DA |
771 | /* token field is not unique for isochronous requests, |
772 | * so use the destination buffer | |
773 | */ | |
774 | if (td->ctrl & TD_CTRL_IOS) { | |
775 | token = td->buffer; | |
776 | isoc = 1; | |
777 | } else { | |
778 | token = td->token; | |
779 | isoc = 0; | |
780 | } | |
781 | ||
782 | async = uhci_async_find_td(s, addr, token); | |
54f254f9 AL |
783 | if (async) { |
784 | /* Already submitted */ | |
a145ea51 | 785 | async->valid = 32; |
54f254f9 AL |
786 | |
787 | if (!async->done) | |
788 | return 1; | |
789 | ||
790 | uhci_async_unlink(s, async); | |
791 | goto done; | |
792 | } | |
793 | ||
794 | /* Allocate new packet */ | |
795 | async = uhci_async_alloc(s); | |
796 | if (!async) | |
797 | return 1; | |
798 | ||
8e65b7c0 DA |
799 | /* valid needs to be large enough to handle 10 frame delay |
800 | * for initial isochronous requests | |
801 | */ | |
802 | async->valid = 32; | |
54f254f9 | 803 | async->td = addr; |
8e65b7c0 DA |
804 | async->token = token; |
805 | async->isoc = isoc; | |
54f254f9 AL |
806 | |
807 | max_len = ((td->token >> 21) + 1) & 0x7ff; | |
808 | pid = td->token & 0xff; | |
809 | ||
810 | async->packet.pid = pid; | |
811 | async->packet.devaddr = (td->token >> 8) & 0x7f; | |
812 | async->packet.devep = (td->token >> 15) & 0xf; | |
813 | async->packet.data = async->buffer; | |
814 | async->packet.len = max_len; | |
54f254f9 AL |
815 | |
816 | switch(pid) { | |
817 | case USB_TOKEN_OUT: | |
818 | case USB_TOKEN_SETUP: | |
819 | cpu_physical_memory_read(td->buffer, async->buffer, max_len); | |
5d808245 AJ |
820 | len = uhci_broadcast_packet(s, &async->packet); |
821 | if (len >= 0) | |
822 | len = max_len; | |
54f254f9 AL |
823 | break; |
824 | ||
825 | case USB_TOKEN_IN: | |
5d808245 | 826 | len = uhci_broadcast_packet(s, &async->packet); |
54f254f9 AL |
827 | break; |
828 | ||
829 | default: | |
830 | /* invalid pid : frame interrupted */ | |
831 | uhci_async_free(s, async); | |
832 | s->status |= UHCI_STS_HCPERR; | |
833 | uhci_update_irq(s); | |
834 | return -1; | |
835 | } | |
836 | ||
5d808245 | 837 | if (len == USB_RET_ASYNC) { |
54f254f9 AL |
838 | uhci_async_link(s, async); |
839 | return 2; | |
840 | } | |
841 | ||
5d808245 | 842 | async->packet.len = len; |
54f254f9 AL |
843 | |
844 | done: | |
5d808245 | 845 | len = uhci_complete_td(s, td, async, int_mask); |
54f254f9 | 846 | uhci_async_free(s, async); |
5d808245 | 847 | return len; |
54f254f9 AL |
848 | } |
849 | ||
13a9a0d3 | 850 | static void uhci_async_complete(USBDevice *dev, USBPacket *packet) |
4d611c9a | 851 | { |
7b5a44c5 GH |
852 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
853 | UHCIState *s = async->uhci; | |
54f254f9 | 854 | |
d0f2c4c6 | 855 | DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token); |
54f254f9 | 856 | |
8e65b7c0 DA |
857 | if (async->isoc) { |
858 | UHCI_TD td; | |
859 | uint32_t link = async->td; | |
860 | uint32_t int_mask = 0, val; | |
d4c4e6fd | 861 | |
8e65b7c0 DA |
862 | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
863 | le32_to_cpus(&td.link); | |
864 | le32_to_cpus(&td.ctrl); | |
865 | le32_to_cpus(&td.token); | |
866 | le32_to_cpus(&td.buffer); | |
867 | ||
868 | uhci_async_unlink(s, async); | |
d4c4e6fd | 869 | uhci_complete_td(s, &td, async, &int_mask); |
8e65b7c0 | 870 | s->pending_int_mask |= int_mask; |
54f254f9 | 871 | |
8e65b7c0 DA |
872 | /* update the status bits of the TD */ |
873 | val = cpu_to_le32(td.ctrl); | |
874 | cpu_physical_memory_write((link & ~0xf) + 4, | |
875 | (const uint8_t *)&val, sizeof(val)); | |
876 | uhci_async_free(s, async); | |
877 | } else { | |
878 | async->done = 1; | |
879 | uhci_process_frame(s); | |
880 | } | |
54f254f9 AL |
881 | } |
882 | ||
883 | static int is_valid(uint32_t link) | |
884 | { | |
885 | return (link & 1) == 0; | |
886 | } | |
887 | ||
888 | static int is_qh(uint32_t link) | |
889 | { | |
890 | return (link & 2) != 0; | |
891 | } | |
892 | ||
893 | static int depth_first(uint32_t link) | |
894 | { | |
895 | return (link & 4) != 0; | |
896 | } | |
897 | ||
898 | /* QH DB used for detecting QH loops */ | |
899 | #define UHCI_MAX_QUEUES 128 | |
900 | typedef struct { | |
901 | uint32_t addr[UHCI_MAX_QUEUES]; | |
902 | int count; | |
903 | } QhDb; | |
904 | ||
905 | static void qhdb_reset(QhDb *db) | |
906 | { | |
907 | db->count = 0; | |
908 | } | |
909 | ||
910 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
911 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
912 | { | |
913 | int i; | |
914 | for (i = 0; i < db->count; i++) | |
915 | if (db->addr[i] == addr) | |
916 | return 1; | |
917 | ||
918 | if (db->count >= UHCI_MAX_QUEUES) | |
919 | return 1; | |
920 | ||
921 | db->addr[db->count++] = addr; | |
922 | return 0; | |
923 | } | |
924 | ||
925 | static void uhci_process_frame(UHCIState *s) | |
926 | { | |
927 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
928 | uint32_t curr_qh; | |
929 | int cnt, ret; | |
4d611c9a | 930 | UHCI_TD td; |
54f254f9 AL |
931 | UHCI_QH qh; |
932 | QhDb qhdb; | |
4d611c9a | 933 | |
54f254f9 AL |
934 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
935 | ||
d0f2c4c6 | 936 | DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr); |
54f254f9 AL |
937 | |
938 | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4); | |
939 | le32_to_cpus(&link); | |
b9dc033c | 940 | |
54f254f9 AL |
941 | int_mask = 0; |
942 | curr_qh = 0; | |
943 | ||
944 | qhdb_reset(&qhdb); | |
945 | ||
946 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
947 | if (is_qh(link)) { | |
948 | /* QH */ | |
949 | ||
950 | if (qhdb_insert(&qhdb, link)) { | |
951 | /* | |
952 | * We're going in circles. Which is not a bug because | |
953 | * HCD is allowed to do that as part of the BW management. | |
954 | * In our case though it makes no sense to spin here. Sync transations | |
955 | * are already done, and async completion handler will re-process | |
956 | * the frame when something is ready. | |
957 | */ | |
d0f2c4c6 | 958 | DPRINTF("uhci: detected loop. qh 0x%x\n", link); |
54f254f9 AL |
959 | break; |
960 | } | |
961 | ||
962 | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); | |
963 | le32_to_cpus(&qh.link); | |
964 | le32_to_cpus(&qh.el_link); | |
965 | ||
d0f2c4c6 | 966 | DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n", |
54f254f9 AL |
967 | link, qh.link, qh.el_link); |
968 | ||
969 | if (!is_valid(qh.el_link)) { | |
970 | /* QH w/o elements */ | |
971 | curr_qh = 0; | |
972 | link = qh.link; | |
973 | } else { | |
974 | /* QH with elements */ | |
975 | curr_qh = link; | |
976 | link = qh.el_link; | |
977 | } | |
978 | continue; | |
979 | } | |
980 | ||
981 | /* TD */ | |
982 | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); | |
b9dc033c AZ |
983 | le32_to_cpus(&td.link); |
984 | le32_to_cpus(&td.ctrl); | |
985 | le32_to_cpus(&td.token); | |
986 | le32_to_cpus(&td.buffer); | |
b9dc033c | 987 | |
d0f2c4c6 | 988 | DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
989 | link, td.link, td.ctrl, td.token, curr_qh); |
990 | ||
991 | old_td_ctrl = td.ctrl; | |
992 | ret = uhci_handle_td(s, link, &td, &int_mask); | |
b9dc033c | 993 | if (old_td_ctrl != td.ctrl) { |
54f254f9 | 994 | /* update the status bits of the TD */ |
b9dc033c AZ |
995 | val = cpu_to_le32(td.ctrl); |
996 | cpu_physical_memory_write((link & ~0xf) + 4, | |
54f254f9 | 997 | (const uint8_t *)&val, sizeof(val)); |
b9dc033c | 998 | } |
54f254f9 AL |
999 | |
1000 | if (ret < 0) { | |
1001 | /* interrupted frame */ | |
1002 | break; | |
b9dc033c | 1003 | } |
b9dc033c | 1004 | |
54f254f9 | 1005 | if (ret == 2 || ret == 1) { |
d0f2c4c6 | 1006 | DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1007 | link, ret == 2 ? "pend" : "skip", |
1008 | td.link, td.ctrl, td.token, curr_qh); | |
b9dc033c | 1009 | |
54f254f9 AL |
1010 | link = curr_qh ? qh.link : td.link; |
1011 | continue; | |
4d611c9a | 1012 | } |
54f254f9 AL |
1013 | |
1014 | /* completed TD */ | |
1015 | ||
d0f2c4c6 | 1016 | DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1017 | link, td.link, td.ctrl, td.token, curr_qh); |
1018 | ||
1019 | link = td.link; | |
1020 | ||
1021 | if (curr_qh) { | |
1022 | /* update QH element link */ | |
1023 | qh.el_link = link; | |
4d611c9a | 1024 | val = cpu_to_le32(qh.el_link); |
54f254f9 AL |
1025 | cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1026 | (const uint8_t *)&val, sizeof(val)); | |
1027 | ||
1028 | if (!depth_first(link)) { | |
1029 | /* done with this QH */ | |
1030 | ||
d0f2c4c6 | 1031 | DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n", |
54f254f9 AL |
1032 | curr_qh, qh.link, qh.el_link); |
1033 | ||
1034 | curr_qh = 0; | |
1035 | link = qh.link; | |
1036 | } | |
4d611c9a | 1037 | } |
54f254f9 AL |
1038 | |
1039 | /* go to the next entry */ | |
4d611c9a | 1040 | } |
54f254f9 | 1041 | |
8e65b7c0 | 1042 | s->pending_int_mask |= int_mask; |
4d611c9a PB |
1043 | } |
1044 | ||
bb36d470 FB |
1045 | static void uhci_frame_timer(void *opaque) |
1046 | { | |
1047 | UHCIState *s = opaque; | |
8e65b7c0 DA |
1048 | |
1049 | /* prepare the timer for the next frame */ | |
1050 | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
bb36d470 FB |
1051 | |
1052 | if (!(s->cmd & UHCI_CMD_RS)) { | |
54f254f9 | 1053 | /* Full stop */ |
bb36d470 | 1054 | qemu_del_timer(s->frame_timer); |
52328140 FB |
1055 | /* set hchalted bit in status - UHCI11D 2.1.2 */ |
1056 | s->status |= UHCI_STS_HCHALTED; | |
6f382b5e | 1057 | |
d0f2c4c6 | 1058 | DPRINTF("uhci: halted\n"); |
bb36d470 FB |
1059 | return; |
1060 | } | |
54f254f9 AL |
1061 | |
1062 | /* Complete the previous frame */ | |
4d611c9a PB |
1063 | if (s->pending_int_mask) { |
1064 | s->status2 |= s->pending_int_mask; | |
54f254f9 | 1065 | s->status |= UHCI_STS_USBINT; |
4d611c9a PB |
1066 | uhci_update_irq(s); |
1067 | } | |
8e65b7c0 | 1068 | s->pending_int_mask = 0; |
b9dc033c | 1069 | |
54f254f9 AL |
1070 | /* Start new frame */ |
1071 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1072 | ||
d0f2c4c6 | 1073 | DPRINTF("uhci: new frame #%u\n" , s->frnum); |
54f254f9 AL |
1074 | |
1075 | uhci_async_validate_begin(s); | |
1076 | ||
1077 | uhci_process_frame(s); | |
1078 | ||
1079 | uhci_async_validate_end(s); | |
b9dc033c | 1080 | |
8e65b7c0 | 1081 | qemu_mod_timer(s->frame_timer, s->expire_time); |
bb36d470 FB |
1082 | } |
1083 | ||
5fafdf24 | 1084 | static void uhci_map(PCIDevice *pci_dev, int region_num, |
6e355d90 | 1085 | pcibus_t addr, pcibus_t size, int type) |
bb36d470 FB |
1086 | { |
1087 | UHCIState *s = (UHCIState *)pci_dev; | |
1088 | ||
1089 | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); | |
1090 | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); | |
1091 | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); | |
1092 | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); | |
1093 | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); | |
1094 | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); | |
1095 | } | |
1096 | ||
07771f6f GH |
1097 | static void uhci_device_destroy(USBBus *bus, USBDevice *dev) |
1098 | { | |
1099 | UHCIState *s = container_of(bus, UHCIState, bus); | |
1100 | ||
1101 | uhci_async_cancel_device(s, dev); | |
1102 | } | |
1103 | ||
0d86d2be GH |
1104 | static USBPortOps uhci_port_ops = { |
1105 | .attach = uhci_attach, | |
618c169b | 1106 | .detach = uhci_detach, |
9159f679 | 1107 | .wakeup = uhci_wakeup, |
13a9a0d3 | 1108 | .complete = uhci_async_complete, |
0d86d2be GH |
1109 | }; |
1110 | ||
07771f6f GH |
1111 | static USBBusOps uhci_bus_ops = { |
1112 | .device_destroy = uhci_device_destroy, | |
1113 | }; | |
1114 | ||
6cf9b6f1 | 1115 | static int usb_uhci_common_initfn(UHCIState *s) |
bb36d470 | 1116 | { |
6cf9b6f1 | 1117 | uint8_t *pci_conf = s->dev.config; |
bb36d470 FB |
1118 | int i; |
1119 | ||
db579e9e MT |
1120 | pci_conf[PCI_REVISION_ID] = 0x01; // revision number |
1121 | pci_conf[PCI_CLASS_PROG] = 0x00; | |
173a543b | 1122 | pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB); |
db579e9e MT |
1123 | /* TODO: reset value should be 0. */ |
1124 | pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3 | |
e59d33a7 | 1125 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number |
3b46e624 | 1126 | |
07771f6f | 1127 | usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); |
bb36d470 | 1128 | for(i = 0; i < NB_PORTS; i++) { |
ace1318b | 1129 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, |
843d4e0c | 1130 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
c7a2196a | 1131 | usb_port_location(&s->ports[i].port, NULL, i+1); |
bb36d470 | 1132 | } |
74475455 PB |
1133 | s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
1134 | s->expire_time = qemu_get_clock_ns(vm_clock) + | |
8e65b7c0 | 1135 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
64e58fe5 | 1136 | s->num_ports_vmstate = NB_PORTS; |
ddf6583f | 1137 | QTAILQ_INIT(&s->async_pending); |
bb36d470 | 1138 | |
a08d4367 | 1139 | qemu_register_reset(uhci_reset, s); |
bb36d470 | 1140 | |
38ca0f6d PB |
1141 | /* Use region 4 for consistency with real hardware. BSD guests seem |
1142 | to rely on this. */ | |
28c2c264 | 1143 | pci_register_bar(&s->dev, 4, 0x20, |
0392a017 | 1144 | PCI_BASE_ADDRESS_SPACE_IO, uhci_map); |
6f382b5e | 1145 | |
6cf9b6f1 | 1146 | return 0; |
bb36d470 | 1147 | } |
afcc3cdf | 1148 | |
6cf9b6f1 | 1149 | static int usb_uhci_piix3_initfn(PCIDevice *dev) |
afcc3cdf | 1150 | { |
6cf9b6f1 GH |
1151 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1152 | uint8_t *pci_conf = s->dev.config; | |
1153 | ||
1154 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); | |
1155 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); | |
1156 | return usb_uhci_common_initfn(s); | |
1157 | } | |
1158 | ||
1159 | static int usb_uhci_piix4_initfn(PCIDevice *dev) | |
1160 | { | |
1161 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1162 | uint8_t *pci_conf = s->dev.config; | |
afcc3cdf | 1163 | |
deb54399 AL |
1164 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
1165 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); | |
6cf9b6f1 GH |
1166 | return usb_uhci_common_initfn(s); |
1167 | } | |
afcc3cdf | 1168 | |
30235a54 HC |
1169 | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1170 | { | |
1171 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1172 | uint8_t *pci_conf = s->dev.config; | |
1173 | ||
1174 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); | |
1175 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI); | |
1176 | ||
1177 | /* USB misc control 1/2 */ | |
1178 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1179 | /* PM capability */ | |
1180 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1181 | /* USB legacy support */ | |
1182 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1183 | ||
1184 | return usb_uhci_common_initfn(s); | |
1185 | } | |
1186 | ||
6cf9b6f1 GH |
1187 | static PCIDeviceInfo uhci_info[] = { |
1188 | { | |
556cd098 | 1189 | .qdev.name = "piix3-usb-uhci", |
6cf9b6f1 | 1190 | .qdev.size = sizeof(UHCIState), |
be73cfe2 | 1191 | .qdev.vmsd = &vmstate_uhci, |
6cf9b6f1 GH |
1192 | .init = usb_uhci_piix3_initfn, |
1193 | },{ | |
556cd098 | 1194 | .qdev.name = "piix4-usb-uhci", |
6cf9b6f1 | 1195 | .qdev.size = sizeof(UHCIState), |
be73cfe2 | 1196 | .qdev.vmsd = &vmstate_uhci, |
6cf9b6f1 | 1197 | .init = usb_uhci_piix4_initfn, |
30235a54 HC |
1198 | },{ |
1199 | .qdev.name = "vt82c686b-usb-uhci", | |
1200 | .qdev.size = sizeof(UHCIState), | |
1201 | .qdev.vmsd = &vmstate_uhci, | |
1202 | .init = usb_uhci_vt82c686b_initfn, | |
6cf9b6f1 GH |
1203 | },{ |
1204 | /* end of list */ | |
afcc3cdf | 1205 | } |
6cf9b6f1 | 1206 | }; |
afcc3cdf | 1207 | |
6cf9b6f1 GH |
1208 | static void uhci_register(void) |
1209 | { | |
1210 | pci_qdev_register_many(uhci_info); | |
1211 | } | |
1212 | device_init(uhci_register); | |
afcc3cdf | 1213 | |
6cf9b6f1 GH |
1214 | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1215 | { | |
556cd098 | 1216 | pci_create_simple(bus, devfn, "piix3-usb-uhci"); |
6cf9b6f1 | 1217 | } |
54f254f9 | 1218 | |
6cf9b6f1 GH |
1219 | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1220 | { | |
556cd098 | 1221 | pci_create_simple(bus, devfn, "piix4-usb-uhci"); |
afcc3cdf | 1222 | } |
30235a54 HC |
1223 | |
1224 | void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) | |
1225 | { | |
1226 | pci_create_simple(bus, devfn, "vt82c686b-usb-uhci"); | |
1227 | } |