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Commit | Line | Data |
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bb36d470 FB |
1 | /* |
2 | * USB UHCI controller emulation | |
5fafdf24 | 3 | * |
bb36d470 | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
54f254f9 AL |
6 | * Copyright (c) 2008 Max Krasnyansky |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
bb36d470 FB |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
87ecb68b PB |
28 | #include "hw.h" |
29 | #include "usb.h" | |
30 | #include "pci.h" | |
31 | #include "qemu-timer.h" | |
18e08a55 | 32 | #include "usb-uhci.h" |
bb36d470 FB |
33 | |
34 | //#define DEBUG | |
54f254f9 | 35 | //#define DEBUG_DUMP_DATA |
bb36d470 | 36 | |
96217e31 TS |
37 | #define UHCI_CMD_FGR (1 << 4) |
38 | #define UHCI_CMD_EGSM (1 << 3) | |
bb36d470 FB |
39 | #define UHCI_CMD_GRESET (1 << 2) |
40 | #define UHCI_CMD_HCRESET (1 << 1) | |
41 | #define UHCI_CMD_RS (1 << 0) | |
42 | ||
43 | #define UHCI_STS_HCHALTED (1 << 5) | |
44 | #define UHCI_STS_HCPERR (1 << 4) | |
45 | #define UHCI_STS_HSERR (1 << 3) | |
46 | #define UHCI_STS_RD (1 << 2) | |
47 | #define UHCI_STS_USBERR (1 << 1) | |
48 | #define UHCI_STS_USBINT (1 << 0) | |
49 | ||
50 | #define TD_CTRL_SPD (1 << 29) | |
51 | #define TD_CTRL_ERROR_SHIFT 27 | |
52 | #define TD_CTRL_IOS (1 << 25) | |
53 | #define TD_CTRL_IOC (1 << 24) | |
54 | #define TD_CTRL_ACTIVE (1 << 23) | |
55 | #define TD_CTRL_STALL (1 << 22) | |
56 | #define TD_CTRL_BABBLE (1 << 20) | |
57 | #define TD_CTRL_NAK (1 << 19) | |
58 | #define TD_CTRL_TIMEOUT (1 << 18) | |
59 | ||
9159f679 | 60 | #define UHCI_PORT_SUSPEND (1 << 12) |
bb36d470 FB |
61 | #define UHCI_PORT_RESET (1 << 9) |
62 | #define UHCI_PORT_LSDA (1 << 8) | |
9159f679 | 63 | #define UHCI_PORT_RD (1 << 6) |
bb36d470 FB |
64 | #define UHCI_PORT_ENC (1 << 3) |
65 | #define UHCI_PORT_EN (1 << 2) | |
66 | #define UHCI_PORT_CSC (1 << 1) | |
67 | #define UHCI_PORT_CCS (1 << 0) | |
68 | ||
9159f679 GH |
69 | #define UHCI_PORT_READ_ONLY (0x1bb) |
70 | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) | |
71 | ||
bb36d470 FB |
72 | #define FRAME_TIMER_FREQ 1000 |
73 | ||
74 | #define FRAME_MAX_LOOPS 100 | |
75 | ||
76 | #define NB_PORTS 2 | |
77 | ||
54f254f9 | 78 | #ifdef DEBUG |
d0f2c4c6 | 79 | #define DPRINTF printf |
54f254f9 | 80 | |
0bf9e31a | 81 | static const char *pid2str(int pid) |
54f254f9 AL |
82 | { |
83 | switch (pid) { | |
84 | case USB_TOKEN_SETUP: return "SETUP"; | |
85 | case USB_TOKEN_IN: return "IN"; | |
86 | case USB_TOKEN_OUT: return "OUT"; | |
87 | } | |
88 | return "?"; | |
89 | } | |
90 | ||
91 | #else | |
d0f2c4c6 | 92 | #define DPRINTF(...) |
54f254f9 AL |
93 | #endif |
94 | ||
95 | #ifdef DEBUG_DUMP_DATA | |
96 | static void dump_data(const uint8_t *data, int len) | |
97 | { | |
98 | int i; | |
99 | ||
100 | printf("uhci: data: "); | |
101 | for(i = 0; i < len; i++) | |
102 | printf(" %02x", data[i]); | |
103 | printf("\n"); | |
104 | } | |
105 | #else | |
106 | static void dump_data(const uint8_t *data, int len) {} | |
107 | #endif | |
108 | ||
7b5a44c5 GH |
109 | typedef struct UHCIState UHCIState; |
110 | ||
54f254f9 AL |
111 | /* |
112 | * Pending async transaction. | |
113 | * 'packet' must be the first field because completion | |
114 | * handler does "(UHCIAsync *) pkt" cast. | |
115 | */ | |
116 | typedef struct UHCIAsync { | |
117 | USBPacket packet; | |
7b5a44c5 | 118 | UHCIState *uhci; |
ddf6583f | 119 | QTAILQ_ENTRY(UHCIAsync) next; |
54f254f9 AL |
120 | uint32_t td; |
121 | uint32_t token; | |
122 | int8_t valid; | |
8e65b7c0 | 123 | uint8_t isoc; |
54f254f9 AL |
124 | uint8_t done; |
125 | uint8_t buffer[2048]; | |
126 | } UHCIAsync; | |
127 | ||
bb36d470 FB |
128 | typedef struct UHCIPort { |
129 | USBPort port; | |
130 | uint16_t ctrl; | |
bb36d470 FB |
131 | } UHCIPort; |
132 | ||
7b5a44c5 | 133 | struct UHCIState { |
bb36d470 | 134 | PCIDevice dev; |
35e4977f | 135 | USBBus bus; /* Note unused when we're a companion controller */ |
bb36d470 FB |
136 | uint16_t cmd; /* cmd register */ |
137 | uint16_t status; | |
138 | uint16_t intr; /* interrupt enable register */ | |
139 | uint16_t frnum; /* frame number */ | |
140 | uint32_t fl_base_addr; /* frame list base address */ | |
141 | uint8_t sof_timing; | |
142 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
8e65b7c0 | 143 | int64_t expire_time; |
bb36d470 FB |
144 | QEMUTimer *frame_timer; |
145 | UHCIPort ports[NB_PORTS]; | |
4d611c9a PB |
146 | |
147 | /* Interrupts that should be raised at the end of the current frame. */ | |
148 | uint32_t pending_int_mask; | |
54f254f9 AL |
149 | |
150 | /* Active packets */ | |
ddf6583f | 151 | QTAILQ_HEAD(,UHCIAsync) async_pending; |
64e58fe5 | 152 | uint8_t num_ports_vmstate; |
35e4977f HG |
153 | |
154 | /* Properties */ | |
155 | char *masterbus; | |
156 | uint32_t firstport; | |
7b5a44c5 | 157 | }; |
bb36d470 FB |
158 | |
159 | typedef struct UHCI_TD { | |
160 | uint32_t link; | |
161 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
162 | uint32_t token; | |
163 | uint32_t buffer; | |
164 | } UHCI_TD; | |
165 | ||
166 | typedef struct UHCI_QH { | |
167 | uint32_t link; | |
168 | uint32_t el_link; | |
169 | } UHCI_QH; | |
170 | ||
54f254f9 AL |
171 | static UHCIAsync *uhci_async_alloc(UHCIState *s) |
172 | { | |
173 | UHCIAsync *async = qemu_malloc(sizeof(UHCIAsync)); | |
487414f1 AL |
174 | |
175 | memset(&async->packet, 0, sizeof(async->packet)); | |
7b5a44c5 | 176 | async->uhci = s; |
487414f1 AL |
177 | async->valid = 0; |
178 | async->td = 0; | |
179 | async->token = 0; | |
180 | async->done = 0; | |
8e65b7c0 | 181 | async->isoc = 0; |
54f254f9 AL |
182 | |
183 | return async; | |
184 | } | |
185 | ||
186 | static void uhci_async_free(UHCIState *s, UHCIAsync *async) | |
187 | { | |
188 | qemu_free(async); | |
189 | } | |
190 | ||
191 | static void uhci_async_link(UHCIState *s, UHCIAsync *async) | |
192 | { | |
ddf6583f | 193 | QTAILQ_INSERT_HEAD(&s->async_pending, async, next); |
54f254f9 AL |
194 | } |
195 | ||
196 | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) | |
197 | { | |
ddf6583f | 198 | QTAILQ_REMOVE(&s->async_pending, async, next); |
54f254f9 AL |
199 | } |
200 | ||
201 | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) | |
202 | { | |
d0f2c4c6 | 203 | DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n", |
54f254f9 AL |
204 | async->td, async->token, async->done); |
205 | ||
206 | if (!async->done) | |
207 | usb_cancel_packet(&async->packet); | |
208 | uhci_async_free(s, async); | |
209 | } | |
210 | ||
211 | /* | |
212 | * Mark all outstanding async packets as invalid. | |
213 | * This is used for canceling them when TDs are removed by the HCD. | |
214 | */ | |
215 | static UHCIAsync *uhci_async_validate_begin(UHCIState *s) | |
216 | { | |
ddf6583f | 217 | UHCIAsync *async; |
54f254f9 | 218 | |
ddf6583f | 219 | QTAILQ_FOREACH(async, &s->async_pending, next) { |
54f254f9 | 220 | async->valid--; |
54f254f9 AL |
221 | } |
222 | return NULL; | |
223 | } | |
224 | ||
225 | /* | |
226 | * Cancel async packets that are no longer valid | |
227 | */ | |
228 | static void uhci_async_validate_end(UHCIState *s) | |
229 | { | |
ddf6583f | 230 | UHCIAsync *curr, *n; |
54f254f9 | 231 | |
ddf6583f | 232 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
54f254f9 | 233 | if (curr->valid > 0) { |
54f254f9 AL |
234 | continue; |
235 | } | |
ddf6583f | 236 | uhci_async_unlink(s, curr); |
54f254f9 | 237 | uhci_async_cancel(s, curr); |
54f254f9 AL |
238 | } |
239 | } | |
240 | ||
07771f6f GH |
241 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
242 | { | |
243 | UHCIAsync *curr, *n; | |
244 | ||
245 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { | |
246 | if (curr->packet.owner != dev) { | |
247 | continue; | |
248 | } | |
249 | uhci_async_unlink(s, curr); | |
250 | uhci_async_cancel(s, curr); | |
251 | } | |
252 | } | |
253 | ||
54f254f9 AL |
254 | static void uhci_async_cancel_all(UHCIState *s) |
255 | { | |
ddf6583f | 256 | UHCIAsync *curr, *n; |
54f254f9 | 257 | |
ddf6583f GH |
258 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
259 | uhci_async_unlink(s, curr); | |
54f254f9 | 260 | uhci_async_cancel(s, curr); |
54f254f9 | 261 | } |
54f254f9 AL |
262 | } |
263 | ||
264 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token) | |
265 | { | |
ddf6583f | 266 | UHCIAsync *async; |
e8ee3c72 AJ |
267 | UHCIAsync *match = NULL; |
268 | int count = 0; | |
269 | ||
270 | /* | |
271 | * We're looking for the best match here. ie both td addr and token. | |
272 | * Otherwise we return last good match. ie just token. | |
273 | * It's ok to match just token because it identifies the transaction | |
274 | * rather well, token includes: device addr, endpoint, size, etc. | |
275 | * | |
276 | * Also since we queue async transactions in reverse order by returning | |
277 | * last good match we restores the order. | |
278 | * | |
279 | * It's expected that we wont have a ton of outstanding transactions. | |
280 | * If we ever do we'd want to optimize this algorithm. | |
281 | */ | |
54f254f9 | 282 | |
ddf6583f | 283 | QTAILQ_FOREACH(async, &s->async_pending, next) { |
e8ee3c72 AJ |
284 | if (async->token == token) { |
285 | /* Good match */ | |
286 | match = async; | |
287 | ||
288 | if (async->td == addr) { | |
289 | /* Best match */ | |
290 | break; | |
54f254f9 AL |
291 | } |
292 | } | |
e8ee3c72 | 293 | count++; |
54f254f9 | 294 | } |
e8ee3c72 AJ |
295 | |
296 | if (count > 64) | |
297 | fprintf(stderr, "uhci: warning lots of async transactions\n"); | |
298 | ||
299 | return match; | |
54f254f9 AL |
300 | } |
301 | ||
bb36d470 FB |
302 | static void uhci_update_irq(UHCIState *s) |
303 | { | |
304 | int level; | |
305 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
306 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
307 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
308 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
309 | (s->status & UHCI_STS_HSERR) || | |
310 | (s->status & UHCI_STS_HCPERR)) { | |
311 | level = 1; | |
312 | } else { | |
313 | level = 0; | |
314 | } | |
d537cf6c | 315 | qemu_set_irq(s->dev.irq[3], level); |
bb36d470 FB |
316 | } |
317 | ||
c8075ac3 | 318 | static void uhci_reset(void *opaque) |
bb36d470 | 319 | { |
c8075ac3 | 320 | UHCIState *s = opaque; |
bb36d470 FB |
321 | uint8_t *pci_conf; |
322 | int i; | |
323 | UHCIPort *port; | |
324 | ||
d0f2c4c6 | 325 | DPRINTF("uhci: full reset\n"); |
6f382b5e | 326 | |
bb36d470 FB |
327 | pci_conf = s->dev.config; |
328 | ||
329 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
330 | pci_conf[0x6b] = 0x00; | |
331 | s->cmd = 0; | |
332 | s->status = 0; | |
333 | s->status2 = 0; | |
334 | s->intr = 0; | |
335 | s->fl_base_addr = 0; | |
336 | s->sof_timing = 64; | |
54f254f9 | 337 | |
bb36d470 FB |
338 | for(i = 0; i < NB_PORTS; i++) { |
339 | port = &s->ports[i]; | |
340 | port->ctrl = 0x0080; | |
618c169b GH |
341 | if (port->port.dev) { |
342 | usb_attach(&port->port, port->port.dev); | |
343 | } | |
bb36d470 | 344 | } |
54f254f9 AL |
345 | |
346 | uhci_async_cancel_all(s); | |
bb36d470 FB |
347 | } |
348 | ||
817afc61 | 349 | static void uhci_pre_save(void *opaque) |
b9dc033c AZ |
350 | { |
351 | UHCIState *s = opaque; | |
b9dc033c | 352 | |
6f382b5e | 353 | uhci_async_cancel_all(s); |
b9dc033c AZ |
354 | } |
355 | ||
817afc61 JQ |
356 | static const VMStateDescription vmstate_uhci_port = { |
357 | .name = "uhci port", | |
358 | .version_id = 1, | |
359 | .minimum_version_id = 1, | |
360 | .minimum_version_id_old = 1, | |
361 | .fields = (VMStateField []) { | |
362 | VMSTATE_UINT16(ctrl, UHCIPort), | |
363 | VMSTATE_END_OF_LIST() | |
364 | } | |
365 | }; | |
366 | ||
367 | static const VMStateDescription vmstate_uhci = { | |
368 | .name = "uhci", | |
6881dd5f | 369 | .version_id = 2, |
817afc61 JQ |
370 | .minimum_version_id = 1, |
371 | .minimum_version_id_old = 1, | |
372 | .pre_save = uhci_pre_save, | |
373 | .fields = (VMStateField []) { | |
374 | VMSTATE_PCI_DEVICE(dev, UHCIState), | |
375 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), | |
376 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, | |
377 | vmstate_uhci_port, UHCIPort), | |
378 | VMSTATE_UINT16(cmd, UHCIState), | |
379 | VMSTATE_UINT16(status, UHCIState), | |
380 | VMSTATE_UINT16(intr, UHCIState), | |
381 | VMSTATE_UINT16(frnum, UHCIState), | |
382 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
383 | VMSTATE_UINT8(sof_timing, UHCIState), | |
384 | VMSTATE_UINT8(status2, UHCIState), | |
385 | VMSTATE_TIMER(frame_timer, UHCIState), | |
6881dd5f | 386 | VMSTATE_INT64_V(expire_time, UHCIState, 2), |
817afc61 JQ |
387 | VMSTATE_END_OF_LIST() |
388 | } | |
389 | }; | |
b9dc033c | 390 | |
bb36d470 FB |
391 | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
392 | { | |
393 | UHCIState *s = opaque; | |
3b46e624 | 394 | |
bb36d470 FB |
395 | addr &= 0x1f; |
396 | switch(addr) { | |
397 | case 0x0c: | |
398 | s->sof_timing = val; | |
399 | break; | |
400 | } | |
401 | } | |
402 | ||
403 | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) | |
404 | { | |
405 | UHCIState *s = opaque; | |
406 | uint32_t val; | |
407 | ||
408 | addr &= 0x1f; | |
409 | switch(addr) { | |
410 | case 0x0c: | |
411 | val = s->sof_timing; | |
d80cfb3f | 412 | break; |
bb36d470 FB |
413 | default: |
414 | val = 0xff; | |
415 | break; | |
416 | } | |
417 | return val; | |
418 | } | |
419 | ||
420 | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
421 | { | |
422 | UHCIState *s = opaque; | |
3b46e624 | 423 | |
bb36d470 | 424 | addr &= 0x1f; |
d0f2c4c6 | 425 | DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val); |
54f254f9 | 426 | |
bb36d470 FB |
427 | switch(addr) { |
428 | case 0x00: | |
429 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
430 | /* start frame processing */ | |
94cc916a GH |
431 | s->expire_time = qemu_get_clock_ns(vm_clock) + |
432 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
74475455 | 433 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
52328140 | 434 | s->status &= ~UHCI_STS_HCHALTED; |
467d409f | 435 | } else if (!(val & UHCI_CMD_RS)) { |
52328140 | 436 | s->status |= UHCI_STS_HCHALTED; |
bb36d470 FB |
437 | } |
438 | if (val & UHCI_CMD_GRESET) { | |
439 | UHCIPort *port; | |
440 | USBDevice *dev; | |
441 | int i; | |
442 | ||
443 | /* send reset on the USB bus */ | |
444 | for(i = 0; i < NB_PORTS; i++) { | |
445 | port = &s->ports[i]; | |
a594cfbf | 446 | dev = port->port.dev; |
bb36d470 | 447 | if (dev) { |
4d611c9a | 448 | usb_send_msg(dev, USB_MSG_RESET); |
bb36d470 FB |
449 | } |
450 | } | |
451 | uhci_reset(s); | |
452 | return; | |
453 | } | |
5e9ab4c4 | 454 | if (val & UHCI_CMD_HCRESET) { |
bb36d470 FB |
455 | uhci_reset(s); |
456 | return; | |
457 | } | |
458 | s->cmd = val; | |
459 | break; | |
460 | case 0x02: | |
461 | s->status &= ~val; | |
462 | /* XXX: the chip spec is not coherent, so we add a hidden | |
463 | register to distinguish between IOC and SPD */ | |
464 | if (val & UHCI_STS_USBINT) | |
465 | s->status2 = 0; | |
466 | uhci_update_irq(s); | |
467 | break; | |
468 | case 0x04: | |
469 | s->intr = val; | |
470 | uhci_update_irq(s); | |
471 | break; | |
472 | case 0x06: | |
473 | if (s->status & UHCI_STS_HCHALTED) | |
474 | s->frnum = val & 0x7ff; | |
475 | break; | |
476 | case 0x10 ... 0x1f: | |
477 | { | |
478 | UHCIPort *port; | |
479 | USBDevice *dev; | |
480 | int n; | |
481 | ||
482 | n = (addr >> 1) & 7; | |
483 | if (n >= NB_PORTS) | |
484 | return; | |
485 | port = &s->ports[n]; | |
a594cfbf | 486 | dev = port->port.dev; |
bb36d470 FB |
487 | if (dev) { |
488 | /* port reset */ | |
5fafdf24 | 489 | if ( (val & UHCI_PORT_RESET) && |
bb36d470 | 490 | !(port->ctrl & UHCI_PORT_RESET) ) { |
4d611c9a | 491 | usb_send_msg(dev, USB_MSG_RESET); |
bb36d470 FB |
492 | } |
493 | } | |
9159f679 GH |
494 | port->ctrl &= UHCI_PORT_READ_ONLY; |
495 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); | |
bb36d470 | 496 | /* some bits are reset when a '1' is written to them */ |
9159f679 | 497 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
bb36d470 FB |
498 | } |
499 | break; | |
500 | } | |
501 | } | |
502 | ||
503 | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) | |
504 | { | |
505 | UHCIState *s = opaque; | |
506 | uint32_t val; | |
507 | ||
508 | addr &= 0x1f; | |
509 | switch(addr) { | |
510 | case 0x00: | |
511 | val = s->cmd; | |
512 | break; | |
513 | case 0x02: | |
514 | val = s->status; | |
515 | break; | |
516 | case 0x04: | |
517 | val = s->intr; | |
518 | break; | |
519 | case 0x06: | |
520 | val = s->frnum; | |
521 | break; | |
522 | case 0x10 ... 0x1f: | |
523 | { | |
524 | UHCIPort *port; | |
525 | int n; | |
526 | n = (addr >> 1) & 7; | |
5fafdf24 | 527 | if (n >= NB_PORTS) |
bb36d470 FB |
528 | goto read_default; |
529 | port = &s->ports[n]; | |
530 | val = port->ctrl; | |
531 | } | |
532 | break; | |
533 | default: | |
534 | read_default: | |
535 | val = 0xff7f; /* disabled port */ | |
536 | break; | |
537 | } | |
54f254f9 | 538 | |
d0f2c4c6 | 539 | DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val); |
54f254f9 | 540 | |
bb36d470 FB |
541 | return val; |
542 | } | |
543 | ||
544 | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
545 | { | |
546 | UHCIState *s = opaque; | |
547 | ||
548 | addr &= 0x1f; | |
d0f2c4c6 | 549 | DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val); |
54f254f9 | 550 | |
bb36d470 FB |
551 | switch(addr) { |
552 | case 0x08: | |
553 | s->fl_base_addr = val & ~0xfff; | |
554 | break; | |
555 | } | |
556 | } | |
557 | ||
558 | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) | |
559 | { | |
560 | UHCIState *s = opaque; | |
561 | uint32_t val; | |
562 | ||
563 | addr &= 0x1f; | |
564 | switch(addr) { | |
565 | case 0x08: | |
566 | val = s->fl_base_addr; | |
567 | break; | |
568 | default: | |
569 | val = 0xffffffff; | |
570 | break; | |
571 | } | |
572 | return val; | |
573 | } | |
574 | ||
96217e31 TS |
575 | /* signal resume if controller suspended */ |
576 | static void uhci_resume (void *opaque) | |
577 | { | |
578 | UHCIState *s = (UHCIState *)opaque; | |
579 | ||
580 | if (!s) | |
581 | return; | |
582 | ||
583 | if (s->cmd & UHCI_CMD_EGSM) { | |
584 | s->cmd |= UHCI_CMD_FGR; | |
585 | s->status |= UHCI_STS_RD; | |
586 | uhci_update_irq(s); | |
587 | } | |
588 | } | |
589 | ||
618c169b | 590 | static void uhci_attach(USBPort *port1) |
bb36d470 FB |
591 | { |
592 | UHCIState *s = port1->opaque; | |
593 | UHCIPort *port = &s->ports[port1->index]; | |
594 | ||
618c169b GH |
595 | /* set connect status */ |
596 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
61064870 | 597 | |
618c169b GH |
598 | /* update speed */ |
599 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
600 | port->ctrl |= UHCI_PORT_LSDA; | |
bb36d470 | 601 | } else { |
618c169b GH |
602 | port->ctrl &= ~UHCI_PORT_LSDA; |
603 | } | |
96217e31 | 604 | |
618c169b GH |
605 | uhci_resume(s); |
606 | } | |
96217e31 | 607 | |
618c169b GH |
608 | static void uhci_detach(USBPort *port1) |
609 | { | |
610 | UHCIState *s = port1->opaque; | |
611 | UHCIPort *port = &s->ports[port1->index]; | |
612 | ||
4706ab6c HG |
613 | uhci_async_cancel_device(s, port1->dev); |
614 | ||
618c169b GH |
615 | /* set connect status */ |
616 | if (port->ctrl & UHCI_PORT_CCS) { | |
617 | port->ctrl &= ~UHCI_PORT_CCS; | |
618 | port->ctrl |= UHCI_PORT_CSC; | |
bb36d470 | 619 | } |
618c169b GH |
620 | /* disable port */ |
621 | if (port->ctrl & UHCI_PORT_EN) { | |
622 | port->ctrl &= ~UHCI_PORT_EN; | |
623 | port->ctrl |= UHCI_PORT_ENC; | |
624 | } | |
625 | ||
626 | uhci_resume(s); | |
bb36d470 FB |
627 | } |
628 | ||
4706ab6c HG |
629 | static void uhci_child_detach(USBPort *port1, USBDevice *child) |
630 | { | |
631 | UHCIState *s = port1->opaque; | |
632 | ||
633 | uhci_async_cancel_device(s, child); | |
634 | } | |
635 | ||
d47e59b8 | 636 | static void uhci_wakeup(USBPort *port1) |
9159f679 | 637 | { |
d47e59b8 HG |
638 | UHCIState *s = port1->opaque; |
639 | UHCIPort *port = &s->ports[port1->index]; | |
9159f679 GH |
640 | |
641 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
642 | port->ctrl |= UHCI_PORT_RD; | |
643 | uhci_resume(s); | |
644 | } | |
645 | } | |
646 | ||
4d611c9a | 647 | static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
bb36d470 | 648 | { |
bb36d470 FB |
649 | int i, ret; |
650 | ||
d0f2c4c6 | 651 | DPRINTF("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n", |
54f254f9 | 652 | pid2str(p->pid), p->devaddr, p->devep, p->len); |
5d808245 | 653 | if (p->pid == USB_TOKEN_OUT || p->pid == USB_TOKEN_SETUP) |
54f254f9 AL |
654 | dump_data(p->data, p->len); |
655 | ||
656 | ret = USB_RET_NODEV; | |
657 | for (i = 0; i < NB_PORTS && ret == USB_RET_NODEV; i++) { | |
658 | UHCIPort *port = &s->ports[i]; | |
659 | USBDevice *dev = port->port.dev; | |
660 | ||
661 | if (dev && (port->ctrl & UHCI_PORT_EN)) | |
53aa8c0e | 662 | ret = usb_handle_packet(dev, p); |
bb36d470 | 663 | } |
54f254f9 | 664 | |
d0f2c4c6 | 665 | DPRINTF("uhci: packet exit. ret %d len %d\n", ret, p->len); |
54f254f9 AL |
666 | if (p->pid == USB_TOKEN_IN && ret > 0) |
667 | dump_data(p->data, ret); | |
668 | ||
669 | return ret; | |
bb36d470 FB |
670 | } |
671 | ||
d47e59b8 | 672 | static void uhci_async_complete(USBPort *port, USBPacket *packet); |
54f254f9 | 673 | static void uhci_process_frame(UHCIState *s); |
4d611c9a | 674 | |
bb36d470 FB |
675 | /* return -1 if fatal error (frame must be stopped) |
676 | 0 if TD successful | |
677 | 1 if TD unsuccessful or inactive | |
678 | */ | |
54f254f9 | 679 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
bb36d470 | 680 | { |
54f254f9 | 681 | int len = 0, max_len, err, ret; |
bb36d470 | 682 | uint8_t pid; |
bb36d470 | 683 | |
54f254f9 AL |
684 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
685 | pid = td->token & 0xff; | |
686 | ||
687 | ret = async->packet.len; | |
688 | ||
54f254f9 AL |
689 | if (td->ctrl & TD_CTRL_IOS) |
690 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
bb36d470 | 691 | |
54f254f9 AL |
692 | if (ret < 0) |
693 | goto out; | |
b9dc033c | 694 | |
54f254f9 AL |
695 | len = async->packet.len; |
696 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); | |
697 | ||
698 | /* The NAK bit may have been set by a previous frame, so clear it | |
699 | here. The docs are somewhat unclear, but win2k relies on this | |
700 | behavior. */ | |
701 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
5bd2c0d7 PB |
702 | if (td->ctrl & TD_CTRL_IOC) |
703 | *int_mask |= 0x01; | |
54f254f9 AL |
704 | |
705 | if (pid == USB_TOKEN_IN) { | |
706 | if (len > max_len) { | |
54f254f9 AL |
707 | ret = USB_RET_BABBLE; |
708 | goto out; | |
4d611c9a | 709 | } |
b9dc033c | 710 | |
54f254f9 AL |
711 | if (len > 0) { |
712 | /* write the data back */ | |
713 | cpu_physical_memory_write(td->buffer, async->buffer, len); | |
714 | } | |
715 | ||
716 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { | |
bb36d470 FB |
717 | *int_mask |= 0x02; |
718 | /* short packet: do not update QH */ | |
d0f2c4c6 | 719 | DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token); |
bb36d470 | 720 | return 1; |
bb36d470 | 721 | } |
54f254f9 AL |
722 | } |
723 | ||
724 | /* success */ | |
725 | return 0; | |
726 | ||
727 | out: | |
728 | switch(ret) { | |
729 | case USB_RET_STALL: | |
730 | td->ctrl |= TD_CTRL_STALL; | |
731 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a JV |
732 | s->status |= UHCI_STS_USBERR; |
733 | uhci_update_irq(s); | |
54f254f9 AL |
734 | return 1; |
735 | ||
736 | case USB_RET_BABBLE: | |
737 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
738 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a JV |
739 | s->status |= UHCI_STS_USBERR; |
740 | uhci_update_irq(s); | |
54f254f9 AL |
741 | /* frame interrupted */ |
742 | return -1; | |
743 | ||
744 | case USB_RET_NAK: | |
745 | td->ctrl |= TD_CTRL_NAK; | |
746 | if (pid == USB_TOKEN_SETUP) | |
747 | break; | |
748 | return 1; | |
749 | ||
750 | case USB_RET_NODEV: | |
751 | default: | |
752 | break; | |
753 | } | |
754 | ||
755 | /* Retry the TD if error count is not zero */ | |
756 | ||
757 | td->ctrl |= TD_CTRL_TIMEOUT; | |
758 | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; | |
759 | if (err != 0) { | |
760 | err--; | |
761 | if (err == 0) { | |
bb36d470 | 762 | td->ctrl &= ~TD_CTRL_ACTIVE; |
54f254f9 | 763 | s->status |= UHCI_STS_USBERR; |
5bd2c0d7 PB |
764 | if (td->ctrl & TD_CTRL_IOC) |
765 | *int_mask |= 0x01; | |
54f254f9 | 766 | uhci_update_irq(s); |
bb36d470 FB |
767 | } |
768 | } | |
54f254f9 AL |
769 | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | |
770 | (err << TD_CTRL_ERROR_SHIFT); | |
771 | return 1; | |
bb36d470 FB |
772 | } |
773 | ||
54f254f9 AL |
774 | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
775 | { | |
776 | UHCIAsync *async; | |
5d808245 | 777 | int len = 0, max_len; |
8e65b7c0 DA |
778 | uint8_t pid, isoc; |
779 | uint32_t token; | |
54f254f9 AL |
780 | |
781 | /* Is active ? */ | |
782 | if (!(td->ctrl & TD_CTRL_ACTIVE)) | |
783 | return 1; | |
784 | ||
8e65b7c0 DA |
785 | /* token field is not unique for isochronous requests, |
786 | * so use the destination buffer | |
787 | */ | |
788 | if (td->ctrl & TD_CTRL_IOS) { | |
789 | token = td->buffer; | |
790 | isoc = 1; | |
791 | } else { | |
792 | token = td->token; | |
793 | isoc = 0; | |
794 | } | |
795 | ||
796 | async = uhci_async_find_td(s, addr, token); | |
54f254f9 AL |
797 | if (async) { |
798 | /* Already submitted */ | |
a145ea51 | 799 | async->valid = 32; |
54f254f9 AL |
800 | |
801 | if (!async->done) | |
802 | return 1; | |
803 | ||
804 | uhci_async_unlink(s, async); | |
805 | goto done; | |
806 | } | |
807 | ||
808 | /* Allocate new packet */ | |
809 | async = uhci_async_alloc(s); | |
810 | if (!async) | |
811 | return 1; | |
812 | ||
8e65b7c0 DA |
813 | /* valid needs to be large enough to handle 10 frame delay |
814 | * for initial isochronous requests | |
815 | */ | |
816 | async->valid = 32; | |
54f254f9 | 817 | async->td = addr; |
8e65b7c0 DA |
818 | async->token = token; |
819 | async->isoc = isoc; | |
54f254f9 AL |
820 | |
821 | max_len = ((td->token >> 21) + 1) & 0x7ff; | |
822 | pid = td->token & 0xff; | |
823 | ||
824 | async->packet.pid = pid; | |
825 | async->packet.devaddr = (td->token >> 8) & 0x7f; | |
826 | async->packet.devep = (td->token >> 15) & 0xf; | |
827 | async->packet.data = async->buffer; | |
828 | async->packet.len = max_len; | |
54f254f9 AL |
829 | |
830 | switch(pid) { | |
831 | case USB_TOKEN_OUT: | |
832 | case USB_TOKEN_SETUP: | |
833 | cpu_physical_memory_read(td->buffer, async->buffer, max_len); | |
5d808245 AJ |
834 | len = uhci_broadcast_packet(s, &async->packet); |
835 | if (len >= 0) | |
836 | len = max_len; | |
54f254f9 AL |
837 | break; |
838 | ||
839 | case USB_TOKEN_IN: | |
5d808245 | 840 | len = uhci_broadcast_packet(s, &async->packet); |
54f254f9 AL |
841 | break; |
842 | ||
843 | default: | |
844 | /* invalid pid : frame interrupted */ | |
845 | uhci_async_free(s, async); | |
846 | s->status |= UHCI_STS_HCPERR; | |
847 | uhci_update_irq(s); | |
848 | return -1; | |
849 | } | |
850 | ||
5d808245 | 851 | if (len == USB_RET_ASYNC) { |
54f254f9 AL |
852 | uhci_async_link(s, async); |
853 | return 2; | |
854 | } | |
855 | ||
5d808245 | 856 | async->packet.len = len; |
54f254f9 AL |
857 | |
858 | done: | |
5d808245 | 859 | len = uhci_complete_td(s, td, async, int_mask); |
54f254f9 | 860 | uhci_async_free(s, async); |
5d808245 | 861 | return len; |
54f254f9 AL |
862 | } |
863 | ||
d47e59b8 | 864 | static void uhci_async_complete(USBPort *port, USBPacket *packet) |
4d611c9a | 865 | { |
7b5a44c5 GH |
866 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
867 | UHCIState *s = async->uhci; | |
54f254f9 | 868 | |
d0f2c4c6 | 869 | DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token); |
54f254f9 | 870 | |
8e65b7c0 DA |
871 | if (async->isoc) { |
872 | UHCI_TD td; | |
873 | uint32_t link = async->td; | |
874 | uint32_t int_mask = 0, val; | |
d4c4e6fd | 875 | |
8e65b7c0 DA |
876 | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); |
877 | le32_to_cpus(&td.link); | |
878 | le32_to_cpus(&td.ctrl); | |
879 | le32_to_cpus(&td.token); | |
880 | le32_to_cpus(&td.buffer); | |
881 | ||
882 | uhci_async_unlink(s, async); | |
d4c4e6fd | 883 | uhci_complete_td(s, &td, async, &int_mask); |
8e65b7c0 | 884 | s->pending_int_mask |= int_mask; |
54f254f9 | 885 | |
8e65b7c0 DA |
886 | /* update the status bits of the TD */ |
887 | val = cpu_to_le32(td.ctrl); | |
888 | cpu_physical_memory_write((link & ~0xf) + 4, | |
889 | (const uint8_t *)&val, sizeof(val)); | |
890 | uhci_async_free(s, async); | |
891 | } else { | |
892 | async->done = 1; | |
893 | uhci_process_frame(s); | |
894 | } | |
54f254f9 AL |
895 | } |
896 | ||
897 | static int is_valid(uint32_t link) | |
898 | { | |
899 | return (link & 1) == 0; | |
900 | } | |
901 | ||
902 | static int is_qh(uint32_t link) | |
903 | { | |
904 | return (link & 2) != 0; | |
905 | } | |
906 | ||
907 | static int depth_first(uint32_t link) | |
908 | { | |
909 | return (link & 4) != 0; | |
910 | } | |
911 | ||
912 | /* QH DB used for detecting QH loops */ | |
913 | #define UHCI_MAX_QUEUES 128 | |
914 | typedef struct { | |
915 | uint32_t addr[UHCI_MAX_QUEUES]; | |
916 | int count; | |
917 | } QhDb; | |
918 | ||
919 | static void qhdb_reset(QhDb *db) | |
920 | { | |
921 | db->count = 0; | |
922 | } | |
923 | ||
924 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
925 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
926 | { | |
927 | int i; | |
928 | for (i = 0; i < db->count; i++) | |
929 | if (db->addr[i] == addr) | |
930 | return 1; | |
931 | ||
932 | if (db->count >= UHCI_MAX_QUEUES) | |
933 | return 1; | |
934 | ||
935 | db->addr[db->count++] = addr; | |
936 | return 0; | |
937 | } | |
938 | ||
939 | static void uhci_process_frame(UHCIState *s) | |
940 | { | |
941 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
942 | uint32_t curr_qh; | |
943 | int cnt, ret; | |
4d611c9a | 944 | UHCI_TD td; |
54f254f9 AL |
945 | UHCI_QH qh; |
946 | QhDb qhdb; | |
4d611c9a | 947 | |
54f254f9 AL |
948 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
949 | ||
d0f2c4c6 | 950 | DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr); |
54f254f9 AL |
951 | |
952 | cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4); | |
953 | le32_to_cpus(&link); | |
b9dc033c | 954 | |
54f254f9 AL |
955 | int_mask = 0; |
956 | curr_qh = 0; | |
957 | ||
958 | qhdb_reset(&qhdb); | |
959 | ||
960 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
961 | if (is_qh(link)) { | |
962 | /* QH */ | |
963 | ||
964 | if (qhdb_insert(&qhdb, link)) { | |
965 | /* | |
966 | * We're going in circles. Which is not a bug because | |
967 | * HCD is allowed to do that as part of the BW management. | |
968 | * In our case though it makes no sense to spin here. Sync transations | |
969 | * are already done, and async completion handler will re-process | |
970 | * the frame when something is ready. | |
971 | */ | |
d0f2c4c6 | 972 | DPRINTF("uhci: detected loop. qh 0x%x\n", link); |
54f254f9 AL |
973 | break; |
974 | } | |
975 | ||
976 | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &qh, sizeof(qh)); | |
977 | le32_to_cpus(&qh.link); | |
978 | le32_to_cpus(&qh.el_link); | |
979 | ||
d0f2c4c6 | 980 | DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n", |
54f254f9 AL |
981 | link, qh.link, qh.el_link); |
982 | ||
983 | if (!is_valid(qh.el_link)) { | |
984 | /* QH w/o elements */ | |
985 | curr_qh = 0; | |
986 | link = qh.link; | |
987 | } else { | |
988 | /* QH with elements */ | |
989 | curr_qh = link; | |
990 | link = qh.el_link; | |
991 | } | |
992 | continue; | |
993 | } | |
994 | ||
995 | /* TD */ | |
996 | cpu_physical_memory_read(link & ~0xf, (uint8_t *) &td, sizeof(td)); | |
b9dc033c AZ |
997 | le32_to_cpus(&td.link); |
998 | le32_to_cpus(&td.ctrl); | |
999 | le32_to_cpus(&td.token); | |
1000 | le32_to_cpus(&td.buffer); | |
b9dc033c | 1001 | |
d0f2c4c6 | 1002 | DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1003 | link, td.link, td.ctrl, td.token, curr_qh); |
1004 | ||
1005 | old_td_ctrl = td.ctrl; | |
1006 | ret = uhci_handle_td(s, link, &td, &int_mask); | |
b9dc033c | 1007 | if (old_td_ctrl != td.ctrl) { |
54f254f9 | 1008 | /* update the status bits of the TD */ |
b9dc033c AZ |
1009 | val = cpu_to_le32(td.ctrl); |
1010 | cpu_physical_memory_write((link & ~0xf) + 4, | |
54f254f9 | 1011 | (const uint8_t *)&val, sizeof(val)); |
b9dc033c | 1012 | } |
54f254f9 AL |
1013 | |
1014 | if (ret < 0) { | |
1015 | /* interrupted frame */ | |
1016 | break; | |
b9dc033c | 1017 | } |
b9dc033c | 1018 | |
54f254f9 | 1019 | if (ret == 2 || ret == 1) { |
d0f2c4c6 | 1020 | DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1021 | link, ret == 2 ? "pend" : "skip", |
1022 | td.link, td.ctrl, td.token, curr_qh); | |
b9dc033c | 1023 | |
54f254f9 AL |
1024 | link = curr_qh ? qh.link : td.link; |
1025 | continue; | |
4d611c9a | 1026 | } |
54f254f9 AL |
1027 | |
1028 | /* completed TD */ | |
1029 | ||
d0f2c4c6 | 1030 | DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1031 | link, td.link, td.ctrl, td.token, curr_qh); |
1032 | ||
1033 | link = td.link; | |
1034 | ||
1035 | if (curr_qh) { | |
1036 | /* update QH element link */ | |
1037 | qh.el_link = link; | |
4d611c9a | 1038 | val = cpu_to_le32(qh.el_link); |
54f254f9 AL |
1039 | cpu_physical_memory_write((curr_qh & ~0xf) + 4, |
1040 | (const uint8_t *)&val, sizeof(val)); | |
1041 | ||
1042 | if (!depth_first(link)) { | |
1043 | /* done with this QH */ | |
1044 | ||
d0f2c4c6 | 1045 | DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n", |
54f254f9 AL |
1046 | curr_qh, qh.link, qh.el_link); |
1047 | ||
1048 | curr_qh = 0; | |
1049 | link = qh.link; | |
1050 | } | |
4d611c9a | 1051 | } |
54f254f9 AL |
1052 | |
1053 | /* go to the next entry */ | |
4d611c9a | 1054 | } |
54f254f9 | 1055 | |
8e65b7c0 | 1056 | s->pending_int_mask |= int_mask; |
4d611c9a PB |
1057 | } |
1058 | ||
bb36d470 FB |
1059 | static void uhci_frame_timer(void *opaque) |
1060 | { | |
1061 | UHCIState *s = opaque; | |
8e65b7c0 DA |
1062 | |
1063 | /* prepare the timer for the next frame */ | |
1064 | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
bb36d470 FB |
1065 | |
1066 | if (!(s->cmd & UHCI_CMD_RS)) { | |
54f254f9 | 1067 | /* Full stop */ |
bb36d470 | 1068 | qemu_del_timer(s->frame_timer); |
52328140 FB |
1069 | /* set hchalted bit in status - UHCI11D 2.1.2 */ |
1070 | s->status |= UHCI_STS_HCHALTED; | |
6f382b5e | 1071 | |
d0f2c4c6 | 1072 | DPRINTF("uhci: halted\n"); |
bb36d470 FB |
1073 | return; |
1074 | } | |
54f254f9 AL |
1075 | |
1076 | /* Complete the previous frame */ | |
4d611c9a PB |
1077 | if (s->pending_int_mask) { |
1078 | s->status2 |= s->pending_int_mask; | |
54f254f9 | 1079 | s->status |= UHCI_STS_USBINT; |
4d611c9a PB |
1080 | uhci_update_irq(s); |
1081 | } | |
8e65b7c0 | 1082 | s->pending_int_mask = 0; |
b9dc033c | 1083 | |
54f254f9 AL |
1084 | /* Start new frame */ |
1085 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1086 | ||
d0f2c4c6 | 1087 | DPRINTF("uhci: new frame #%u\n" , s->frnum); |
54f254f9 AL |
1088 | |
1089 | uhci_async_validate_begin(s); | |
1090 | ||
1091 | uhci_process_frame(s); | |
1092 | ||
1093 | uhci_async_validate_end(s); | |
b9dc033c | 1094 | |
8e65b7c0 | 1095 | qemu_mod_timer(s->frame_timer, s->expire_time); |
bb36d470 FB |
1096 | } |
1097 | ||
5fafdf24 | 1098 | static void uhci_map(PCIDevice *pci_dev, int region_num, |
6e355d90 | 1099 | pcibus_t addr, pcibus_t size, int type) |
bb36d470 FB |
1100 | { |
1101 | UHCIState *s = (UHCIState *)pci_dev; | |
1102 | ||
1103 | register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); | |
1104 | register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); | |
1105 | register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); | |
1106 | register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); | |
1107 | register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); | |
1108 | register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); | |
1109 | } | |
1110 | ||
0d86d2be GH |
1111 | static USBPortOps uhci_port_ops = { |
1112 | .attach = uhci_attach, | |
618c169b | 1113 | .detach = uhci_detach, |
4706ab6c | 1114 | .child_detach = uhci_child_detach, |
9159f679 | 1115 | .wakeup = uhci_wakeup, |
13a9a0d3 | 1116 | .complete = uhci_async_complete, |
0d86d2be GH |
1117 | }; |
1118 | ||
07771f6f | 1119 | static USBBusOps uhci_bus_ops = { |
07771f6f GH |
1120 | }; |
1121 | ||
dc638fad | 1122 | static int usb_uhci_common_initfn(PCIDevice *dev) |
bb36d470 | 1123 | { |
dc638fad | 1124 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
6cf9b6f1 | 1125 | uint8_t *pci_conf = s->dev.config; |
bb36d470 FB |
1126 | int i; |
1127 | ||
db579e9e | 1128 | pci_conf[PCI_CLASS_PROG] = 0x00; |
db579e9e MT |
1129 | /* TODO: reset value should be 0. */ |
1130 | pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3 | |
e59d33a7 | 1131 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number |
3b46e624 | 1132 | |
35e4977f HG |
1133 | if (s->masterbus) { |
1134 | USBPort *ports[NB_PORTS]; | |
1135 | for(i = 0; i < NB_PORTS; i++) { | |
1136 | ports[i] = &s->ports[i].port; | |
1137 | } | |
1138 | if (usb_register_companion(s->masterbus, ports, NB_PORTS, | |
1139 | s->firstport, s, &uhci_port_ops, | |
1140 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { | |
1141 | return -1; | |
1142 | } | |
1143 | } else { | |
1144 | usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); | |
1145 | for (i = 0; i < NB_PORTS; i++) { | |
1146 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, | |
1147 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1148 | } | |
bb36d470 | 1149 | } |
74475455 | 1150 | s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
64e58fe5 | 1151 | s->num_ports_vmstate = NB_PORTS; |
ddf6583f | 1152 | QTAILQ_INIT(&s->async_pending); |
bb36d470 | 1153 | |
a08d4367 | 1154 | qemu_register_reset(uhci_reset, s); |
bb36d470 | 1155 | |
38ca0f6d PB |
1156 | /* Use region 4 for consistency with real hardware. BSD guests seem |
1157 | to rely on this. */ | |
28c2c264 | 1158 | pci_register_bar(&s->dev, 4, 0x20, |
0392a017 | 1159 | PCI_BASE_ADDRESS_SPACE_IO, uhci_map); |
6f382b5e | 1160 | |
6cf9b6f1 | 1161 | return 0; |
bb36d470 | 1162 | } |
afcc3cdf | 1163 | |
30235a54 HC |
1164 | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1165 | { | |
1166 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1167 | uint8_t *pci_conf = s->dev.config; | |
1168 | ||
30235a54 HC |
1169 | /* USB misc control 1/2 */ |
1170 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1171 | /* PM capability */ | |
1172 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1173 | /* USB legacy support */ | |
1174 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1175 | ||
dc638fad | 1176 | return usb_uhci_common_initfn(dev); |
30235a54 HC |
1177 | } |
1178 | ||
6cf9b6f1 GH |
1179 | static PCIDeviceInfo uhci_info[] = { |
1180 | { | |
556cd098 | 1181 | .qdev.name = "piix3-usb-uhci", |
6cf9b6f1 | 1182 | .qdev.size = sizeof(UHCIState), |
be73cfe2 | 1183 | .qdev.vmsd = &vmstate_uhci, |
dc638fad IY |
1184 | .init = usb_uhci_common_initfn, |
1185 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1186 | .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, | |
1187 | .revision = 0x01, | |
1188 | .class_id = PCI_CLASS_SERIAL_USB, | |
35e4977f HG |
1189 | .qdev.props = (Property[]) { |
1190 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), | |
1191 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
1192 | DEFINE_PROP_END_OF_LIST(), | |
1193 | }, | |
6cf9b6f1 | 1194 | },{ |
556cd098 | 1195 | .qdev.name = "piix4-usb-uhci", |
6cf9b6f1 | 1196 | .qdev.size = sizeof(UHCIState), |
be73cfe2 | 1197 | .qdev.vmsd = &vmstate_uhci, |
dc638fad IY |
1198 | .init = usb_uhci_common_initfn, |
1199 | .vendor_id = PCI_VENDOR_ID_INTEL, | |
1200 | .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, | |
1201 | .revision = 0x01, | |
1202 | .class_id = PCI_CLASS_SERIAL_USB, | |
35e4977f HG |
1203 | .qdev.props = (Property[]) { |
1204 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), | |
1205 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
1206 | DEFINE_PROP_END_OF_LIST(), | |
1207 | }, | |
30235a54 HC |
1208 | },{ |
1209 | .qdev.name = "vt82c686b-usb-uhci", | |
1210 | .qdev.size = sizeof(UHCIState), | |
1211 | .qdev.vmsd = &vmstate_uhci, | |
1212 | .init = usb_uhci_vt82c686b_initfn, | |
dc638fad IY |
1213 | .vendor_id = PCI_VENDOR_ID_VIA, |
1214 | .device_id = PCI_DEVICE_ID_VIA_UHCI, | |
1215 | .revision = 0x01, | |
1216 | .class_id = PCI_CLASS_SERIAL_USB, | |
35e4977f HG |
1217 | .qdev.props = (Property[]) { |
1218 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), | |
1219 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
1220 | DEFINE_PROP_END_OF_LIST(), | |
1221 | }, | |
6cf9b6f1 GH |
1222 | },{ |
1223 | /* end of list */ | |
afcc3cdf | 1224 | } |
6cf9b6f1 | 1225 | }; |
afcc3cdf | 1226 | |
6cf9b6f1 GH |
1227 | static void uhci_register(void) |
1228 | { | |
1229 | pci_qdev_register_many(uhci_info); | |
1230 | } | |
1231 | device_init(uhci_register); | |
afcc3cdf | 1232 | |
6cf9b6f1 GH |
1233 | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1234 | { | |
556cd098 | 1235 | pci_create_simple(bus, devfn, "piix3-usb-uhci"); |
6cf9b6f1 | 1236 | } |
54f254f9 | 1237 | |
6cf9b6f1 GH |
1238 | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1239 | { | |
556cd098 | 1240 | pci_create_simple(bus, devfn, "piix4-usb-uhci"); |
afcc3cdf | 1241 | } |
30235a54 HC |
1242 | |
1243 | void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) | |
1244 | { | |
1245 | pci_create_simple(bus, devfn, "vt82c686b-usb-uhci"); | |
1246 | } |