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5fafdf24 | 1 | /* |
502a5395 PB |
2 | * ARM Versatile/PB PCI host controller |
3 | * | |
0027b06d | 4 | * Copyright (c) 2006-2009 CodeSourcery. |
502a5395 PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This code is licenced under the LGPL. | |
8 | */ | |
9 | ||
0027b06d | 10 | #include "sysbus.h" |
87ecb68b | 11 | #include "pci.h" |
0027b06d PB |
12 | |
13 | typedef struct { | |
14 | SysBusDevice busdev; | |
15 | qemu_irq irq[4]; | |
16 | int realview; | |
17 | int mem_config; | |
18 | } PCIVPBState; | |
502a5395 | 19 | |
c227f099 | 20 | static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr) |
502a5395 | 21 | { |
80b3ada7 | 22 | return addr & 0xffffff; |
502a5395 PB |
23 | } |
24 | ||
c227f099 | 25 | static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
26 | uint32_t val) |
27 | { | |
28 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1); | |
29 | } | |
30 | ||
c227f099 | 31 | static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
32 | uint32_t val) |
33 | { | |
34 | #ifdef TARGET_WORDS_BIGENDIAN | |
35 | val = bswap16(val); | |
36 | #endif | |
37 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2); | |
38 | } | |
39 | ||
c227f099 | 40 | static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, |
502a5395 PB |
41 | uint32_t val) |
42 | { | |
43 | #ifdef TARGET_WORDS_BIGENDIAN | |
44 | val = bswap32(val); | |
45 | #endif | |
46 | pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4); | |
47 | } | |
48 | ||
c227f099 | 49 | static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
50 | { |
51 | uint32_t val; | |
52 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1); | |
53 | return val; | |
54 | } | |
55 | ||
c227f099 | 56 | static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
57 | { |
58 | uint32_t val; | |
59 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2); | |
60 | #ifdef TARGET_WORDS_BIGENDIAN | |
61 | val = bswap16(val); | |
62 | #endif | |
63 | return val; | |
64 | } | |
65 | ||
c227f099 | 66 | static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr) |
502a5395 PB |
67 | { |
68 | uint32_t val; | |
69 | val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4); | |
70 | #ifdef TARGET_WORDS_BIGENDIAN | |
71 | val = bswap32(val); | |
72 | #endif | |
73 | return val; | |
74 | } | |
75 | ||
d60efc6b | 76 | static CPUWriteMemoryFunc * const pci_vpb_config_write[] = { |
502a5395 PB |
77 | &pci_vpb_config_writeb, |
78 | &pci_vpb_config_writew, | |
79 | &pci_vpb_config_writel, | |
80 | }; | |
81 | ||
d60efc6b | 82 | static CPUReadMemoryFunc * const pci_vpb_config_read[] = { |
502a5395 PB |
83 | &pci_vpb_config_readb, |
84 | &pci_vpb_config_readw, | |
85 | &pci_vpb_config_readl, | |
86 | }; | |
87 | ||
d2b59317 PB |
88 | static int pci_vpb_map_irq(PCIDevice *d, int irq_num) |
89 | { | |
90 | return irq_num; | |
91 | } | |
92 | ||
5d4e84c8 | 93 | static void pci_vpb_set_irq(void *opaque, int irq_num, int level) |
502a5395 | 94 | { |
5d4e84c8 JQ |
95 | qemu_irq *pic = opaque; |
96 | ||
97aff481 | 97 | qemu_set_irq(pic[irq_num], level); |
502a5395 PB |
98 | } |
99 | ||
c227f099 | 100 | static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base) |
502a5395 | 101 | { |
0027b06d PB |
102 | PCIVPBState *s = (PCIVPBState *)dev; |
103 | /* Selfconfig area. */ | |
104 | cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config); | |
105 | /* Normal config area. */ | |
106 | cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config); | |
107 | ||
108 | if (s->realview) { | |
109 | /* IO memory area. */ | |
110 | isa_mmio_init(base + 0x03000000, 0x00100000); | |
111 | } | |
112 | } | |
113 | ||
81a322d4 | 114 | static int pci_vpb_init(SysBusDevice *dev) |
0027b06d PB |
115 | { |
116 | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); | |
117 | PCIBus *bus; | |
97aff481 | 118 | int i; |
e69954b9 | 119 | |
97aff481 | 120 | for (i = 0; i < 4; i++) { |
0027b06d | 121 | sysbus_init_irq(dev, &s->irq[i]); |
e69954b9 | 122 | } |
02e2da45 PB |
123 | bus = pci_register_bus(&dev->qdev, "pci", |
124 | pci_vpb_set_irq, pci_vpb_map_irq, s->irq, | |
0027b06d | 125 | 11 << 3, 4); |
0027b06d | 126 | |
502a5395 PB |
127 | /* ??? Register memory space. */ |
128 | ||
1eed09cb | 129 | s->mem_config = cpu_register_io_memory(pci_vpb_config_read, |
0027b06d PB |
130 | pci_vpb_config_write, bus); |
131 | sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map); | |
e69954b9 | 132 | |
0027b06d | 133 | pci_create_simple(bus, -1, "versatile_pci_host"); |
81a322d4 | 134 | return 0; |
0027b06d | 135 | } |
e69954b9 | 136 | |
81a322d4 | 137 | static int pci_realview_init(SysBusDevice *dev) |
0027b06d PB |
138 | { |
139 | PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev); | |
140 | s->realview = 1; | |
81a322d4 | 141 | return pci_vpb_init(dev); |
0027b06d | 142 | } |
502a5395 | 143 | |
81a322d4 | 144 | static int versatile_pci_host_init(PCIDevice *d) |
0027b06d | 145 | { |
deb54399 | 146 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX); |
e69954b9 | 147 | /* Both boards have the same device ID. Oh well. */ |
a770dc7e | 148 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30); |
502a5395 PB |
149 | d->config[0x04] = 0x00; |
150 | d->config[0x05] = 0x00; | |
151 | d->config[0x06] = 0x20; | |
152 | d->config[0x07] = 0x02; | |
153 | d->config[0x08] = 0x00; // revision | |
154 | d->config[0x09] = 0x00; // programming i/f | |
173a543b | 155 | pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO); |
502a5395 | 156 | d->config[0x0D] = 0x10; // latency_timer |
81a322d4 | 157 | return 0; |
0027b06d | 158 | } |
502a5395 | 159 | |
0aab0d3a GH |
160 | static PCIDeviceInfo versatile_pci_host_info = { |
161 | .qdev.name = "versatile_pci_host", | |
162 | .qdev.size = sizeof(PCIDevice), | |
163 | .init = versatile_pci_host_init, | |
164 | }; | |
165 | ||
0027b06d PB |
166 | static void versatile_pci_register_devices(void) |
167 | { | |
168 | sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init); | |
169 | sysbus_register_dev("realview_pci", sizeof(PCIVPBState), | |
170 | pci_realview_init); | |
0aab0d3a | 171 | pci_qdev_register(&versatile_pci_host_info); |
502a5395 | 172 | } |
0027b06d PB |
173 | |
174 | device_init(versatile_pci_register_devices) |