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2055283b PM |
1 | /* |
2 | * ARM Versatile Express emulation. | |
3 | * | |
4 | * Copyright (c) 2010 - 2011 B Labs Ltd. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
6b620ca3 PB |
19 | * |
20 | * Contributions after 2012-01-13 are licensed under the terms of the | |
21 | * GNU GPL, version 2 or (at your option) any later version. | |
2055283b PM |
22 | */ |
23 | ||
24 | #include "sysbus.h" | |
25 | #include "arm-misc.h" | |
26 | #include "primecell.h" | |
27 | #include "devices.h" | |
28 | #include "net.h" | |
29 | #include "sysemu.h" | |
30 | #include "boards.h" | |
e6d17b05 | 31 | #include "exec-memory.h" |
2055283b | 32 | |
2055283b PM |
33 | #define VEXPRESS_BOARD_ID 0x8e0 |
34 | ||
aac1e02c | 35 | static struct arm_boot_info vexpress_binfo; |
2558e0a6 PM |
36 | |
37 | /* Address maps for peripherals: | |
38 | * the Versatile Express motherboard has two possible maps, | |
39 | * the "legacy" one (used for A9) and the "Cortex-A Series" | |
40 | * map (used for newer cores). | |
41 | * Individual daughterboards can also have different maps for | |
42 | * their peripherals. | |
43 | */ | |
44 | ||
45 | enum { | |
46 | VE_SYSREGS, | |
47 | VE_SP810, | |
48 | VE_SERIALPCI, | |
49 | VE_PL041, | |
50 | VE_MMCI, | |
51 | VE_KMI0, | |
52 | VE_KMI1, | |
53 | VE_UART0, | |
54 | VE_UART1, | |
55 | VE_UART2, | |
56 | VE_UART3, | |
57 | VE_WDT, | |
58 | VE_TIMER01, | |
59 | VE_TIMER23, | |
60 | VE_SERIALDVI, | |
61 | VE_RTC, | |
62 | VE_COMPACTFLASH, | |
63 | VE_CLCD, | |
64 | VE_NORFLASH0, | |
2558e0a6 PM |
65 | VE_NORFLASH1, |
66 | VE_SRAM, | |
67 | VE_VIDEORAM, | |
68 | VE_ETHERNET, | |
69 | VE_USB, | |
70 | VE_DAPROM, | |
71 | }; | |
72 | ||
73 | static target_phys_addr_t motherboard_legacy_map[] = { | |
74 | /* CS7: 0x10000000 .. 0x10020000 */ | |
75 | [VE_SYSREGS] = 0x10000000, | |
76 | [VE_SP810] = 0x10001000, | |
77 | [VE_SERIALPCI] = 0x10002000, | |
78 | [VE_PL041] = 0x10004000, | |
79 | [VE_MMCI] = 0x10005000, | |
80 | [VE_KMI0] = 0x10006000, | |
81 | [VE_KMI1] = 0x10007000, | |
82 | [VE_UART0] = 0x10009000, | |
83 | [VE_UART1] = 0x1000a000, | |
84 | [VE_UART2] = 0x1000b000, | |
85 | [VE_UART3] = 0x1000c000, | |
86 | [VE_WDT] = 0x1000f000, | |
87 | [VE_TIMER01] = 0x10011000, | |
88 | [VE_TIMER23] = 0x10012000, | |
89 | [VE_SERIALDVI] = 0x10016000, | |
90 | [VE_RTC] = 0x10017000, | |
91 | [VE_COMPACTFLASH] = 0x1001a000, | |
92 | [VE_CLCD] = 0x1001f000, | |
93 | /* CS0: 0x40000000 .. 0x44000000 */ | |
94 | [VE_NORFLASH0] = 0x40000000, | |
95 | /* CS1: 0x44000000 .. 0x48000000 */ | |
96 | [VE_NORFLASH1] = 0x44000000, | |
97 | /* CS2: 0x48000000 .. 0x4a000000 */ | |
98 | [VE_SRAM] = 0x48000000, | |
99 | /* CS3: 0x4c000000 .. 0x50000000 */ | |
100 | [VE_VIDEORAM] = 0x4c000000, | |
101 | [VE_ETHERNET] = 0x4e000000, | |
102 | [VE_USB] = 0x4f000000, | |
2055283b PM |
103 | }; |
104 | ||
961f195e | 105 | static target_phys_addr_t motherboard_aseries_map[] = { |
3e1954cb FL |
106 | /* CS0: 0x08000000 .. 0x0c000000 */ |
107 | [VE_NORFLASH0] = 0x08000000, | |
961f195e PM |
108 | /* CS4: 0x0c000000 .. 0x10000000 */ |
109 | [VE_NORFLASH1] = 0x0c000000, | |
110 | /* CS5: 0x10000000 .. 0x14000000 */ | |
111 | /* CS1: 0x14000000 .. 0x18000000 */ | |
112 | [VE_SRAM] = 0x14000000, | |
113 | /* CS2: 0x18000000 .. 0x1c000000 */ | |
114 | [VE_VIDEORAM] = 0x18000000, | |
115 | [VE_ETHERNET] = 0x1a000000, | |
116 | [VE_USB] = 0x1b000000, | |
117 | /* CS3: 0x1c000000 .. 0x20000000 */ | |
118 | [VE_DAPROM] = 0x1c000000, | |
119 | [VE_SYSREGS] = 0x1c010000, | |
120 | [VE_SP810] = 0x1c020000, | |
121 | [VE_SERIALPCI] = 0x1c030000, | |
122 | [VE_PL041] = 0x1c040000, | |
123 | [VE_MMCI] = 0x1c050000, | |
124 | [VE_KMI0] = 0x1c060000, | |
125 | [VE_KMI1] = 0x1c070000, | |
126 | [VE_UART0] = 0x1c090000, | |
127 | [VE_UART1] = 0x1c0a0000, | |
128 | [VE_UART2] = 0x1c0b0000, | |
129 | [VE_UART3] = 0x1c0c0000, | |
130 | [VE_WDT] = 0x1c0f0000, | |
131 | [VE_TIMER01] = 0x1c110000, | |
132 | [VE_TIMER23] = 0x1c120000, | |
133 | [VE_SERIALDVI] = 0x1c160000, | |
134 | [VE_RTC] = 0x1c170000, | |
135 | [VE_COMPACTFLASH] = 0x1c1a0000, | |
136 | [VE_CLCD] = 0x1c1f0000, | |
137 | }; | |
138 | ||
4c3b29b8 PM |
139 | /* Structure defining the peculiarities of a specific daughterboard */ |
140 | ||
141 | typedef struct VEDBoardInfo VEDBoardInfo; | |
142 | ||
143 | typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, | |
144 | ram_addr_t ram_size, | |
145 | const char *cpu_model, | |
146 | qemu_irq *pic, uint32_t *proc_id); | |
147 | ||
148 | struct VEDBoardInfo { | |
149 | const target_phys_addr_t *motherboard_map; | |
150 | target_phys_addr_t loader_start; | |
96eacf64 | 151 | const target_phys_addr_t gic_cpu_if_addr; |
4c3b29b8 PM |
152 | DBoardInitFn *init; |
153 | }; | |
154 | ||
155 | static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, | |
156 | ram_addr_t ram_size, | |
157 | const char *cpu_model, | |
158 | qemu_irq *pic, uint32_t *proc_id) | |
2055283b | 159 | { |
e6d17b05 AK |
160 | MemoryRegion *sysmem = get_system_memory(); |
161 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
162 | MemoryRegion *lowram = g_new(MemoryRegion, 1); | |
4c3b29b8 | 163 | DeviceState *dev; |
2055283b PM |
164 | SysBusDevice *busdev; |
165 | qemu_irq *irqp; | |
2055283b PM |
166 | int n; |
167 | qemu_irq cpu_irq[4]; | |
4c3b29b8 | 168 | ram_addr_t low_ram_size; |
2055283b PM |
169 | |
170 | if (!cpu_model) { | |
171 | cpu_model = "cortex-a9"; | |
172 | } | |
173 | ||
4c3b29b8 PM |
174 | *proc_id = 0x0c000191; |
175 | ||
2055283b | 176 | for (n = 0; n < smp_cpus; n++) { |
64c9e297 AF |
177 | ARMCPU *cpu = cpu_arm_init(cpu_model); |
178 | if (!cpu) { | |
2055283b PM |
179 | fprintf(stderr, "Unable to find CPU definition\n"); |
180 | exit(1); | |
181 | } | |
4bd74661 | 182 | irqp = arm_pic_init_cpu(cpu); |
2055283b PM |
183 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
184 | } | |
185 | ||
186 | if (ram_size > 0x40000000) { | |
187 | /* 1GB is the maximum the address space permits */ | |
4c3b29b8 | 188 | fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n"); |
2055283b PM |
189 | exit(1); |
190 | } | |
191 | ||
c5705a77 AK |
192 | memory_region_init_ram(ram, "vexpress.highmem", ram_size); |
193 | vmstate_register_ram_global(ram); | |
2055283b PM |
194 | low_ram_size = ram_size; |
195 | if (low_ram_size > 0x4000000) { | |
196 | low_ram_size = 0x4000000; | |
197 | } | |
198 | /* RAM is from 0x60000000 upwards. The bottom 64MB of the | |
199 | * address space should in theory be remappable to various | |
200 | * things including ROM or RAM; we always map the RAM there. | |
201 | */ | |
e6d17b05 AK |
202 | memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size); |
203 | memory_region_add_subregion(sysmem, 0x0, lowram); | |
204 | memory_region_add_subregion(sysmem, 0x60000000, ram); | |
2055283b PM |
205 | |
206 | /* 0x1e000000 A9MPCore (SCU) private memory region */ | |
207 | dev = qdev_create(NULL, "a9mpcore_priv"); | |
208 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
209 | qdev_init_nofail(dev); | |
210 | busdev = sysbus_from_qdev(dev); | |
96eacf64 | 211 | sysbus_mmio_map(busdev, 0, 0x1e000000); |
2055283b PM |
212 | for (n = 0; n < smp_cpus; n++) { |
213 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
214 | } | |
215 | /* Interrupts [42:0] are from the motherboard; | |
216 | * [47:43] are reserved; [63:48] are daughterboard | |
217 | * peripherals. Note that some documentation numbers | |
218 | * external interrupts starting from 32 (because the | |
219 | * A9MP has internal interrupts 0..31). | |
220 | */ | |
221 | for (n = 0; n < 64; n++) { | |
222 | pic[n] = qdev_get_gpio_in(dev, n); | |
223 | } | |
224 | ||
4c3b29b8 PM |
225 | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ |
226 | ||
227 | /* 0x10020000 PL111 CLCD (daughterboard) */ | |
228 | sysbus_create_simple("pl111", 0x10020000, pic[44]); | |
229 | ||
230 | /* 0x10060000 AXI RAM */ | |
231 | /* 0x100e0000 PL341 Dynamic Memory Controller */ | |
232 | /* 0x100e1000 PL354 Static Memory Controller */ | |
233 | /* 0x100e2000 System Configuration Controller */ | |
234 | ||
235 | sysbus_create_simple("sp804", 0x100e4000, pic[48]); | |
236 | /* 0x100e5000 SP805 Watchdog module */ | |
237 | /* 0x100e6000 BP147 TrustZone Protection Controller */ | |
238 | /* 0x100e9000 PL301 'Fast' AXI matrix */ | |
239 | /* 0x100ea000 PL301 'Slow' AXI matrix */ | |
240 | /* 0x100ec000 TrustZone Address Space Controller */ | |
241 | /* 0x10200000 CoreSight debug APB */ | |
242 | /* 0x1e00a000 PL310 L2 Cache Controller */ | |
243 | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); | |
244 | } | |
245 | ||
246 | static const VEDBoardInfo a9_daughterboard = { | |
247 | .motherboard_map = motherboard_legacy_map, | |
248 | .loader_start = 0x60000000, | |
96eacf64 | 249 | .gic_cpu_if_addr = 0x1e000100, |
4c3b29b8 PM |
250 | .init = a9_daughterboard_init, |
251 | }; | |
252 | ||
961f195e PM |
253 | static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, |
254 | ram_addr_t ram_size, | |
255 | const char *cpu_model, | |
256 | qemu_irq *pic, uint32_t *proc_id) | |
257 | { | |
258 | int n; | |
961f195e PM |
259 | MemoryRegion *sysmem = get_system_memory(); |
260 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
261 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
262 | qemu_irq cpu_irq[4]; | |
263 | DeviceState *dev; | |
264 | SysBusDevice *busdev; | |
265 | ||
266 | if (!cpu_model) { | |
267 | cpu_model = "cortex-a15"; | |
268 | } | |
269 | ||
270 | *proc_id = 0x14000217; | |
271 | ||
272 | for (n = 0; n < smp_cpus; n++) { | |
64c9e297 | 273 | ARMCPU *cpu; |
961f195e | 274 | qemu_irq *irqp; |
64c9e297 AF |
275 | |
276 | cpu = cpu_arm_init(cpu_model); | |
277 | if (!cpu) { | |
961f195e PM |
278 | fprintf(stderr, "Unable to find CPU definition\n"); |
279 | exit(1); | |
280 | } | |
4bd74661 | 281 | irqp = arm_pic_init_cpu(cpu); |
961f195e PM |
282 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
283 | } | |
284 | ||
25d71699 PM |
285 | { |
286 | /* We have to use a separate 64 bit variable here to avoid the gcc | |
287 | * "comparison is always false due to limited range of data type" | |
288 | * warning if we are on a host where ram_addr_t is 32 bits. | |
289 | */ | |
290 | uint64_t rsz = ram_size; | |
291 | if (rsz > (30ULL * 1024 * 1024 * 1024)) { | |
292 | fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n"); | |
293 | exit(1); | |
294 | } | |
961f195e PM |
295 | } |
296 | ||
297 | memory_region_init_ram(ram, "vexpress.highmem", ram_size); | |
298 | vmstate_register_ram_global(ram); | |
299 | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ | |
300 | memory_region_add_subregion(sysmem, 0x80000000, ram); | |
301 | ||
302 | /* 0x2c000000 A15MPCore private memory region (GIC) */ | |
303 | dev = qdev_create(NULL, "a15mpcore_priv"); | |
304 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
305 | qdev_init_nofail(dev); | |
306 | busdev = sysbus_from_qdev(dev); | |
307 | sysbus_mmio_map(busdev, 0, 0x2c000000); | |
308 | for (n = 0; n < smp_cpus; n++) { | |
309 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
310 | } | |
311 | /* Interrupts [42:0] are from the motherboard; | |
312 | * [47:43] are reserved; [63:48] are daughterboard | |
313 | * peripherals. Note that some documentation numbers | |
314 | * external interrupts starting from 32 (because there | |
315 | * are internal interrupts 0..31). | |
316 | */ | |
317 | for (n = 0; n < 64; n++) { | |
318 | pic[n] = qdev_get_gpio_in(dev, n); | |
319 | } | |
320 | ||
321 | /* A15 daughterboard peripherals: */ | |
322 | ||
323 | /* 0x20000000: CoreSight interfaces: not modelled */ | |
324 | /* 0x2a000000: PL301 AXI interconnect: not modelled */ | |
325 | /* 0x2a420000: SCC: not modelled */ | |
326 | /* 0x2a430000: system counter: not modelled */ | |
327 | /* 0x2b000000: HDLCD controller: not modelled */ | |
328 | /* 0x2b060000: SP805 watchdog: not modelled */ | |
329 | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ | |
330 | /* 0x2e000000: system SRAM */ | |
331 | memory_region_init_ram(sram, "vexpress.a15sram", 0x10000); | |
332 | vmstate_register_ram_global(sram); | |
333 | memory_region_add_subregion(sysmem, 0x2e000000, sram); | |
334 | ||
335 | /* 0x7ffb0000: DMA330 DMA controller: not modelled */ | |
336 | /* 0x7ffd0000: PL354 static memory controller: not modelled */ | |
337 | } | |
338 | ||
339 | static const VEDBoardInfo a15_daughterboard = { | |
340 | .motherboard_map = motherboard_aseries_map, | |
341 | .loader_start = 0x80000000, | |
342 | .gic_cpu_if_addr = 0x2c002000, | |
343 | .init = a15_daughterboard_init, | |
344 | }; | |
345 | ||
4c3b29b8 PM |
346 | static void vexpress_common_init(const VEDBoardInfo *daughterboard, |
347 | ram_addr_t ram_size, | |
348 | const char *boot_device, | |
349 | const char *kernel_filename, | |
350 | const char *kernel_cmdline, | |
351 | const char *initrd_filename, | |
352 | const char *cpu_model) | |
353 | { | |
354 | DeviceState *dev, *sysctl, *pl041; | |
355 | qemu_irq pic[64]; | |
356 | uint32_t proc_id; | |
357 | uint32_t sys_id; | |
358 | ram_addr_t vram_size, sram_size; | |
359 | MemoryRegion *sysmem = get_system_memory(); | |
360 | MemoryRegion *vram = g_new(MemoryRegion, 1); | |
361 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
362 | const target_phys_addr_t *map = daughterboard->motherboard_map; | |
363 | ||
364 | daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id); | |
365 | ||
2558e0a6 PM |
366 | /* Motherboard peripherals: the wiring is the same but the |
367 | * addresses vary between the legacy and A-Series memory maps. | |
368 | */ | |
369 | ||
2055283b | 370 | sys_id = 0x1190f500; |
2055283b | 371 | |
2055283b PM |
372 | sysctl = qdev_create(NULL, "realview_sysctl"); |
373 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
2055283b | 374 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); |
7a65c8cc | 375 | qdev_init_nofail(sysctl); |
2558e0a6 PM |
376 | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]); |
377 | ||
378 | /* VE_SP810: not modelled */ | |
379 | /* VE_SERIALPCI: not modelled */ | |
2055283b | 380 | |
03a0e944 PM |
381 | pl041 = qdev_create(NULL, "pl041"); |
382 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
383 | qdev_init_nofail(pl041); | |
2558e0a6 | 384 | sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]); |
03a0e944 | 385 | sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]); |
2055283b | 386 | |
2558e0a6 | 387 | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
2055283b PM |
388 | /* Wire up MMC card detect and read-only signals */ |
389 | qdev_connect_gpio_out(dev, 0, | |
390 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); | |
391 | qdev_connect_gpio_out(dev, 1, | |
392 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); | |
393 | ||
2558e0a6 PM |
394 | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
395 | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); | |
2055283b | 396 | |
2558e0a6 PM |
397 | sysbus_create_simple("pl011", map[VE_UART0], pic[5]); |
398 | sysbus_create_simple("pl011", map[VE_UART1], pic[6]); | |
399 | sysbus_create_simple("pl011", map[VE_UART2], pic[7]); | |
400 | sysbus_create_simple("pl011", map[VE_UART3], pic[8]); | |
2055283b | 401 | |
2558e0a6 PM |
402 | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
403 | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); | |
2055283b | 404 | |
2558e0a6 | 405 | /* VE_SERIALDVI: not modelled */ |
2055283b | 406 | |
2558e0a6 | 407 | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
2055283b | 408 | |
2558e0a6 | 409 | /* VE_COMPACTFLASH: not modelled */ |
2055283b | 410 | |
b7206878 | 411 | sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); |
2055283b | 412 | |
2558e0a6 | 413 | /* VE_NORFLASH0: not modelled */ |
2558e0a6 PM |
414 | /* VE_NORFLASH1: not modelled */ |
415 | ||
2055283b | 416 | sram_size = 0x2000000; |
c5705a77 AK |
417 | memory_region_init_ram(sram, "vexpress.sram", sram_size); |
418 | vmstate_register_ram_global(sram); | |
2558e0a6 | 419 | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
2055283b | 420 | |
2055283b | 421 | vram_size = 0x800000; |
c5705a77 AK |
422 | memory_region_init_ram(vram, "vexpress.vram", vram_size); |
423 | vmstate_register_ram_global(vram); | |
2558e0a6 | 424 | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
2055283b PM |
425 | |
426 | /* 0x4e000000 LAN9118 Ethernet */ | |
a005d073 | 427 | if (nd_table[0].used) { |
2558e0a6 | 428 | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
2055283b PM |
429 | } |
430 | ||
2558e0a6 PM |
431 | /* VE_USB: not modelled */ |
432 | ||
433 | /* VE_DAPROM: not modelled */ | |
2055283b | 434 | |
2055283b PM |
435 | vexpress_binfo.ram_size = ram_size; |
436 | vexpress_binfo.kernel_filename = kernel_filename; | |
437 | vexpress_binfo.kernel_cmdline = kernel_cmdline; | |
438 | vexpress_binfo.initrd_filename = initrd_filename; | |
439 | vexpress_binfo.nb_cpus = smp_cpus; | |
440 | vexpress_binfo.board_id = VEXPRESS_BOARD_ID; | |
4c3b29b8 | 441 | vexpress_binfo.loader_start = daughterboard->loader_start; |
aac1e02c | 442 | vexpress_binfo.smp_loader_start = map[VE_SRAM]; |
2558e0a6 | 443 | vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; |
96eacf64 | 444 | vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; |
3aaa8dfa | 445 | arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo); |
2055283b PM |
446 | } |
447 | ||
4c3b29b8 PM |
448 | static void vexpress_a9_init(ram_addr_t ram_size, |
449 | const char *boot_device, | |
450 | const char *kernel_filename, | |
451 | const char *kernel_cmdline, | |
452 | const char *initrd_filename, | |
453 | const char *cpu_model) | |
454 | { | |
455 | vexpress_common_init(&a9_daughterboard, | |
456 | ram_size, boot_device, kernel_filename, | |
457 | kernel_cmdline, initrd_filename, cpu_model); | |
458 | } | |
2055283b | 459 | |
961f195e PM |
460 | static void vexpress_a15_init(ram_addr_t ram_size, |
461 | const char *boot_device, | |
462 | const char *kernel_filename, | |
463 | const char *kernel_cmdline, | |
464 | const char *initrd_filename, | |
465 | const char *cpu_model) | |
466 | { | |
467 | vexpress_common_init(&a15_daughterboard, | |
468 | ram_size, boot_device, kernel_filename, | |
469 | kernel_cmdline, initrd_filename, cpu_model); | |
470 | } | |
471 | ||
2055283b PM |
472 | static QEMUMachine vexpress_a9_machine = { |
473 | .name = "vexpress-a9", | |
474 | .desc = "ARM Versatile Express for Cortex-A9", | |
475 | .init = vexpress_a9_init, | |
476 | .use_scsi = 1, | |
477 | .max_cpus = 4, | |
478 | }; | |
479 | ||
961f195e PM |
480 | static QEMUMachine vexpress_a15_machine = { |
481 | .name = "vexpress-a15", | |
482 | .desc = "ARM Versatile Express for Cortex-A15", | |
483 | .init = vexpress_a15_init, | |
484 | .use_scsi = 1, | |
485 | .max_cpus = 4, | |
486 | }; | |
487 | ||
2055283b PM |
488 | static void vexpress_machine_init(void) |
489 | { | |
490 | qemu_register_machine(&vexpress_a9_machine); | |
961f195e | 491 | qemu_register_machine(&vexpress_a15_machine); |
2055283b PM |
492 | } |
493 | ||
494 | machine_init(vexpress_machine_init); |