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pci: helper functions to access PCIDevice::config
[qemu.git] / hw / vmware_vga.c
CommitLineData
d34cab9f
TS		 1/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB		 24#include "hw.h"
25#include "console.h"
26#include "pci.h"
d34cab9f
TS		 27
28#define VERBOSE
d34cab9f
TS		 29#undef DIRECT_VRAM
30#define HW_RECT_ACCEL
31#define HW_FILL_ACCEL
32#define HW_MOUSE_ACCEL
33
d34cab9f 34# include "vga_int.h"
d34cab9f
TS		 35
36struct vmsvga_state_s {
4e12cd94 37 VGACommonState vga;
d34cab9f
TS		 38
39 int width;
40 int height;
41 int invalidated;
42 int depth;
43 int bypp;
44 int enable;
45 int config;
46 struct {
47 int id;
48 int x;
49 int y;
50 int on;
51 } cursor;
52
c227f099 53 target_phys_addr_t vram_base;
d34cab9f
TS		 54
55 int index;
56 int scratch_size;
57 uint32_t *scratch;
58 int new_width;
59 int new_height;
60 uint32_t guest;
61 uint32_t svgaid;
62 uint32_t wred;
63 uint32_t wgreen;
64 uint32_t wblue;
65 int syncing;
66 int fb_size;
67
68 union {
69 uint32_t *fifo;
70 struct __attribute__((__packed__)) {
71 uint32_t min;
72 uint32_t max;
73 uint32_t next_cmd;
74 uint32_t stop;
75 /* Add registers here when adding capabilities. */
76 uint32_t fifo[0];
77 } *cmd;
78 };
79
80#define REDRAW_FIFO_LEN 512
81 struct vmsvga_rect_s {
82 int x, y, w, h;
83 } redraw_fifo[REDRAW_FIFO_LEN];
84 int redraw_fifo_first, redraw_fifo_last;
85};
86
87struct pci_vmsvga_state_s {
88 PCIDevice card;
89 struct vmsvga_state_s chip;
90};
91
92#define SVGA_MAGIC 0x900000UL
93#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
94#define SVGA_ID_0 SVGA_MAKE_ID(0)
95#define SVGA_ID_1 SVGA_MAKE_ID(1)
96#define SVGA_ID_2 SVGA_MAKE_ID(2)
97
98#define SVGA_LEGACY_BASE_PORT 0x4560
99#define SVGA_INDEX_PORT 0x0
100#define SVGA_VALUE_PORT 0x1
101#define SVGA_BIOS_PORT 0x2
102
103#define SVGA_VERSION_2
104
105#ifdef SVGA_VERSION_2
106# define SVGA_ID SVGA_ID_2
107# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
108# define SVGA_IO_MUL 1
109# define SVGA_FIFO_SIZE 0x10000
1f72aae5 110# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 111# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
112#else
113# define SVGA_ID SVGA_ID_1
114# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
115# define SVGA_IO_MUL 4
116# define SVGA_FIFO_SIZE 0x10000
1f72aae5 117# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 118# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
119#endif
120
121enum {
122 /* ID 0, 1 and 2 registers */
123 SVGA_REG_ID = 0,
124 SVGA_REG_ENABLE = 1,
125 SVGA_REG_WIDTH = 2,
126 SVGA_REG_HEIGHT = 3,
127 SVGA_REG_MAX_WIDTH = 4,
128 SVGA_REG_MAX_HEIGHT = 5,
129 SVGA_REG_DEPTH = 6,
130 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
131 SVGA_REG_PSEUDOCOLOR = 8,
132 SVGA_REG_RED_MASK = 9,
133 SVGA_REG_GREEN_MASK = 10,
134 SVGA_REG_BLUE_MASK = 11,
135 SVGA_REG_BYTES_PER_LINE = 12,
136 SVGA_REG_FB_START = 13,
137 SVGA_REG_FB_OFFSET = 14,
138 SVGA_REG_VRAM_SIZE = 15,
139 SVGA_REG_FB_SIZE = 16,
140
141 /* ID 1 and 2 registers */
142 SVGA_REG_CAPABILITIES = 17,
143 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
144 SVGA_REG_MEM_SIZE = 19,
145 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
146 SVGA_REG_SYNC = 21, /* Write to force synchronization */
147 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
148 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
149 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
150 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
151 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
152 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
153 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
154 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
155 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
156 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
157 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
158
159 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
160 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
161 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
162};
163
164#define SVGA_CAP_NONE 0
165#define SVGA_CAP_RECT_FILL (1 << 0)
166#define SVGA_CAP_RECT_COPY (1 << 1)
167#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
168#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
169#define SVGA_CAP_RASTER_OP (1 << 4)
170#define SVGA_CAP_CURSOR (1 << 5)
171#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
172#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
173#define SVGA_CAP_8BIT_EMULATION (1 << 8)
174#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
175#define SVGA_CAP_GLYPH (1 << 10)
176#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
177#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
178#define SVGA_CAP_ALPHA_BLEND (1 << 13)
179#define SVGA_CAP_3D (1 << 14)
180#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
181#define SVGA_CAP_MULTIMON (1 << 16)
182#define SVGA_CAP_PITCHLOCK (1 << 17)
183
184/*
185 * FIFO offsets (seen as an array of 32-bit words)
186 */
187enum {
188 /*
189 * The original defined FIFO offsets
190 */
191 SVGA_FIFO_MIN = 0,
192 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
193 SVGA_FIFO_NEXT_CMD,
194 SVGA_FIFO_STOP,
195
196 /*
197 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
198 */
199 SVGA_FIFO_CAPABILITIES = 4,
200 SVGA_FIFO_FLAGS,
201 SVGA_FIFO_FENCE,
202 SVGA_FIFO_3D_HWVERSION,
203 SVGA_FIFO_PITCHLOCK,
204};
205
206#define SVGA_FIFO_CAP_NONE 0
207#define SVGA_FIFO_CAP_FENCE (1 << 0)
208#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
209#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
210
211#define SVGA_FIFO_FLAG_NONE 0
212#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
213
214/* These values can probably be changed arbitrarily. */
215#define SVGA_SCRATCH_SIZE 0x8000
216#define SVGA_MAX_WIDTH 2360
217#define SVGA_MAX_HEIGHT 1770
218
219#ifdef VERBOSE
220# define GUEST_OS_BASE 0x5001
221static const char *vmsvga_guest_id[] = {
f707cfba
AZ		 222 [0x00] = "Dos",
223 [0x01] = "Windows 3.1",
224 [0x02] = "Windows 95",
225 [0x03] = "Windows 98",
226 [0x04] = "Windows ME",
227 [0x05] = "Windows NT",
228 [0x06] = "Windows 2000",
229 [0x07] = "Linux",
230 [0x08] = "OS/2",
511d2b14 231 [0x09] = "an unknown OS",
f707cfba
AZ		 232 [0x0a] = "BSD",
233 [0x0b] = "Whistler",
511d2b14
BS		 234 [0x0c] = "an unknown OS",
235 [0x0d] = "an unknown OS",
236 [0x0e] = "an unknown OS",
237 [0x0f] = "an unknown OS",
238 [0x10] = "an unknown OS",
239 [0x11] = "an unknown OS",
240 [0x12] = "an unknown OS",
241 [0x13] = "an unknown OS",
242 [0x14] = "an unknown OS",
f707cfba 243 [0x15] = "Windows 2003",
d34cab9f
TS		 244};
245#endif
246
247enum {
248 SVGA_CMD_INVALID_CMD = 0,
249 SVGA_CMD_UPDATE = 1,
250 SVGA_CMD_RECT_FILL = 2,
251 SVGA_CMD_RECT_COPY = 3,
252 SVGA_CMD_DEFINE_BITMAP = 4,
253 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
254 SVGA_CMD_DEFINE_PIXMAP = 6,
255 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
256 SVGA_CMD_RECT_BITMAP_FILL = 8,
257 SVGA_CMD_RECT_PIXMAP_FILL = 9,
258 SVGA_CMD_RECT_BITMAP_COPY = 10,
259 SVGA_CMD_RECT_PIXMAP_COPY = 11,
260 SVGA_CMD_FREE_OBJECT = 12,
261 SVGA_CMD_RECT_ROP_FILL = 13,
262 SVGA_CMD_RECT_ROP_COPY = 14,
263 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
264 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
265 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
266 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
267 SVGA_CMD_DEFINE_CURSOR = 19,
268 SVGA_CMD_DISPLAY_CURSOR = 20,
269 SVGA_CMD_MOVE_CURSOR = 21,
270 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
271 SVGA_CMD_DRAW_GLYPH = 23,
272 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
273 SVGA_CMD_UPDATE_VERBOSE = 25,
274 SVGA_CMD_SURFACE_FILL = 26,
275 SVGA_CMD_SURFACE_COPY = 27,
276 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
277 SVGA_CMD_FRONT_ROP_FILL = 29,
278 SVGA_CMD_FENCE = 30,
279};
280
281/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
282enum {
283 SVGA_CURSOR_ON_HIDE = 0,
284 SVGA_CURSOR_ON_SHOW = 1,
285 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
286 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
287};
288
289static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
290 int x, int y, int w, int h)
291{
292#ifndef DIRECT_VRAM
a8fbaf96
AZ		 293 int line;
294 int bypl;
295 int width;
296 int start;
297 uint8_t *src;
298 uint8_t *dst;
299
300 if (x + w > s->width) {
301 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
302 __FUNCTION__, x, w);
303 x = MIN(x, s->width);
304 w = s->width - x;
305 }
306
307 if (y + h > s->height) {
308 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
309 __FUNCTION__, y, h);
310 y = MIN(y, s->height);
311 h = s->height - y;
312 }
313
314 line = h;
315 bypl = s->bypp * s->width;
316 width = s->bypp * w;
317 start = s->bypp * x + bypl * y;
4e12cd94
AK		 318 src = s->vga.vram_ptr + start;
319 dst = ds_get_data(s->vga.ds) + start;
d34cab9f
TS		 320
321 for (; line > 0; line --, src += bypl, dst += bypl)
322 memcpy(dst, src, width);
323#endif
324
4e12cd94 325 dpy_update(s->vga.ds, x, y, w, h);
d34cab9f
TS		 326}
327
328static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
329{
330#ifndef DIRECT_VRAM
4e12cd94 331 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
d34cab9f
TS		 332#endif
333
4e12cd94 334 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
d34cab9f
TS		 335}
336
337#ifdef DIRECT_VRAM
338# define vmsvga_update_rect_delayed vmsvga_update_rect
339#else
340static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
341 int x, int y, int w, int h)
342{
343 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
344 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
345 rect->x = x;
346 rect->y = y;
347 rect->w = w;
348 rect->h = h;
349}
350#endif
351
352static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
353{
354 struct vmsvga_rect_s *rect;
355 if (s->invalidated) {
356 s->redraw_fifo_first = s->redraw_fifo_last;
357 return;
358 }
359 /* Overlapping region updates can be optimised out here - if someone
360 * knows a smart algorithm to do that, please share. */
361 while (s->redraw_fifo_first != s->redraw_fifo_last) {
362 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
363 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
364 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
365 }
366}
367
368#ifdef HW_RECT_ACCEL
369static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
370 int x0, int y0, int x1, int y1, int w, int h)
371{
372# ifdef DIRECT_VRAM
0e1f5a0c 373 uint8_t *vram = ds_get_data(s->ds);
d34cab9f 374# else
4e12cd94 375 uint8_t *vram = s->vga.vram_ptr;
d34cab9f
TS		 376# endif
377 int bypl = s->bypp * s->width;
378 int width = s->bypp * w;
379 int line = h;
380 uint8_t *ptr[2];
381
382# ifdef DIRECT_VRAM
383 if (s->ds->dpy_copy)
3023f332 384 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
d34cab9f
TS		 385 else
386# endif
387 {
388 if (y1 > y0) {
389 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
390 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
391 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
392 memmove(ptr[1], ptr[0], width);
393 } else {
394 ptr[0] = vram + s->bypp * x0 + bypl * y0;
395 ptr[1] = vram + s->bypp * x1 + bypl * y1;
396 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
397 memmove(ptr[1], ptr[0], width);
398 }
399 }
400
401 vmsvga_update_rect_delayed(s, x1, y1, w, h);
402}
403#endif
404
405#ifdef HW_FILL_ACCEL
406static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
407 uint32_t c, int x, int y, int w, int h)
408{
409# ifdef DIRECT_VRAM
0e1f5a0c 410 uint8_t *vram = ds_get_data(s->ds);
d34cab9f 411# else
4e12cd94 412 uint8_t *vram = s->vga.vram_ptr;
d34cab9f
TS		 413# endif
414 int bypp = s->bypp;
415 int bypl = bypp * s->width;
416 int width = bypp * w;
417 int line = h;
418 int column;
419 uint8_t *fst = vram + bypp * x + bypl * y;
420 uint8_t *dst;
421 uint8_t *src;
422 uint8_t col[4];
423
424# ifdef DIRECT_VRAM
425 if (s->ds->dpy_fill)
426 s->ds->dpy_fill(s->ds, x, y, w, h, c);
427 else
428# endif
429 {
430 col[0] = c;
431 col[1] = c >> 8;
432 col[2] = c >> 16;
433 col[3] = c >> 24;
434
435 if (line --) {
436 dst = fst;
437 src = col;
438 for (column = width; column > 0; column --) {
439 *(dst ++) = *(src ++);
440 if (src - col == bypp)
441 src = col;
442 }
443 dst = fst;
444 for (; line > 0; line --) {
445 dst += bypl;
446 memcpy(dst, fst, width);
447 }
448 }
449 }
450
451 vmsvga_update_rect_delayed(s, x, y, w, h);
452}
453#endif
454
455struct vmsvga_cursor_definition_s {
456 int width;
457 int height;
458 int id;
459 int bpp;
460 int hot_x;
461 int hot_y;
462 uint32_t mask[1024];
463 uint32_t image[1024];
464};
465
466#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
467#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
468
469#ifdef HW_MOUSE_ACCEL
470static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
471 struct vmsvga_cursor_definition_s *c)
472{
473 int i;
474 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
475 c->mask[i] = ~c->mask[i];
476
4e12cd94
AK		 477 if (s->vga.ds->cursor_define)
478 s->vga.ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
d34cab9f
TS		 479 (uint8_t *) c->image, (uint8_t *) c->mask);
480}
481#endif
482
ff9cf2cb
AZ		 483#define CMD(f) le32_to_cpu(s->cmd->f)
484
d34cab9f
TS		 485static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
486{
487 if (!s->config || !s->enable)
f707cfba 488 return 1;
d34cab9f
TS		 489 return (s->cmd->next_cmd == s->cmd->stop);
490}
491
ff9cf2cb 492static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
d34cab9f 493{
ff9cf2cb
AZ		 494 uint32_t cmd = s->fifo[CMD(stop) >> 2];
495 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
496 if (CMD(stop) >= CMD(max))
d34cab9f
TS		 497 s->cmd->stop = s->cmd->min;
498 return cmd;
499}
500
ff9cf2cb
AZ		 501static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
502{
503 return le32_to_cpu(vmsvga_fifo_read_raw(s));
504}
505
d34cab9f
TS		 506static void vmsvga_fifo_run(struct vmsvga_state_s *s)
507{
508 uint32_t cmd, colour;
509 int args = 0;
510 int x, y, dx, dy, width, height;
511 struct vmsvga_cursor_definition_s cursor;
512 while (!vmsvga_fifo_empty(s))
513 switch (cmd = vmsvga_fifo_read(s)) {
514 case SVGA_CMD_UPDATE:
515 case SVGA_CMD_UPDATE_VERBOSE:
516 x = vmsvga_fifo_read(s);
517 y = vmsvga_fifo_read(s);
518 width = vmsvga_fifo_read(s);
519 height = vmsvga_fifo_read(s);
520 vmsvga_update_rect_delayed(s, x, y, width, height);
521 break;
522
523 case SVGA_CMD_RECT_FILL:
524 colour = vmsvga_fifo_read(s);
525 x = vmsvga_fifo_read(s);
526 y = vmsvga_fifo_read(s);
527 width = vmsvga_fifo_read(s);
528 height = vmsvga_fifo_read(s);
529#ifdef HW_FILL_ACCEL
530 vmsvga_fill_rect(s, colour, x, y, width, height);
531 break;
532#else
533 goto badcmd;
534#endif
535
536 case SVGA_CMD_RECT_COPY:
537 x = vmsvga_fifo_read(s);
538 y = vmsvga_fifo_read(s);
539 dx = vmsvga_fifo_read(s);
540 dy = vmsvga_fifo_read(s);
541 width = vmsvga_fifo_read(s);
542 height = vmsvga_fifo_read(s);
543#ifdef HW_RECT_ACCEL
544 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
545 break;
546#else
547 goto badcmd;
548#endif
549
550 case SVGA_CMD_DEFINE_CURSOR:
551 cursor.id = vmsvga_fifo_read(s);
552 cursor.hot_x = vmsvga_fifo_read(s);
553 cursor.hot_y = vmsvga_fifo_read(s);
554 cursor.width = x = vmsvga_fifo_read(s);
555 cursor.height = y = vmsvga_fifo_read(s);
556 vmsvga_fifo_read(s);
557 cursor.bpp = vmsvga_fifo_read(s);
558 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
ff9cf2cb 559 cursor.mask[args] = vmsvga_fifo_read_raw(s);
d34cab9f 560 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
ff9cf2cb 561 cursor.image[args] = vmsvga_fifo_read_raw(s);
d34cab9f
TS		 562#ifdef HW_MOUSE_ACCEL
563 vmsvga_cursor_define(s, &cursor);
564 break;
565#else
566 args = 0;
567 goto badcmd;
568#endif
569
570 /*
571 * Other commands that we at least know the number of arguments
572 * for so we can avoid FIFO desync if driver uses them illegally.
573 */
574 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
575 vmsvga_fifo_read(s);
576 vmsvga_fifo_read(s);
577 vmsvga_fifo_read(s);
578 x = vmsvga_fifo_read(s);
579 y = vmsvga_fifo_read(s);
580 args = x * y;
581 goto badcmd;
582 case SVGA_CMD_RECT_ROP_FILL:
583 args = 6;
584 goto badcmd;
585 case SVGA_CMD_RECT_ROP_COPY:
586 args = 7;
587 goto badcmd;
588 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
589 vmsvga_fifo_read(s);
590 vmsvga_fifo_read(s);
591 args = 7 + (vmsvga_fifo_read(s) >> 2);
592 goto badcmd;
593 case SVGA_CMD_SURFACE_ALPHA_BLEND:
594 args = 12;
595 goto badcmd;
596
597 /*
598 * Other commands that are not listed as depending on any
599 * CAPABILITIES bits, but are not described in the README either.
600 */
601 case SVGA_CMD_SURFACE_FILL:
602 case SVGA_CMD_SURFACE_COPY:
603 case SVGA_CMD_FRONT_ROP_FILL:
604 case SVGA_CMD_FENCE:
605 case SVGA_CMD_INVALID_CMD:
606 break; /* Nop */
607
608 default:
609 badcmd:
610 while (args --)
611 vmsvga_fifo_read(s);
612 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
613 __FUNCTION__, cmd);
614 break;
615 }
616
617 s->syncing = 0;
618}
619
620static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
621{
467d44b2 622 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 623 return s->index;
624}
625
626static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
627{
467d44b2 628 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 629 s->index = index;
630}
631
632static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
633{
634 uint32_t caps;
467d44b2 635 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 636 switch (s->index) {
637 case SVGA_REG_ID:
638 return s->svgaid;
639
640 case SVGA_REG_ENABLE:
641 return s->enable;
642
643 case SVGA_REG_WIDTH:
644 return s->width;
645
646 case SVGA_REG_HEIGHT:
647 return s->height;
648
649 case SVGA_REG_MAX_WIDTH:
650 return SVGA_MAX_WIDTH;
651
652 case SVGA_REG_MAX_HEIGHT:
f707cfba 653 return SVGA_MAX_HEIGHT;
d34cab9f
TS		 654
655 case SVGA_REG_DEPTH:
656 return s->depth;
657
658 case SVGA_REG_BITS_PER_PIXEL:
659 return (s->depth + 7) & ~7;
660
661 case SVGA_REG_PSEUDOCOLOR:
662 return 0x0;
663
664 case SVGA_REG_RED_MASK:
665 return s->wred;
666 case SVGA_REG_GREEN_MASK:
667 return s->wgreen;
668 case SVGA_REG_BLUE_MASK:
669 return s->wblue;
670
671 case SVGA_REG_BYTES_PER_LINE:
672 return ((s->depth + 7) >> 3) * s->new_width;
673
674 case SVGA_REG_FB_START:
3016d80b 675 return s->vram_base;
d34cab9f
TS		 676
677 case SVGA_REG_FB_OFFSET:
678 return 0x0;
679
680 case SVGA_REG_VRAM_SIZE:
4e12cd94 681 return s->vga.vram_size - SVGA_FIFO_SIZE;
d34cab9f
TS		 682
683 case SVGA_REG_FB_SIZE:
684 return s->fb_size;
685
686 case SVGA_REG_CAPABILITIES:
687 caps = SVGA_CAP_NONE;
688#ifdef HW_RECT_ACCEL
689 caps |= SVGA_CAP_RECT_COPY;
690#endif
691#ifdef HW_FILL_ACCEL
692 caps |= SVGA_CAP_RECT_FILL;
693#endif
694#ifdef HW_MOUSE_ACCEL
4e12cd94 695 if (s->vga.ds->mouse_set)
d34cab9f
TS		 696 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
697 SVGA_CAP_CURSOR_BYPASS;
698#endif
699 return caps;
700
701 case SVGA_REG_MEM_START:
4e12cd94 702 return s->vram_base + s->vga.vram_size - SVGA_FIFO_SIZE;
d34cab9f
TS		 703
704 case SVGA_REG_MEM_SIZE:
705 return SVGA_FIFO_SIZE;
706
707 case SVGA_REG_CONFIG_DONE:
708 return s->config;
709
710 case SVGA_REG_SYNC:
711 case SVGA_REG_BUSY:
712 return s->syncing;
713
714 case SVGA_REG_GUEST_ID:
715 return s->guest;
716
717 case SVGA_REG_CURSOR_ID:
718 return s->cursor.id;
719
720 case SVGA_REG_CURSOR_X:
721 return s->cursor.x;
722
723 case SVGA_REG_CURSOR_Y:
724 return s->cursor.x;
725
726 case SVGA_REG_CURSOR_ON:
727 return s->cursor.on;
728
729 case SVGA_REG_HOST_BITS_PER_PIXEL:
730 return (s->depth + 7) & ~7;
731
732 case SVGA_REG_SCRATCH_SIZE:
733 return s->scratch_size;
734
735 case SVGA_REG_MEM_REGS:
736 case SVGA_REG_NUM_DISPLAYS:
737 case SVGA_REG_PITCHLOCK:
738 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
739 return 0;
740
741 default:
742 if (s->index >= SVGA_SCRATCH_BASE &&
743 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
744 return s->scratch[s->index - SVGA_SCRATCH_BASE];
745 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
746 }
747
748 return 0;
749}
750
751static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
752{
467d44b2 753 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 754 switch (s->index) {
755 case SVGA_REG_ID:
756 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
757 s->svgaid = value;
758 break;
759
760 case SVGA_REG_ENABLE:
f707cfba
AZ		 761 s->enable = value;
762 s->config &= !!value;
d34cab9f
TS		 763 s->width = -1;
764 s->height = -1;
765 s->invalidated = 1;
4e12cd94 766 s->vga.invalidate(&s->vga);
d34cab9f
TS		 767 if (s->enable)
768 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
769 break;
770
771 case SVGA_REG_WIDTH:
772 s->new_width = value;
773 s->invalidated = 1;
774 break;
775
776 case SVGA_REG_HEIGHT:
777 s->new_height = value;
778 s->invalidated = 1;
779 break;
780
781 case SVGA_REG_DEPTH:
782 case SVGA_REG_BITS_PER_PIXEL:
783 if (value != s->depth) {
784 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
785 s->config = 0;
786 }
787 break;
788
789 case SVGA_REG_CONFIG_DONE:
790 if (value) {
4e12cd94 791 s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
d34cab9f 792 /* Check range and alignment. */
ff9cf2cb
AZ		 793 if ((CMD(min) | CMD(max) |
794 CMD(next_cmd) | CMD(stop)) & 3)
d34cab9f 795 break;
ff9cf2cb 796 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
d34cab9f 797 break;
ff9cf2cb 798 if (CMD(max) > SVGA_FIFO_SIZE)
d34cab9f 799 break;
ff9cf2cb 800 if (CMD(max) < CMD(min) + 10 * 1024)
d34cab9f
TS		 801 break;
802 }
f707cfba 803 s->config = !!value;
d34cab9f
TS		 804 break;
805
806 case SVGA_REG_SYNC:
807 s->syncing = 1;
808 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
809 break;
810
811 case SVGA_REG_GUEST_ID:
812 s->guest = value;
813#ifdef VERBOSE
814 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
b1503cda 815 ARRAY_SIZE(vmsvga_guest_id))
d34cab9f
TS		 816 printf("%s: guest runs %s.\n", __FUNCTION__,
817 vmsvga_guest_id[value - GUEST_OS_BASE]);
818#endif
819 break;
820
821 case SVGA_REG_CURSOR_ID:
822 s->cursor.id = value;
823 break;
824
825 case SVGA_REG_CURSOR_X:
826 s->cursor.x = value;
827 break;
828
829 case SVGA_REG_CURSOR_Y:
830 s->cursor.y = value;
831 break;
832
833 case SVGA_REG_CURSOR_ON:
834 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
835 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
836#ifdef HW_MOUSE_ACCEL
4e12cd94
AK		 837 if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
838 s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
d34cab9f
TS		 839#endif
840 break;
841
842 case SVGA_REG_MEM_REGS:
843 case SVGA_REG_NUM_DISPLAYS:
844 case SVGA_REG_PITCHLOCK:
845 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
846 break;
847
848 default:
849 if (s->index >= SVGA_SCRATCH_BASE &&
850 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
851 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
852 break;
853 }
854 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
855 }
856}
857
858static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
859{
860 printf("%s: what are we supposed to return?\n", __FUNCTION__);
861 return 0xcafe;
862}
863
864static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
865{
866 printf("%s: what are we supposed to do with (%08x)?\n",
867 __FUNCTION__, data);
868}
869
870static inline void vmsvga_size(struct vmsvga_state_s *s)
871{
872 if (s->new_width != s->width || s->new_height != s->height) {
873 s->width = s->new_width;
874 s->height = s->new_height;
4e12cd94 875 qemu_console_resize(s->vga.ds, s->width, s->height);
d34cab9f
TS		 876 s->invalidated = 1;
877 }
878}
879
880static void vmsvga_update_display(void *opaque)
881{
467d44b2 882 struct vmsvga_state_s *s = opaque;
d34cab9f 883 if (!s->enable) {
4e12cd94 884 s->vga.update(&s->vga);
d34cab9f
TS		 885 return;
886 }
887
888 vmsvga_size(s);
889
890 vmsvga_fifo_run(s);
891 vmsvga_update_rect_flush(s);
892
893 /*
894 * Is it more efficient to look at vram VGA-dirty bits or wait
895 * for the driver to issue SVGA_CMD_UPDATE?
896 */
897 if (s->invalidated) {
898 s->invalidated = 0;
899 vmsvga_update_screen(s);
900 }
901}
902
903static void vmsvga_reset(struct vmsvga_state_s *s)
904{
905 s->index = 0;
906 s->enable = 0;
907 s->config = 0;
908 s->width = -1;
909 s->height = -1;
910 s->svgaid = SVGA_ID;
4445b0a6 911 s->depth = 24;
d34cab9f
TS		 912 s->bypp = (s->depth + 7) >> 3;
913 s->cursor.on = 0;
914 s->redraw_fifo_first = 0;
915 s->redraw_fifo_last = 0;
916 switch (s->depth) {
917 case 8:
918 s->wred = 0x00000007;
919 s->wgreen = 0x00000038;
920 s->wblue = 0x000000c0;
921 break;
922 case 15:
923 s->wred = 0x0000001f;
924 s->wgreen = 0x000003e0;
925 s->wblue = 0x00007c00;
926 break;
927 case 16:
928 s->wred = 0x0000001f;
929 s->wgreen = 0x000007e0;
930 s->wblue = 0x0000f800;
931 break;
932 case 24:
f707cfba 933 s->wred = 0x00ff0000;
d34cab9f 934 s->wgreen = 0x0000ff00;
f707cfba 935 s->wblue = 0x000000ff;
d34cab9f
TS		 936 break;
937 case 32:
f707cfba 938 s->wred = 0x00ff0000;
d34cab9f 939 s->wgreen = 0x0000ff00;
f707cfba 940 s->wblue = 0x000000ff;
d34cab9f
TS		 941 break;
942 }
943 s->syncing = 0;
944}
945
946static void vmsvga_invalidate_display(void *opaque)
947{
467d44b2 948 struct vmsvga_state_s *s = opaque;
d34cab9f 949 if (!s->enable) {
4e12cd94 950 s->vga.invalidate(&s->vga);
d34cab9f
TS		 951 return;
952 }
953
954 s->invalidated = 1;
955}
956
f707cfba
AZ		 957/* save the vga display in a PPM image even if no display is
958 available */
d34cab9f
TS		 959static void vmsvga_screen_dump(void *opaque, const char *filename)
960{
467d44b2 961 struct vmsvga_state_s *s = opaque;
d34cab9f 962 if (!s->enable) {
4e12cd94 963 s->vga.screen_dump(&s->vga, filename);
d34cab9f
TS		 964 return;
965 }
966
f707cfba 967 if (s->depth == 32) {
e07d630a 968 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
4e12cd94 969 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
e07d630a
AL		 970 ppm_save(filename, ds);
971 qemu_free(ds);
f707cfba 972 }
d34cab9f
TS		 973}
974
c227f099 975static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
4d3b6f6e 976{
467d44b2 977 struct vmsvga_state_s *s = opaque;
4d3b6f6e 978
4e12cd94
AK		 979 if (s->vga.text_update)
980 s->vga.text_update(&s->vga, chardata);
4d3b6f6e
AZ		 981}
982
d34cab9f 983#ifdef DIRECT_VRAM
c227f099 984static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
d34cab9f 985{
467d44b2 986 struct vmsvga_state_s *s = opaque;
d34cab9f 987 if (addr < s->fb_size)
0e1f5a0c 988 return *(uint8_t *) (ds_get_data(s->ds) + addr);
d34cab9f 989 else
b584726d 990 return *(uint8_t *) (s->vram_ptr + addr);
d34cab9f
TS		 991}
992
c227f099 993static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
d34cab9f 994{
467d44b2 995 struct vmsvga_state_s *s = opaque;
d34cab9f 996 if (addr < s->fb_size)
0e1f5a0c 997 return *(uint16_t *) (ds_get_data(s->ds) + addr);
d34cab9f 998 else
b584726d 999 return *(uint16_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1000}
1001
c227f099 1002static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
d34cab9f 1003{
467d44b2 1004 struct vmsvga_state_s *s = opaque;
d34cab9f 1005 if (addr < s->fb_size)
0e1f5a0c 1006 return *(uint32_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1007 else
b584726d 1008 return *(uint32_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1009}
1010
c227f099 1011static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1012 uint32_t value)
1013{
467d44b2 1014 struct vmsvga_state_s *s = opaque;
d34cab9f 1015 if (addr < s->fb_size)
0e1f5a0c 1016 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1017 else
b584726d 1018 *(uint8_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1019}
1020
c227f099 1021static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1022 uint32_t value)
1023{
467d44b2 1024 struct vmsvga_state_s *s = opaque;
d34cab9f 1025 if (addr < s->fb_size)
0e1f5a0c 1026 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1027 else
b584726d 1028 *(uint16_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1029}
1030
c227f099 1031static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1032 uint32_t value)
1033{
467d44b2 1034 struct vmsvga_state_s *s = opaque;
d34cab9f 1035 if (addr < s->fb_size)
0e1f5a0c 1036 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1037 else
b584726d 1038 *(uint32_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1039}
1040
d60efc6b 1041static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
d34cab9f
TS		 1042 vmsvga_vram_readb,
1043 vmsvga_vram_readw,
1044 vmsvga_vram_readl,
1045};
1046
d60efc6b 1047static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
d34cab9f
TS		 1048 vmsvga_vram_writeb,
1049 vmsvga_vram_writew,
1050 vmsvga_vram_writel,
1051};
1052#endif
1053
bacbe284 1054static int vmsvga_post_load(void *opaque, int version_id)
d34cab9f 1055{
bacbe284 1056 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 1057
1058 s->invalidated = 1;
1059 if (s->config)
4e12cd94 1060 s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
d34cab9f
TS		 1061
1062 return 0;
1063}
1064
bacbe284
JQ		 1065const VMStateDescription vmstate_vmware_vga_internal = {
1066 .name = "vmware_vga_internal",
1067 .version_id = 0,
1068 .minimum_version_id = 0,
1069 .minimum_version_id_old = 0,
1070 .post_load = vmsvga_post_load,
1071 .fields = (VMStateField []) {
1072 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1073 VMSTATE_INT32(enable, struct vmsvga_state_s),
1074 VMSTATE_INT32(config, struct vmsvga_state_s),
1075 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1076 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1077 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1078 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1079 VMSTATE_INT32(index, struct vmsvga_state_s),
1080 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1081 scratch_size, 0, vmstate_info_uint32, uint32_t),
1082 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1083 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1084 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1085 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1086 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1087 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1088 VMSTATE_END_OF_LIST()
1089 }
1090};
1091
1092const VMStateDescription vmstate_vmware_vga = {
1093 .name = "vmware_vga",
1094 .version_id = 0,
1095 .minimum_version_id = 0,
1096 .minimum_version_id_old = 0,
1097 .fields = (VMStateField []) {
1098 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1099 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1100 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1101 VMSTATE_END_OF_LIST()
1102 }
1103};
1104
b584726d 1105static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
d34cab9f 1106{
d34cab9f 1107 s->scratch_size = SVGA_SCRATCH_SIZE;
fe740c43 1108 s->scratch = qemu_malloc(s->scratch_size * 4);
d34cab9f 1109
4445b0a6
AZ		 1110 vmsvga_reset(s);
1111
a4a2f59c
JQ		 1112 vga_common_init(&s->vga, vga_ram_size);
1113 vga_init(&s->vga);
f74599c4 1114 vmstate_register(0, &vmstate_vga_common, &s->vga);
e93a5f4f 1115
4e12cd94
AK		 1116 s->vga.ds = graphic_console_init(vmsvga_update_display,
1117 vmsvga_invalidate_display,
1118 vmsvga_screen_dump,
c89507f7 1119 vmsvga_text_update, s);
931ea435
AZ		 1120
1121#ifdef CONFIG_BOCHS_VBE
1122 /* XXX: use optimized standard vga accesses */
1123 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
4e12cd94 1124 vga_ram_size, s->vga.vram_offset);
931ea435 1125#endif
d34cab9f
TS		 1126}
1127
1492a3c4
AZ		 1128static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1129 uint32_t addr, uint32_t size, int type)
1130{
1131 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1132 struct vmsvga_state_s *s = &d->chip;
1133
1134 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1135 1, 4, vmsvga_index_read, s);
1136 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1137 1, 4, vmsvga_index_write, s);
1138 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1139 1, 4, vmsvga_value_read, s);
1140 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1141 1, 4, vmsvga_value_write, s);
1142 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1143 1, 4, vmsvga_bios_read, s);
1144 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1145 1, 4, vmsvga_bios_write, s);
1146}
1147
3016d80b
AZ		 1148static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1149 uint32_t addr, uint32_t size, int type)
1150{
1151 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1152 struct vmsvga_state_s *s = &d->chip;
c227f099 1153 ram_addr_t iomemtype;
3016d80b
AZ		 1154
1155 s->vram_base = addr;
1156#ifdef DIRECT_VRAM
1eed09cb 1157 iomemtype = cpu_register_io_memory(vmsvga_vram_read,
3016d80b
AZ		 1158 vmsvga_vram_write, s);
1159#else
4e12cd94 1160 iomemtype = s->vga.vram_offset | IO_MEM_RAM;
3016d80b 1161#endif
4e12cd94 1162 cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
3016d80b
AZ		 1163 iomemtype);
1164}
1165
81a322d4 1166static int pci_vmsvga_initfn(PCIDevice *dev)
d34cab9f 1167{
a414c306
GH		 1168 struct pci_vmsvga_state_s *s =
1169 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
d34cab9f 1170
deb54399
AL		 1171 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1172 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
d34cab9f 1173 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
173a543b 1174 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
d34cab9f
TS		 1175 s->card.config[0x0c] = 0x08; /* Cache line size */
1176 s->card.config[0x0d] = 0x40; /* Latency timer */
6407f373 1177 s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
d34cab9f
TS		 1178 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1179 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1180 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1181 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1182 s->card.config[0x3c] = 0xff; /* End */
1183
28c2c264 1184 pci_register_bar(&s->card, 0, 0x10,
1492a3c4 1185 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
28c2c264 1186 pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
3016d80b 1187 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1492a3c4 1188
fbe1b595 1189 vmsvga_init(&s->chip, VGA_RAM_SIZE);
d34cab9f 1190
bacbe284 1191 vmstate_register(0, &vmstate_vmware_vga, s);
81a322d4 1192 return 0;
d34cab9f 1193}
a414c306
GH		 1194
1195void pci_vmsvga_init(PCIBus *bus)
1196{
1197 pci_create_simple(bus, -1, "QEMUware SVGA");
1198}
1199
1200static PCIDeviceInfo vmsvga_info = {
1201 .qdev.name = "QEMUware SVGA",
1202 .qdev.size = sizeof(struct pci_vmsvga_state_s),
1203 .init = pci_vmsvga_initfn,
1204};
1205
1206static void vmsvga_register(void)
1207{
1208 pci_qdev_register(&vmsvga_info);
1209}
1210device_init(vmsvga_register);
Qemu copy for testing