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1da177e4 LT |
1 | /* |
2 | * linux/include/asm-arm/arch-omap/mux.h | |
3 | * | |
4 | * Table of the Omap register configurations for the FUNC_MUX and | |
5 | * PULL_DWN combinations. | |
6 | * | |
9330899e TL |
7 | * Copyright (C) 2004 - 2008 Texas Instruments Inc. |
8 | * Copyright (C) 2003 - 2008 Nokia Corporation | |
1da177e4 | 9 | * |
9330899e | 10 | * Written by Tony Lindgren |
1da177e4 LT |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | * NOTE: Please use the following naming style for new pin entries. | |
27 | * For example, W8_1610_MMC2_DAT0, where: | |
28 | * - W8 = ball | |
29 | * - 1610 = 1510 or 1610, none if common for both 1510 and 1610 | |
30 | * - MMC2_DAT0 = function | |
1da177e4 LT |
31 | */ |
32 | ||
33 | #ifndef __ASM_ARCH_MUX_H | |
34 | #define __ASM_ARCH_MUX_H | |
35 | ||
36 | #define PU_PD_SEL_NA 0 /* No pu_pd reg available */ | |
37 | #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ | |
38 | ||
39 | #ifdef CONFIG_OMAP_MUX_DEBUG | |
40 | #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ | |
41 | .mux_reg = FUNC_MUX_CTRL_##reg, \ | |
42 | .mask_offset = mode_offset, \ | |
43 | .mask = mode, | |
44 | ||
45 | #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ | |
46 | .pull_reg = PULL_DWN_CTRL_##reg, \ | |
47 | .pull_bit = bit, \ | |
48 | .pull_val = status, | |
49 | ||
50 | #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ | |
51 | .pu_pd_reg = PU_PD_SEL_##reg, \ | |
52 | .pu_pd_val = status, | |
53 | ||
9ad5897c TL |
54 | #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ |
55 | .mux_reg = OMAP730_IO_CONF_##reg, \ | |
56 | .mask_offset = mode_offset, \ | |
57 | .mask = mode, | |
58 | ||
59 | #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ | |
60 | .pull_reg = OMAP730_IO_CONF_##reg, \ | |
61 | .pull_bit = bit, \ | |
62 | .pull_val = status, | |
63 | ||
1da177e4 LT |
64 | #else |
65 | ||
66 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ | |
67 | .mask_offset = mode_offset, \ | |
68 | .mask = mode, | |
69 | ||
70 | #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ | |
71 | .pull_bit = bit, \ | |
72 | .pull_val = status, | |
73 | ||
74 | #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ | |
75 | .pu_pd_val = status, | |
76 | ||
9ad5897c TL |
77 | #define MUX_REG_730(reg, mode_offset, mode) \ |
78 | .mux_reg = OMAP730_IO_CONF_##reg, \ | |
79 | .mask_offset = mode_offset, \ | |
80 | .mask = mode, | |
81 | ||
82 | #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ | |
83 | .pull_bit = bit, \ | |
84 | .pull_val = status, | |
85 | ||
1da177e4 LT |
86 | #endif /* CONFIG_OMAP_MUX_DEBUG */ |
87 | ||
88 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ | |
89 | pull_reg, pull_bit, pull_status, \ | |
90 | pu_pd_reg, pu_pd_status, debug_status) \ | |
91 | { \ | |
92 | .name = desc, \ | |
93 | .debug = debug_status, \ | |
94 | MUX_REG(mux_reg, mode_offset, mode) \ | |
95 | PULL_REG(pull_reg, pull_bit, pull_status) \ | |
96 | PU_PD_REG(pu_pd_reg, pu_pd_status) \ | |
97 | }, | |
98 | ||
9ad5897c TL |
99 | |
100 | /* | |
101 | * OMAP730 has a slightly different config for the pin mux. | |
102 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and | |
103 | * not the FUNC_MUX_CTRL_x regs from hardware.h | |
104 | * - for pull-up/down, only has one enable bit which is is in the same register | |
105 | * as mux config | |
106 | */ | |
107 | #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ | |
8d7f9f50 | 108 | pull_bit, pull_status, debug_status)\ |
9ad5897c TL |
109 | { \ |
110 | .name = desc, \ | |
111 | .debug = debug_status, \ | |
112 | MUX_REG_730(mux_reg, mode_offset, mode) \ | |
113 | PULL_REG_730(mux_reg, pull_bit, pull_status) \ | |
8d7f9f50 | 114 | PU_PD_REG(NA, 0) \ |
9ad5897c TL |
115 | }, |
116 | ||
117 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | |
118 | pull_en, pull_mode, dbg) \ | |
119 | { \ | |
120 | .name = desc, \ | |
121 | .debug = dbg, \ | |
122 | .mux_reg = reg_offset, \ | |
123 | .mask = mode, \ | |
124 | .pull_val = pull_en, \ | |
125 | .pu_pd_val = pull_mode, \ | |
126 | }, | |
127 | ||
128 | ||
1da177e4 LT |
129 | #define PULL_DISABLED 0 |
130 | #define PULL_ENABLED 1 | |
131 | ||
132 | #define PULL_DOWN 0 | |
133 | #define PULL_UP 1 | |
134 | ||
9ad5897c | 135 | struct pin_config { |
1da177e4 LT |
136 | char *name; |
137 | unsigned char busy; | |
138 | unsigned char debug; | |
139 | ||
140 | const char *mux_reg_name; | |
141 | const unsigned int mux_reg; | |
142 | const unsigned char mask_offset; | |
143 | const unsigned char mask; | |
144 | ||
145 | const char *pull_name; | |
146 | const unsigned int pull_reg; | |
147 | const unsigned char pull_val; | |
148 | const unsigned char pull_bit; | |
149 | ||
150 | const char *pu_pd_name; | |
151 | const unsigned int pu_pd_reg; | |
152 | const unsigned char pu_pd_val; | |
9ad5897c | 153 | }; |
1da177e4 | 154 | |
9ad5897c TL |
155 | enum omap730_index { |
156 | /* OMAP 730 keyboard */ | |
157 | E2_730_KBR0, | |
158 | J7_730_KBR1, | |
159 | E1_730_KBR2, | |
160 | F3_730_KBR3, | |
161 | D2_730_KBR4, | |
162 | C2_730_KBC0, | |
163 | D3_730_KBC1, | |
164 | E4_730_KBC2, | |
165 | F4_730_KBC3, | |
166 | E3_730_KBC4, | |
8d7f9f50 TL |
167 | |
168 | /* USB */ | |
169 | AA17_730_USB_DM, | |
170 | W16_730_USB_PU_EN, | |
171 | W17_730_USB_VBUSI, | |
9ad5897c TL |
172 | }; |
173 | ||
174 | enum omap1xxx_index { | |
1da177e4 LT |
175 | /* UART1 (BT_UART_GATING)*/ |
176 | UART1_TX = 0, | |
177 | UART1_RTS, | |
178 | ||
179 | /* UART2 (COM_UART_GATING)*/ | |
180 | UART2_TX, | |
181 | UART2_RX, | |
182 | UART2_CTS, | |
183 | UART2_RTS, | |
184 | ||
185 | /* UART3 (GIGA_UART_GATING) */ | |
186 | UART3_TX, | |
187 | UART3_RX, | |
188 | UART3_CTS, | |
189 | UART3_RTS, | |
190 | UART3_CLKREQ, | |
191 | UART3_BCLK, /* 12MHz clock out */ | |
192 | Y15_1610_UART3_RTS, | |
193 | ||
194 | /* PWT & PWL */ | |
195 | PWT, | |
196 | PWL, | |
197 | ||
198 | /* USB master generic */ | |
199 | R18_USB_VBUS, | |
200 | R18_1510_USB_GPIO0, | |
201 | W4_USB_PUEN, | |
202 | W4_USB_CLKO, | |
203 | W4_USB_HIGHZ, | |
204 | W4_GPIO58, | |
205 | ||
206 | /* USB1 master */ | |
207 | USB1_SUSP, | |
208 | USB1_SEO, | |
209 | W13_1610_USB1_SE0, | |
210 | USB1_TXEN, | |
211 | USB1_TXD, | |
212 | USB1_VP, | |
213 | USB1_VM, | |
214 | USB1_RCV, | |
215 | USB1_SPEED, | |
216 | R13_1610_USB1_SPEED, | |
217 | R13_1710_USB1_SE0, | |
218 | ||
219 | /* USB2 master */ | |
220 | USB2_SUSP, | |
221 | USB2_VP, | |
222 | USB2_TXEN, | |
223 | USB2_VM, | |
224 | USB2_RCV, | |
225 | USB2_SEO, | |
226 | USB2_TXD, | |
227 | ||
228 | /* OMAP-1510 GPIO */ | |
229 | R18_1510_GPIO0, | |
230 | R19_1510_GPIO1, | |
231 | M14_1510_GPIO2, | |
232 | ||
233 | /* OMAP1610 GPIO */ | |
234 | P18_1610_GPIO3, | |
235 | Y15_1610_GPIO17, | |
236 | ||
237 | /* OMAP-1710 GPIO */ | |
238 | R18_1710_GPIO0, | |
239 | V2_1710_GPIO10, | |
240 | N21_1710_GPIO14, | |
241 | W15_1710_GPIO40, | |
242 | ||
243 | /* MPUIO */ | |
244 | MPUIO2, | |
9839c6b8 | 245 | N15_1610_MPUIO2, |
1da177e4 LT |
246 | MPUIO4, |
247 | MPUIO5, | |
248 | T20_1610_MPUIO5, | |
249 | W11_1610_MPUIO6, | |
250 | V10_1610_MPUIO7, | |
251 | W11_1610_MPUIO9, | |
252 | V10_1610_MPUIO10, | |
253 | W10_1610_MPUIO11, | |
254 | E20_1610_MPUIO13, | |
255 | U20_1610_MPUIO14, | |
256 | E19_1610_MPUIO15, | |
257 | ||
258 | /* MCBSP2 */ | |
259 | MCBSP2_CLKR, | |
260 | MCBSP2_CLKX, | |
261 | MCBSP2_DR, | |
262 | MCBSP2_DX, | |
263 | MCBSP2_FSR, | |
264 | MCBSP2_FSX, | |
265 | ||
266 | /* MCBSP3 */ | |
267 | MCBSP3_CLKX, | |
268 | ||
269 | /* Misc ballouts */ | |
270 | BALLOUT_V8_ARMIO3, | |
9839c6b8 | 271 | N20_HDQ, |
1da177e4 LT |
272 | |
273 | /* OMAP-1610 MMC2 */ | |
274 | W8_1610_MMC2_DAT0, | |
275 | V8_1610_MMC2_DAT1, | |
276 | W15_1610_MMC2_DAT2, | |
277 | R10_1610_MMC2_DAT3, | |
278 | Y10_1610_MMC2_CLK, | |
279 | Y8_1610_MMC2_CMD, | |
280 | V9_1610_MMC2_CMDDIR, | |
281 | V5_1610_MMC2_DATDIR0, | |
282 | W19_1610_MMC2_DATDIR1, | |
283 | R18_1610_MMC2_CLKIN, | |
284 | ||
285 | /* OMAP-1610 External Trace Interface */ | |
286 | M19_1610_ETM_PSTAT0, | |
287 | L15_1610_ETM_PSTAT1, | |
288 | L18_1610_ETM_PSTAT2, | |
289 | L19_1610_ETM_D0, | |
290 | J19_1610_ETM_D6, | |
291 | J18_1610_ETM_D7, | |
292 | ||
bb13b5fd | 293 | /* OMAP16XX GPIO */ |
1da177e4 LT |
294 | P20_1610_GPIO4, |
295 | V9_1610_GPIO7, | |
296 | W8_1610_GPIO9, | |
9839c6b8 | 297 | N20_1610_GPIO11, |
1da177e4 LT |
298 | N19_1610_GPIO13, |
299 | P10_1610_GPIO22, | |
300 | V5_1610_GPIO24, | |
301 | AA20_1610_GPIO_41, | |
302 | W19_1610_GPIO48, | |
303 | M7_1610_GPIO62, | |
bb13b5fd TL |
304 | V14_16XX_GPIO37, |
305 | R9_16XX_GPIO18, | |
306 | L14_16XX_GPIO49, | |
1da177e4 LT |
307 | |
308 | /* OMAP-1610 uWire */ | |
309 | V19_1610_UWIRE_SCLK, | |
310 | U18_1610_UWIRE_SDI, | |
311 | W21_1610_UWIRE_SDO, | |
312 | N14_1610_UWIRE_CS0, | |
9839c6b8 | 313 | P15_1610_UWIRE_CS3, |
1da177e4 LT |
314 | N15_1610_UWIRE_CS1, |
315 | ||
75a1d10e MH |
316 | /* OMAP-1610 SPI */ |
317 | U19_1610_SPIF_SCK, | |
318 | U18_1610_SPIF_DIN, | |
319 | P20_1610_SPIF_DIN, | |
320 | W21_1610_SPIF_DOUT, | |
321 | R18_1610_SPIF_DOUT, | |
322 | N14_1610_SPIF_CS0, | |
323 | N15_1610_SPIF_CS1, | |
324 | T19_1610_SPIF_CS2, | |
325 | P15_1610_SPIF_CS3, | |
326 | ||
1da177e4 LT |
327 | /* OMAP-1610 Flash */ |
328 | L3_1610_FLASH_CS2B_OE, | |
329 | M8_1610_FLASH_CS2B_WE, | |
330 | ||
331 | /* First MMC */ | |
332 | MMC_CMD, | |
333 | MMC_DAT1, | |
334 | MMC_DAT2, | |
335 | MMC_DAT0, | |
336 | MMC_CLK, | |
337 | MMC_DAT3, | |
338 | ||
339 | /* OMAP-1710 MMC CMDDIR and DATDIR0 */ | |
340 | M15_1710_MMC_CLKI, | |
341 | P19_1710_MMC_CMDDIR, | |
342 | P20_1710_MMC_DATDIR0, | |
343 | ||
344 | /* OMAP-1610 USB0 alternate pin configuration */ | |
345 | W9_USB0_TXEN, | |
346 | AA9_USB0_VP, | |
347 | Y5_USB0_RCV, | |
348 | R9_USB0_VM, | |
349 | V6_USB0_TXD, | |
350 | W5_USB0_SE0, | |
351 | V9_USB0_SPEED, | |
352 | V9_USB0_SUSP, | |
353 | ||
354 | /* USB2 */ | |
355 | W9_USB2_TXEN, | |
356 | AA9_USB2_VP, | |
357 | Y5_USB2_RCV, | |
358 | R9_USB2_VM, | |
359 | V6_USB2_TXD, | |
360 | W5_USB2_SE0, | |
361 | ||
bb13b5fd | 362 | /* 16XX UART */ |
1da177e4 | 363 | R13_1610_UART1_TX, |
bb13b5fd | 364 | V14_16XX_UART1_RX, |
1da177e4 LT |
365 | R14_1610_UART1_CTS, |
366 | AA15_1610_UART1_RTS, | |
bb13b5fd TL |
367 | R9_16XX_UART2_RX, |
368 | L14_16XX_UART3_RX, | |
1da177e4 LT |
369 | |
370 | /* I2C OMAP-1610 */ | |
371 | I2C_SCL, | |
372 | I2C_SDA, | |
373 | ||
374 | /* Keypad */ | |
375 | F18_1610_KBC0, | |
376 | D20_1610_KBC1, | |
377 | D19_1610_KBC2, | |
378 | E18_1610_KBC3, | |
379 | C21_1610_KBC4, | |
380 | G18_1610_KBR0, | |
381 | F19_1610_KBR1, | |
382 | H14_1610_KBR2, | |
383 | E20_1610_KBR3, | |
384 | E19_1610_KBR4, | |
385 | N19_1610_KBR5, | |
386 | ||
387 | /* Power management */ | |
388 | T20_1610_LOW_PWR, | |
389 | ||
390 | /* MCLK Settings */ | |
391 | V5_1710_MCLK_ON, | |
392 | V5_1710_MCLK_OFF, | |
393 | R10_1610_MCLK_ON, | |
394 | R10_1610_MCLK_OFF, | |
395 | ||
396 | /* CompactFlash controller */ | |
397 | P11_1610_CF_CD2, | |
398 | R11_1610_CF_IOIS16, | |
399 | V10_1610_CF_IREQ, | |
400 | W10_1610_CF_RESET, | |
401 | W11_1610_CF_CD1, | |
c72d8950 DB |
402 | |
403 | /* parallel camera */ | |
404 | J15_1610_CAM_LCLK, | |
405 | J18_1610_CAM_D7, | |
406 | J19_1610_CAM_D6, | |
407 | J14_1610_CAM_D5, | |
408 | K18_1610_CAM_D4, | |
409 | K19_1610_CAM_D3, | |
410 | K15_1610_CAM_D2, | |
411 | K14_1610_CAM_D1, | |
412 | L19_1610_CAM_D0, | |
413 | L18_1610_CAM_VS, | |
414 | L15_1610_CAM_HS, | |
415 | M19_1610_CAM_RSTZ, | |
416 | Y15_1610_CAM_OUTCLK, | |
417 | ||
418 | /* serial camera */ | |
419 | H19_1610_CAM_EXCLK, | |
420 | Y12_1610_CCP_CLKP, | |
421 | W13_1610_CCP_CLKM, | |
422 | W14_1610_CCP_DATAP, | |
423 | Y14_1610_CCP_DATAM, | |
424 | ||
9ad5897c | 425 | }; |
1da177e4 | 426 | |
9ad5897c TL |
427 | enum omap24xx_index { |
428 | /* 24xx I2C */ | |
429 | M19_24XX_I2C1_SCL, | |
430 | L15_24XX_I2C1_SDA, | |
431 | J15_24XX_I2C2_SCL, | |
432 | H19_24XX_I2C2_SDA, | |
1da177e4 | 433 | |
9ad5897c TL |
434 | /* 24xx Menelaus interrupt */ |
435 | W19_24XX_SYS_NIRQ, | |
1da177e4 | 436 | |
8d7f9f50 TL |
437 | /* 24xx clock */ |
438 | W14_24XX_SYS_CLKOUT, | |
439 | ||
7bbb3cc5 KP |
440 | /* 24xx GPMC chipselects, wait pin monitoring */ |
441 | E2_GPMC_NCS2, | |
442 | L2_GPMC_NCS7, | |
3cbc9605 TL |
443 | L3_GPMC_WAIT0, |
444 | N7_GPMC_WAIT1, | |
445 | M1_GPMC_WAIT2, | |
446 | P1_GPMC_WAIT3, | |
447 | ||
8d7f9f50 TL |
448 | /* 242X McBSP */ |
449 | Y15_24XX_MCBSP2_CLKX, | |
450 | R14_24XX_MCBSP2_FSX, | |
451 | W15_24XX_MCBSP2_DR, | |
452 | V15_24XX_MCBSP2_DX, | |
453 | ||
9ad5897c | 454 | /* 24xx GPIO */ |
8d7f9f50 | 455 | M21_242X_GPIO11, |
7bbb3cc5 | 456 | P21_242X_GPIO12, |
8d7f9f50 TL |
457 | AA10_242X_GPIO13, |
458 | AA6_242X_GPIO14, | |
459 | AA4_242X_GPIO15, | |
460 | Y11_242X_GPIO16, | |
461 | AA12_242X_GPIO17, | |
462 | AA8_242X_GPIO58, | |
9ad5897c | 463 | Y20_24XX_GPIO60, |
8d7f9f50 | 464 | W4__24XX_GPIO74, |
f7337a19 | 465 | N15_24XX_GPIO85, |
9ad5897c | 466 | M15_24XX_GPIO92, |
f7337a19 TL |
467 | P20_24XX_GPIO93, |
468 | P18_24XX_GPIO95, | |
469 | M18_24XX_GPIO96, | |
470 | L14_24XX_GPIO97, | |
7bbb3cc5 | 471 | J15_24XX_GPIO99, |
8d7f9f50 | 472 | V14_24XX_GPIO117, |
7bbb3cc5 | 473 | P14_24XX_GPIO125, |
8d7f9f50 | 474 | |
5ac42153 TL |
475 | /* 242x DBG GPIO */ |
476 | V4_242X_GPIO49, | |
477 | W2_242X_GPIO50, | |
478 | U4_242X_GPIO51, | |
479 | V3_242X_GPIO52, | |
480 | V2_242X_GPIO53, | |
481 | V6_242X_GPIO53, | |
482 | T4_242X_GPIO54, | |
483 | Y4_242X_GPIO54, | |
484 | T3_242X_GPIO55, | |
485 | U2_242X_GPIO56, | |
486 | ||
487 | /* 24xx external DMA requests */ | |
488 | AA10_242X_DMAREQ0, | |
489 | AA6_242X_DMAREQ1, | |
490 | E4_242X_DMAREQ2, | |
491 | G4_242X_DMAREQ3, | |
492 | D3_242X_DMAREQ4, | |
493 | E3_242X_DMAREQ5, | |
494 | ||
8d7f9f50 TL |
495 | /* UART3 */ |
496 | K15_24XX_UART3_TX, | |
497 | K14_24XX_UART3_RX, | |
498 | ||
abc45e1d KP |
499 | /* MMC/SDIO */ |
500 | G19_24XX_MMC_CLKO, | |
501 | H18_24XX_MMC_CMD, | |
502 | F20_24XX_MMC_DAT0, | |
503 | H14_24XX_MMC_DAT1, | |
504 | E19_24XX_MMC_DAT2, | |
505 | D19_24XX_MMC_DAT3, | |
506 | F19_24XX_MMC_DAT_DIR0, | |
507 | E20_24XX_MMC_DAT_DIR1, | |
508 | F18_24XX_MMC_DAT_DIR2, | |
509 | E18_24XX_MMC_DAT_DIR3, | |
510 | G18_24XX_MMC_CMD_DIR, | |
511 | H15_24XX_MMC_CLKI, | |
512 | ||
7bbb3cc5 KP |
513 | /* Full speed USB */ |
514 | J20_24XX_USB0_PUEN, | |
515 | J19_24XX_USB0_VP, | |
516 | K20_24XX_USB0_VM, | |
517 | J18_24XX_USB0_RCV, | |
518 | K19_24XX_USB0_TXEN, | |
519 | J14_24XX_USB0_SE0, | |
520 | K18_24XX_USB0_DAT, | |
521 | ||
522 | N14_24XX_USB1_SE0, | |
523 | W12_24XX_USB1_SE0, | |
524 | P15_24XX_USB1_DAT, | |
525 | R13_24XX_USB1_DAT, | |
526 | W20_24XX_USB1_TXEN, | |
527 | P13_24XX_USB1_TXEN, | |
528 | V19_24XX_USB1_RCV, | |
529 | V12_24XX_USB1_RCV, | |
530 | ||
531 | AA10_24XX_USB2_SE0, | |
532 | Y11_24XX_USB2_DAT, | |
533 | AA12_24XX_USB2_TXEN, | |
534 | AA6_24XX_USB2_RCV, | |
535 | AA4_24XX_USB2_TLLSE0, | |
536 | ||
8d7f9f50 TL |
537 | /* Keypad GPIO*/ |
538 | T19_24XX_KBR0, | |
539 | R19_24XX_KBR1, | |
540 | V18_24XX_KBR2, | |
541 | M21_24XX_KBR3, | |
542 | E5__24XX_KBR4, | |
543 | M18_24XX_KBR5, | |
544 | R20_24XX_KBC0, | |
545 | M14_24XX_KBC1, | |
546 | H19_24XX_KBC2, | |
547 | V17_24XX_KBC3, | |
548 | P21_24XX_KBC4, | |
549 | L14_24XX_KBC5, | |
550 | N19_24XX_KBC6, | |
551 | ||
552 | /* 24xx Menelaus Keypad GPIO */ | |
553 | B3__24XX_KBR5, | |
554 | AA4_24XX_KBC2, | |
555 | B13_24XX_KBC6, | |
f7337a19 TL |
556 | |
557 | /* 2430 USB */ | |
558 | AD9_2430_USB0_PUEN, | |
559 | Y11_2430_USB0_VP, | |
560 | AD7_2430_USB0_VM, | |
561 | AE7_2430_USB0_RCV, | |
562 | AD4_2430_USB0_TXEN, | |
563 | AF9_2430_USB0_SE0, | |
564 | AE6_2430_USB0_DAT, | |
565 | AD24_2430_USB1_SE0, | |
566 | AB24_2430_USB1_RCV, | |
567 | Y25_2430_USB1_TXEN, | |
568 | AA26_2430_USB1_DAT, | |
569 | ||
570 | /* 2430 HS-USB */ | |
571 | AD9_2430_USB0HS_DATA3, | |
572 | Y11_2430_USB0HS_DATA4, | |
573 | AD7_2430_USB0HS_DATA5, | |
574 | AE7_2430_USB0HS_DATA6, | |
575 | AD4_2430_USB0HS_DATA2, | |
576 | AF9_2430_USB0HS_DATA0, | |
577 | AE6_2430_USB0HS_DATA1, | |
578 | AE8_2430_USB0HS_CLK, | |
579 | AD8_2430_USB0HS_DIR, | |
580 | AE5_2430_USB0HS_STP, | |
581 | AE9_2430_USB0HS_NXT, | |
582 | AC7_2430_USB0HS_DATA7, | |
583 | ||
584 | /* 2430 McBSP */ | |
585 | AC10_2430_MCBSP2_FSX, | |
586 | AD16_2430_MCBSP2_CLX, | |
587 | AE13_2430_MCBSP2_DX, | |
588 | AD13_2430_MCBSP2_DR, | |
589 | AC10_2430_MCBSP2_FSX_OFF, | |
590 | AD16_2430_MCBSP2_CLX_OFF, | |
591 | AE13_2430_MCBSP2_DX_OFF, | |
592 | AD13_2430_MCBSP2_DR_OFF, | |
593 | ||
9ad5897c | 594 | }; |
1da177e4 | 595 | |
7d7f665d TL |
596 | struct omap_mux_cfg { |
597 | struct pin_config *pins; | |
598 | unsigned long size; | |
599 | int (*cfg_reg)(const struct pin_config *cfg); | |
600 | }; | |
601 | ||
1da177e4 LT |
602 | #ifdef CONFIG_OMAP_MUX |
603 | /* setup pin muxing in Linux */ | |
9ad5897c TL |
604 | extern int omap1_mux_init(void); |
605 | extern int omap2_mux_init(void); | |
7d7f665d | 606 | extern int omap_mux_register(struct omap_mux_cfg *); |
9ad5897c | 607 | extern int omap_cfg_reg(unsigned long reg_cfg); |
1da177e4 LT |
608 | #else |
609 | /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ | |
9ad5897c TL |
610 | static inline int omap1_mux_init(void) { return 0; } |
611 | static inline int omap2_mux_init(void) { return 0; } | |
612 | static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } | |
1da177e4 LT |
613 | #endif |
614 | ||
615 | #endif |