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a09e64fb | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | |
4 | * http://www.simtec.co.uk/products/SWLINUX/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * S3C2410 Watchdog timer control | |
1da177e4 LT |
11 | */ |
12 | ||
13 | ||
14 | #ifndef __ASM_ARCH_REGS_WATCHDOG_H | |
15 | #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $" | |
16 | ||
530ef3c2 | 17 | #define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) |
1da177e4 | 18 | |
530ef3c2 BD |
19 | #define S3C2410_WTCON S3C_WDOGREG(0x00) |
20 | #define S3C2410_WTDAT S3C_WDOGREG(0x04) | |
21 | #define S3C2410_WTCNT S3C_WDOGREG(0x08) | |
1da177e4 LT |
22 | |
23 | /* the watchdog can either generate a reset pulse, or an | |
24 | * interrupt. | |
25 | */ | |
26 | ||
27 | #define S3C2410_WTCON_RSTEN (0x01) | |
28 | #define S3C2410_WTCON_INTEN (1<<2) | |
29 | #define S3C2410_WTCON_ENABLE (1<<5) | |
30 | ||
31 | #define S3C2410_WTCON_DIV16 (0<<3) | |
32 | #define S3C2410_WTCON_DIV32 (1<<3) | |
33 | #define S3C2410_WTCON_DIV64 (2<<3) | |
34 | #define S3C2410_WTCON_DIV128 (3<<3) | |
35 | ||
36 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | |
37 | #define S3C2410_WTCON_PRESCALE_MASK (0xff00) | |
38 | ||
39 | #endif /* __ASM_ARCH_REGS_WATCHDOG_H */ | |
40 | ||
41 |