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Commit | Line | Data |
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3f7e212d AB |
1 | /* Generic I/O port emulation, based on MN10300 code |
2 | * | |
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public Licence | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the Licence, or (at your option) any later version. | |
10 | */ | |
11 | #ifndef __ASM_GENERIC_IO_H | |
12 | #define __ASM_GENERIC_IO_H | |
13 | ||
14 | #include <asm/page.h> /* I/O is all done through memory accesses */ | |
9216efaf | 15 | #include <linux/string.h> /* for memset() and memcpy() */ |
3f7e212d AB |
16 | #include <linux/types.h> |
17 | ||
18 | #ifdef CONFIG_GENERIC_IOMAP | |
19 | #include <asm-generic/iomap.h> | |
20 | #endif | |
21 | ||
66eab4df MT |
22 | #include <asm-generic/pci_iomap.h> |
23 | ||
35dbc0e0 | 24 | #ifndef mmiowb |
3f7e212d | 25 | #define mmiowb() do {} while (0) |
35dbc0e0 | 26 | #endif |
3f7e212d | 27 | |
3f7e212d | 28 | /* |
9216efaf TR |
29 | * __raw_{read,write}{b,w,l,q}() access memory in native endianness. |
30 | * | |
31 | * On some architectures memory mapped IO needs to be accessed differently. | |
32 | * On the simple architectures, we just read/write the memory location | |
33 | * directly. | |
3f7e212d | 34 | */ |
9216efaf | 35 | |
35dbc0e0 | 36 | #ifndef __raw_readb |
9216efaf | 37 | #define __raw_readb __raw_readb |
3f7e212d AB |
38 | static inline u8 __raw_readb(const volatile void __iomem *addr) |
39 | { | |
9216efaf | 40 | return *(const volatile u8 __force *)addr; |
3f7e212d | 41 | } |
35dbc0e0 | 42 | #endif |
3f7e212d | 43 | |
35dbc0e0 | 44 | #ifndef __raw_readw |
9216efaf | 45 | #define __raw_readw __raw_readw |
3f7e212d AB |
46 | static inline u16 __raw_readw(const volatile void __iomem *addr) |
47 | { | |
9216efaf | 48 | return *(const volatile u16 __force *)addr; |
3f7e212d | 49 | } |
35dbc0e0 | 50 | #endif |
3f7e212d | 51 | |
35dbc0e0 | 52 | #ifndef __raw_readl |
9216efaf | 53 | #define __raw_readl __raw_readl |
3f7e212d AB |
54 | static inline u32 __raw_readl(const volatile void __iomem *addr) |
55 | { | |
9216efaf | 56 | return *(const volatile u32 __force *)addr; |
3f7e212d | 57 | } |
35dbc0e0 | 58 | #endif |
3f7e212d | 59 | |
9216efaf TR |
60 | #ifdef CONFIG_64BIT |
61 | #ifndef __raw_readq | |
62 | #define __raw_readq __raw_readq | |
63 | static inline u64 __raw_readq(const volatile void __iomem *addr) | |
7292e7e0 | 64 | { |
9216efaf | 65 | return *(const volatile u64 __force *)addr; |
7292e7e0 | 66 | } |
9216efaf TR |
67 | #endif |
68 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 69 | |
35dbc0e0 | 70 | #ifndef __raw_writeb |
9216efaf TR |
71 | #define __raw_writeb __raw_writeb |
72 | static inline void __raw_writeb(u8 value, volatile void __iomem *addr) | |
3f7e212d | 73 | { |
9216efaf | 74 | *(volatile u8 __force *)addr = value; |
3f7e212d | 75 | } |
35dbc0e0 | 76 | #endif |
3f7e212d | 77 | |
35dbc0e0 | 78 | #ifndef __raw_writew |
9216efaf TR |
79 | #define __raw_writew __raw_writew |
80 | static inline void __raw_writew(u16 value, volatile void __iomem *addr) | |
3f7e212d | 81 | { |
9216efaf | 82 | *(volatile u16 __force *)addr = value; |
3f7e212d | 83 | } |
35dbc0e0 | 84 | #endif |
3f7e212d | 85 | |
35dbc0e0 | 86 | #ifndef __raw_writel |
9216efaf TR |
87 | #define __raw_writel __raw_writel |
88 | static inline void __raw_writel(u32 value, volatile void __iomem *addr) | |
3f7e212d | 89 | { |
9216efaf | 90 | *(volatile u32 __force *)addr = value; |
3f7e212d | 91 | } |
35dbc0e0 | 92 | #endif |
3f7e212d | 93 | |
3f7e212d | 94 | #ifdef CONFIG_64BIT |
9216efaf TR |
95 | #ifndef __raw_writeq |
96 | #define __raw_writeq __raw_writeq | |
97 | static inline void __raw_writeq(u64 value, volatile void __iomem *addr) | |
3f7e212d | 98 | { |
9216efaf | 99 | *(volatile u64 __force *)addr = value; |
3f7e212d | 100 | } |
cd248341 | 101 | #endif |
9216efaf | 102 | #endif /* CONFIG_64BIT */ |
cd248341 | 103 | |
9216efaf TR |
104 | /* |
105 | * {read,write}{b,w,l,q}() access little endian memory and return result in | |
106 | * native endianness. | |
107 | */ | |
3f7e212d | 108 | |
9216efaf TR |
109 | #ifndef readb |
110 | #define readb readb | |
111 | static inline u8 readb(const volatile void __iomem *addr) | |
3f7e212d | 112 | { |
9216efaf | 113 | return __raw_readb(addr); |
3f7e212d | 114 | } |
3f7e212d AB |
115 | #endif |
116 | ||
9216efaf TR |
117 | #ifndef readw |
118 | #define readw readw | |
119 | static inline u16 readw(const volatile void __iomem *addr) | |
120 | { | |
121 | return __le16_to_cpu(__raw_readw(addr)); | |
122 | } | |
7dc59bdd G |
123 | #endif |
124 | ||
9216efaf TR |
125 | #ifndef readl |
126 | #define readl readl | |
127 | static inline u32 readl(const volatile void __iomem *addr) | |
3f7e212d | 128 | { |
9216efaf | 129 | return __le32_to_cpu(__raw_readl(addr)); |
3f7e212d | 130 | } |
9216efaf | 131 | #endif |
3f7e212d | 132 | |
9216efaf TR |
133 | #ifdef CONFIG_64BIT |
134 | #ifndef readq | |
135 | #define readq readq | |
136 | static inline u64 readq(const volatile void __iomem *addr) | |
3f7e212d | 137 | { |
9216efaf | 138 | return __le64_to_cpu(__raw_readq(addr)); |
3f7e212d | 139 | } |
9216efaf TR |
140 | #endif |
141 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 142 | |
9216efaf TR |
143 | #ifndef writeb |
144 | #define writeb writeb | |
145 | static inline void writeb(u8 value, volatile void __iomem *addr) | |
3f7e212d | 146 | { |
9216efaf | 147 | __raw_writeb(value, addr); |
3f7e212d | 148 | } |
9216efaf | 149 | #endif |
3f7e212d | 150 | |
9216efaf TR |
151 | #ifndef writew |
152 | #define writew writew | |
153 | static inline void writew(u16 value, volatile void __iomem *addr) | |
3f7e212d | 154 | { |
9216efaf | 155 | __raw_writew(cpu_to_le16(value), addr); |
3f7e212d | 156 | } |
9216efaf | 157 | #endif |
3f7e212d | 158 | |
9216efaf TR |
159 | #ifndef writel |
160 | #define writel writel | |
161 | static inline void writel(u32 value, volatile void __iomem *addr) | |
3f7e212d | 162 | { |
9216efaf | 163 | __raw_writel(__cpu_to_le32(value), addr); |
3f7e212d | 164 | } |
9216efaf | 165 | #endif |
3f7e212d | 166 | |
9216efaf TR |
167 | #ifdef CONFIG_64BIT |
168 | #ifndef writeq | |
169 | #define writeq writeq | |
170 | static inline void writeq(u64 value, volatile void __iomem *addr) | |
3f7e212d | 171 | { |
9216efaf | 172 | __raw_writeq(__cpu_to_le64(value), addr); |
3f7e212d | 173 | } |
9216efaf TR |
174 | #endif |
175 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 176 | |
9ab3a7a0 TR |
177 | /* |
178 | * {read,write}s{b,w,l,q}() repeatedly access the same memory address in | |
179 | * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). | |
180 | */ | |
181 | #ifndef readsb | |
182 | #define readsb readsb | |
183 | static inline void readsb(const volatile void __iomem *addr, void *buffer, | |
184 | unsigned int count) | |
3f7e212d AB |
185 | { |
186 | if (count) { | |
187 | u8 *buf = buffer; | |
9ab3a7a0 | 188 | |
3f7e212d | 189 | do { |
9ab3a7a0 | 190 | u8 x = __raw_readb(addr); |
3f7e212d AB |
191 | *buf++ = x; |
192 | } while (--count); | |
193 | } | |
194 | } | |
35dbc0e0 | 195 | #endif |
3f7e212d | 196 | |
9ab3a7a0 TR |
197 | #ifndef readsw |
198 | #define readsw readsw | |
199 | static inline void readsw(const volatile void __iomem *addr, void *buffer, | |
200 | unsigned int count) | |
3f7e212d AB |
201 | { |
202 | if (count) { | |
203 | u16 *buf = buffer; | |
9ab3a7a0 | 204 | |
3f7e212d | 205 | do { |
9ab3a7a0 | 206 | u16 x = __raw_readw(addr); |
3f7e212d AB |
207 | *buf++ = x; |
208 | } while (--count); | |
209 | } | |
210 | } | |
35dbc0e0 | 211 | #endif |
3f7e212d | 212 | |
9ab3a7a0 TR |
213 | #ifndef readsl |
214 | #define readsl readsl | |
215 | static inline void readsl(const volatile void __iomem *addr, void *buffer, | |
216 | unsigned int count) | |
3f7e212d AB |
217 | { |
218 | if (count) { | |
219 | u32 *buf = buffer; | |
9ab3a7a0 | 220 | |
3f7e212d | 221 | do { |
9ab3a7a0 | 222 | u32 x = __raw_readl(addr); |
3f7e212d AB |
223 | *buf++ = x; |
224 | } while (--count); | |
225 | } | |
226 | } | |
35dbc0e0 | 227 | #endif |
3f7e212d | 228 | |
9ab3a7a0 TR |
229 | #ifdef CONFIG_64BIT |
230 | #ifndef readsq | |
231 | #define readsq readsq | |
232 | static inline void readsq(const volatile void __iomem *addr, void *buffer, | |
233 | unsigned int count) | |
234 | { | |
235 | if (count) { | |
236 | u64 *buf = buffer; | |
237 | ||
238 | do { | |
239 | u64 x = __raw_readq(addr); | |
240 | *buf++ = x; | |
241 | } while (--count); | |
242 | } | |
243 | } | |
244 | #endif | |
245 | #endif /* CONFIG_64BIT */ | |
246 | ||
247 | #ifndef writesb | |
248 | #define writesb writesb | |
249 | static inline void writesb(volatile void __iomem *addr, const void *buffer, | |
250 | unsigned int count) | |
3f7e212d AB |
251 | { |
252 | if (count) { | |
253 | const u8 *buf = buffer; | |
9ab3a7a0 | 254 | |
3f7e212d | 255 | do { |
9ab3a7a0 | 256 | __raw_writeb(*buf++, addr); |
3f7e212d AB |
257 | } while (--count); |
258 | } | |
259 | } | |
35dbc0e0 | 260 | #endif |
3f7e212d | 261 | |
9ab3a7a0 TR |
262 | #ifndef writesw |
263 | #define writesw writesw | |
264 | static inline void writesw(volatile void __iomem *addr, const void *buffer, | |
265 | unsigned int count) | |
3f7e212d AB |
266 | { |
267 | if (count) { | |
268 | const u16 *buf = buffer; | |
9ab3a7a0 | 269 | |
3f7e212d | 270 | do { |
9ab3a7a0 | 271 | __raw_writew(*buf++, addr); |
3f7e212d AB |
272 | } while (--count); |
273 | } | |
274 | } | |
35dbc0e0 | 275 | #endif |
3f7e212d | 276 | |
9ab3a7a0 TR |
277 | #ifndef writesl |
278 | #define writesl writesl | |
279 | static inline void writesl(volatile void __iomem *addr, const void *buffer, | |
280 | unsigned int count) | |
3f7e212d AB |
281 | { |
282 | if (count) { | |
283 | const u32 *buf = buffer; | |
9ab3a7a0 | 284 | |
3f7e212d | 285 | do { |
9ab3a7a0 | 286 | __raw_writel(*buf++, addr); |
3f7e212d AB |
287 | } while (--count); |
288 | } | |
289 | } | |
35dbc0e0 | 290 | #endif |
3f7e212d | 291 | |
9ab3a7a0 TR |
292 | #ifdef CONFIG_64BIT |
293 | #ifndef writesq | |
294 | #define writesq writesq | |
295 | static inline void writesq(volatile void __iomem *addr, const void *buffer, | |
296 | unsigned int count) | |
297 | { | |
298 | if (count) { | |
299 | const u64 *buf = buffer; | |
300 | ||
301 | do { | |
302 | __raw_writeq(*buf++, addr); | |
303 | } while (--count); | |
304 | } | |
305 | } | |
306 | #endif | |
307 | #endif /* CONFIG_64BIT */ | |
3f7e212d | 308 | |
9216efaf TR |
309 | #ifndef PCI_IOBASE |
310 | #define PCI_IOBASE ((void __iomem *)0) | |
311 | #endif | |
312 | ||
7dc59bdd G |
313 | #ifndef IO_SPACE_LIMIT |
314 | #define IO_SPACE_LIMIT 0xffff | |
315 | #endif | |
3f7e212d | 316 | |
9216efaf TR |
317 | /* |
318 | * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be | |
319 | * implemented on hardware that needs an additional delay for I/O accesses to | |
320 | * take effect. | |
321 | */ | |
322 | ||
323 | #ifndef inb | |
324 | #define inb inb | |
325 | static inline u8 inb(unsigned long addr) | |
326 | { | |
327 | return readb(PCI_IOBASE + addr); | |
328 | } | |
329 | #endif | |
330 | ||
331 | #ifndef inw | |
332 | #define inw inw | |
333 | static inline u16 inw(unsigned long addr) | |
334 | { | |
335 | return readw(PCI_IOBASE + addr); | |
336 | } | |
337 | #endif | |
338 | ||
339 | #ifndef inl | |
340 | #define inl inl | |
341 | static inline u32 inl(unsigned long addr) | |
342 | { | |
343 | return readl(PCI_IOBASE + addr); | |
344 | } | |
345 | #endif | |
346 | ||
347 | #ifndef outb | |
348 | #define outb outb | |
349 | static inline void outb(u8 value, unsigned long addr) | |
350 | { | |
351 | writeb(value, PCI_IOBASE + addr); | |
352 | } | |
353 | #endif | |
354 | ||
355 | #ifndef outw | |
356 | #define outw outw | |
357 | static inline void outw(u16 value, unsigned long addr) | |
358 | { | |
359 | writew(value, PCI_IOBASE + addr); | |
360 | } | |
361 | #endif | |
362 | ||
363 | #ifndef outl | |
364 | #define outl outl | |
365 | static inline void outl(u32 value, unsigned long addr) | |
366 | { | |
367 | writel(value, PCI_IOBASE + addr); | |
368 | } | |
369 | #endif | |
370 | ||
371 | #ifndef inb_p | |
372 | #define inb_p inb_p | |
373 | static inline u8 inb_p(unsigned long addr) | |
374 | { | |
375 | return inb(addr); | |
376 | } | |
377 | #endif | |
378 | ||
379 | #ifndef inw_p | |
380 | #define inw_p inw_p | |
381 | static inline u16 inw_p(unsigned long addr) | |
382 | { | |
383 | return inw(addr); | |
384 | } | |
385 | #endif | |
386 | ||
387 | #ifndef inl_p | |
388 | #define inl_p inl_p | |
389 | static inline u32 inl_p(unsigned long addr) | |
390 | { | |
391 | return inl(addr); | |
392 | } | |
393 | #endif | |
394 | ||
395 | #ifndef outb_p | |
396 | #define outb_p outb_p | |
397 | static inline void outb_p(u8 value, unsigned long addr) | |
398 | { | |
399 | outb(value, addr); | |
400 | } | |
401 | #endif | |
402 | ||
403 | #ifndef outw_p | |
404 | #define outw_p outw_p | |
405 | static inline void outw_p(u16 value, unsigned long addr) | |
406 | { | |
407 | outw(value, addr); | |
408 | } | |
409 | #endif | |
410 | ||
411 | #ifndef outl_p | |
412 | #define outl_p outl_p | |
413 | static inline void outl_p(u32 value, unsigned long addr) | |
414 | { | |
415 | outl(value, addr); | |
416 | } | |
417 | #endif | |
418 | ||
9ab3a7a0 TR |
419 | /* |
420 | * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a | |
421 | * single I/O port multiple times. | |
422 | */ | |
423 | ||
424 | #ifndef insb | |
425 | #define insb insb | |
426 | static inline void insb(unsigned long addr, void *buffer, unsigned int count) | |
427 | { | |
428 | readsb(PCI_IOBASE + addr, buffer, count); | |
429 | } | |
430 | #endif | |
431 | ||
432 | #ifndef insw | |
433 | #define insw insw | |
434 | static inline void insw(unsigned long addr, void *buffer, unsigned int count) | |
435 | { | |
436 | readsw(PCI_IOBASE + addr, buffer, count); | |
437 | } | |
438 | #endif | |
439 | ||
440 | #ifndef insl | |
441 | #define insl insl | |
442 | static inline void insl(unsigned long addr, void *buffer, unsigned int count) | |
443 | { | |
444 | readsl(PCI_IOBASE + addr, buffer, count); | |
445 | } | |
446 | #endif | |
447 | ||
448 | #ifndef outsb | |
449 | #define outsb outsb | |
450 | static inline void outsb(unsigned long addr, const void *buffer, | |
451 | unsigned int count) | |
452 | { | |
453 | writesb(PCI_IOBASE + addr, buffer, count); | |
454 | } | |
455 | #endif | |
456 | ||
457 | #ifndef outsw | |
458 | #define outsw outsw | |
459 | static inline void outsw(unsigned long addr, const void *buffer, | |
460 | unsigned int count) | |
461 | { | |
462 | writesw(PCI_IOBASE + addr, buffer, count); | |
463 | } | |
464 | #endif | |
465 | ||
466 | #ifndef outsl | |
467 | #define outsl outsl | |
468 | static inline void outsl(unsigned long addr, const void *buffer, | |
469 | unsigned int count) | |
470 | { | |
471 | writesl(PCI_IOBASE + addr, buffer, count); | |
472 | } | |
473 | #endif | |
474 | ||
475 | #ifndef insb_p | |
476 | #define insb_p insb_p | |
477 | static inline void insb_p(unsigned long addr, void *buffer, unsigned int count) | |
478 | { | |
479 | insb(addr, buffer, count); | |
480 | } | |
481 | #endif | |
482 | ||
483 | #ifndef insw_p | |
484 | #define insw_p insw_p | |
485 | static inline void insw_p(unsigned long addr, void *buffer, unsigned int count) | |
486 | { | |
487 | insw(addr, buffer, count); | |
488 | } | |
489 | #endif | |
490 | ||
491 | #ifndef insl_p | |
492 | #define insl_p insl_p | |
493 | static inline void insl_p(unsigned long addr, void *buffer, unsigned int count) | |
494 | { | |
495 | insl(addr, buffer, count); | |
496 | } | |
497 | #endif | |
498 | ||
499 | #ifndef outsb_p | |
500 | #define outsb_p outsb_p | |
501 | static inline void outsb_p(unsigned long addr, const void *buffer, | |
502 | unsigned int count) | |
503 | { | |
504 | outsb(addr, buffer, count); | |
505 | } | |
506 | #endif | |
507 | ||
508 | #ifndef outsw_p | |
509 | #define outsw_p outsw_p | |
510 | static inline void outsw_p(unsigned long addr, const void *buffer, | |
511 | unsigned int count) | |
512 | { | |
513 | outsw(addr, buffer, count); | |
514 | } | |
515 | #endif | |
516 | ||
517 | #ifndef outsl_p | |
518 | #define outsl_p outsl_p | |
519 | static inline void outsl_p(unsigned long addr, const void *buffer, | |
520 | unsigned int count) | |
521 | { | |
522 | outsl(addr, buffer, count); | |
523 | } | |
524 | #endif | |
525 | ||
9216efaf TR |
526 | #ifndef CONFIG_GENERIC_IOMAP |
527 | #ifndef ioread8 | |
528 | #define ioread8 ioread8 | |
529 | static inline u8 ioread8(const volatile void __iomem *addr) | |
530 | { | |
531 | return readb(addr); | |
532 | } | |
533 | #endif | |
534 | ||
535 | #ifndef ioread16 | |
536 | #define ioread16 ioread16 | |
537 | static inline u16 ioread16(const volatile void __iomem *addr) | |
538 | { | |
539 | return readw(addr); | |
540 | } | |
541 | #endif | |
542 | ||
543 | #ifndef ioread32 | |
544 | #define ioread32 ioread32 | |
545 | static inline u32 ioread32(const volatile void __iomem *addr) | |
546 | { | |
547 | return readl(addr); | |
548 | } | |
549 | #endif | |
550 | ||
551 | #ifndef iowrite8 | |
552 | #define iowrite8 iowrite8 | |
553 | static inline void iowrite8(u8 value, volatile void __iomem *addr) | |
554 | { | |
555 | writeb(value, addr); | |
556 | } | |
557 | #endif | |
558 | ||
559 | #ifndef iowrite16 | |
560 | #define iowrite16 iowrite16 | |
561 | static inline void iowrite16(u16 value, volatile void __iomem *addr) | |
562 | { | |
563 | writew(value, addr); | |
564 | } | |
565 | #endif | |
566 | ||
567 | #ifndef iowrite32 | |
568 | #define iowrite32 iowrite32 | |
569 | static inline void iowrite32(u32 value, volatile void __iomem *addr) | |
570 | { | |
571 | writel(value, addr); | |
572 | } | |
573 | #endif | |
574 | ||
575 | #ifndef ioread16be | |
576 | #define ioread16be ioread16be | |
577 | static inline u16 ioread16be(const volatile void __iomem *addr) | |
578 | { | |
579 | return __be16_to_cpu(__raw_readw(addr)); | |
580 | } | |
581 | #endif | |
582 | ||
583 | #ifndef ioread32be | |
584 | #define ioread32be ioread32be | |
585 | static inline u32 ioread32be(const volatile void __iomem *addr) | |
586 | { | |
587 | return __be32_to_cpu(__raw_readl(addr)); | |
588 | } | |
589 | #endif | |
590 | ||
591 | #ifndef iowrite16be | |
592 | #define iowrite16be iowrite16be | |
593 | static inline void iowrite16be(u16 value, void volatile __iomem *addr) | |
594 | { | |
595 | __raw_writew(__cpu_to_be16(value), addr); | |
596 | } | |
597 | #endif | |
598 | ||
599 | #ifndef iowrite32be | |
600 | #define iowrite32be iowrite32be | |
601 | static inline void iowrite32be(u32 value, volatile void __iomem *addr) | |
602 | { | |
603 | __raw_writel(__cpu_to_be32(value), addr); | |
604 | } | |
605 | #endif | |
9ab3a7a0 TR |
606 | |
607 | #ifndef ioread8_rep | |
608 | #define ioread8_rep ioread8_rep | |
609 | static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer, | |
610 | unsigned int count) | |
611 | { | |
612 | readsb(addr, buffer, count); | |
613 | } | |
614 | #endif | |
615 | ||
616 | #ifndef ioread16_rep | |
617 | #define ioread16_rep ioread16_rep | |
618 | static inline void ioread16_rep(const volatile void __iomem *addr, | |
619 | void *buffer, unsigned int count) | |
620 | { | |
621 | readsw(addr, buffer, count); | |
622 | } | |
623 | #endif | |
624 | ||
625 | #ifndef ioread32_rep | |
626 | #define ioread32_rep ioread32_rep | |
627 | static inline void ioread32_rep(const volatile void __iomem *addr, | |
628 | void *buffer, unsigned int count) | |
629 | { | |
630 | readsl(addr, buffer, count); | |
631 | } | |
632 | #endif | |
633 | ||
634 | #ifndef iowrite8_rep | |
635 | #define iowrite8_rep iowrite8_rep | |
636 | static inline void iowrite8_rep(volatile void __iomem *addr, | |
637 | const void *buffer, | |
638 | unsigned int count) | |
639 | { | |
640 | writesb(addr, buffer, count); | |
641 | } | |
642 | #endif | |
643 | ||
644 | #ifndef iowrite16_rep | |
645 | #define iowrite16_rep iowrite16_rep | |
646 | static inline void iowrite16_rep(volatile void __iomem *addr, | |
647 | const void *buffer, | |
648 | unsigned int count) | |
649 | { | |
650 | writesw(addr, buffer, count); | |
651 | } | |
652 | #endif | |
653 | ||
654 | #ifndef iowrite32_rep | |
655 | #define iowrite32_rep iowrite32_rep | |
656 | static inline void iowrite32_rep(volatile void __iomem *addr, | |
657 | const void *buffer, | |
658 | unsigned int count) | |
659 | { | |
660 | writesl(addr, buffer, count); | |
661 | } | |
662 | #endif | |
9216efaf TR |
663 | #endif /* CONFIG_GENERIC_IOMAP */ |
664 | ||
3f7e212d AB |
665 | #ifdef __KERNEL__ |
666 | ||
667 | #include <linux/vmalloc.h> | |
9216efaf | 668 | #define __io_virt(x) ((void __force *)(x)) |
3f7e212d AB |
669 | |
670 | #ifndef CONFIG_GENERIC_IOMAP | |
3f7e212d | 671 | struct pci_dev; |
cd248341 JG |
672 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); |
673 | ||
674 | #ifndef pci_iounmap | |
9216efaf | 675 | #define pci_iounmap pci_iounmap |
3f7e212d AB |
676 | static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p) |
677 | { | |
678 | } | |
cd248341 | 679 | #endif |
3f7e212d AB |
680 | #endif /* CONFIG_GENERIC_IOMAP */ |
681 | ||
682 | /* | |
683 | * Change virtual addresses to physical addresses and vv. | |
684 | * These are pretty trivial | |
685 | */ | |
cd248341 | 686 | #ifndef virt_to_phys |
9216efaf | 687 | #define virt_to_phys virt_to_phys |
3f7e212d AB |
688 | static inline unsigned long virt_to_phys(volatile void *address) |
689 | { | |
690 | return __pa((unsigned long)address); | |
691 | } | |
9216efaf | 692 | #endif |
3f7e212d | 693 | |
9216efaf TR |
694 | #ifndef phys_to_virt |
695 | #define phys_to_virt phys_to_virt | |
3f7e212d AB |
696 | static inline void *phys_to_virt(unsigned long address) |
697 | { | |
698 | return __va(address); | |
699 | } | |
cd248341 | 700 | #endif |
3f7e212d AB |
701 | |
702 | /* | |
703 | * Change "struct page" to physical address. | |
f1ecc698 JB |
704 | * |
705 | * This implementation is for the no-MMU case only... if you have an MMU | |
706 | * you'll need to provide your own definitions. | |
3f7e212d | 707 | */ |
9216efaf | 708 | |
f1ecc698 | 709 | #ifndef CONFIG_MMU |
9216efaf TR |
710 | #ifndef ioremap |
711 | #define ioremap ioremap | |
712 | static inline void __iomem *ioremap(phys_addr_t offset, size_t size) | |
3f7e212d | 713 | { |
9216efaf | 714 | return (void __iomem *)(unsigned long)offset; |
3f7e212d | 715 | } |
9216efaf | 716 | #endif |
3f7e212d | 717 | |
9216efaf TR |
718 | #ifndef __ioremap |
719 | #define __ioremap __ioremap | |
720 | static inline void __iomem *__ioremap(phys_addr_t offset, size_t size, | |
721 | unsigned long flags) | |
722 | { | |
723 | return ioremap(offset, size); | |
724 | } | |
725 | #endif | |
3f7e212d AB |
726 | |
727 | #ifndef ioremap_nocache | |
9216efaf TR |
728 | #define ioremap_nocache ioremap_nocache |
729 | static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size) | |
730 | { | |
731 | return ioremap(offset, size); | |
732 | } | |
3f7e212d AB |
733 | #endif |
734 | ||
735 | #ifndef ioremap_wc | |
9216efaf TR |
736 | #define ioremap_wc ioremap_wc |
737 | static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size) | |
738 | { | |
739 | return ioremap_nocache(offset, size); | |
740 | } | |
3f7e212d AB |
741 | #endif |
742 | ||
9216efaf TR |
743 | #ifndef iounmap |
744 | #define iounmap iounmap | |
e66d3c49 | 745 | static inline void iounmap(void __iomem *addr) |
3f7e212d AB |
746 | { |
747 | } | |
9216efaf | 748 | #endif |
f1ecc698 | 749 | #endif /* CONFIG_MMU */ |
3f7e212d | 750 | |
ce816fa8 | 751 | #ifdef CONFIG_HAS_IOPORT_MAP |
3f7e212d | 752 | #ifndef CONFIG_GENERIC_IOMAP |
9216efaf TR |
753 | #ifndef ioport_map |
754 | #define ioport_map ioport_map | |
3f7e212d AB |
755 | static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) |
756 | { | |
112eeaa7 | 757 | return PCI_IOBASE + (port & IO_SPACE_LIMIT); |
3f7e212d | 758 | } |
9216efaf | 759 | #endif |
3f7e212d | 760 | |
9216efaf TR |
761 | #ifndef ioport_unmap |
762 | #define ioport_unmap ioport_unmap | |
3f7e212d AB |
763 | static inline void ioport_unmap(void __iomem *p) |
764 | { | |
765 | } | |
9216efaf | 766 | #endif |
3f7e212d AB |
767 | #else /* CONFIG_GENERIC_IOMAP */ |
768 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | |
769 | extern void ioport_unmap(void __iomem *p); | |
770 | #endif /* CONFIG_GENERIC_IOMAP */ | |
ce816fa8 | 771 | #endif /* CONFIG_HAS_IOPORT_MAP */ |
3f7e212d | 772 | |
576ebd74 | 773 | #ifndef xlate_dev_kmem_ptr |
9216efaf TR |
774 | #define xlate_dev_kmem_ptr xlate_dev_kmem_ptr |
775 | static inline void *xlate_dev_kmem_ptr(void *addr) | |
776 | { | |
777 | return addr; | |
778 | } | |
576ebd74 | 779 | #endif |
9216efaf | 780 | |
576ebd74 | 781 | #ifndef xlate_dev_mem_ptr |
9216efaf TR |
782 | #define xlate_dev_mem_ptr xlate_dev_mem_ptr |
783 | static inline void *xlate_dev_mem_ptr(phys_addr_t addr) | |
784 | { | |
785 | return __va(addr); | |
786 | } | |
787 | #endif | |
788 | ||
789 | #ifndef unxlate_dev_mem_ptr | |
790 | #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr | |
791 | static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr) | |
792 | { | |
793 | } | |
576ebd74 | 794 | #endif |
3f7e212d | 795 | |
c93d0312 | 796 | #ifdef CONFIG_VIRT_TO_BUS |
3f7e212d | 797 | #ifndef virt_to_bus |
9216efaf | 798 | static inline unsigned long virt_to_bus(void *address) |
3f7e212d | 799 | { |
9216efaf | 800 | return (unsigned long)address; |
3f7e212d AB |
801 | } |
802 | ||
803 | static inline void *bus_to_virt(unsigned long address) | |
804 | { | |
9216efaf | 805 | return (void *)address; |
3f7e212d AB |
806 | } |
807 | #endif | |
c93d0312 | 808 | #endif |
3f7e212d | 809 | |
cd248341 | 810 | #ifndef memset_io |
9216efaf TR |
811 | #define memset_io memset_io |
812 | static inline void memset_io(volatile void __iomem *addr, int value, | |
813 | size_t size) | |
814 | { | |
815 | memset(__io_virt(addr), value, size); | |
816 | } | |
cd248341 JG |
817 | #endif |
818 | ||
819 | #ifndef memcpy_fromio | |
9216efaf TR |
820 | #define memcpy_fromio memcpy_fromio |
821 | static inline void memcpy_fromio(void *buffer, | |
822 | const volatile void __iomem *addr, | |
823 | size_t size) | |
824 | { | |
825 | memcpy(buffer, __io_virt(addr), size); | |
826 | } | |
cd248341 | 827 | #endif |
9216efaf | 828 | |
cd248341 | 829 | #ifndef memcpy_toio |
9216efaf TR |
830 | #define memcpy_toio memcpy_toio |
831 | static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer, | |
832 | size_t size) | |
833 | { | |
834 | memcpy(__io_virt(addr), buffer, size); | |
835 | } | |
cd248341 | 836 | #endif |
3f7e212d AB |
837 | |
838 | #endif /* __KERNEL__ */ | |
839 | ||
840 | #endif /* __ASM_GENERIC_IO_H */ |