[mirror_ubuntu-artful-kernel.git] / include / asm-mips / txx9 / tx4927.h

/*
 * Author: MontaVista Software, Inc.
 *         source@mvista.com
 *
 * Copyright 2001-2006 MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#ifndef __ASM_TXX9_TX4927_H
#define __ASM_TXX9_TX4927_H

#include <linux/types.h>
#include <linux/io.h>
#include <asm/txx9irq.h>
#include <asm/txx9/tx4927pcic.h>

#ifdef CONFIG_64BIT
#define TX4927_REG_BASE	0xffffffffff1f0000UL
#else
#define TX4927_REG_BASE	0xff1f0000UL
#endif
#define TX4927_REG_SIZE	0x00010000

#define TX4927_SDRAMC_REG	(TX4927_REG_BASE + 0x8000)
#define TX4927_EBUSC_REG	(TX4927_REG_BASE + 0x9000)
#define TX4927_PCIC_REG		(TX4927_REG_BASE + 0xd000)
#define TX4927_CCFG_REG		(TX4927_REG_BASE + 0xe000)
#define TX4927_IRC_REG		(TX4927_REG_BASE + 0xf600)
#define TX4927_NR_TMR	3
#define TX4927_TMR_REG(ch)	(TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
#define TX4927_NR_SIO	2
#define TX4927_SIO_REG(ch)	(TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
#define TX4927_PIO_REG		(TX4927_REG_BASE + 0xf500)

#define TX4927_IR_INT(n)	(2 + (n))
#define TX4927_IR_SIO(n)	(8 + (n))
#define TX4927_IR_PCIC		16
#define TX4927_NUM_IR_TMR	3
#define TX4927_IR_TMR(n)	(17 + (n))
#define TX4927_IR_PCIERR	22
#define TX4927_NUM_IR	32

#define TX4927_IRC_INT	2	/* IP[2] in Status register */

#define TX4927_NUM_PIO	16

struct tx4927_sdramc_reg {
	u64 cr[4];
	u64 unused0[4];
	u64 tr;
	u64 unused1[2];
	u64 cmd;
};

struct tx4927_ebusc_reg {
	u64 cr[8];
};

struct tx4927_ccfg_reg {
	u64 ccfg;
	u64 crir;
	u64 pcfg;
	u64 toea;
	u64 clkctr;
	u64 unused0;
	u64 garbc;
	u64 unused1;
	u64 unused2;
	u64 ramp;
};

/*
 * CCFG
 */
/* CCFG : Chip Configuration */
#define TX4927_CCFG_WDRST	0x0000020000000000ULL
#define TX4927_CCFG_WDREXEN	0x0000010000000000ULL
#define TX4927_CCFG_BCFG_MASK	0x000000ff00000000ULL
#define TX4927_CCFG_TINTDIS	0x01000000
#define TX4927_CCFG_PCI66	0x00800000
#define TX4927_CCFG_PCIMODE	0x00400000
#define TX4927_CCFG_DIVMODE_MASK	0x000e0000
#define TX4927_CCFG_DIVMODE_8	(0x0 << 17)
#define TX4927_CCFG_DIVMODE_12	(0x1 << 17)
#define TX4927_CCFG_DIVMODE_16	(0x2 << 17)
#define TX4927_CCFG_DIVMODE_10	(0x3 << 17)
#define TX4927_CCFG_DIVMODE_2	(0x4 << 17)
#define TX4927_CCFG_DIVMODE_3	(0x5 << 17)
#define TX4927_CCFG_DIVMODE_4	(0x6 << 17)
#define TX4927_CCFG_DIVMODE_2_5	(0x7 << 17)
#define TX4927_CCFG_BEOW	0x00010000
#define TX4927_CCFG_WR	0x00008000
#define TX4927_CCFG_TOE	0x00004000
#define TX4927_CCFG_PCIARB	0x00002000
#define TX4927_CCFG_PCIDIVMODE_MASK	0x00001800
#define TX4927_CCFG_PCIDIVMODE_2_5	0x00000000
#define TX4927_CCFG_PCIDIVMODE_3	0x00000800
#define TX4927_CCFG_PCIDIVMODE_5	0x00001000
#define TX4927_CCFG_PCIDIVMODE_6	0x00001800
#define TX4927_CCFG_SYSSP_MASK	0x000000c0
#define TX4927_CCFG_ENDIAN	0x00000004
#define TX4927_CCFG_HALT	0x00000002
#define TX4927_CCFG_ACEHOLD	0x00000001
#define TX4927_CCFG_W1CBITS	(TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)

/* PCFG : Pin Configuration */
#define TX4927_PCFG_SDCLKDLY_MASK	0x30000000
#define TX4927_PCFG_SDCLKDLY(d)	((d)<<28)
#define TX4927_PCFG_SYSCLKEN	0x08000000
#define TX4927_PCFG_SDCLKEN_ALL	0x07800000
#define TX4927_PCFG_SDCLKEN(ch)	(0x00800000<<(ch))
#define TX4927_PCFG_PCICLKEN_ALL	0x003f0000
#define TX4927_PCFG_PCICLKEN(ch)	(0x00010000<<(ch))
#define TX4927_PCFG_SEL2	0x00000200
#define TX4927_PCFG_SEL1	0x00000100
#define TX4927_PCFG_DMASEL_ALL	0x000000ff
#define TX4927_PCFG_DMASEL0_MASK	0x00000003
#define TX4927_PCFG_DMASEL1_MASK	0x0000000c
#define TX4927_PCFG_DMASEL2_MASK	0x00000030
#define TX4927_PCFG_DMASEL3_MASK	0x000000c0
#define TX4927_PCFG_DMASEL0_DRQ0	0x00000000
#define TX4927_PCFG_DMASEL0_SIO1	0x00000001
#define TX4927_PCFG_DMASEL0_ACL0	0x00000002
#define TX4927_PCFG_DMASEL0_ACL2	0x00000003
#define TX4927_PCFG_DMASEL1_DRQ1	0x00000000
#define TX4927_PCFG_DMASEL1_SIO1	0x00000004
#define TX4927_PCFG_DMASEL1_ACL1	0x00000008
#define TX4927_PCFG_DMASEL1_ACL3	0x0000000c
#define TX4927_PCFG_DMASEL2_DRQ2	0x00000000	/* SEL2=0 */
#define TX4927_PCFG_DMASEL2_SIO0	0x00000010	/* SEL2=0 */
#define TX4927_PCFG_DMASEL2_ACL1	0x00000000	/* SEL2=1 */
#define TX4927_PCFG_DMASEL2_ACL2	0x00000020	/* SEL2=1 */
#define TX4927_PCFG_DMASEL2_ACL0	0x00000030	/* SEL2=1 */
#define TX4927_PCFG_DMASEL3_DRQ3	0x00000000
#define TX4927_PCFG_DMASEL3_SIO0	0x00000040
#define TX4927_PCFG_DMASEL3_ACL3	0x00000080
#define TX4927_PCFG_DMASEL3_ACL1	0x000000c0

/* CLKCTR : Clock Control */
#define TX4927_CLKCTR_ACLCKD	0x02000000
#define TX4927_CLKCTR_PIOCKD	0x01000000
#define TX4927_CLKCTR_DMACKD	0x00800000
#define TX4927_CLKCTR_PCICKD	0x00400000
#define TX4927_CLKCTR_TM0CKD	0x00100000
#define TX4927_CLKCTR_TM1CKD	0x00080000
#define TX4927_CLKCTR_TM2CKD	0x00040000
#define TX4927_CLKCTR_SIO0CKD	0x00020000
#define TX4927_CLKCTR_SIO1CKD	0x00010000
#define TX4927_CLKCTR_ACLRST	0x00000200
#define TX4927_CLKCTR_PIORST	0x00000100
#define TX4927_CLKCTR_DMARST	0x00000080
#define TX4927_CLKCTR_PCIRST	0x00000040
#define TX4927_CLKCTR_TM0RST	0x00000010
#define TX4927_CLKCTR_TM1RST	0x00000008
#define TX4927_CLKCTR_TM2RST	0x00000004
#define TX4927_CLKCTR_SIO0RST	0x00000002
#define TX4927_CLKCTR_SIO1RST	0x00000001

#define tx4927_sdramcptr \
		((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
#define tx4927_pcicptr \
		((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
#define tx4927_ccfgptr \
		((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
#define tx4927_ebuscptr \
		((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
#define tx4927_pioptr		((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)

#define TX4927_REV_PCODE()	\
	((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)

#define TX4927_SDRAMC_CR(ch)	__raw_readq(&tx4927_sdramcptr->cr[(ch)])
#define TX4927_SDRAMC_BA(ch)	((TX4927_SDRAMC_CR(ch) >> 49) << 21)
#define TX4927_SDRAMC_SIZE(ch)	\
	((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)

#define TX4927_EBUSC_CR(ch)	__raw_readq(&tx4927_ebuscptr->cr[(ch)])
#define TX4927_EBUSC_BA(ch)	((TX4927_EBUSC_CR(ch) >> 48) << 20)
#define TX4927_EBUSC_SIZE(ch)	\
	(0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))

/* utilities */
static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
{
#ifdef CONFIG_32BIT
	unsigned long flags;
	local_irq_save(flags);
#endif
	____raw_writeq(____raw_readq(adr) & ~bits, adr);
#ifdef CONFIG_32BIT
	local_irq_restore(flags);
#endif
}
static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
{
#ifdef CONFIG_32BIT
	unsigned long flags;
	local_irq_save(flags);
#endif
	____raw_writeq(____raw_readq(adr) | bits, adr);
#ifdef CONFIG_32BIT
	local_irq_restore(flags);
#endif
}

/* These functions are not interrupt safe. */
static inline void tx4927_ccfg_clear(__u64 bits)
{
	____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
		       & ~(TX4927_CCFG_W1CBITS | bits),
		       &tx4927_ccfgptr->ccfg);
}
static inline void tx4927_ccfg_set(__u64 bits)
{
	____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
			& ~TX4927_CCFG_W1CBITS) | bits,
		       &tx4927_ccfgptr->ccfg);
}
static inline void tx4927_ccfg_change(__u64 change, __u64 new)
{
	____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
			& ~(TX4927_CCFG_W1CBITS | change)) |
		       new,
		       &tx4927_ccfgptr->ccfg);
}

unsigned int tx4927_get_mem_size(void);
void tx4927_wdt_init(void);
void tx4927_setup(void);
void tx4927_time_init(unsigned int tmrnr);
void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
int tx4927_report_pciclk(void);
int tx4927_pciclk66_setup(void);
void tx4927_setup_pcierr_irq(void);
void tx4927_irq_init(void);

#endif /* __ASM_TXX9_TX4927_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* source@mvista.com
	4	*
6fe2a568	5	* Copyright 2001-2006 MontaVista Software Inc.
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	13	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	14	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	15	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	16	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	17	* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
	18	* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	19	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
	20	* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
	21	* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	22	*
	23	* You should have received a copy of the GNU General Public License along
	24	* with this program; if not, write to the Free Software Foundation, Inc.,
	25	* 675 Mass Ave, Cambridge, MA 02139, USA.
	26	*/
22b1d707 AN	27	#ifndef __ASM_TXX9_TX4927_H
22b1d707 AN	28	#define __ASM_TXX9_TX4927_H
1da177e4	29
89d63fe1 AN	30	#include <linux/types.h>
89d63fe1 AN	31	#include <linux/io.h>
c87abd75	32	#include <asm/txx9irq.h>
89d63fe1	33	#include <asm/txx9/tx4927pcic.h>
1da177e4	34
255033a9 AN	35	#ifdef CONFIG_64BIT
	36	#define TX4927_REG_BASE 0xffffffffff1f0000UL
	37	#else
	38	#define TX4927_REG_BASE 0xff1f0000UL
	39	#endif
	40	#define TX4927_REG_SIZE 0x00010000
	41
	42	#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
	43	#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
	44	#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
	45	#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
	46	#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
b29eee49	47	#define TX4927_NR_TMR 3
255033a9	48	#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
94a4c329 AN	49	#define TX4927_NR_SIO 2
	50	#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
	51	#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
b29eee49	52
edcaf1a6 AN	53	#define TX4927_IR_INT(n) (2 + (n))
edcaf1a6 AN	54	#define TX4927_IR_SIO(n) (8 + (n))
b29eee49	55	#define TX4927_IR_PCIC 16
94a4c329 AN	56	#define TX4927_NUM_IR_TMR 3
94a4c329 AN	57	#define TX4927_IR_TMR(n) (17 + (n))
b29eee49	58	#define TX4927_IR_PCIERR 22
89d63fe1	59	#define TX4927_NUM_IR 32
b29eee49	60
edcaf1a6 AN	61	#define TX4927_IRC_INT 2 /* IP[2] in Status register */
edcaf1a6 AN	62
94a4c329 AN	63	#define TX4927_NUM_PIO 16
94a4c329 AN	64
b29eee49	65	struct tx4927_sdramc_reg {
255033a9 AN	66	u64 cr[4];
	67	u64 unused0[4];
	68	u64 tr;
	69	u64 unused1[2];
	70	u64 cmd;
b29eee49 AN	71	};
	72
	73	struct tx4927_ebusc_reg {
255033a9	74	u64 cr[8];
b29eee49 AN	75	};
	76
	77	struct tx4927_ccfg_reg {
89d63fe1 AN	78	u64 ccfg;
	79	u64 crir;
	80	u64 pcfg;
	81	u64 toea;
	82	u64 clkctr;
	83	u64 unused0;
	84	u64 garbc;
	85	u64 unused1;
	86	u64 unused2;
	87	u64 ramp;
b29eee49 AN	88	};
b29eee49 AN	89
b29eee49 AN	90	/*
	91	* CCFG
	92	*/
	93	/* CCFG : Chip Configuration */
89d63fe1 AN	94	#define TX4927_CCFG_WDRST 0x0000020000000000ULL
	95	#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
	96	#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
	97	#define TX4927_CCFG_TINTDIS 0x01000000
b29eee49	98	#define TX4927_CCFG_PCI66 0x00800000
89d63fe1 AN	99	#define TX4927_CCFG_PCIMODE 0x00400000
	100	#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
	101	#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
	102	#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
	103	#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
	104	#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
	105	#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
	106	#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
	107	#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
	108	#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
	109	#define TX4927_CCFG_BEOW 0x00010000
	110	#define TX4927_CCFG_WR 0x00008000
	111	#define TX4927_CCFG_TOE 0x00004000
	112	#define TX4927_CCFG_PCIARB 0x00002000
b29eee49 AN	113	#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
	114	#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
	115	#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
	116	#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
	117	#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
89d63fe1 AN	118	#define TX4927_CCFG_SYSSP_MASK 0x000000c0
	119	#define TX4927_CCFG_ENDIAN 0x00000004
	120	#define TX4927_CCFG_HALT 0x00000002
	121	#define TX4927_CCFG_ACEHOLD 0x00000001
	122	#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST \| TX4927_CCFG_BEOW)
b29eee49 AN	123
b29eee49 AN	124	/* PCFG : Pin Configuration */
89d63fe1 AN	125	#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
	126	#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
	127	#define TX4927_PCFG_SYSCLKEN 0x08000000
	128	#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
	129	#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
b29eee49 AN	130	#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
b29eee49 AN	131	#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
89d63fe1 AN	132	#define TX4927_PCFG_SEL2 0x00000200
	133	#define TX4927_PCFG_SEL1 0x00000100
	134	#define TX4927_PCFG_DMASEL_ALL 0x000000ff
	135	#define TX4927_PCFG_DMASEL0_MASK 0x00000003
	136	#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
	137	#define TX4927_PCFG_DMASEL2_MASK 0x00000030
	138	#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
	139	#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
	140	#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
	141	#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
	142	#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
	143	#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
	144	#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
	145	#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
	146	#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
	147	#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
	148	#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
	149	#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
	150	#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
	151	#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
	152	#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
	153	#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
	154	#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
	155	#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
b29eee49 AN	156
b29eee49 AN	157	/* CLKCTR : Clock Control */
89d63fe1 AN	158	#define TX4927_CLKCTR_ACLCKD 0x02000000
	159	#define TX4927_CLKCTR_PIOCKD 0x01000000
	160	#define TX4927_CLKCTR_DMACKD 0x00800000
b29eee49	161	#define TX4927_CLKCTR_PCICKD 0x00400000
89d63fe1 AN	162	#define TX4927_CLKCTR_TM0CKD 0x00100000
	163	#define TX4927_CLKCTR_TM1CKD 0x00080000
	164	#define TX4927_CLKCTR_TM2CKD 0x00040000
	165	#define TX4927_CLKCTR_SIO0CKD 0x00020000
	166	#define TX4927_CLKCTR_SIO1CKD 0x00010000
	167	#define TX4927_CLKCTR_ACLRST 0x00000200
	168	#define TX4927_CLKCTR_PIORST 0x00000100
	169	#define TX4927_CLKCTR_DMARST 0x00000080
b29eee49	170	#define TX4927_CLKCTR_PCIRST 0x00000040
89d63fe1 AN	171	#define TX4927_CLKCTR_TM0RST 0x00000010
	172	#define TX4927_CLKCTR_TM1RST 0x00000008
	173	#define TX4927_CLKCTR_TM2RST 0x00000004
	174	#define TX4927_CLKCTR_SIO0RST 0x00000002
	175	#define TX4927_CLKCTR_SIO1RST 0x00000001
b29eee49	176
255033a9 AN	177	#define tx4927_sdramcptr \
255033a9 AN	178	((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
89d63fe1 AN	179	#define tx4927_pcicptr \
	180	((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
	181	#define tx4927_ccfgptr \
	182	((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
255033a9 AN	183	#define tx4927_ebuscptr \
255033a9 AN	184	((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
94a4c329 AN	185	#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
	186
	187	#define TX4927_REV_PCODE() \
	188	((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
255033a9 AN	189
	190	#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
	191	#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
	192	#define TX4927_SDRAMC_SIZE(ch) \
	193	((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
	194
	195	#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
	196	#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
	197	#define TX4927_EBUSC_SIZE(ch) \
	198	(0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
b29eee49	199
89d63fe1 AN	200	/* utilities */
	201	static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
	202	{
	203	#ifdef CONFIG_32BIT
	204	unsigned long flags;
	205	local_irq_save(flags);
	206	#endif
	207	____raw_writeq(____raw_readq(adr) & ~bits, adr);
	208	#ifdef CONFIG_32BIT
	209	local_irq_restore(flags);
	210	#endif
	211	}
	212	static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
	213	{
	214	#ifdef CONFIG_32BIT
	215	unsigned long flags;
	216	local_irq_save(flags);
	217	#endif
	218	____raw_writeq(____raw_readq(adr) \| bits, adr);
	219	#ifdef CONFIG_32BIT
	220	local_irq_restore(flags);
	221	#endif
	222	}
	223
	224	/* These functions are not interrupt safe. */
	225	static inline void tx4927_ccfg_clear(__u64 bits)
	226	{
	227	____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
	228	& ~(TX4927_CCFG_W1CBITS \| bits),
	229	&tx4927_ccfgptr->ccfg);
	230	}
	231	static inline void tx4927_ccfg_set(__u64 bits)
	232	{
	233	____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
	234	& ~TX4927_CCFG_W1CBITS) \| bits,
	235	&tx4927_ccfgptr->ccfg);
	236	}
	237	static inline void tx4927_ccfg_change(__u64 change, __u64 new)
	238	{
	239	____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
	240	& ~(TX4927_CCFG_W1CBITS \| change)) \|
	241	new,
	242	&tx4927_ccfgptr->ccfg);
	243	}
	244
255033a9	245	unsigned int tx4927_get_mem_size(void);
68314725	246	void tx4927_wdt_init(void);
94a4c329 AN	247	void tx4927_setup(void);
94a4c329 AN	248	void tx4927_time_init(unsigned int tmrnr);
7779a5e0	249	void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
89d63fe1 AN	250	int tx4927_report_pciclk(void);
89d63fe1 AN	251	int tx4927_pciclk66_setup(void);
455cc256	252	void tx4927_setup_pcierr_irq(void);
edcaf1a6	253	void tx4927_irq_init(void);
b29eee49	254
22b1d707	255	#endif /* __ASM_TXX9_TX4927_H */