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2d539553 TG |
1 | #ifndef _ASM_X86_APICDEF_H |
2 | #define _ASM_X86_APICDEF_H | |
3 | ||
4 | /* | |
5 | * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) | |
6 | * | |
7 | * Alan Cox <Alan.Cox@linux.org>, 1995. | |
8 | * Ingo Molnar <mingo@redhat.com>, 1999, 2000 | |
9 | */ | |
10 | ||
11 | #define APIC_DEFAULT_PHYS_BASE 0xfee00000 | |
12 | ||
13 | #define APIC_ID 0x20 | |
14 | ||
15 | #ifdef CONFIG_X86_64 | |
16 | # define APIC_ID_MASK (0xFFu<<24) | |
17 | # define GET_APIC_ID(x) (((x)>>24)&0xFFu) | |
18 | # define SET_APIC_ID(x) (((x)<<24)) | |
19 | #endif | |
20 | ||
21 | #define APIC_LVR 0x30 | |
22 | #define APIC_LVR_MASK 0xFF00FF | |
23 | #define GET_APIC_VERSION(x) ((x)&0xFFu) | |
24 | #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu) | |
25 | #define APIC_INTEGRATED(x) ((x)&0xF0u) | |
26 | #define APIC_XAPIC(x) ((x) >= 0x14) | |
27 | #define APIC_TASKPRI 0x80 | |
28 | #define APIC_TPRI_MASK 0xFFu | |
29 | #define APIC_ARBPRI 0x90 | |
30 | #define APIC_ARBPRI_MASK 0xFFu | |
31 | #define APIC_PROCPRI 0xA0 | |
32 | #define APIC_EOI 0xB0 | |
33 | #define APIC_EIO_ACK 0x0 | |
34 | #define APIC_RRR 0xC0 | |
35 | #define APIC_LDR 0xD0 | |
36 | #define APIC_LDR_MASK (0xFFu<<24) | |
37 | #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu) | |
38 | #define SET_APIC_LOGICAL_ID(x) (((x)<<24)) | |
39 | #define APIC_ALL_CPUS 0xFFu | |
40 | #define APIC_DFR 0xE0 | |
41 | #define APIC_DFR_CLUSTER 0x0FFFFFFFul | |
42 | #define APIC_DFR_FLAT 0xFFFFFFFFul | |
43 | #define APIC_SPIV 0xF0 | |
44 | #define APIC_SPIV_FOCUS_DISABLED (1<<9) | |
45 | #define APIC_SPIV_APIC_ENABLED (1<<8) | |
46 | #define APIC_ISR 0x100 | |
47 | #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ | |
48 | #define APIC_TMR 0x180 | |
49 | #define APIC_IRR 0x200 | |
50 | #define APIC_ESR 0x280 | |
51 | #define APIC_ESR_SEND_CS 0x00001 | |
52 | #define APIC_ESR_RECV_CS 0x00002 | |
53 | #define APIC_ESR_SEND_ACC 0x00004 | |
54 | #define APIC_ESR_RECV_ACC 0x00008 | |
55 | #define APIC_ESR_SENDILL 0x00020 | |
56 | #define APIC_ESR_RECVILL 0x00040 | |
57 | #define APIC_ESR_ILLREGA 0x00080 | |
58 | #define APIC_ICR 0x300 | |
59 | #define APIC_DEST_SELF 0x40000 | |
60 | #define APIC_DEST_ALLINC 0x80000 | |
61 | #define APIC_DEST_ALLBUT 0xC0000 | |
62 | #define APIC_ICR_RR_MASK 0x30000 | |
63 | #define APIC_ICR_RR_INVALID 0x00000 | |
64 | #define APIC_ICR_RR_INPROG 0x10000 | |
65 | #define APIC_ICR_RR_VALID 0x20000 | |
66 | #define APIC_INT_LEVELTRIG 0x08000 | |
67 | #define APIC_INT_ASSERT 0x04000 | |
68 | #define APIC_ICR_BUSY 0x01000 | |
69 | #define APIC_DEST_LOGICAL 0x00800 | |
70 | #define APIC_DEST_PHYSICAL 0x00000 | |
71 | #define APIC_DM_FIXED 0x00000 | |
72 | #define APIC_DM_LOWEST 0x00100 | |
73 | #define APIC_DM_SMI 0x00200 | |
74 | #define APIC_DM_REMRD 0x00300 | |
75 | #define APIC_DM_NMI 0x00400 | |
76 | #define APIC_DM_INIT 0x00500 | |
77 | #define APIC_DM_STARTUP 0x00600 | |
78 | #define APIC_DM_EXTINT 0x00700 | |
79 | #define APIC_VECTOR_MASK 0x000FF | |
80 | #define APIC_ICR2 0x310 | |
81 | #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) | |
82 | #define SET_APIC_DEST_FIELD(x) ((x)<<24) | |
83 | #define APIC_LVTT 0x320 | |
84 | #define APIC_LVTTHMR 0x330 | |
85 | #define APIC_LVTPC 0x340 | |
86 | #define APIC_LVT0 0x350 | |
87 | #define APIC_LVT_TIMER_BASE_MASK (0x3<<18) | |
88 | #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3) | |
89 | #define SET_APIC_TIMER_BASE(x) (((x)<<18)) | |
90 | #define APIC_TIMER_BASE_CLKIN 0x0 | |
91 | #define APIC_TIMER_BASE_TMBASE 0x1 | |
92 | #define APIC_TIMER_BASE_DIV 0x2 | |
93 | #define APIC_LVT_TIMER_PERIODIC (1<<17) | |
94 | #define APIC_LVT_MASKED (1<<16) | |
95 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) | |
96 | #define APIC_LVT_REMOTE_IRR (1<<14) | |
97 | #define APIC_INPUT_POLARITY (1<<13) | |
98 | #define APIC_SEND_PENDING (1<<12) | |
99 | #define APIC_MODE_MASK 0x700 | |
100 | #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) | |
cff90dbf | 101 | #define SET_APIC_DELIVERY_MODE(x, y) (((x)&~0x700)|((y)<<8)) |
2d539553 TG |
102 | #define APIC_MODE_FIXED 0x0 |
103 | #define APIC_MODE_NMI 0x4 | |
104 | #define APIC_MODE_EXTINT 0x7 | |
105 | #define APIC_LVT1 0x360 | |
106 | #define APIC_LVTERR 0x370 | |
107 | #define APIC_TMICT 0x380 | |
108 | #define APIC_TMCCT 0x390 | |
109 | #define APIC_TDCR 0x3E0 | |
110 | #define APIC_TDR_DIV_TMBASE (1<<2) | |
111 | #define APIC_TDR_DIV_1 0xB | |
112 | #define APIC_TDR_DIV_2 0x0 | |
113 | #define APIC_TDR_DIV_4 0x1 | |
114 | #define APIC_TDR_DIV_8 0x2 | |
115 | #define APIC_TDR_DIV_16 0x3 | |
116 | #define APIC_TDR_DIV_32 0x8 | |
117 | #define APIC_TDR_DIV_64 0x9 | |
118 | #define APIC_TDR_DIV_128 0xA | |
7b83dae7 RR |
119 | #define APIC_EILVT0 0x500 |
120 | #define APIC_EILVT_NR_AMD_K8 1 /* Number of extended interrupts */ | |
121 | #define APIC_EILVT_NR_AMD_10H 4 | |
122 | #define APIC_EILVT_LVTOFF(x) (((x)>>4)&0xF) | |
123 | #define APIC_EILVT_MSG_FIX 0x0 | |
124 | #define APIC_EILVT_MSG_SMI 0x2 | |
125 | #define APIC_EILVT_MSG_NMI 0x4 | |
126 | #define APIC_EILVT_MSG_EXT 0x7 | |
127 | #define APIC_EILVT_MASKED (1<<16) | |
128 | #define APIC_EILVT1 0x510 | |
129 | #define APIC_EILVT2 0x520 | |
130 | #define APIC_EILVT3 0x530 | |
cff90dbf | 131 | |
2d539553 TG |
132 | #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
133 | ||
96a388de | 134 | #ifdef CONFIG_X86_32 |
2d539553 | 135 | # define MAX_IO_APICS 64 |
96a388de | 136 | #else |
2d539553 TG |
137 | # define MAX_IO_APICS 128 |
138 | # define MAX_LOCAL_APIC 256 | |
139 | #endif | |
140 | ||
141 | /* | |
142 | * All x86-64 systems are xAPIC compatible. | |
143 | * In the following, "apicid" is a physical APIC ID. | |
144 | */ | |
145 | #define XAPIC_DEST_CPUS_SHIFT 4 | |
146 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) | |
147 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) | |
148 | #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) | |
149 | #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) | |
150 | #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) | |
151 | #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) | |
152 | ||
153 | /* | |
154 | * the local APIC register structure, memory mapped. Not terribly well | |
155 | * tested, but we might eventually use this one in the future - the | |
156 | * problem why we cannot use it right now is the P5 APIC, it has an | |
157 | * errata which cannot take 8-bit reads and writes, only 32-bit ones ... | |
158 | */ | |
159 | #define u32 unsigned int | |
160 | ||
161 | struct local_apic { | |
162 | ||
163 | /*000*/ struct { u32 __reserved[4]; } __reserved_01; | |
164 | ||
165 | /*010*/ struct { u32 __reserved[4]; } __reserved_02; | |
166 | ||
167 | /*020*/ struct { /* APIC ID Register */ | |
168 | u32 __reserved_1 : 24, | |
169 | phys_apic_id : 4, | |
170 | __reserved_2 : 4; | |
171 | u32 __reserved[3]; | |
172 | } id; | |
173 | ||
174 | /*030*/ const | |
175 | struct { /* APIC Version Register */ | |
176 | u32 version : 8, | |
177 | __reserved_1 : 8, | |
178 | max_lvt : 8, | |
179 | __reserved_2 : 8; | |
180 | u32 __reserved[3]; | |
181 | } version; | |
182 | ||
183 | /*040*/ struct { u32 __reserved[4]; } __reserved_03; | |
184 | ||
185 | /*050*/ struct { u32 __reserved[4]; } __reserved_04; | |
186 | ||
187 | /*060*/ struct { u32 __reserved[4]; } __reserved_05; | |
188 | ||
189 | /*070*/ struct { u32 __reserved[4]; } __reserved_06; | |
190 | ||
191 | /*080*/ struct { /* Task Priority Register */ | |
192 | u32 priority : 8, | |
193 | __reserved_1 : 24; | |
194 | u32 __reserved_2[3]; | |
195 | } tpr; | |
196 | ||
197 | /*090*/ const | |
198 | struct { /* Arbitration Priority Register */ | |
199 | u32 priority : 8, | |
200 | __reserved_1 : 24; | |
201 | u32 __reserved_2[3]; | |
202 | } apr; | |
203 | ||
204 | /*0A0*/ const | |
205 | struct { /* Processor Priority Register */ | |
206 | u32 priority : 8, | |
207 | __reserved_1 : 24; | |
208 | u32 __reserved_2[3]; | |
209 | } ppr; | |
210 | ||
211 | /*0B0*/ struct { /* End Of Interrupt Register */ | |
212 | u32 eoi; | |
213 | u32 __reserved[3]; | |
214 | } eoi; | |
215 | ||
216 | /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; | |
217 | ||
218 | /*0D0*/ struct { /* Logical Destination Register */ | |
219 | u32 __reserved_1 : 24, | |
220 | logical_dest : 8; | |
221 | u32 __reserved_2[3]; | |
222 | } ldr; | |
223 | ||
224 | /*0E0*/ struct { /* Destination Format Register */ | |
225 | u32 __reserved_1 : 28, | |
226 | model : 4; | |
227 | u32 __reserved_2[3]; | |
228 | } dfr; | |
229 | ||
230 | /*0F0*/ struct { /* Spurious Interrupt Vector Register */ | |
231 | u32 spurious_vector : 8, | |
232 | apic_enabled : 1, | |
233 | focus_cpu : 1, | |
234 | __reserved_2 : 22; | |
235 | u32 __reserved_3[3]; | |
236 | } svr; | |
237 | ||
238 | /*100*/ struct { /* In Service Register */ | |
239 | /*170*/ u32 bitfield; | |
240 | u32 __reserved[3]; | |
241 | } isr [8]; | |
242 | ||
243 | /*180*/ struct { /* Trigger Mode Register */ | |
244 | /*1F0*/ u32 bitfield; | |
245 | u32 __reserved[3]; | |
246 | } tmr [8]; | |
247 | ||
248 | /*200*/ struct { /* Interrupt Request Register */ | |
249 | /*270*/ u32 bitfield; | |
250 | u32 __reserved[3]; | |
251 | } irr [8]; | |
252 | ||
253 | /*280*/ union { /* Error Status Register */ | |
254 | struct { | |
255 | u32 send_cs_error : 1, | |
256 | receive_cs_error : 1, | |
257 | send_accept_error : 1, | |
258 | receive_accept_error : 1, | |
259 | __reserved_1 : 1, | |
260 | send_illegal_vector : 1, | |
261 | receive_illegal_vector : 1, | |
262 | illegal_register_address : 1, | |
263 | __reserved_2 : 24; | |
264 | u32 __reserved_3[3]; | |
265 | } error_bits; | |
266 | struct { | |
267 | u32 errors; | |
268 | u32 __reserved_3[3]; | |
269 | } all_errors; | |
270 | } esr; | |
271 | ||
272 | /*290*/ struct { u32 __reserved[4]; } __reserved_08; | |
273 | ||
274 | /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; | |
275 | ||
276 | /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; | |
277 | ||
278 | /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; | |
279 | ||
280 | /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; | |
281 | ||
282 | /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; | |
283 | ||
284 | /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; | |
285 | ||
286 | /*300*/ struct { /* Interrupt Command Register 1 */ | |
287 | u32 vector : 8, | |
288 | delivery_mode : 3, | |
289 | destination_mode : 1, | |
290 | delivery_status : 1, | |
291 | __reserved_1 : 1, | |
292 | level : 1, | |
293 | trigger : 1, | |
294 | __reserved_2 : 2, | |
295 | shorthand : 2, | |
296 | __reserved_3 : 12; | |
297 | u32 __reserved_4[3]; | |
298 | } icr1; | |
299 | ||
300 | /*310*/ struct { /* Interrupt Command Register 2 */ | |
301 | union { | |
302 | u32 __reserved_1 : 24, | |
303 | phys_dest : 4, | |
304 | __reserved_2 : 4; | |
305 | u32 __reserved_3 : 24, | |
306 | logical_dest : 8; | |
307 | } dest; | |
308 | u32 __reserved_4[3]; | |
309 | } icr2; | |
310 | ||
311 | /*320*/ struct { /* LVT - Timer */ | |
312 | u32 vector : 8, | |
313 | __reserved_1 : 4, | |
314 | delivery_status : 1, | |
315 | __reserved_2 : 3, | |
316 | mask : 1, | |
317 | timer_mode : 1, | |
318 | __reserved_3 : 14; | |
319 | u32 __reserved_4[3]; | |
320 | } lvt_timer; | |
321 | ||
322 | /*330*/ struct { /* LVT - Thermal Sensor */ | |
323 | u32 vector : 8, | |
324 | delivery_mode : 3, | |
325 | __reserved_1 : 1, | |
326 | delivery_status : 1, | |
327 | __reserved_2 : 3, | |
328 | mask : 1, | |
329 | __reserved_3 : 15; | |
330 | u32 __reserved_4[3]; | |
331 | } lvt_thermal; | |
332 | ||
333 | /*340*/ struct { /* LVT - Performance Counter */ | |
334 | u32 vector : 8, | |
335 | delivery_mode : 3, | |
336 | __reserved_1 : 1, | |
337 | delivery_status : 1, | |
338 | __reserved_2 : 3, | |
339 | mask : 1, | |
340 | __reserved_3 : 15; | |
341 | u32 __reserved_4[3]; | |
342 | } lvt_pc; | |
343 | ||
344 | /*350*/ struct { /* LVT - LINT0 */ | |
345 | u32 vector : 8, | |
346 | delivery_mode : 3, | |
347 | __reserved_1 : 1, | |
348 | delivery_status : 1, | |
349 | polarity : 1, | |
350 | remote_irr : 1, | |
351 | trigger : 1, | |
352 | mask : 1, | |
353 | __reserved_2 : 15; | |
354 | u32 __reserved_3[3]; | |
355 | } lvt_lint0; | |
356 | ||
357 | /*360*/ struct { /* LVT - LINT1 */ | |
358 | u32 vector : 8, | |
359 | delivery_mode : 3, | |
360 | __reserved_1 : 1, | |
361 | delivery_status : 1, | |
362 | polarity : 1, | |
363 | remote_irr : 1, | |
364 | trigger : 1, | |
365 | mask : 1, | |
366 | __reserved_2 : 15; | |
367 | u32 __reserved_3[3]; | |
368 | } lvt_lint1; | |
369 | ||
370 | /*370*/ struct { /* LVT - Error */ | |
371 | u32 vector : 8, | |
372 | __reserved_1 : 4, | |
373 | delivery_status : 1, | |
374 | __reserved_2 : 3, | |
375 | mask : 1, | |
376 | __reserved_3 : 15; | |
377 | u32 __reserved_4[3]; | |
378 | } lvt_error; | |
379 | ||
380 | /*380*/ struct { /* Timer Initial Count Register */ | |
381 | u32 initial_count; | |
382 | u32 __reserved_2[3]; | |
383 | } timer_icr; | |
384 | ||
385 | /*390*/ const | |
386 | struct { /* Timer Current Count Register */ | |
387 | u32 curr_count; | |
388 | u32 __reserved_2[3]; | |
389 | } timer_ccr; | |
390 | ||
391 | /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; | |
392 | ||
393 | /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; | |
394 | ||
395 | /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; | |
396 | ||
397 | /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; | |
398 | ||
399 | /*3E0*/ struct { /* Timer Divide Configuration Register */ | |
400 | u32 divisor : 4, | |
401 | __reserved_1 : 28; | |
402 | u32 __reserved_2[3]; | |
403 | } timer_dcr; | |
404 | ||
405 | /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; | |
406 | ||
407 | } __attribute__ ((packed)); | |
408 | ||
409 | #undef u32 | |
410 | ||
411 | #define BAD_APICID 0xFFu | |
412 | ||
96a388de | 413 | #endif |