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CommitLineData
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1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H 1
3
07f35073 4/* CPU interfaces that are target independent. */
1ad2134f 5
ce927ed9 6#ifndef CONFIG_USER_ONLY
022c62cb 7#include "exec/hwaddr.h"
ce927ed9 8#endif
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9
10#ifndef NEED_CPU_H
022c62cb 11#include "exec/poison.h"
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12#endif
13
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14#include "qemu/bswap.h"
15#include "qemu/queue.h"
1ad2134f 16
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17/**
18 * CPUListState:
19 * @cpu_fprintf: Print function.
20 * @file: File to print to using @cpu_fprint.
21 *
22 * State commonly used for iterating over CPU models.
23 */
24typedef struct CPUListState {
25 fprintf_function cpu_fprintf;
26 FILE *file;
27} CPUListState;
28
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29typedef enum MMUAccessType {
30 MMU_DATA_LOAD = 0,
31 MMU_DATA_STORE = 1,
32 MMU_INST_FETCH = 2
33} MMUAccessType;
34
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35#if !defined(CONFIG_USER_ONLY)
36
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37enum device_endian {
38 DEVICE_NATIVE_ENDIAN,
39 DEVICE_BIG_ENDIAN,
40 DEVICE_LITTLE_ENDIAN,
41};
42
1ad2134f 43/* address in the RAM (different from a physical address) */
4be403c8 44#if defined(CONFIG_XEN_BACKEND)
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45typedef uint64_t ram_addr_t;
46# define RAM_ADDR_MAX UINT64_MAX
47# define RAM_ADDR_FMT "%" PRIx64
48#else
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49typedef uintptr_t ram_addr_t;
50# define RAM_ADDR_MAX UINTPTR_MAX
51# define RAM_ADDR_FMT "%" PRIxPTR
f15fbc4b 52#endif
1ad2134f 53
96d0e26c 54extern ram_addr_t ram_size;
87a45cfe 55ram_addr_t get_current_ram_size(void);
96d0e26c 56
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57/* memory API */
58
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59typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
60typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
1ad2134f 61
cd19cfa2 62void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
1ad2134f 63/* This should not be used by devices. */
1b5ec234 64MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
c5705a77 65void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
20cfe881 66void qemu_ram_unset_idstr(ram_addr_t addr);
1ad2134f 67
a8170e5e 68void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
1ad2134f 69 int len, int is_write);
a8170e5e 70static inline void cpu_physical_memory_read(hwaddr addr,
3bad9814 71 void *buf, int len)
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72{
73 cpu_physical_memory_rw(addr, buf, len, 0);
74}
a8170e5e 75static inline void cpu_physical_memory_write(hwaddr addr,
3bad9814 76 const void *buf, int len)
1ad2134f 77{
3bad9814 78 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
1ad2134f 79}
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80void *cpu_physical_memory_map(hwaddr addr,
81 hwaddr *plen,
1ad2134f 82 int is_write);
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83void cpu_physical_memory_unmap(void *buffer, hwaddr len,
84 int is_write, hwaddr access_len);
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85void cpu_register_map_client(QEMUBH *bh);
86void cpu_unregister_map_client(QEMUBH *bh);
1ad2134f 87
a8170e5e 88bool cpu_physical_memory_is_io(hwaddr phys_addr);
76f35538 89
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90/* Coalesced MMIO regions are areas where write operations can be reordered.
91 * This usually implies that write operations are side-effect free. This allows
92 * batching which can make a major impact on performance when using
93 * virtualization.
94 */
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95void qemu_flush_coalesced_mmio_buffer(void);
96
2c17449b 97uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
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98uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
99uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
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100uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
101uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
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102uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
103uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
db3be60d 104void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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105void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
106void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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107void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
108void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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109void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
110void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
c227f099 111
21673cde 112#ifdef NEED_CPU_H
41701aa4 113uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
fdfba1a2 114uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
2c17449b 115uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
2198a121 116void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
5ce5944d 117void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
ab1da857 118void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
f606604f 119void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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120#endif
121
2a221651 122void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
1ad2134f 123 const uint8_t *buf, int len);
582b55a9 124void cpu_flush_icache_range(hwaddr start, int len);
1ad2134f 125
0e0df1e2 126extern struct MemoryRegion io_mem_rom;
0e0df1e2 127extern struct MemoryRegion io_mem_notdirty;
1ad2134f 128
e3807054 129typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
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130 ram_addr_t offset, ram_addr_t length, void *opaque);
131
e3807054 132int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
bd2fa51f 133
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134#endif
135
1ad2134f 136#endif /* !CPU_COMMON_H */