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Commit | Line | Data |
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9fdf0c29 DG |
1 | #if !defined(__HW_SPAPR_H__) |
2 | #define __HW_SPAPR_H__ | |
3 | ||
9c17d615 | 4 | #include "sysemu/dma.h" |
0d09e41a | 5 | #include "hw/ppc/xics.h" |
277f9acf | 6 | |
4040ab72 | 7 | struct VIOsPAPRBus; |
3384f95c | 8 | struct sPAPRPHBState; |
639e8102 | 9 | struct sPAPRNVRAM; |
4040ab72 | 10 | |
4be21d56 DG |
11 | #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL |
12 | ||
9fdf0c29 | 13 | typedef struct sPAPREnvironment { |
4040ab72 | 14 | struct VIOsPAPRBus *vio_bus; |
3384f95c | 15 | QLIST_HEAD(, sPAPRPHBState) phbs; |
f1c2dc7c AK |
16 | hwaddr msi_win_addr; |
17 | MemoryRegion msiwindow; | |
639e8102 | 18 | struct sPAPRNVRAM *nvram; |
c04d6cfa | 19 | XICSState *icp; |
a3467baa | 20 | |
a8170e5e | 21 | hwaddr ram_limit; |
a3467baa | 22 | void *htab; |
4be21d56 | 23 | uint32_t htab_shift; |
a8170e5e | 24 | hwaddr rma_size; |
7f763a5d | 25 | int vrma_adjust; |
a8170e5e | 26 | hwaddr fdt_addr, rtas_addr; |
a3467baa DG |
27 | long rtas_size; |
28 | void *fdt_skel; | |
29 | target_ulong entry_point; | |
4be21d56 DG |
30 | uint32_t next_irq; |
31 | uint64_t rtc_offset; | |
98a8b524 | 32 | struct PPCTimebase tb; |
3fc5acde | 33 | bool has_graphics; |
74d042e5 DG |
34 | |
35 | uint32_t epow_irq; | |
36 | Notifier epow_notifier; | |
4be21d56 DG |
37 | |
38 | /* Migration state */ | |
39 | int htab_save_index; | |
40 | bool htab_first_pass; | |
e68cb8b4 | 41 | int htab_fd; |
9fdf0c29 DG |
42 | } sPAPREnvironment; |
43 | ||
44 | #define H_SUCCESS 0 | |
45 | #define H_BUSY 1 /* Hardware busy -- retry later */ | |
46 | #define H_CLOSED 2 /* Resource closed */ | |
47 | #define H_NOT_AVAILABLE 3 | |
48 | #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ | |
49 | #define H_PARTIAL 5 | |
50 | #define H_IN_PROGRESS 14 /* Kind of like busy */ | |
51 | #define H_PAGE_REGISTERED 15 | |
52 | #define H_PARTIAL_STORE 16 | |
53 | #define H_PENDING 17 /* returned from H_POLL_PENDING */ | |
54 | #define H_CONTINUE 18 /* Returned from H_Join on success */ | |
55 | #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ | |
56 | #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ | |
57 | is a good time to retry */ | |
58 | #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ | |
59 | is a good time to retry */ | |
60 | #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ | |
61 | is a good time to retry */ | |
62 | #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ | |
63 | is a good time to retry */ | |
64 | #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ | |
65 | is a good time to retry */ | |
66 | #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ | |
67 | is a good time to retry */ | |
68 | #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ | |
69 | #define H_HARDWARE -1 /* Hardware error */ | |
70 | #define H_FUNCTION -2 /* Function not supported */ | |
71 | #define H_PRIVILEGE -3 /* Caller not privileged */ | |
72 | #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ | |
73 | #define H_BAD_MODE -5 /* Illegal msr value */ | |
74 | #define H_PTEG_FULL -6 /* PTEG is full */ | |
75 | #define H_NOT_FOUND -7 /* PTE was not found" */ | |
76 | #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ | |
77 | #define H_NO_MEM -9 | |
78 | #define H_AUTHORITY -10 | |
79 | #define H_PERMISSION -11 | |
80 | #define H_DROPPED -12 | |
81 | #define H_SOURCE_PARM -13 | |
82 | #define H_DEST_PARM -14 | |
83 | #define H_REMOTE_PARM -15 | |
84 | #define H_RESOURCE -16 | |
85 | #define H_ADAPTER_PARM -17 | |
86 | #define H_RH_PARM -18 | |
87 | #define H_RCQ_PARM -19 | |
88 | #define H_SCQ_PARM -20 | |
89 | #define H_EQ_PARM -21 | |
90 | #define H_RT_PARM -22 | |
91 | #define H_ST_PARM -23 | |
92 | #define H_SIGT_PARM -24 | |
93 | #define H_TOKEN_PARM -25 | |
94 | #define H_MLENGTH_PARM -27 | |
95 | #define H_MEM_PARM -28 | |
96 | #define H_MEM_ACCESS_PARM -29 | |
97 | #define H_ATTR_PARM -30 | |
98 | #define H_PORT_PARM -31 | |
99 | #define H_MCG_PARM -32 | |
100 | #define H_VL_PARM -33 | |
101 | #define H_TSIZE_PARM -34 | |
102 | #define H_TRACE_PARM -35 | |
103 | ||
104 | #define H_MASK_PARM -37 | |
105 | #define H_MCG_FULL -38 | |
106 | #define H_ALIAS_EXIST -39 | |
107 | #define H_P_COUNTER -40 | |
108 | #define H_TABLE_FULL -41 | |
109 | #define H_ALT_TABLE -42 | |
110 | #define H_MR_CONDITION -43 | |
111 | #define H_NOT_ENOUGH_RESOURCES -44 | |
112 | #define H_R_STATE -45 | |
113 | #define H_RESCINDEND -46 | |
42561bf2 AB |
114 | #define H_P2 -55 |
115 | #define H_P3 -56 | |
116 | #define H_P4 -57 | |
117 | #define H_P5 -58 | |
118 | #define H_P6 -59 | |
119 | #define H_P7 -60 | |
120 | #define H_P8 -61 | |
121 | #define H_P9 -62 | |
122 | #define H_UNSUPPORTED_FLAG -256 | |
9fdf0c29 DG |
123 | #define H_MULTI_THREADS_ACTIVE -9005 |
124 | ||
125 | ||
126 | /* Long Busy is a condition that can be returned by the firmware | |
127 | * when a call cannot be completed now, but the identical call | |
128 | * should be retried later. This prevents calls blocking in the | |
129 | * firmware for long periods of time. Annoyingly the firmware can return | |
130 | * a range of return codes, hinting at how long we should wait before | |
131 | * retrying. If you don't care for the hint, the macro below is a good | |
132 | * way to check for the long_busy return codes | |
133 | */ | |
134 | #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ | |
135 | && (x <= H_LONG_BUSY_END_RANGE)) | |
136 | ||
137 | /* Flags */ | |
138 | #define H_LARGE_PAGE (1ULL<<(63-16)) | |
139 | #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ | |
140 | #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ | |
141 | #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ | |
142 | #define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) | |
143 | #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) | |
144 | #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) | |
145 | #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) | |
146 | #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE | |
147 | #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ | |
148 | #define H_ANDCOND (1ULL<<(63-33)) | |
149 | #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ | |
150 | #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ | |
151 | #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ | |
152 | #define H_COPY_PAGE (1ULL<<(63-49)) | |
153 | #define H_N (1ULL<<(63-61)) | |
154 | #define H_PP1 (1ULL<<(63-62)) | |
155 | #define H_PP2 (1ULL<<(63-63)) | |
156 | ||
a46622fd AK |
157 | /* Values for 2nd argument to H_SET_MODE */ |
158 | #define H_SET_MODE_RESOURCE_SET_CIABR 1 | |
159 | #define H_SET_MODE_RESOURCE_SET_DAWR 2 | |
160 | #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 | |
161 | #define H_SET_MODE_RESOURCE_LE 4 | |
162 | ||
163 | /* Flags for H_SET_MODE_RESOURCE_LE */ | |
42561bf2 AB |
164 | #define H_SET_MODE_ENDIAN_BIG 0 |
165 | #define H_SET_MODE_ENDIAN_LITTLE 1 | |
166 | ||
d5ac4f54 AK |
167 | /* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */ |
168 | #define H_SET_MODE_ADDR_TRANS_NONE 0 | |
169 | #define H_SET_MODE_ADDR_TRANS_0001_8000 2 | |
170 | #define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3 | |
171 | ||
9fdf0c29 DG |
172 | /* VASI States */ |
173 | #define H_VASI_INVALID 0 | |
174 | #define H_VASI_ENABLED 1 | |
175 | #define H_VASI_ABORTED 2 | |
176 | #define H_VASI_SUSPENDING 3 | |
177 | #define H_VASI_SUSPENDED 4 | |
178 | #define H_VASI_RESUMED 5 | |
179 | #define H_VASI_COMPLETED 6 | |
180 | ||
181 | /* DABRX flags */ | |
182 | #define H_DABRX_HYPERVISOR (1ULL<<(63-61)) | |
183 | #define H_DABRX_KERNEL (1ULL<<(63-62)) | |
184 | #define H_DABRX_USER (1ULL<<(63-63)) | |
185 | ||
66a0a2cb | 186 | /* Each control block has to be on a 4K boundary */ |
9fdf0c29 DG |
187 | #define H_CB_ALIGNMENT 4096 |
188 | ||
189 | /* pSeries hypervisor opcodes */ | |
190 | #define H_REMOVE 0x04 | |
191 | #define H_ENTER 0x08 | |
192 | #define H_READ 0x0c | |
193 | #define H_CLEAR_MOD 0x10 | |
194 | #define H_CLEAR_REF 0x14 | |
195 | #define H_PROTECT 0x18 | |
196 | #define H_GET_TCE 0x1c | |
197 | #define H_PUT_TCE 0x20 | |
198 | #define H_SET_SPRG0 0x24 | |
199 | #define H_SET_DABR 0x28 | |
200 | #define H_PAGE_INIT 0x2c | |
201 | #define H_SET_ASR 0x30 | |
202 | #define H_ASR_ON 0x34 | |
203 | #define H_ASR_OFF 0x38 | |
204 | #define H_LOGICAL_CI_LOAD 0x3c | |
205 | #define H_LOGICAL_CI_STORE 0x40 | |
206 | #define H_LOGICAL_CACHE_LOAD 0x44 | |
207 | #define H_LOGICAL_CACHE_STORE 0x48 | |
208 | #define H_LOGICAL_ICBI 0x4c | |
209 | #define H_LOGICAL_DCBF 0x50 | |
210 | #define H_GET_TERM_CHAR 0x54 | |
211 | #define H_PUT_TERM_CHAR 0x58 | |
212 | #define H_REAL_TO_LOGICAL 0x5c | |
213 | #define H_HYPERVISOR_DATA 0x60 | |
214 | #define H_EOI 0x64 | |
215 | #define H_CPPR 0x68 | |
216 | #define H_IPI 0x6c | |
217 | #define H_IPOLL 0x70 | |
218 | #define H_XIRR 0x74 | |
219 | #define H_PERFMON 0x7c | |
220 | #define H_MIGRATE_DMA 0x78 | |
221 | #define H_REGISTER_VPA 0xDC | |
222 | #define H_CEDE 0xE0 | |
223 | #define H_CONFER 0xE4 | |
224 | #define H_PROD 0xE8 | |
225 | #define H_GET_PPP 0xEC | |
226 | #define H_SET_PPP 0xF0 | |
227 | #define H_PURR 0xF4 | |
228 | #define H_PIC 0xF8 | |
229 | #define H_REG_CRQ 0xFC | |
230 | #define H_FREE_CRQ 0x100 | |
231 | #define H_VIO_SIGNAL 0x104 | |
232 | #define H_SEND_CRQ 0x108 | |
233 | #define H_COPY_RDMA 0x110 | |
234 | #define H_REGISTER_LOGICAL_LAN 0x114 | |
235 | #define H_FREE_LOGICAL_LAN 0x118 | |
236 | #define H_ADD_LOGICAL_LAN_BUFFER 0x11C | |
237 | #define H_SEND_LOGICAL_LAN 0x120 | |
238 | #define H_BULK_REMOVE 0x124 | |
239 | #define H_MULTICAST_CTRL 0x130 | |
240 | #define H_SET_XDABR 0x134 | |
241 | #define H_STUFF_TCE 0x138 | |
242 | #define H_PUT_TCE_INDIRECT 0x13C | |
243 | #define H_CHANGE_LOGICAL_LAN_MAC 0x14C | |
244 | #define H_VTERM_PARTNER_INFO 0x150 | |
245 | #define H_REGISTER_VTERM 0x154 | |
246 | #define H_FREE_VTERM 0x158 | |
247 | #define H_RESET_EVENTS 0x15C | |
248 | #define H_ALLOC_RESOURCE 0x160 | |
249 | #define H_FREE_RESOURCE 0x164 | |
250 | #define H_MODIFY_QP 0x168 | |
251 | #define H_QUERY_QP 0x16C | |
252 | #define H_REREGISTER_PMR 0x170 | |
253 | #define H_REGISTER_SMR 0x174 | |
254 | #define H_QUERY_MR 0x178 | |
255 | #define H_QUERY_MW 0x17C | |
256 | #define H_QUERY_HCA 0x180 | |
257 | #define H_QUERY_PORT 0x184 | |
258 | #define H_MODIFY_PORT 0x188 | |
259 | #define H_DEFINE_AQP1 0x18C | |
260 | #define H_GET_TRACE_BUFFER 0x190 | |
261 | #define H_DEFINE_AQP0 0x194 | |
262 | #define H_RESIZE_MR 0x198 | |
263 | #define H_ATTACH_MCQP 0x19C | |
264 | #define H_DETACH_MCQP 0x1A0 | |
265 | #define H_CREATE_RPT 0x1A4 | |
266 | #define H_REMOVE_RPT 0x1A8 | |
267 | #define H_REGISTER_RPAGES 0x1AC | |
268 | #define H_DISABLE_AND_GETC 0x1B0 | |
269 | #define H_ERROR_DATA 0x1B4 | |
270 | #define H_GET_HCA_INFO 0x1B8 | |
271 | #define H_GET_PERF_COUNT 0x1BC | |
272 | #define H_MANAGE_TRACE 0x1C0 | |
273 | #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 | |
274 | #define H_QUERY_INT_STATE 0x1E4 | |
275 | #define H_POLL_PENDING 0x1D8 | |
276 | #define H_ILLAN_ATTRIBUTES 0x244 | |
277 | #define H_MODIFY_HEA_QP 0x250 | |
278 | #define H_QUERY_HEA_QP 0x254 | |
279 | #define H_QUERY_HEA 0x258 | |
280 | #define H_QUERY_HEA_PORT 0x25C | |
281 | #define H_MODIFY_HEA_PORT 0x260 | |
282 | #define H_REG_BCMC 0x264 | |
283 | #define H_DEREG_BCMC 0x268 | |
284 | #define H_REGISTER_HEA_RPAGES 0x26C | |
285 | #define H_DISABLE_AND_GET_HEA 0x270 | |
286 | #define H_GET_HEA_INFO 0x274 | |
287 | #define H_ALLOC_HEA_RESOURCE 0x278 | |
288 | #define H_ADD_CONN 0x284 | |
289 | #define H_DEL_CONN 0x288 | |
290 | #define H_JOIN 0x298 | |
291 | #define H_VASI_STATE 0x2A4 | |
292 | #define H_ENABLE_CRQ 0x2B0 | |
293 | #define H_GET_EM_PARMS 0x2B8 | |
294 | #define H_SET_MPP 0x2D0 | |
295 | #define H_GET_MPP 0x2D4 | |
5d87e4b7 | 296 | #define H_XIRR_X 0x2FC |
42561bf2 AB |
297 | #define H_SET_MODE 0x31C |
298 | #define MAX_HCALL_OPCODE H_SET_MODE | |
9fdf0c29 | 299 | |
39ac8455 DG |
300 | /* The hcalls above are standardized in PAPR and implemented by pHyp |
301 | * as well. | |
302 | * | |
303 | * We also need some hcalls which are specific to qemu / KVM-on-POWER. | |
304 | * So far we just need one for H_RTAS, but in future we'll need more | |
305 | * for extensions like virtio. We put those into the 0xf000-0xfffc | |
306 | * range which is reserved by PAPR for "platform-specific" hcalls. | |
307 | */ | |
308 | #define KVMPPC_HCALL_BASE 0xf000 | |
309 | #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) | |
c73e3771 | 310 | #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) |
2a6593cb AK |
311 | /* Client Architecture support */ |
312 | #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) | |
313 | #define KVMPPC_HCALL_MAX KVMPPC_H_CAS | |
39ac8455 | 314 | |
9fdf0c29 DG |
315 | extern sPAPREnvironment *spapr; |
316 | ||
2a6593cb AK |
317 | typedef struct sPAPRDeviceTreeUpdateHeader { |
318 | uint32_t version_id; | |
319 | } sPAPRDeviceTreeUpdateHeader; | |
320 | ||
9fdf0c29 DG |
321 | /*#define DEBUG_SPAPR_HCALLS*/ |
322 | ||
323 | #ifdef DEBUG_SPAPR_HCALLS | |
324 | #define hcall_dprintf(fmt, ...) \ | |
d9599c92 | 325 | do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0) |
9fdf0c29 DG |
326 | #else |
327 | #define hcall_dprintf(fmt, ...) \ | |
328 | do { } while (0) | |
329 | #endif | |
330 | ||
b13ce26d | 331 | typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
9fdf0c29 DG |
332 | target_ulong opcode, |
333 | target_ulong *args); | |
334 | ||
335 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); | |
aa100fa4 | 336 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
337 | target_ulong *args); |
338 | ||
ff9d2afa | 339 | int spapr_allocate_irq(int hint, bool lsi); |
f1c2dc7c | 340 | int spapr_allocate_irq_block(int num, bool lsi, bool msi); |
d07fee7e | 341 | |
a307d594 | 342 | static inline int spapr_allocate_msi(int hint) |
d07fee7e | 343 | { |
ff9d2afa | 344 | return spapr_allocate_irq(hint, false); |
d07fee7e DG |
345 | } |
346 | ||
a307d594 | 347 | static inline int spapr_allocate_lsi(int hint) |
d07fee7e | 348 | { |
ff9d2afa | 349 | return spapr_allocate_irq(hint, true); |
d07fee7e | 350 | } |
277f9acf | 351 | |
a64d325d AK |
352 | /* RTAS return codes */ |
353 | #define RTAS_OUT_SUCCESS 0 | |
354 | #define RTAS_OUT_NO_ERRORS_FOUND 1 | |
355 | #define RTAS_OUT_HW_ERROR -1 | |
356 | #define RTAS_OUT_BUSY -2 | |
357 | #define RTAS_OUT_PARAM_ERROR -3 | |
3ada6b11 AK |
358 | #define RTAS_OUT_NOT_SUPPORTED -3 |
359 | #define RTAS_OUT_NOT_AUTHORIZED -9002 | |
a64d325d | 360 | |
3a3b8502 AK |
361 | /* RTAS tokens */ |
362 | #define RTAS_TOKEN_BASE 0x2000 | |
363 | ||
364 | #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) | |
365 | #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) | |
366 | #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) | |
367 | #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) | |
368 | #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) | |
369 | #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) | |
370 | #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) | |
371 | #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) | |
372 | #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) | |
373 | #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) | |
374 | #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) | |
375 | #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) | |
376 | #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) | |
377 | #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) | |
378 | #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) | |
379 | #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) | |
380 | #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) | |
381 | #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) | |
382 | #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) | |
383 | #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) | |
384 | #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) | |
385 | #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) | |
386 | #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) | |
387 | #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) | |
388 | #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) | |
389 | #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) | |
390 | #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) | |
391 | #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) | |
392 | #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) | |
393 | #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) | |
394 | #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) | |
395 | #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) | |
396 | #define RTAS_IBM_EXTENDED_OS_TERM (RTAS_TOKEN_BASE + 0x20) | |
397 | ||
398 | #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x21) | |
399 | ||
3052d951 S |
400 | /* RTAS ibm,get-system-parameter token values */ |
401 | #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 | |
b907d7b0 | 402 | #define RTAS_SYSPARM_UUID 48 |
3052d951 S |
403 | |
404 | /* Possible values for the platform-processor-diagnostics-run-mode parameter | |
405 | * of the RTAS ibm,get-system-parameter call. | |
406 | */ | |
407 | #define DIAGNOSTICS_RUN_MODE_DISABLED 0 | |
408 | #define DIAGNOSTICS_RUN_MODE_STAGGERED 1 | |
409 | #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 | |
410 | #define DIAGNOSTICS_RUN_MODE_PERIODIC 3 | |
411 | ||
4fe822e0 AK |
412 | static inline uint64_t ppc64_phys_to_real(uint64_t addr) |
413 | { | |
414 | return addr & ~0xF000000000000000ULL; | |
415 | } | |
416 | ||
39ac8455 DG |
417 | static inline uint32_t rtas_ld(target_ulong phys, int n) |
418 | { | |
fdfba1a2 | 419 | return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); |
39ac8455 DG |
420 | } |
421 | ||
422 | static inline void rtas_st(target_ulong phys, int n, uint32_t val) | |
423 | { | |
ab1da857 | 424 | stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); |
39ac8455 DG |
425 | } |
426 | ||
ce3fa1ec S |
427 | |
428 | static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len, | |
429 | uint8_t *buffer, uint16_t buffer_len) | |
430 | { | |
431 | if (phys_len < 2) { | |
432 | return; | |
433 | } | |
434 | stw_be_phys(&address_space_memory, | |
435 | ppc64_phys_to_real(phys), buffer_len); | |
436 | cpu_physical_memory_write(ppc64_phys_to_real(phys + 2), | |
437 | buffer, MIN(buffer_len, phys_len - 2)); | |
438 | } | |
439 | ||
210b580b AL |
440 | typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
441 | uint32_t token, | |
39ac8455 DG |
442 | uint32_t nargs, target_ulong args, |
443 | uint32_t nret, target_ulong rets); | |
3a3b8502 | 444 | void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); |
210b580b | 445 | target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
39ac8455 DG |
446 | uint32_t token, uint32_t nargs, target_ulong args, |
447 | uint32_t nret, target_ulong rets); | |
a8170e5e AK |
448 | int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr, |
449 | hwaddr rtas_size); | |
39ac8455 | 450 | |
ad0ebb91 DG |
451 | #define SPAPR_TCE_PAGE_SHIFT 12 |
452 | #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) | |
453 | #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) | |
454 | ||
ad0ebb91 | 455 | #define SPAPR_VIO_BASE_LIOBN 0x00000000 |
edded454 | 456 | #define SPAPR_PCI_BASE_LIOBN 0x80000000 |
ad0ebb91 | 457 | |
74d042e5 DG |
458 | #define RTAS_ERROR_LOG_MAX 2048 |
459 | ||
2b7dc949 | 460 | typedef struct sPAPRTCETable sPAPRTCETable; |
74d042e5 | 461 | |
a83000f5 AL |
462 | #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" |
463 | #define SPAPR_TCE_TABLE(obj) \ | |
464 | OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE) | |
465 | ||
466 | struct sPAPRTCETable { | |
467 | DeviceState parent; | |
468 | uint32_t liobn; | |
a83000f5 | 469 | uint32_t nb_table; |
1b8eceee | 470 | uint64_t bus_offset; |
650f33ad | 471 | uint32_t page_shift; |
a83000f5 AL |
472 | uint64_t *table; |
473 | bool bypass; | |
9bb62a07 | 474 | bool vfio_accel; |
a83000f5 AL |
475 | int fd; |
476 | MemoryRegion iommu; | |
477 | QLIST_ENTRY(sPAPRTCETable) list; | |
478 | }; | |
479 | ||
74d042e5 DG |
480 | void spapr_events_init(sPAPREnvironment *spapr); |
481 | void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq); | |
2a6593cb | 482 | int spapr_h_cas_compose_response(target_ulong addr, target_ulong size); |
84af6d9f | 483 | sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, |
1b8eceee | 484 | uint64_t bus_offset, |
650f33ad | 485 | uint32_t page_shift, |
9bb62a07 AK |
486 | uint32_t nb_table, |
487 | bool vfio_accel); | |
a84bb436 | 488 | MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet); |
2b7dc949 | 489 | void spapr_tce_set_bypass(sPAPRTCETable *tcet, bool bypass); |
ad0ebb91 | 490 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
5c4cbcf2 AK |
491 | uint32_t liobn, uint64_t window, uint32_t size); |
492 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
2b7dc949 | 493 | sPAPRTCETable *tcet); |
ad0ebb91 | 494 | |
9fdf0c29 | 495 | #endif /* !defined (__HW_SPAPR_H__) */ |