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7adca78e YS |
1 | /* |
2 | * Renesas 8bit timer Object | |
3 | * | |
4 | * Copyright (c) 2018 Yoshinori Sato | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
8 | ||
9 | #ifndef HW_TIMER_RENESAS_TMR_H | |
10 | #define HW_TIMER_RENESAS_TMR_H | |
11 | ||
12 | #include "qemu/timer.h" | |
13 | #include "hw/sysbus.h" | |
db1015e9 | 14 | #include "qom/object.h" |
7adca78e YS |
15 | |
16 | #define TYPE_RENESAS_TMR "renesas-tmr" | |
db1015e9 | 17 | typedef struct RTMRState RTMRState; |
8110fa1d EH |
18 | DECLARE_INSTANCE_CHECKER(RTMRState, RTMR, |
19 | TYPE_RENESAS_TMR) | |
7adca78e YS |
20 | |
21 | enum timer_event { | |
22 | cmia = 0, | |
23 | cmib = 1, | |
24 | ovi = 2, | |
25 | none = 3, | |
26 | TMR_NR_EVENTS = 4 | |
27 | }; | |
28 | ||
29 | enum { | |
30 | TMR_CH = 2, | |
31 | TMR_NR_IRQ = 3 * TMR_CH | |
32 | }; | |
33 | ||
db1015e9 | 34 | struct RTMRState { |
7adca78e YS |
35 | /*< private >*/ |
36 | SysBusDevice parent_obj; | |
37 | /*< public >*/ | |
38 | ||
39 | uint64_t input_freq; | |
40 | MemoryRegion memory; | |
41 | ||
42 | int64_t tick; | |
43 | uint8_t tcnt[TMR_CH]; | |
44 | uint8_t tcora[TMR_CH]; | |
45 | uint8_t tcorb[TMR_CH]; | |
46 | uint8_t tcr[TMR_CH]; | |
47 | uint8_t tccr[TMR_CH]; | |
48 | uint8_t tcor[TMR_CH]; | |
49 | uint8_t tcsr[TMR_CH]; | |
50 | int64_t div_round[TMR_CH]; | |
51 | uint8_t next[TMR_CH]; | |
52 | qemu_irq cmia[TMR_CH]; | |
53 | qemu_irq cmib[TMR_CH]; | |
54 | qemu_irq ovi[TMR_CH]; | |
55 | QEMUTimer timer[TMR_CH]; | |
db1015e9 | 56 | }; |
7adca78e YS |
57 | |
58 | #endif |