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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __ASM_ARM_KVM_VGIC_H | |
20 | #define __ASM_ARM_KVM_VGIC_H | |
21 | ||
b47ef92a MZ |
22 | #include <linux/kernel.h> |
23 | #include <linux/kvm.h> | |
b47ef92a MZ |
24 | #include <linux/irqreturn.h> |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/types.h> | |
1a89dd91 | 27 | |
5fb66da6 | 28 | #define VGIC_NR_IRQS_LEGACY 256 |
b47ef92a MZ |
29 | #define VGIC_NR_SGIS 16 |
30 | #define VGIC_NR_PPIS 16 | |
31 | #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) | |
8f186d52 MZ |
32 | |
33 | #define VGIC_V2_MAX_LRS (1 << 6) | |
b2fb1c0d | 34 | #define VGIC_V3_MAX_LRS 16 |
c3c91836 | 35 | #define VGIC_MAX_IRQS 1024 |
3caa2d8c | 36 | #define VGIC_V2_MAX_CPUS 8 |
b47ef92a MZ |
37 | |
38 | /* Sanity checks... */ | |
ac3d3735 AP |
39 | #if (KVM_MAX_VCPUS > 255) |
40 | #error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now | |
b47ef92a MZ |
41 | #endif |
42 | ||
5fb66da6 | 43 | #if (VGIC_NR_IRQS_LEGACY & 31) |
b47ef92a MZ |
44 | #error "VGIC_NR_IRQS must be a multiple of 32" |
45 | #endif | |
46 | ||
5fb66da6 | 47 | #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) |
b47ef92a MZ |
48 | #error "VGIC_NR_IRQS must be <= 1024" |
49 | #endif | |
50 | ||
51 | /* | |
52 | * The GIC distributor registers describing interrupts have two parts: | |
53 | * - 32 per-CPU interrupts (SGI + PPI) | |
54 | * - a bunch of shared interrupts (SPI) | |
55 | */ | |
56 | struct vgic_bitmap { | |
c1bfb577 MZ |
57 | /* |
58 | * - One UL per VCPU for private interrupts (assumes UL is at | |
59 | * least 32 bits) | |
60 | * - As many UL as necessary for shared interrupts. | |
61 | * | |
62 | * The private interrupts are accessed via the "private" | |
63 | * field, one UL per vcpu (the state for vcpu n is in | |
64 | * private[n]). The shared interrupts are accessed via the | |
65 | * "shared" pointer (IRQn state is at bit n-32 in the bitmap). | |
66 | */ | |
67 | unsigned long *private; | |
68 | unsigned long *shared; | |
b47ef92a MZ |
69 | }; |
70 | ||
71 | struct vgic_bytemap { | |
c1bfb577 MZ |
72 | /* |
73 | * - 8 u32 per VCPU for private interrupts | |
74 | * - As many u32 as necessary for shared interrupts. | |
75 | * | |
76 | * The private interrupts are accessed via the "private" | |
77 | * field, (the state for vcpu n is in private[n*8] to | |
78 | * private[n*8 + 7]). The shared interrupts are accessed via | |
79 | * the "shared" pointer (IRQn state is at byte (n-32)%4 of the | |
80 | * shared[(n-32)/4] word). | |
81 | */ | |
82 | u32 *private; | |
83 | u32 *shared; | |
b47ef92a MZ |
84 | }; |
85 | ||
8d5c6b06 MZ |
86 | struct kvm_vcpu; |
87 | ||
1a9b1305 MZ |
88 | enum vgic_type { |
89 | VGIC_V2, /* Good ol' GICv2 */ | |
b2fb1c0d | 90 | VGIC_V3, /* New fancy GICv3 */ |
1a9b1305 MZ |
91 | }; |
92 | ||
8d5c6b06 MZ |
93 | #define LR_STATE_PENDING (1 << 0) |
94 | #define LR_STATE_ACTIVE (1 << 1) | |
95 | #define LR_STATE_MASK (3 << 0) | |
96 | #define LR_EOI_INT (1 << 2) | |
97 | ||
98 | struct vgic_lr { | |
99 | u16 irq; | |
100 | u8 source; | |
101 | u8 state; | |
102 | }; | |
103 | ||
beee38b9 MZ |
104 | struct vgic_vmcr { |
105 | u32 ctlr; | |
106 | u32 abpr; | |
107 | u32 bpr; | |
108 | u32 pmr; | |
109 | }; | |
110 | ||
8d5c6b06 MZ |
111 | struct vgic_ops { |
112 | struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); | |
113 | void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); | |
69bb2c9f MZ |
114 | void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr); |
115 | u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); | |
8d6a0313 | 116 | u64 (*get_eisr)(const struct kvm_vcpu *vcpu); |
495dd859 | 117 | u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); |
909d9b50 MZ |
118 | void (*enable_underflow)(struct kvm_vcpu *vcpu); |
119 | void (*disable_underflow)(struct kvm_vcpu *vcpu); | |
beee38b9 MZ |
120 | void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
121 | void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); | |
da8dafd1 | 122 | void (*enable)(struct kvm_vcpu *vcpu); |
8d5c6b06 MZ |
123 | }; |
124 | ||
ca85f623 | 125 | struct vgic_params { |
1a9b1305 MZ |
126 | /* vgic type */ |
127 | enum vgic_type type; | |
ca85f623 MZ |
128 | /* Physical address of vgic virtual cpu interface */ |
129 | phys_addr_t vcpu_base; | |
130 | /* Number of list registers */ | |
131 | u32 nr_lr; | |
132 | /* Interrupt number */ | |
133 | unsigned int maint_irq; | |
134 | /* Virtual control interface base address */ | |
135 | void __iomem *vctrl_base; | |
3caa2d8c | 136 | int max_gic_vcpus; |
b5d84ff6 AP |
137 | /* Only needed for the legacy KVM_CREATE_IRQCHIP */ |
138 | bool can_emulate_gicv2; | |
ca85f623 MZ |
139 | }; |
140 | ||
b26e5fda AP |
141 | struct vgic_vm_ops { |
142 | bool (*handle_mmio)(struct kvm_vcpu *, struct kvm_run *, | |
143 | struct kvm_exit_mmio *); | |
144 | bool (*queue_sgi)(struct kvm_vcpu *, int irq); | |
145 | void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); | |
146 | int (*init_model)(struct kvm *); | |
147 | int (*map_resources)(struct kvm *, const struct vgic_params *); | |
148 | }; | |
149 | ||
1a89dd91 | 150 | struct vgic_dist { |
b47ef92a | 151 | spinlock_t lock; |
f982cf4e | 152 | bool in_kernel; |
01ac5e34 | 153 | bool ready; |
b47ef92a | 154 | |
59892136 AP |
155 | /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ |
156 | u32 vgic_model; | |
157 | ||
c1bfb577 MZ |
158 | int nr_cpus; |
159 | int nr_irqs; | |
160 | ||
b47ef92a MZ |
161 | /* Virtual control interface mapping */ |
162 | void __iomem *vctrl_base; | |
163 | ||
330690cd CD |
164 | /* Distributor and vcpu interface mapping in the guest */ |
165 | phys_addr_t vgic_dist_base; | |
a0675c25 AP |
166 | /* GICv2 and GICv3 use different mapped register blocks */ |
167 | union { | |
168 | phys_addr_t vgic_cpu_base; | |
169 | phys_addr_t vgic_redist_base; | |
170 | }; | |
b47ef92a MZ |
171 | |
172 | /* Distributor enabled */ | |
173 | u32 enabled; | |
174 | ||
175 | /* Interrupt enabled (one bit per IRQ) */ | |
176 | struct vgic_bitmap irq_enabled; | |
177 | ||
faa1b46c CD |
178 | /* Level-triggered interrupt external input is asserted */ |
179 | struct vgic_bitmap irq_level; | |
180 | ||
181 | /* | |
182 | * Interrupt state is pending on the distributor | |
183 | */ | |
227844f5 | 184 | struct vgic_bitmap irq_pending; |
b47ef92a | 185 | |
faa1b46c CD |
186 | /* |
187 | * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered | |
188 | * interrupts. Essentially holds the state of the flip-flop in | |
189 | * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. | |
190 | * Once set, it is only cleared for level-triggered interrupts on | |
191 | * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. | |
192 | */ | |
193 | struct vgic_bitmap irq_soft_pend; | |
194 | ||
dbf20f9d CD |
195 | /* Level-triggered interrupt queued on VCPU interface */ |
196 | struct vgic_bitmap irq_queued; | |
b47ef92a | 197 | |
47a98b15 CD |
198 | /* Interrupt was active when unqueue from VCPU interface */ |
199 | struct vgic_bitmap irq_active; | |
200 | ||
b47ef92a MZ |
201 | /* Interrupt priority. Not used yet. */ |
202 | struct vgic_bytemap irq_priority; | |
203 | ||
204 | /* Level/edge triggered */ | |
205 | struct vgic_bitmap irq_cfg; | |
206 | ||
c1bfb577 MZ |
207 | /* |
208 | * Source CPU per SGI and target CPU: | |
209 | * | |
210 | * Each byte represent a SGI observable on a VCPU, each bit of | |
211 | * this byte indicating if the corresponding VCPU has | |
212 | * generated this interrupt. This is a GICv2 feature only. | |
213 | * | |
214 | * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are | |
215 | * the SGIs observable on VCPUn. | |
216 | */ | |
217 | u8 *irq_sgi_sources; | |
b47ef92a | 218 | |
c1bfb577 MZ |
219 | /* |
220 | * Target CPU for each SPI: | |
221 | * | |
222 | * Array of available SPI, each byte indicating the target | |
223 | * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32]. | |
224 | */ | |
225 | u8 *irq_spi_cpu; | |
226 | ||
227 | /* | |
228 | * Reverse lookup of irq_spi_cpu for faster compute pending: | |
229 | * | |
230 | * Array of bitmaps, one per VCPU, describing if IRQn is | |
231 | * routed to a particular VCPU. | |
232 | */ | |
233 | struct vgic_bitmap *irq_spi_target; | |
b47ef92a | 234 | |
a0675c25 AP |
235 | /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */ |
236 | u32 *irq_spi_mpidr; | |
237 | ||
b47ef92a | 238 | /* Bitmap indicating which CPU has something pending */ |
c1bfb577 | 239 | unsigned long *irq_pending_on_cpu; |
b26e5fda | 240 | |
47a98b15 CD |
241 | /* Bitmap indicating which CPU has active IRQs */ |
242 | unsigned long *irq_active_on_cpu; | |
243 | ||
b26e5fda | 244 | struct vgic_vm_ops vm_ops; |
1a89dd91 MZ |
245 | }; |
246 | ||
eede821d MZ |
247 | struct vgic_v2_cpu_if { |
248 | u32 vgic_hcr; | |
249 | u32 vgic_vmcr; | |
250 | u32 vgic_misr; /* Saved only */ | |
2df36a5d CD |
251 | u64 vgic_eisr; /* Saved only */ |
252 | u64 vgic_elrsr; /* Saved only */ | |
eede821d | 253 | u32 vgic_apr; |
8f186d52 | 254 | u32 vgic_lr[VGIC_V2_MAX_LRS]; |
eede821d MZ |
255 | }; |
256 | ||
b2fb1c0d MZ |
257 | struct vgic_v3_cpu_if { |
258 | #ifdef CONFIG_ARM_GIC_V3 | |
259 | u32 vgic_hcr; | |
260 | u32 vgic_vmcr; | |
2f5fa41a | 261 | u32 vgic_sre; /* Restored only, change ignored */ |
b2fb1c0d MZ |
262 | u32 vgic_misr; /* Saved only */ |
263 | u32 vgic_eisr; /* Saved only */ | |
264 | u32 vgic_elrsr; /* Saved only */ | |
265 | u32 vgic_ap0r[4]; | |
266 | u32 vgic_ap1r[4]; | |
267 | u64 vgic_lr[VGIC_V3_MAX_LRS]; | |
268 | #endif | |
269 | }; | |
270 | ||
1a89dd91 | 271 | struct vgic_cpu { |
9d949dce | 272 | /* per IRQ to LR mapping */ |
c1bfb577 | 273 | u8 *vgic_irq_lr_map; |
9d949dce | 274 | |
47a98b15 | 275 | /* Pending/active/both interrupts on this VCPU */ |
9d949dce | 276 | DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); |
47a98b15 CD |
277 | DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS); |
278 | DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS); | |
279 | ||
280 | /* Pending/active/both shared interrupts, dynamically sized */ | |
c1bfb577 | 281 | unsigned long *pending_shared; |
47a98b15 CD |
282 | unsigned long *active_shared; |
283 | unsigned long *pend_act_shared; | |
9d949dce MZ |
284 | |
285 | /* Bitmap of used/free list registers */ | |
8f186d52 | 286 | DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); |
9d949dce MZ |
287 | |
288 | /* Number of list registers on this CPU */ | |
289 | int nr_lr; | |
290 | ||
291 | /* CPU vif control registers for world switch */ | |
eede821d MZ |
292 | union { |
293 | struct vgic_v2_cpu_if vgic_v2; | |
b2fb1c0d | 294 | struct vgic_v3_cpu_if vgic_v3; |
eede821d | 295 | }; |
1a89dd91 MZ |
296 | }; |
297 | ||
9d949dce MZ |
298 | #define LR_EMPTY 0xff |
299 | ||
495dd859 MZ |
300 | #define INT_STATUS_EOI (1 << 0) |
301 | #define INT_STATUS_UNDERFLOW (1 << 1) | |
302 | ||
1a89dd91 MZ |
303 | struct kvm; |
304 | struct kvm_vcpu; | |
305 | struct kvm_run; | |
306 | struct kvm_exit_mmio; | |
307 | ||
ce01e4e8 | 308 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); |
01ac5e34 | 309 | int kvm_vgic_hyp_init(void); |
6d3cfbe2 | 310 | int kvm_vgic_map_resources(struct kvm *kvm); |
3caa2d8c | 311 | int kvm_vgic_get_max_vcpus(void); |
59892136 | 312 | int kvm_vgic_create(struct kvm *kvm, u32 type); |
c1bfb577 | 313 | void kvm_vgic_destroy(struct kvm *kvm); |
c1bfb577 | 314 | void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); |
9d949dce MZ |
315 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); |
316 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); | |
5863c2ce MZ |
317 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, |
318 | bool level); | |
6d52f35a | 319 | void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); |
9d949dce | 320 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); |
47a98b15 | 321 | int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu); |
1a89dd91 MZ |
322 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, |
323 | struct kvm_exit_mmio *mmio); | |
324 | ||
f982cf4e | 325 | #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) |
1f57be28 | 326 | #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) |
c52edf5f | 327 | #define vgic_ready(k) ((k)->arch.vgic.ready) |
9d949dce | 328 | |
8f186d52 MZ |
329 | int vgic_v2_probe(struct device_node *vgic_node, |
330 | const struct vgic_ops **ops, | |
331 | const struct vgic_params **params); | |
b2fb1c0d MZ |
332 | #ifdef CONFIG_ARM_GIC_V3 |
333 | int vgic_v3_probe(struct device_node *vgic_node, | |
334 | const struct vgic_ops **ops, | |
335 | const struct vgic_params **params); | |
336 | #else | |
337 | static inline int vgic_v3_probe(struct device_node *vgic_node, | |
338 | const struct vgic_ops **ops, | |
339 | const struct vgic_params **params) | |
340 | { | |
341 | return -ENODEV; | |
342 | } | |
343 | #endif | |
8f186d52 | 344 | |
1a89dd91 | 345 | #endif |