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1a89dd91 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __ASM_ARM_KVM_VGIC_H | |
20 | #define __ASM_ARM_KVM_VGIC_H | |
21 | ||
b47ef92a MZ |
22 | #include <linux/kernel.h> |
23 | #include <linux/kvm.h> | |
b47ef92a MZ |
24 | #include <linux/irqreturn.h> |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/types.h> | |
1a89dd91 MZ |
27 | #include <linux/irqchip/arm-gic.h> |
28 | ||
9b2d2e0d | 29 | #define VGIC_NR_IRQS 256 |
b47ef92a MZ |
30 | #define VGIC_NR_SGIS 16 |
31 | #define VGIC_NR_PPIS 16 | |
32 | #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) | |
33 | #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS) | |
34 | #define VGIC_MAX_CPUS KVM_MAX_VCPUS | |
9d949dce | 35 | #define VGIC_MAX_LRS (1 << 6) |
b47ef92a MZ |
36 | |
37 | /* Sanity checks... */ | |
38 | #if (VGIC_MAX_CPUS > 8) | |
39 | #error Invalid number of CPU interfaces | |
40 | #endif | |
41 | ||
42 | #if (VGIC_NR_IRQS & 31) | |
43 | #error "VGIC_NR_IRQS must be a multiple of 32" | |
44 | #endif | |
45 | ||
46 | #if (VGIC_NR_IRQS > 1024) | |
47 | #error "VGIC_NR_IRQS must be <= 1024" | |
48 | #endif | |
49 | ||
50 | /* | |
51 | * The GIC distributor registers describing interrupts have two parts: | |
52 | * - 32 per-CPU interrupts (SGI + PPI) | |
53 | * - a bunch of shared interrupts (SPI) | |
54 | */ | |
55 | struct vgic_bitmap { | |
56 | union { | |
57 | u32 reg[VGIC_NR_PRIVATE_IRQS / 32]; | |
58 | DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS); | |
59 | } percpu[VGIC_MAX_CPUS]; | |
60 | union { | |
61 | u32 reg[VGIC_NR_SHARED_IRQS / 32]; | |
62 | DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS); | |
63 | } shared; | |
64 | }; | |
65 | ||
66 | struct vgic_bytemap { | |
67 | u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4]; | |
68 | u32 shared[VGIC_NR_SHARED_IRQS / 4]; | |
69 | }; | |
70 | ||
1a89dd91 | 71 | struct vgic_dist { |
b47ef92a MZ |
72 | #ifdef CONFIG_KVM_ARM_VGIC |
73 | spinlock_t lock; | |
01ac5e34 | 74 | bool ready; |
b47ef92a MZ |
75 | |
76 | /* Virtual control interface mapping */ | |
77 | void __iomem *vctrl_base; | |
78 | ||
330690cd CD |
79 | /* Distributor and vcpu interface mapping in the guest */ |
80 | phys_addr_t vgic_dist_base; | |
81 | phys_addr_t vgic_cpu_base; | |
b47ef92a MZ |
82 | |
83 | /* Distributor enabled */ | |
84 | u32 enabled; | |
85 | ||
86 | /* Interrupt enabled (one bit per IRQ) */ | |
87 | struct vgic_bitmap irq_enabled; | |
88 | ||
89 | /* Interrupt 'pin' level */ | |
90 | struct vgic_bitmap irq_state; | |
91 | ||
92 | /* Level-triggered interrupt in progress */ | |
93 | struct vgic_bitmap irq_active; | |
94 | ||
95 | /* Interrupt priority. Not used yet. */ | |
96 | struct vgic_bytemap irq_priority; | |
97 | ||
98 | /* Level/edge triggered */ | |
99 | struct vgic_bitmap irq_cfg; | |
100 | ||
101 | /* Source CPU per SGI and target CPU */ | |
102 | u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS]; | |
103 | ||
104 | /* Target CPU for each IRQ */ | |
105 | u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS]; | |
106 | struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS]; | |
107 | ||
108 | /* Bitmap indicating which CPU has something pending */ | |
109 | unsigned long irq_pending_on_cpu; | |
110 | #endif | |
1a89dd91 MZ |
111 | }; |
112 | ||
eede821d MZ |
113 | struct vgic_v2_cpu_if { |
114 | u32 vgic_hcr; | |
115 | u32 vgic_vmcr; | |
116 | u32 vgic_misr; /* Saved only */ | |
117 | u32 vgic_eisr[2]; /* Saved only */ | |
118 | u32 vgic_elrsr[2]; /* Saved only */ | |
119 | u32 vgic_apr; | |
120 | u32 vgic_lr[VGIC_MAX_LRS]; | |
121 | }; | |
122 | ||
1a89dd91 | 123 | struct vgic_cpu { |
9d949dce MZ |
124 | #ifdef CONFIG_KVM_ARM_VGIC |
125 | /* per IRQ to LR mapping */ | |
126 | u8 vgic_irq_lr_map[VGIC_NR_IRQS]; | |
127 | ||
128 | /* Pending interrupts on this VCPU */ | |
129 | DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); | |
130 | DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS); | |
131 | ||
132 | /* Bitmap of used/free list registers */ | |
133 | DECLARE_BITMAP( lr_used, VGIC_MAX_LRS); | |
134 | ||
135 | /* Number of list registers on this CPU */ | |
136 | int nr_lr; | |
137 | ||
138 | /* CPU vif control registers for world switch */ | |
eede821d MZ |
139 | union { |
140 | struct vgic_v2_cpu_if vgic_v2; | |
141 | }; | |
9d949dce | 142 | #endif |
1a89dd91 MZ |
143 | }; |
144 | ||
9d949dce MZ |
145 | #define LR_EMPTY 0xff |
146 | ||
1a89dd91 MZ |
147 | struct kvm; |
148 | struct kvm_vcpu; | |
149 | struct kvm_run; | |
150 | struct kvm_exit_mmio; | |
151 | ||
152 | #ifdef CONFIG_KVM_ARM_VGIC | |
ce01e4e8 | 153 | int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); |
01ac5e34 MZ |
154 | int kvm_vgic_hyp_init(void); |
155 | int kvm_vgic_init(struct kvm *kvm); | |
156 | int kvm_vgic_create(struct kvm *kvm); | |
157 | int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); | |
9d949dce MZ |
158 | void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); |
159 | void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); | |
5863c2ce MZ |
160 | int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, |
161 | bool level); | |
9d949dce | 162 | int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); |
1a89dd91 MZ |
163 | bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, |
164 | struct kvm_exit_mmio *mmio); | |
165 | ||
9d949dce | 166 | #define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base)) |
01ac5e34 | 167 | #define vgic_initialized(k) ((k)->arch.vgic.ready) |
9d949dce | 168 | |
1a89dd91 MZ |
169 | #else |
170 | static inline int kvm_vgic_hyp_init(void) | |
171 | { | |
172 | return 0; | |
173 | } | |
174 | ||
330690cd CD |
175 | static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr) |
176 | { | |
177 | return 0; | |
178 | } | |
179 | ||
6cbde825 MZ |
180 | static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write) |
181 | { | |
182 | return -ENXIO; | |
183 | } | |
184 | ||
1a89dd91 MZ |
185 | static inline int kvm_vgic_init(struct kvm *kvm) |
186 | { | |
187 | return 0; | |
188 | } | |
189 | ||
190 | static inline int kvm_vgic_create(struct kvm *kvm) | |
191 | { | |
192 | return 0; | |
193 | } | |
194 | ||
195 | static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) | |
196 | { | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {} | |
201 | static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {} | |
202 | ||
5863c2ce MZ |
203 | static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, |
204 | unsigned int irq_num, bool level) | |
205 | { | |
206 | return 0; | |
207 | } | |
208 | ||
1a89dd91 MZ |
209 | static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) |
210 | { | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
215 | struct kvm_exit_mmio *mmio) | |
216 | { | |
217 | return false; | |
218 | } | |
219 | ||
220 | static inline int irqchip_in_kernel(struct kvm *kvm) | |
221 | { | |
222 | return 0; | |
223 | } | |
01ac5e34 MZ |
224 | |
225 | static inline bool vgic_initialized(struct kvm *kvm) | |
226 | { | |
227 | return true; | |
228 | } | |
1a89dd91 MZ |
229 | #endif |
230 | ||
231 | #endif |