[mirror_ubuntu-bionic-kernel.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_H
#define __KVM_ARM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/static_key.h>
#include <linux/types.h>
#include <kvm/iodev.h>
#include <linux/list.h>

#define VGIC_V3_MAX_CPUS	255
#define VGIC_V2_MAX_CPUS	8
#define VGIC_NR_IRQS_LEGACY     256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
#define VGIC_MAX_PRIVATE	(VGIC_NR_PRIVATE_IRQS - 1)
#define VGIC_MAX_SPI		1019
#define VGIC_MAX_RESERVED	1023
#define VGIC_MIN_LPI		8192
#define KVM_IRQCHIP_NUM_PINS	(1020 - 32)

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
	/* type of the host GIC */
	enum vgic_type		type;

	/* Physical address of vgic virtual cpu interface */
	phys_addr_t		vcpu_base;

	/* virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Number of implemented list registers */
	int			nr_lr;

	/* Maintenance IRQ number */
	unsigned int		maint_irq;

	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
	int			max_gic_vcpus;

	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool			can_emulate_gicv2;
};

extern struct vgic_global kvm_vgic_global_state;

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_V3_LR_INDEX(lr)	(VGIC_V3_MAX_LRS - 1 - lr)

enum vgic_irq_config {
	VGIC_CONFIG_EDGE = 0,
	VGIC_CONFIG_LEVEL
};

struct vgic_irq {
	spinlock_t irq_lock;		/* Protects the content of the struct */
	struct list_head lpi_list;	/* Used to link all LPIs together */
	struct list_head ap_list;

	struct kvm_vcpu *vcpu;		/* SGIs and PPIs: The VCPU
					 * SPIs and LPIs: The VCPU whose ap_list
					 * this is queued on.
					 */

	struct kvm_vcpu *target_vcpu;	/* The VCPU that this interrupt should
					 * be sent to, as a result of the
					 * targets reg (v2) or the
					 * affinity reg (v3).
					 */

	u32 intid;			/* Guest visible INTID */
	bool pending;
	bool line_level;		/* Level only */
	bool soft_pending;		/* Level only */
	bool active;			/* not used for LPIs */
	bool enabled;
	bool hw;			/* Tied to HW IRQ */
	struct kref refcount;		/* Used for LPIs */
	u32 hwintid;			/* HW INTID number */
	union {
		u8 targets;			/* GICv2 target VCPUs mask */
		u32 mpidr;			/* GICv3 target VCPU */
	};
	u8 source;			/* GICv2 SGIs only */
	u8 priority;
	enum vgic_irq_config config;	/* Level or edge */
};

struct vgic_register_region;
struct vgic_its;

enum iodev_type {
	IODEV_CPUIF,
	IODEV_DIST,
	IODEV_REDIST,
	IODEV_ITS
};

struct vgic_io_device {
	gpa_t base_addr;
	union {
		struct kvm_vcpu *redist_vcpu;
		struct vgic_its *its;
	};
	const struct vgic_register_region *regions;
	enum iodev_type iodev_type;
	int nr_regions;
	struct kvm_io_device dev;
};

struct vgic_its {
	/* The base address of the ITS control register frame */
	gpa_t			vgic_its_base;

	bool			enabled;
	bool			initialized;
	struct vgic_io_device	iodev;
	struct kvm_device	*dev;

	/* These registers correspond to GITS_BASER{0,1} */
	u64			baser_device_table;
	u64			baser_coll_table;

	/* Protects the command queue */
	struct mutex		cmd_lock;
	u64			cbaser;
	u32			creadr;
	u32			cwriter;

	/* Protects the device and collection lists */
	struct mutex		its_lock;
	struct list_head	device_list;
	struct list_head	collection_list;
};

struct vgic_dist {
	bool			in_kernel;
	bool			ready;
	bool			initialized;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	/* Do injected MSIs require an additional device ID? */
	bool			msis_require_devid;

	int			nr_spis;

	/* TODO: Consider moving to global state */
	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* base addresses in guest physical address space: */
	gpa_t			vgic_dist_base;		/* distributor */
	union {
		/* either a GICv2 CPU interface */
		gpa_t			vgic_cpu_base;
		/* or a number of GICv3 redistributor regions */
		gpa_t			vgic_redist_base;
	};

	/* distributor enabled */
	bool			enabled;

	struct vgic_irq		*spis;

	struct vgic_io_device	dist_iodev;

	bool			has_its;

	/*
	 * Contains the attributes and gpa of the LPI configuration table.
	 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	 * one address across all redistributors.
	 * GICv3 spec: 6.1.2 "LPI Configuration tables"
	 */
	u64			propbaser;

	/* Protects the lpi_list and the count value below. */
	spinlock_t		lpi_list_lock;
	struct list_head	lpi_list_head;
	int			lpi_list_count;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_KVM_ARM_VGIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	unsigned int used_lrs;
	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];

	spinlock_t ap_list_lock;	/* Protects the ap_list */

	/*
	 * List of IRQs that this VCPU should consider because they are either
	 * Active or Pending (hence the name; AP list), or because they recently
	 * were one of the two and need to be migrated off this list to another
	 * VCPU.
	 */
	struct list_head ap_list_head;

	u64 live_lrs;

	/*
	 * Members below are used with GICv3 emulation only and represent
	 * parts of the redistributor.
	 */
	struct vgic_io_device	rd_iodev;
	struct vgic_io_device	sgi_iodev;

	/* Contains the attributes and gpa of the LPI pending tables. */
	u64 pendbaser;

	bool lpis_enabled;
};

extern struct static_key_false vgic_v2_cpuif_trap;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_hyp_init(void);

int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			bool level);
int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
			       bool level);
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);

int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	((k)->arch.vgic.initialized)
#define vgic_ready(k)		((k)->arch.vgic.ready)
#define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))

bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);

#ifdef CONFIG_KVM_ARM_VGIC_V3
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
#else
static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
{
}
#endif

/**
 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
 *
 * The host's GIC naturally limits the maximum amount of VCPUs a guest
 * can use.
 */
static inline int kvm_vgic_get_max_vcpus(void)
{
	return kvm_vgic_global_state.max_gic_vcpus;
}

int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi);

/**
 * kvm_vgic_setup_default_irq_routing:
 * Setup a default flat gsi routing table mapping all SPIs
 */
int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);

#endif /* __KVM_ARM_VGIC_H */
Commit	Line	Data
1a89dd91	1	/*
50926d82	2	* Copyright (C) 2015, 2016 ARM Ltd.
1a89dd91 MZ	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
50926d82	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
1a89dd91	15	*/
50926d82 MZ	16	#ifndef __KVM_ARM_VGIC_H
50926d82 MZ	17	#define __KVM_ARM_VGIC_H
b18b5778	18
b47ef92a MZ	19	#include <linux/kernel.h>
b47ef92a MZ	20	#include <linux/kvm.h>
b47ef92a MZ	21	#include <linux/irqreturn.h>
b47ef92a MZ	22	#include <linux/spinlock.h>
fb5ee369	23	#include <linux/static_key.h>
b47ef92a	24	#include <linux/types.h>
6777f77f	25	#include <kvm/iodev.h>
424c3383	26	#include <linux/list.h>
1a89dd91	27
50926d82 MZ	28	#define VGIC_V3_MAX_CPUS 255
	29	#define VGIC_V2_MAX_CPUS 8
	30	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	31	#define VGIC_NR_SGIS 16
	32	#define VGIC_NR_PPIS 16
	33	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
50926d82 MZ	34	#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
	35	#define VGIC_MAX_SPI 1019
	36	#define VGIC_MAX_RESERVED 1023
	37	#define VGIC_MIN_LPI 8192
180ae7b1	38	#define KVM_IRQCHIP_NUM_PINS (1020 - 32)
8f186d52	39
50926d82 MZ	40	enum vgic_type {
	41	VGIC_V2, /* Good ol' GICv2 */
	42	VGIC_V3, /* New fancy GICv3 */
	43	};
b47ef92a	44
50926d82 MZ	45	/* same for all guests, as depending only on the _host's_ GIC model */
	46	struct vgic_global {
	47	/* type of the host GIC */
	48	enum vgic_type type;
b47ef92a	49
50926d82 MZ	50	/* Physical address of vgic virtual cpu interface */
50926d82 MZ	51	phys_addr_t vcpu_base;
b47ef92a	52
50926d82 MZ	53	/* virtual control interface mapping */
50926d82 MZ	54	void __iomem *vctrl_base;
b47ef92a	55
50926d82 MZ	56	/* Number of implemented list registers */
50926d82 MZ	57	int nr_lr;
8d5c6b06	58
50926d82 MZ	59	/* Maintenance IRQ number */
50926d82 MZ	60	unsigned int maint_irq;
1a9b1305	61
50926d82 MZ	62	/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
50926d82 MZ	63	int max_gic_vcpus;
8d5c6b06	64
50926d82 MZ	65	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
50926d82 MZ	66	bool can_emulate_gicv2;
8d5c6b06 MZ	67	};
8d5c6b06 MZ	68
50926d82	69	extern struct vgic_global kvm_vgic_global_state;
beee38b9	70
50926d82 MZ	71	#define VGIC_V2_MAX_LRS (1 << 6)
	72	#define VGIC_V3_MAX_LRS 16
	73	#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
8d5c6b06	74
50926d82 MZ	75	enum vgic_irq_config {
	76	VGIC_CONFIG_EDGE = 0,
	77	VGIC_CONFIG_LEVEL
ca85f623 MZ	78	};
ca85f623 MZ	79
50926d82 MZ	80	struct vgic_irq {
50926d82 MZ	81	spinlock_t irq_lock; /* Protects the content of the struct */
3802411d	82	struct list_head lpi_list; /* Used to link all LPIs together */
50926d82 MZ	83	struct list_head ap_list;
	84
	85	struct kvm_vcpu vcpu; / SGIs and PPIs: The VCPU
	86	* SPIs and LPIs: The VCPU whose ap_list
	87	* this is queued on.
	88	*/
	89
	90	struct kvm_vcpu target_vcpu; / The VCPU that this interrupt should
	91	* be sent to, as a result of the
	92	* targets reg (v2) or the
	93	* affinity reg (v3).
	94	*/
	95
	96	u32 intid; /* Guest visible INTID */
	97	bool pending;
	98	bool line_level; /* Level only */
	99	bool soft_pending; /* Level only */
	100	bool active; /* not used for LPIs */
	101	bool enabled;
	102	bool hw; /* Tied to HW IRQ */
5dd4b924	103	struct kref refcount; /* Used for LPIs */
50926d82 MZ	104	u32 hwintid; /* HW INTID number */
	105	union {
	106	u8 targets; /* GICv2 target VCPUs mask */
	107	u32 mpidr; /* GICv3 target VCPU */
	108	};
	109	u8 source; /* GICv2 SGIs only */
	110	u8 priority;
	111	enum vgic_irq_config config; /* Level or edge */
b26e5fda AP	112	};
b26e5fda AP	113
50926d82	114	struct vgic_register_region;
59c5ab40 AP	115	struct vgic_its;
	116
	117	enum iodev_type {
	118	IODEV_CPUIF,
	119	IODEV_DIST,
	120	IODEV_REDIST,
	121	IODEV_ITS
	122	};
50926d82	123
6777f77f	124	struct vgic_io_device {
50926d82	125	gpa_t base_addr;
59c5ab40 AP	126	union {
	127	struct kvm_vcpu *redist_vcpu;
	128	struct vgic_its *its;
	129	};
50926d82	130	const struct vgic_register_region *regions;
59c5ab40	131	enum iodev_type iodev_type;
50926d82	132	int nr_regions;
6777f77f AP	133	struct kvm_io_device dev;
	134	};
	135
59c5ab40 AP	136	struct vgic_its {
	137	/* The base address of the ITS control register frame */
	138	gpa_t vgic_its_base;
	139
	140	bool enabled;
1085fdc6	141	bool initialized;
59c5ab40	142	struct vgic_io_device iodev;
bb717644	143	struct kvm_device *dev;
424c3383 AP	144
	145	/* These registers correspond to GITS_BASER{0,1} */
	146	u64 baser_device_table;
	147	u64 baser_coll_table;
	148
	149	/* Protects the command queue */
	150	struct mutex cmd_lock;
	151	u64 cbaser;
	152	u32 creadr;
	153	u32 cwriter;
	154
	155	/* Protects the device and collection lists */
	156	struct mutex its_lock;
	157	struct list_head device_list;
	158	struct list_head collection_list;
59c5ab40 AP	159	};
59c5ab40 AP	160
1a89dd91	161	struct vgic_dist {
f982cf4e	162	bool in_kernel;
01ac5e34	163	bool ready;
50926d82	164	bool initialized;
b47ef92a	165
59892136 AP	166	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	167	u32 vgic_model;
	168
0e4e82f1 AP	169	/* Do injected MSIs require an additional device ID? */
	170	bool msis_require_devid;
	171
50926d82	172	int nr_spis;
c1bfb577	173
50926d82	174	/* TODO: Consider moving to global state */
b47ef92a MZ	175	/* Virtual control interface mapping */
	176	void __iomem *vctrl_base;
	177
50926d82 MZ	178	/* base addresses in guest physical address space: */
50926d82 MZ	179	gpa_t vgic_dist_base; /* distributor */
a0675c25	180	union {
50926d82 MZ	181	/* either a GICv2 CPU interface */
	182	gpa_t vgic_cpu_base;
	183	/* or a number of GICv3 redistributor regions */
	184	gpa_t vgic_redist_base;
a0675c25	185	};
b47ef92a	186
50926d82 MZ	187	/* distributor enabled */
50926d82 MZ	188	bool enabled;
47a98b15	189
50926d82	190	struct vgic_irq *spis;
b47ef92a	191
a9cf86f6	192	struct vgic_io_device dist_iodev;
0aa1de57	193
1085fdc6 AP	194	bool has_its;
1085fdc6 AP	195
0aa1de57 AP	196	/*
	197	* Contains the attributes and gpa of the LPI configuration table.
	198	* Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
	199	* one address across all redistributors.
	200	* GICv3 spec: 6.1.2 "LPI Configuration tables"
	201	*/
	202	u64 propbaser;
3802411d AP	203
	204	/* Protects the lpi_list and the count value below. */
	205	spinlock_t lpi_list_lock;
	206	struct list_head lpi_list_head;
	207	int lpi_list_count;
1a89dd91 MZ	208	};
1a89dd91 MZ	209
eede821d MZ	210	struct vgic_v2_cpu_if {
	211	u32 vgic_hcr;
	212	u32 vgic_vmcr;
	213	u32 vgic_misr; /* Saved only */
2df36a5d CD	214	u64 vgic_eisr; /* Saved only */
2df36a5d CD	215	u64 vgic_elrsr; /* Saved only */
eede821d	216	u32 vgic_apr;
8f186d52	217	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	218	};
eede821d MZ	219
b2fb1c0d	220	struct vgic_v3_cpu_if {
4f64cb65	221	#ifdef CONFIG_KVM_ARM_VGIC_V3
b2fb1c0d MZ	222	u32 vgic_hcr;
b2fb1c0d MZ	223	u32 vgic_vmcr;
2f5fa41a	224	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	225	u32 vgic_misr; /* Saved only */
	226	u32 vgic_eisr; /* Saved only */
	227	u32 vgic_elrsr; /* Saved only */
	228	u32 vgic_ap0r[4];
	229	u32 vgic_ap1r[4];
	230	u64 vgic_lr[VGIC_V3_MAX_LRS];
	231	#endif
	232	};
	233
1a89dd91	234	struct vgic_cpu {
9d949dce	235	/* CPU vif control registers for world switch */
eede821d MZ	236	union {
eede821d MZ	237	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	238	struct vgic_v3_cpu_if vgic_v3;
eede821d	239	};
6c3d63c9	240
50926d82 MZ	241	unsigned int used_lrs;
50926d82 MZ	242	struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
1a89dd91	243
50926d82	244	spinlock_t ap_list_lock; /* Protects the ap_list */
9d949dce	245
50926d82 MZ	246	/*
	247	* List of IRQs that this VCPU should consider because they are either
	248	* Active or Pending (hence the name; AP list), or because they recently
	249	* were one of the two and need to be migrated off this list to another
	250	* VCPU.
	251	*/
	252	struct list_head ap_list_head;
495dd859	253
50926d82	254	u64 live_lrs;
8f6cdc1c AP	255
	256	/*
	257	* Members below are used with GICv3 emulation only and represent
	258	* parts of the redistributor.
	259	*/
	260	struct vgic_io_device rd_iodev;
	261	struct vgic_io_device sgi_iodev;
0aa1de57 AP	262
	263	/* Contains the attributes and gpa of the LPI pending tables. */
	264	u64 pendbaser;
	265
	266	bool lpis_enabled;
50926d82	267	};
1a89dd91	268
fb5ee369 MZ	269	extern struct static_key_false vgic_v2_cpuif_trap;
fb5ee369 MZ	270
ce01e4e8	271	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
6c3d63c9	272	void kvm_vgic_early_init(struct kvm *kvm);
59892136	273	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	274	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	275	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	276	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
50926d82 MZ	277	int kvm_vgic_map_resources(struct kvm *kvm);
	278	int kvm_vgic_hyp_init(void);
	279
	280	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
5863c2ce	281	bool level);
50926d82 MZ	282	int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, unsigned int intid,
	283	bool level);
	284	int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq);
63306c28	285	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq);
e262f419	286	bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq);
1a89dd91	287
50926d82 MZ	288	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
50926d82 MZ	289
f982cf4e	290	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
50926d82	291	#define vgic_initialized(k) ((k)->arch.vgic.initialized)
c52edf5f	292	#define vgic_ready(k) ((k)->arch.vgic.ready)
2defaff4	293	#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
50926d82 MZ	294	((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
	295
	296	bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
	297	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
	298	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce	299
4f64cb65	300	#ifdef CONFIG_KVM_ARM_VGIC_V3
50926d82	301	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
b2fb1c0d	302	#else
50926d82	303	static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
b2fb1c0d	304	{
b2fb1c0d MZ	305	}
b2fb1c0d MZ	306	#endif
8f186d52	307
50926d82 MZ	308	/**
	309	* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
	310	*
	311	* The host's GIC naturally limits the maximum amount of VCPUs a guest
	312	* can use.
	313	*/
	314	static inline int kvm_vgic_get_max_vcpus(void)
	315	{
	316	return kvm_vgic_global_state.max_gic_vcpus;
	317	}
	318
0e4e82f1 AP	319	int kvm_send_userspace_msi(struct kvm kvm, struct kvm_msi msi);
0e4e82f1 AP	320
180ae7b1 EA	321	/**
	322	* kvm_vgic_setup_default_irq_routing:
	323	* Setup a default flat gsi routing table mapping all SPIs
	324	*/
	325	int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
	326
50926d82	327	#endif /* __KVM_ARM_VGIC_H */