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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
c13c8260 CL |
14 | * The full GNU General Public License is included in this distribution in the |
15 | * file called COPYING. | |
16 | */ | |
d2ebfb33 RKAL |
17 | #ifndef LINUX_DMAENGINE_H |
18 | #define LINUX_DMAENGINE_H | |
1c0f16e5 | 19 | |
c13c8260 | 20 | #include <linux/device.h> |
0ad7c000 | 21 | #include <linux/err.h> |
c13c8260 | 22 | #include <linux/uio.h> |
187f1882 | 23 | #include <linux/bug.h> |
90b44f8f | 24 | #include <linux/scatterlist.h> |
a8efa9d6 | 25 | #include <linux/bitmap.h> |
dcc043dc | 26 | #include <linux/types.h> |
a8efa9d6 | 27 | #include <asm/page.h> |
b7f080cf | 28 | |
c13c8260 | 29 | /** |
fe4ada2d | 30 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
31 | * |
32 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
33 | */ | |
34 | typedef s32 dma_cookie_t; | |
76bd061f | 35 | #define DMA_MIN_COOKIE 1 |
c13c8260 | 36 | |
71ea1483 DC |
37 | static inline int dma_submit_error(dma_cookie_t cookie) |
38 | { | |
39 | return cookie < 0 ? cookie : 0; | |
40 | } | |
c13c8260 CL |
41 | |
42 | /** | |
43 | * enum dma_status - DMA transaction status | |
adfedd9a | 44 | * @DMA_COMPLETE: transaction completed |
c13c8260 | 45 | * @DMA_IN_PROGRESS: transaction not yet processed |
07934481 | 46 | * @DMA_PAUSED: transaction is paused |
c13c8260 CL |
47 | * @DMA_ERROR: transaction failed |
48 | */ | |
49 | enum dma_status { | |
7db5f727 | 50 | DMA_COMPLETE, |
c13c8260 | 51 | DMA_IN_PROGRESS, |
07934481 | 52 | DMA_PAUSED, |
c13c8260 CL |
53 | DMA_ERROR, |
54 | }; | |
55 | ||
7405f74b DW |
56 | /** |
57 | * enum dma_transaction_type - DMA transaction types/indexes | |
138f4c35 DW |
58 | * |
59 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
60 | * automatically set as dma devices are registered. | |
7405f74b DW |
61 | */ |
62 | enum dma_transaction_type { | |
63 | DMA_MEMCPY, | |
64 | DMA_XOR, | |
b2f46fd8 | 65 | DMA_PQ, |
099f53cb DW |
66 | DMA_XOR_VAL, |
67 | DMA_PQ_VAL, | |
7405f74b | 68 | DMA_INTERRUPT, |
a86ee03c | 69 | DMA_SG, |
59b5ec21 | 70 | DMA_PRIVATE, |
138f4c35 | 71 | DMA_ASYNC_TX, |
dc0ee643 | 72 | DMA_SLAVE, |
782bc950 | 73 | DMA_CYCLIC, |
b14dab79 | 74 | DMA_INTERLEAVE, |
7405f74b | 75 | /* last transaction type for creation of the capabilities mask */ |
b14dab79 JB |
76 | DMA_TX_TYPE_END, |
77 | }; | |
dc0ee643 | 78 | |
49920bc6 VK |
79 | /** |
80 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
81 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
82 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
83 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
84 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
85 | */ | |
86 | enum dma_transfer_direction { | |
87 | DMA_MEM_TO_MEM, | |
88 | DMA_MEM_TO_DEV, | |
89 | DMA_DEV_TO_MEM, | |
90 | DMA_DEV_TO_DEV, | |
62268ce9 | 91 | DMA_TRANS_NONE, |
49920bc6 | 92 | }; |
7405f74b | 93 | |
b14dab79 JB |
94 | /** |
95 | * Interleaved Transfer Request | |
96 | * ---------------------------- | |
97 | * A chunk is collection of contiguous bytes to be transfered. | |
98 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
99 | * ICGs may or maynot change between chunks. | |
100 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
101 | * that when repeated an integral number of times, specifies the transfer. | |
102 | * A transfer template is specification of a Frame, the number of times | |
103 | * it is to be repeated and other per-transfer attributes. | |
104 | * | |
105 | * Practically, a client driver would have ready a template for each | |
106 | * type of transfer it is going to need during its lifetime and | |
107 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
108 | * | |
109 | * | |
110 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
111 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
112 | * | |
113 | * == Chunk size | |
114 | * ... ICG | |
115 | */ | |
116 | ||
117 | /** | |
118 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
119 | * @size: Number of bytes to read from source. | |
120 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
121 | * @icg: Number of bytes to jump after last src/dst address of this | |
122 | * chunk and before first src/dst address for next chunk. | |
123 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
124 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
125 | */ | |
126 | struct data_chunk { | |
127 | size_t size; | |
128 | size_t icg; | |
129 | }; | |
130 | ||
131 | /** | |
132 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
133 | * and attributes. | |
134 | * @src_start: Bus address of source for the first chunk. | |
135 | * @dst_start: Bus address of destination for the first chunk. | |
136 | * @dir: Specifies the type of Source and Destination. | |
137 | * @src_inc: If the source address increments after reading from it. | |
138 | * @dst_inc: If the destination address increments after writing to it. | |
139 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
140 | * Otherwise, source is read contiguously (icg ignored). | |
141 | * Ignored if src_inc is false. | |
142 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
143 | * Otherwise, destination is filled contiguously (icg ignored). | |
144 | * Ignored if dst_inc is false. | |
145 | * @numf: Number of frames in this template. | |
146 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
147 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
148 | */ | |
149 | struct dma_interleaved_template { | |
150 | dma_addr_t src_start; | |
151 | dma_addr_t dst_start; | |
152 | enum dma_transfer_direction dir; | |
153 | bool src_inc; | |
154 | bool dst_inc; | |
155 | bool src_sgl; | |
156 | bool dst_sgl; | |
157 | size_t numf; | |
158 | size_t frame_size; | |
159 | struct data_chunk sgl[0]; | |
160 | }; | |
161 | ||
d4c56f97 | 162 | /** |
636bdeaa | 163 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
b2f46fd8 | 164 | * control completion, and communicate status. |
d4c56f97 | 165 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
b2f46fd8 | 166 | * this transaction |
a88f6667 | 167 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client |
b2f46fd8 DW |
168 | * acknowledges receipt, i.e. has has a chance to establish any dependency |
169 | * chains | |
b2f46fd8 DW |
170 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q |
171 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
172 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
173 | * sources that were the result of a previous operation, in the case of a PQ | |
174 | * operation it continues the calculation with new sources | |
0403e382 DW |
175 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend |
176 | * on the result of this operation | |
d4c56f97 | 177 | */ |
636bdeaa | 178 | enum dma_ctrl_flags { |
d4c56f97 | 179 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 180 | DMA_CTRL_ACK = (1 << 1), |
0776ae7b BZ |
181 | DMA_PREP_PQ_DISABLE_P = (1 << 2), |
182 | DMA_PREP_PQ_DISABLE_Q = (1 << 3), | |
183 | DMA_PREP_CONTINUE = (1 << 4), | |
184 | DMA_PREP_FENCE = (1 << 5), | |
d4c56f97 DW |
185 | }; |
186 | ||
ad283ea4 DW |
187 | /** |
188 | * enum sum_check_bits - bit position of pq_check_flags | |
189 | */ | |
190 | enum sum_check_bits { | |
191 | SUM_CHECK_P = 0, | |
192 | SUM_CHECK_Q = 1, | |
193 | }; | |
194 | ||
195 | /** | |
196 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
197 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
198 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
199 | */ | |
200 | enum sum_check_flags { | |
201 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
202 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
203 | }; | |
204 | ||
205 | ||
7405f74b DW |
206 | /** |
207 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
208 | * See linux/cpumask.h | |
209 | */ | |
210 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
211 | ||
c13c8260 CL |
212 | /** |
213 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
c13c8260 CL |
214 | * @memcpy_count: transaction counter |
215 | * @bytes_transferred: byte counter | |
216 | */ | |
217 | ||
218 | struct dma_chan_percpu { | |
c13c8260 CL |
219 | /* stats */ |
220 | unsigned long memcpy_count; | |
221 | unsigned long bytes_transferred; | |
222 | }; | |
223 | ||
56f13c0d PU |
224 | /** |
225 | * struct dma_router - DMA router structure | |
226 | * @dev: pointer to the DMA router device | |
227 | * @route_free: function to be called when the route can be disconnected | |
228 | */ | |
229 | struct dma_router { | |
230 | struct device *dev; | |
231 | void (*route_free)(struct device *dev, void *route_data); | |
232 | }; | |
233 | ||
c13c8260 CL |
234 | /** |
235 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 236 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 237 | * @cookie: last cookie value returned to client |
4d4e58de | 238 | * @completed_cookie: last completed cookie for this channel |
fe4ada2d | 239 | * @chan_id: channel ID for sysfs |
41d5e59c | 240 | * @dev: class device for sysfs |
c13c8260 CL |
241 | * @device_node: used to add this to the device chan list |
242 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
868d2ee2 | 243 | * @client_count: how many clients are using this channel |
bec08513 | 244 | * @table_count: number of appearances in the mem-to-mem allocation table |
56f13c0d PU |
245 | * @router: pointer to the DMA router structure |
246 | * @route_data: channel specific data for the router | |
287d8592 | 247 | * @private: private data for certain client-channel associations |
c13c8260 CL |
248 | */ |
249 | struct dma_chan { | |
c13c8260 CL |
250 | struct dma_device *device; |
251 | dma_cookie_t cookie; | |
4d4e58de | 252 | dma_cookie_t completed_cookie; |
c13c8260 CL |
253 | |
254 | /* sysfs */ | |
255 | int chan_id; | |
41d5e59c | 256 | struct dma_chan_dev *dev; |
c13c8260 | 257 | |
c13c8260 | 258 | struct list_head device_node; |
a29d8b8e | 259 | struct dma_chan_percpu __percpu *local; |
7cc5bf9a | 260 | int client_count; |
bec08513 | 261 | int table_count; |
56f13c0d PU |
262 | |
263 | /* DMA router */ | |
264 | struct dma_router *router; | |
265 | void *route_data; | |
266 | ||
287d8592 | 267 | void *private; |
c13c8260 CL |
268 | }; |
269 | ||
41d5e59c DW |
270 | /** |
271 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
868d2ee2 VK |
272 | * @chan: driver channel device |
273 | * @device: sysfs device | |
274 | * @dev_id: parent dma_device dev_id | |
275 | * @idr_ref: reference count to gate release of dma_device dev_id | |
41d5e59c DW |
276 | */ |
277 | struct dma_chan_dev { | |
278 | struct dma_chan *chan; | |
279 | struct device device; | |
864498aa DW |
280 | int dev_id; |
281 | atomic_t *idr_ref; | |
41d5e59c DW |
282 | }; |
283 | ||
c156d0a5 | 284 | /** |
ba730340 | 285 | * enum dma_slave_buswidth - defines bus width of the DMA slave |
c156d0a5 LW |
286 | * device, source or target buses |
287 | */ | |
288 | enum dma_slave_buswidth { | |
289 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
290 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
291 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
93c6ee94 | 292 | DMA_SLAVE_BUSWIDTH_3_BYTES = 3, |
c156d0a5 LW |
293 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, |
294 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
534a7298 LP |
295 | DMA_SLAVE_BUSWIDTH_16_BYTES = 16, |
296 | DMA_SLAVE_BUSWIDTH_32_BYTES = 32, | |
297 | DMA_SLAVE_BUSWIDTH_64_BYTES = 64, | |
c156d0a5 LW |
298 | }; |
299 | ||
300 | /** | |
301 | * struct dma_slave_config - dma slave channel runtime config | |
302 | * @direction: whether the data shall go in or out on this slave | |
397321f4 | 303 | * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are |
d9ff958b LP |
304 | * legal values. DEPRECATED, drivers should use the direction argument |
305 | * to the device_prep_slave_sg and device_prep_dma_cyclic functions or | |
306 | * the dir field in the dma_interleaved_template structure. | |
c156d0a5 LW |
307 | * @src_addr: this is the physical address where DMA slave data |
308 | * should be read (RX), if the source is memory this argument is | |
309 | * ignored. | |
310 | * @dst_addr: this is the physical address where DMA slave data | |
311 | * should be written (TX), if the source is memory this argument | |
312 | * is ignored. | |
313 | * @src_addr_width: this is the width in bytes of the source (RX) | |
314 | * register where DMA data shall be read. If the source | |
315 | * is memory this may be ignored depending on architecture. | |
316 | * Legal values: 1, 2, 4, 8. | |
317 | * @dst_addr_width: same as src_addr_width but for destination | |
318 | * target (TX) mutatis mutandis. | |
319 | * @src_maxburst: the maximum number of words (note: words, as in | |
320 | * units of the src_addr_width member, not bytes) that can be sent | |
321 | * in one burst to the device. Typically something like half the | |
322 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
323 | * may or may not be applicable on memory sources. | |
324 | * @dst_maxburst: same as src_maxburst but for destination target | |
325 | * mutatis mutandis. | |
dcc043dc VK |
326 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill |
327 | * with 'true' if peripheral should be flow controller. Direction will be | |
328 | * selected at Runtime. | |
4fd1e324 LD |
329 | * @slave_id: Slave requester id. Only valid for slave channels. The dma |
330 | * slave peripheral will have unique id as dma requester which need to be | |
331 | * pass as slave config. | |
c156d0a5 LW |
332 | * |
333 | * This struct is passed in as configuration data to a DMA engine | |
334 | * in order to set up a certain channel for DMA transport at runtime. | |
335 | * The DMA device/engine has to provide support for an additional | |
2c44ad91 MR |
336 | * callback in the dma_device structure, device_config and this struct |
337 | * will then be passed in as an argument to the function. | |
c156d0a5 | 338 | * |
7cbccb55 LPC |
339 | * The rationale for adding configuration information to this struct is as |
340 | * follows: if it is likely that more than one DMA slave controllers in | |
341 | * the world will support the configuration option, then make it generic. | |
342 | * If not: if it is fixed so that it be sent in static from the platform | |
343 | * data, then prefer to do that. | |
c156d0a5 LW |
344 | */ |
345 | struct dma_slave_config { | |
49920bc6 | 346 | enum dma_transfer_direction direction; |
c156d0a5 LW |
347 | dma_addr_t src_addr; |
348 | dma_addr_t dst_addr; | |
349 | enum dma_slave_buswidth src_addr_width; | |
350 | enum dma_slave_buswidth dst_addr_width; | |
351 | u32 src_maxburst; | |
352 | u32 dst_maxburst; | |
dcc043dc | 353 | bool device_fc; |
4fd1e324 | 354 | unsigned int slave_id; |
c156d0a5 LW |
355 | }; |
356 | ||
50720563 LPC |
357 | /** |
358 | * enum dma_residue_granularity - Granularity of the reported transfer residue | |
359 | * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The | |
360 | * DMA channel is only able to tell whether a descriptor has been completed or | |
361 | * not, which means residue reporting is not supported by this channel. The | |
362 | * residue field of the dma_tx_state field will always be 0. | |
363 | * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully | |
364 | * completed segment of the transfer (For cyclic transfers this is after each | |
365 | * period). This is typically implemented by having the hardware generate an | |
366 | * interrupt after each transferred segment and then the drivers updates the | |
367 | * outstanding residue by the size of the segment. Another possibility is if | |
368 | * the hardware supports scatter-gather and the segment descriptor has a field | |
369 | * which gets set after the segment has been completed. The driver then counts | |
370 | * the number of segments without the flag set to compute the residue. | |
371 | * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred | |
372 | * burst. This is typically only supported if the hardware has a progress | |
373 | * register of some sort (E.g. a register with the current read/write address | |
374 | * or a register with the amount of bursts/beats/bytes that have been | |
375 | * transferred or still need to be transferred). | |
376 | */ | |
377 | enum dma_residue_granularity { | |
378 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, | |
379 | DMA_RESIDUE_GRANULARITY_SEGMENT = 1, | |
380 | DMA_RESIDUE_GRANULARITY_BURST = 2, | |
381 | }; | |
382 | ||
221a27c7 VK |
383 | /* struct dma_slave_caps - expose capabilities of a slave channel only |
384 | * | |
385 | * @src_addr_widths: bit mask of src addr widths the channel supports | |
ceacbdbf | 386 | * @dst_addr_widths: bit mask of dstn addr widths the channel supports |
221a27c7 VK |
387 | * @directions: bit mask of slave direction the channel supported |
388 | * since the enum dma_transfer_direction is not defined as bits for each | |
389 | * type of direction, the dma controller should fill (1 << <TYPE>) and same | |
390 | * should be checked by controller as well | |
391 | * @cmd_pause: true, if pause and thereby resume is supported | |
392 | * @cmd_terminate: true, if terminate cmd is supported | |
50720563 | 393 | * @residue_granularity: granularity of the reported transfer residue |
221a27c7 VK |
394 | */ |
395 | struct dma_slave_caps { | |
396 | u32 src_addr_widths; | |
ceacbdbf | 397 | u32 dst_addr_widths; |
221a27c7 VK |
398 | u32 directions; |
399 | bool cmd_pause; | |
400 | bool cmd_terminate; | |
50720563 | 401 | enum dma_residue_granularity residue_granularity; |
221a27c7 VK |
402 | }; |
403 | ||
41d5e59c DW |
404 | static inline const char *dma_chan_name(struct dma_chan *chan) |
405 | { | |
406 | return dev_name(&chan->dev->device); | |
407 | } | |
d379b01e | 408 | |
c13c8260 CL |
409 | void dma_chan_cleanup(struct kref *kref); |
410 | ||
59b5ec21 DW |
411 | /** |
412 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
413 | * @chan: channel to be reviewed | |
414 | * @filter_param: opaque parameter passed through dma_request_channel | |
415 | * | |
416 | * When this optional parameter is specified in a call to dma_request_channel a | |
417 | * suitable channel is passed to this routine for further dispositioning before | |
418 | * being returned. Where 'suitable' indicates a non-busy channel that | |
7dd60251 DW |
419 | * satisfies the given capability mask. It returns 'true' to indicate that the |
420 | * channel is suitable. | |
59b5ec21 | 421 | */ |
7dd60251 | 422 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); |
59b5ec21 | 423 | |
7405f74b | 424 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
d38a8c62 DW |
425 | |
426 | struct dmaengine_unmap_data { | |
c1f43dd9 | 427 | u8 map_cnt; |
d38a8c62 DW |
428 | u8 to_cnt; |
429 | u8 from_cnt; | |
430 | u8 bidi_cnt; | |
431 | struct device *dev; | |
432 | struct kref kref; | |
433 | size_t len; | |
434 | dma_addr_t addr[0]; | |
435 | }; | |
436 | ||
7405f74b DW |
437 | /** |
438 | * struct dma_async_tx_descriptor - async transaction descriptor | |
439 | * ---dma generic offload fields--- | |
440 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
441 | * this tx is sitting on a dependency list | |
636bdeaa DW |
442 | * @flags: flags to augment operation preparation, control completion, and |
443 | * communicate status | |
7405f74b | 444 | * @phys: physical address of the descriptor |
7405f74b | 445 | * @chan: target channel for this operation |
aba96bad VK |
446 | * @tx_submit: accept the descriptor, assign ordered cookie and mark the |
447 | * descriptor pending. To be pushed on .issue_pending() call | |
7405f74b DW |
448 | * @callback: routine to call after this operation is complete |
449 | * @callback_param: general parameter to pass to the callback routine | |
450 | * ---async_tx api specific fields--- | |
19242d72 | 451 | * @next: at completion submit this descriptor |
7405f74b | 452 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 453 | * @lock: protect the parent and next pointers |
7405f74b DW |
454 | */ |
455 | struct dma_async_tx_descriptor { | |
456 | dma_cookie_t cookie; | |
636bdeaa | 457 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b | 458 | dma_addr_t phys; |
7405f74b DW |
459 | struct dma_chan *chan; |
460 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
461 | dma_async_tx_callback callback; |
462 | void *callback_param; | |
d38a8c62 | 463 | struct dmaengine_unmap_data *unmap; |
5fc6d897 | 464 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
19242d72 | 465 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
466 | struct dma_async_tx_descriptor *parent; |
467 | spinlock_t lock; | |
caa20d97 | 468 | #endif |
7405f74b DW |
469 | }; |
470 | ||
89716462 | 471 | #ifdef CONFIG_DMA_ENGINE |
d38a8c62 DW |
472 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, |
473 | struct dmaengine_unmap_data *unmap) | |
474 | { | |
475 | kref_get(&unmap->kref); | |
476 | tx->unmap = unmap; | |
477 | } | |
478 | ||
89716462 DW |
479 | struct dmaengine_unmap_data * |
480 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); | |
45c463ae | 481 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); |
89716462 DW |
482 | #else |
483 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
484 | struct dmaengine_unmap_data *unmap) | |
485 | { | |
486 | } | |
487 | static inline struct dmaengine_unmap_data * | |
488 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) | |
489 | { | |
490 | return NULL; | |
491 | } | |
492 | static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) | |
493 | { | |
494 | } | |
495 | #endif | |
45c463ae | 496 | |
d38a8c62 DW |
497 | static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) |
498 | { | |
499 | if (tx->unmap) { | |
45c463ae | 500 | dmaengine_unmap_put(tx->unmap); |
d38a8c62 DW |
501 | tx->unmap = NULL; |
502 | } | |
503 | } | |
504 | ||
5fc6d897 | 505 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
caa20d97 DW |
506 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) |
507 | { | |
508 | } | |
509 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
510 | { | |
511 | } | |
512 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
513 | { | |
514 | BUG(); | |
515 | } | |
516 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
517 | { | |
518 | } | |
519 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
520 | { | |
521 | } | |
522 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
523 | { | |
524 | return NULL; | |
525 | } | |
526 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
527 | { | |
528 | return NULL; | |
529 | } | |
530 | ||
531 | #else | |
532 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
533 | { | |
534 | spin_lock_bh(&txd->lock); | |
535 | } | |
536 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
537 | { | |
538 | spin_unlock_bh(&txd->lock); | |
539 | } | |
540 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
541 | { | |
542 | txd->next = next; | |
543 | next->parent = txd; | |
544 | } | |
545 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
546 | { | |
547 | txd->parent = NULL; | |
548 | } | |
549 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
550 | { | |
551 | txd->next = NULL; | |
552 | } | |
553 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
554 | { | |
555 | return txd->parent; | |
556 | } | |
557 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
558 | { | |
559 | return txd->next; | |
560 | } | |
561 | #endif | |
562 | ||
07934481 LW |
563 | /** |
564 | * struct dma_tx_state - filled in to report the status of | |
565 | * a transfer. | |
566 | * @last: last completed DMA cookie | |
567 | * @used: last issued DMA cookie (i.e. the one in progress) | |
568 | * @residue: the remaining number of bytes left to transmit | |
569 | * on the selected transfer for states DMA_IN_PROGRESS and | |
570 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
571 | */ | |
572 | struct dma_tx_state { | |
573 | dma_cookie_t last; | |
574 | dma_cookie_t used; | |
575 | u32 residue; | |
576 | }; | |
577 | ||
c13c8260 CL |
578 | /** |
579 | * struct dma_device - info on the entity supplying DMA services | |
580 | * @chancnt: how many DMA channels are supported | |
0f571515 | 581 | * @privatecnt: how many DMA channels are requested by dma_request_channel |
c13c8260 CL |
582 | * @channels: the list of struct dma_chan |
583 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
584 | * @cap_mask: one or more dma_capability flags |
585 | * @max_xor: maximum number of xor sources, 0 if no capability | |
b2f46fd8 | 586 | * @max_pq: maximum number of PQ sources and PQ-continue capability |
83544ae9 DW |
587 | * @copy_align: alignment shift for memcpy operations |
588 | * @xor_align: alignment shift for xor operations | |
589 | * @pq_align: alignment shift for pq operations | |
fe4ada2d | 590 | * @dev_id: unique device ID |
7405f74b | 591 | * @dev: struct device reference for dma mapping api |
cb8cea51 MR |
592 | * @src_addr_widths: bit mask of src addr widths the device supports |
593 | * @dst_addr_widths: bit mask of dst addr widths the device supports | |
594 | * @directions: bit mask of slave direction the device supports since | |
595 | * the enum dma_transfer_direction is not defined as bits for | |
596 | * each type of direction, the dma controller should fill (1 << | |
597 | * <TYPE>) and same should be checked by controller as well | |
598 | * @residue_granularity: granularity of the transfer residue reported | |
599 | * by tx_status | |
fe4ada2d RD |
600 | * @device_alloc_chan_resources: allocate resources and return the |
601 | * number of allocated descriptors | |
602 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
603 | * @device_prep_dma_memcpy: prepares a memcpy operation |
604 | * @device_prep_dma_xor: prepares a xor operation | |
099f53cb | 605 | * @device_prep_dma_xor_val: prepares a xor validation operation |
b2f46fd8 DW |
606 | * @device_prep_dma_pq: prepares a pq operation |
607 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
7405f74b | 608 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
dc0ee643 | 609 | * @device_prep_slave_sg: prepares a slave dma operation |
782bc950 SH |
610 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. |
611 | * The function takes a buffer of size buf_len. The callback function will | |
612 | * be called after period_len bytes have been transferred. | |
b14dab79 | 613 | * @device_prep_interleaved_dma: Transfer expression in a generic way. |
94a73e30 MR |
614 | * @device_config: Pushes a new configuration to a channel, return 0 or an error |
615 | * code | |
23a3ea2f MR |
616 | * @device_pause: Pauses any transfer happening on a channel. Returns |
617 | * 0 or an error code | |
618 | * @device_resume: Resumes any transfer on a channel previously | |
619 | * paused. Returns 0 or an error code | |
7fa0cf46 MR |
620 | * @device_terminate_all: Aborts all transfers on a channel. Returns 0 |
621 | * or an error code | |
07934481 LW |
622 | * @device_tx_status: poll for transaction completion, the optional |
623 | * txstate parameter can be supplied with a pointer to get a | |
25985edc | 624 | * struct with auxiliary transfer status information, otherwise the call |
07934481 | 625 | * will just return a simple status code |
7405f74b | 626 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
627 | */ |
628 | struct dma_device { | |
629 | ||
630 | unsigned int chancnt; | |
0f571515 | 631 | unsigned int privatecnt; |
c13c8260 CL |
632 | struct list_head channels; |
633 | struct list_head global_node; | |
7405f74b | 634 | dma_cap_mask_t cap_mask; |
b2f46fd8 DW |
635 | unsigned short max_xor; |
636 | unsigned short max_pq; | |
83544ae9 DW |
637 | u8 copy_align; |
638 | u8 xor_align; | |
639 | u8 pq_align; | |
b2f46fd8 | 640 | #define DMA_HAS_PQ_CONTINUE (1 << 15) |
c13c8260 | 641 | |
c13c8260 | 642 | int dev_id; |
7405f74b | 643 | struct device *dev; |
c13c8260 | 644 | |
cb8cea51 MR |
645 | u32 src_addr_widths; |
646 | u32 dst_addr_widths; | |
647 | u32 directions; | |
648 | enum dma_residue_granularity residue_granularity; | |
649 | ||
aa1e6f1a | 650 | int (*device_alloc_chan_resources)(struct dma_chan *chan); |
c13c8260 | 651 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
652 | |
653 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
ceacbdbf | 654 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, |
d4c56f97 | 655 | size_t len, unsigned long flags); |
7405f74b | 656 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
ceacbdbf | 657 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, |
d4c56f97 | 658 | unsigned int src_cnt, size_t len, unsigned long flags); |
099f53cb | 659 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( |
0036731c | 660 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
ad283ea4 | 661 | size_t len, enum sum_check_flags *result, unsigned long flags); |
b2f46fd8 DW |
662 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( |
663 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
664 | unsigned int src_cnt, const unsigned char *scf, | |
665 | size_t len, unsigned long flags); | |
666 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
667 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
668 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
669 | enum sum_check_flags *pqres, unsigned long flags); | |
7405f74b | 670 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 671 | struct dma_chan *chan, unsigned long flags); |
a86ee03c IS |
672 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( |
673 | struct dma_chan *chan, | |
674 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
675 | struct scatterlist *src_sg, unsigned int src_nents, | |
676 | unsigned long flags); | |
7405f74b | 677 | |
dc0ee643 HS |
678 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
679 | struct dma_chan *chan, struct scatterlist *sgl, | |
49920bc6 | 680 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 681 | unsigned long flags, void *context); |
782bc950 SH |
682 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( |
683 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
185ecb5f | 684 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 685 | unsigned long flags); |
b14dab79 JB |
686 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( |
687 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
688 | unsigned long flags); | |
94a73e30 MR |
689 | |
690 | int (*device_config)(struct dma_chan *chan, | |
691 | struct dma_slave_config *config); | |
23a3ea2f MR |
692 | int (*device_pause)(struct dma_chan *chan); |
693 | int (*device_resume)(struct dma_chan *chan); | |
7fa0cf46 | 694 | int (*device_terminate_all)(struct dma_chan *chan); |
dc0ee643 | 695 | |
07934481 LW |
696 | enum dma_status (*device_tx_status)(struct dma_chan *chan, |
697 | dma_cookie_t cookie, | |
698 | struct dma_tx_state *txstate); | |
7405f74b | 699 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
700 | }; |
701 | ||
6e3ecaf0 SH |
702 | static inline int dmaengine_slave_config(struct dma_chan *chan, |
703 | struct dma_slave_config *config) | |
704 | { | |
94a73e30 MR |
705 | if (chan->device->device_config) |
706 | return chan->device->device_config(chan, config); | |
707 | ||
2c44ad91 | 708 | return -ENOSYS; |
6e3ecaf0 SH |
709 | } |
710 | ||
61cc13a5 AS |
711 | static inline bool is_slave_direction(enum dma_transfer_direction direction) |
712 | { | |
713 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
714 | } | |
715 | ||
90b44f8f | 716 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( |
922ee08b | 717 | struct dma_chan *chan, dma_addr_t buf, size_t len, |
49920bc6 | 718 | enum dma_transfer_direction dir, unsigned long flags) |
90b44f8f VK |
719 | { |
720 | struct scatterlist sg; | |
922ee08b KM |
721 | sg_init_table(&sg, 1); |
722 | sg_dma_address(&sg) = buf; | |
723 | sg_dma_len(&sg) = len; | |
90b44f8f | 724 | |
185ecb5f AB |
725 | return chan->device->device_prep_slave_sg(chan, &sg, 1, |
726 | dir, flags, NULL); | |
90b44f8f VK |
727 | } |
728 | ||
16052827 AB |
729 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( |
730 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
731 | enum dma_transfer_direction dir, unsigned long flags) | |
732 | { | |
733 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
185ecb5f | 734 | dir, flags, NULL); |
16052827 AB |
735 | } |
736 | ||
e42d98eb AB |
737 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE |
738 | struct rio_dma_ext; | |
739 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
740 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
741 | enum dma_transfer_direction dir, unsigned long flags, | |
742 | struct rio_dma_ext *rio_ext) | |
743 | { | |
744 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
745 | dir, flags, rio_ext); | |
746 | } | |
747 | #endif | |
748 | ||
16052827 AB |
749 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( |
750 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
e7736cde PU |
751 | size_t period_len, enum dma_transfer_direction dir, |
752 | unsigned long flags) | |
16052827 AB |
753 | { |
754 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, | |
31c1e5a1 | 755 | period_len, dir, flags); |
a14acb4a BS |
756 | } |
757 | ||
758 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
759 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
760 | unsigned long flags) | |
761 | { | |
762 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | |
90b44f8f VK |
763 | } |
764 | ||
b65612a8 VK |
765 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( |
766 | struct dma_chan *chan, | |
767 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
768 | struct scatterlist *src_sg, unsigned int src_nents, | |
769 | unsigned long flags) | |
770 | { | |
771 | return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, | |
772 | src_sg, src_nents, flags); | |
773 | } | |
774 | ||
6e3ecaf0 SH |
775 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
776 | { | |
7fa0cf46 MR |
777 | if (chan->device->device_terminate_all) |
778 | return chan->device->device_terminate_all(chan); | |
779 | ||
2c44ad91 | 780 | return -ENOSYS; |
6e3ecaf0 SH |
781 | } |
782 | ||
783 | static inline int dmaengine_pause(struct dma_chan *chan) | |
784 | { | |
23a3ea2f MR |
785 | if (chan->device->device_pause) |
786 | return chan->device->device_pause(chan); | |
787 | ||
2c44ad91 | 788 | return -ENOSYS; |
6e3ecaf0 SH |
789 | } |
790 | ||
791 | static inline int dmaengine_resume(struct dma_chan *chan) | |
792 | { | |
23a3ea2f MR |
793 | if (chan->device->device_resume) |
794 | return chan->device->device_resume(chan); | |
795 | ||
2c44ad91 | 796 | return -ENOSYS; |
6e3ecaf0 SH |
797 | } |
798 | ||
3052cc2c LPC |
799 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, |
800 | dma_cookie_t cookie, struct dma_tx_state *state) | |
801 | { | |
802 | return chan->device->device_tx_status(chan, cookie, state); | |
803 | } | |
804 | ||
98d530fe | 805 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
6e3ecaf0 SH |
806 | { |
807 | return desc->tx_submit(desc); | |
808 | } | |
809 | ||
83544ae9 DW |
810 | static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) |
811 | { | |
812 | size_t mask; | |
813 | ||
814 | if (!align) | |
815 | return true; | |
816 | mask = (1 << align) - 1; | |
817 | if (mask & (off1 | off2 | len)) | |
818 | return false; | |
819 | return true; | |
820 | } | |
821 | ||
822 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
823 | size_t off2, size_t len) | |
824 | { | |
825 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
826 | } | |
827 | ||
828 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
829 | size_t off2, size_t len) | |
830 | { | |
831 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
832 | } | |
833 | ||
834 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
835 | size_t off2, size_t len) | |
836 | { | |
837 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
838 | } | |
839 | ||
b2f46fd8 DW |
840 | static inline void |
841 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
842 | { | |
843 | dma->max_pq = maxpq; | |
844 | if (has_pq_continue) | |
845 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
846 | } | |
847 | ||
848 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
849 | { | |
850 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
851 | } | |
852 | ||
853 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
854 | { | |
855 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
856 | ||
857 | return (flags & mask) == mask; | |
858 | } | |
859 | ||
860 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
861 | { | |
862 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
863 | } | |
864 | ||
d3f3cf85 | 865 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) |
b2f46fd8 DW |
866 | { |
867 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
868 | } | |
869 | ||
870 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
871 | * @dma - dma device with PQ capability | |
872 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
873 | * | |
874 | * When an engine does not support native continuation we need 3 extra | |
875 | * source slots to reuse P and Q with the following coefficients: | |
876 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
877 | * 2/ {01} * Q : use Q to continue Q' calculation | |
878 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
879 | * | |
880 | * In the case where P is disabled we only need 1 extra source: | |
881 | * 1/ {01} * Q : use Q to continue Q' calculation | |
882 | */ | |
883 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
884 | { | |
885 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
886 | return dma_dev_to_maxpq(dma); | |
887 | else if (dmaf_p_disabled_continue(flags)) | |
888 | return dma_dev_to_maxpq(dma) - 1; | |
889 | else if (dmaf_continue(flags)) | |
890 | return dma_dev_to_maxpq(dma) - 3; | |
891 | BUG(); | |
892 | } | |
893 | ||
c13c8260 CL |
894 | /* --- public DMA engine API --- */ |
895 | ||
649274d9 | 896 | #ifdef CONFIG_DMA_ENGINE |
209b84a8 DW |
897 | void dmaengine_get(void); |
898 | void dmaengine_put(void); | |
649274d9 DW |
899 | #else |
900 | static inline void dmaengine_get(void) | |
901 | { | |
902 | } | |
903 | static inline void dmaengine_put(void) | |
904 | { | |
905 | } | |
906 | #endif | |
907 | ||
729b5d1b DW |
908 | #ifdef CONFIG_ASYNC_TX_DMA |
909 | #define async_dmaengine_get() dmaengine_get() | |
910 | #define async_dmaengine_put() dmaengine_put() | |
5fc6d897 | 911 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH |
138f4c35 DW |
912 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) |
913 | #else | |
729b5d1b | 914 | #define async_dma_find_channel(type) dma_find_channel(type) |
5fc6d897 | 915 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ |
729b5d1b DW |
916 | #else |
917 | static inline void async_dmaengine_get(void) | |
918 | { | |
919 | } | |
920 | static inline void async_dmaengine_put(void) | |
921 | { | |
922 | } | |
923 | static inline struct dma_chan * | |
924 | async_dma_find_channel(enum dma_transaction_type type) | |
925 | { | |
926 | return NULL; | |
927 | } | |
138f4c35 | 928 | #endif /* CONFIG_ASYNC_TX_DMA */ |
7405f74b | 929 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, |
7bced397 | 930 | struct dma_chan *chan); |
c13c8260 | 931 | |
0839875e | 932 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 933 | { |
636bdeaa DW |
934 | tx->flags |= DMA_CTRL_ACK; |
935 | } | |
936 | ||
ef560682 GL |
937 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) |
938 | { | |
939 | tx->flags &= ~DMA_CTRL_ACK; | |
940 | } | |
941 | ||
0839875e | 942 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 943 | { |
0839875e | 944 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
945 | } |
946 | ||
7405f74b DW |
947 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
948 | static inline void | |
949 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 950 | { |
7405f74b DW |
951 | set_bit(tx_type, dstp->bits); |
952 | } | |
c13c8260 | 953 | |
0f571515 AN |
954 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) |
955 | static inline void | |
956 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
957 | { | |
958 | clear_bit(tx_type, dstp->bits); | |
959 | } | |
960 | ||
33df8ca0 DW |
961 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
962 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
963 | { | |
964 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
965 | } | |
966 | ||
7405f74b DW |
967 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
968 | static inline int | |
969 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
970 | { | |
971 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
972 | } |
973 | ||
7405f74b | 974 | #define for_each_dma_cap_mask(cap, mask) \ |
e5a087fd | 975 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) |
7405f74b | 976 | |
c13c8260 | 977 | /** |
7405f74b | 978 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 979 | * @chan: target DMA channel |
c13c8260 CL |
980 | * |
981 | * This allows drivers to push copies to HW in batches, | |
982 | * reducing MMIO writes where possible. | |
983 | */ | |
7405f74b | 984 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 985 | { |
ec8670f1 | 986 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
987 | } |
988 | ||
989 | /** | |
7405f74b | 990 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
991 | * @chan: DMA channel |
992 | * @cookie: transaction identifier to check status of | |
993 | * @last: returns last completed cookie, can be NULL | |
994 | * @used: returns last issued cookie, can be NULL | |
995 | * | |
996 | * If @last and @used are passed in, upon return they reflect the driver | |
997 | * internal state and can be used with dma_async_is_complete() to check | |
998 | * the status of multiple cookies without re-checking hardware state. | |
999 | */ | |
7405f74b | 1000 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
1001 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
1002 | { | |
07934481 LW |
1003 | struct dma_tx_state state; |
1004 | enum dma_status status; | |
1005 | ||
1006 | status = chan->device->device_tx_status(chan, cookie, &state); | |
1007 | if (last) | |
1008 | *last = state.last; | |
1009 | if (used) | |
1010 | *used = state.used; | |
1011 | return status; | |
c13c8260 CL |
1012 | } |
1013 | ||
1014 | /** | |
1015 | * dma_async_is_complete - test a cookie against chan state | |
1016 | * @cookie: transaction identifier to test status of | |
1017 | * @last_complete: last know completed transaction | |
1018 | * @last_used: last cookie value handed out | |
1019 | * | |
e239345f | 1020 | * dma_async_is_complete() is used in dma_async_is_tx_complete() |
8a5703f8 | 1021 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
1022 | */ |
1023 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
1024 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
1025 | { | |
1026 | if (last_complete <= last_used) { | |
1027 | if ((cookie <= last_complete) || (cookie > last_used)) | |
adfedd9a | 1028 | return DMA_COMPLETE; |
c13c8260 CL |
1029 | } else { |
1030 | if ((cookie <= last_complete) && (cookie > last_used)) | |
adfedd9a | 1031 | return DMA_COMPLETE; |
c13c8260 CL |
1032 | } |
1033 | return DMA_IN_PROGRESS; | |
1034 | } | |
1035 | ||
bca34692 DW |
1036 | static inline void |
1037 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
1038 | { | |
1039 | if (st) { | |
1040 | st->last = last; | |
1041 | st->used = used; | |
1042 | st->residue = residue; | |
1043 | } | |
1044 | } | |
1045 | ||
07f2211e | 1046 | #ifdef CONFIG_DMA_ENGINE |
4a43f394 JM |
1047 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
1048 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | |
07f2211e | 1049 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
c50331e8 | 1050 | void dma_issue_pending_all(void); |
a53e28da LPC |
1051 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
1052 | dma_filter_fn fn, void *fn_param); | |
0ad7c000 SW |
1053 | struct dma_chan *dma_request_slave_channel_reason(struct device *dev, |
1054 | const char *name); | |
bef29ec5 | 1055 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
8f33d527 | 1056 | void dma_release_channel(struct dma_chan *chan); |
fdb8df99 | 1057 | int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); |
07f2211e | 1058 | #else |
4a43f394 JM |
1059 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) |
1060 | { | |
1061 | return NULL; | |
1062 | } | |
1063 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | |
1064 | { | |
adfedd9a | 1065 | return DMA_COMPLETE; |
4a43f394 | 1066 | } |
07f2211e DW |
1067 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
1068 | { | |
adfedd9a | 1069 | return DMA_COMPLETE; |
07f2211e | 1070 | } |
c50331e8 DW |
1071 | static inline void dma_issue_pending_all(void) |
1072 | { | |
8f33d527 | 1073 | } |
a53e28da | 1074 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
8f33d527 GL |
1075 | dma_filter_fn fn, void *fn_param) |
1076 | { | |
1077 | return NULL; | |
1078 | } | |
0ad7c000 SW |
1079 | static inline struct dma_chan *dma_request_slave_channel_reason( |
1080 | struct device *dev, const char *name) | |
1081 | { | |
1082 | return ERR_PTR(-ENODEV); | |
1083 | } | |
9a6cecc8 | 1084 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, |
bef29ec5 | 1085 | const char *name) |
9a6cecc8 | 1086 | { |
d18d5f59 | 1087 | return NULL; |
9a6cecc8 | 1088 | } |
8f33d527 GL |
1089 | static inline void dma_release_channel(struct dma_chan *chan) |
1090 | { | |
c50331e8 | 1091 | } |
fdb8df99 LP |
1092 | static inline int dma_get_slave_caps(struct dma_chan *chan, |
1093 | struct dma_slave_caps *caps) | |
1094 | { | |
1095 | return -ENXIO; | |
1096 | } | |
07f2211e | 1097 | #endif |
c13c8260 CL |
1098 | |
1099 | /* --- DMA device --- */ | |
1100 | ||
1101 | int dma_async_device_register(struct dma_device *device); | |
1102 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 1103 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
7bb587f4 | 1104 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); |
8010dad5 | 1105 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); |
59b5ec21 | 1106 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
864ef69b MP |
1107 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
1108 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) | |
1109 | ||
1110 | static inline struct dma_chan | |
a53e28da LPC |
1111 | *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, |
1112 | dma_filter_fn fn, void *fn_param, | |
1113 | struct device *dev, char *name) | |
864ef69b MP |
1114 | { |
1115 | struct dma_chan *chan; | |
1116 | ||
1117 | chan = dma_request_slave_channel(dev, name); | |
1118 | if (chan) | |
1119 | return chan; | |
1120 | ||
1121 | return __dma_request_channel(mask, fn, fn_param); | |
1122 | } | |
c13c8260 | 1123 | #endif /* DMAENGINE_H */ |