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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/cpumask.h> | |
503e5763 | 17 | #include <linux/gfp.h> |
75ffc007 | 18 | #include <linux/irqhandler.h> |
908dcecd | 19 | #include <linux/irqreturn.h> |
dd3a1db9 | 20 | #include <linux/irqnr.h> |
77904fd6 | 21 | #include <linux/errno.h> |
503e5763 | 22 | #include <linux/topology.h> |
3aa551c9 | 23 | #include <linux/wait.h> |
332fd7c4 | 24 | #include <linux/io.h> |
707188f5 | 25 | #include <linux/slab.h> |
1da177e4 LT |
26 | |
27 | #include <asm/irq.h> | |
28 | #include <asm/ptrace.h> | |
7d12e780 | 29 | #include <asm/irq_regs.h> |
1da177e4 | 30 | |
ab7798ff | 31 | struct seq_file; |
ec53cf23 | 32 | struct module; |
515085ef | 33 | struct msi_msg; |
1b7047ed | 34 | enum irqchip_irq_state; |
57a58a94 | 35 | |
1da177e4 LT |
36 | /* |
37 | * IRQ line status. | |
6e213616 | 38 | * |
5d4d8fc9 TG |
39 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
40 | * | |
41 | * IRQ_TYPE_NONE - default, unspecified type | |
42 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
43 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
44 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
45 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
46 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
47 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
48 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
3fca40c7 BH |
49 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
50 | * to setup the HW to a sane default (used | |
51 | * by irqdomain map() callbacks to synchronize | |
52 | * the HW state and SW flags for a newly | |
53 | * allocated descriptor). | |
54 | * | |
5d4d8fc9 TG |
55 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
56 | * | |
57 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
58 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
59 | * updated in the code when the above trigger | |
0911f124 | 60 | * bits are modified via irq_set_irq_type() |
5d4d8fc9 TG |
61 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
62 | * it from affinity setting | |
63 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
64 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
65 | * request_irq() | |
7f1b1244 | 66 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
5d4d8fc9 TG |
67 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
68 | * request/setup_irq() | |
69 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
70 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
92068d17 | 71 | * IRQ_NESTED_THREAD - Interrupt nests into another thread |
31d9d9b6 | 72 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
b39898cd TG |
73 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
74 | * it from the spurious interrupt detection | |
75 | * mechanism and from core side polling. | |
e9849777 | 76 | * IRQ_DISABLE_UNLAZY - Disable lazy irq disable |
1da177e4 | 77 | */ |
5d4d8fc9 TG |
78 | enum { |
79 | IRQ_TYPE_NONE = 0x00000000, | |
80 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
81 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
82 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
83 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
84 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
85 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
86 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
3fca40c7 | 87 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
5d4d8fc9 TG |
88 | |
89 | IRQ_TYPE_PROBE = 0x00000010, | |
90 | ||
91 | IRQ_LEVEL = (1 << 8), | |
92 | IRQ_PER_CPU = (1 << 9), | |
93 | IRQ_NOPROBE = (1 << 10), | |
94 | IRQ_NOREQUEST = (1 << 11), | |
95 | IRQ_NOAUTOEN = (1 << 12), | |
96 | IRQ_NO_BALANCING = (1 << 13), | |
97 | IRQ_MOVE_PCNTXT = (1 << 14), | |
98 | IRQ_NESTED_THREAD = (1 << 15), | |
7f1b1244 | 99 | IRQ_NOTHREAD = (1 << 16), |
31d9d9b6 | 100 | IRQ_PER_CPU_DEVID = (1 << 17), |
b39898cd | 101 | IRQ_IS_POLLED = (1 << 18), |
e9849777 | 102 | IRQ_DISABLE_UNLAZY = (1 << 19), |
5d4d8fc9 | 103 | }; |
950f4427 | 104 | |
44247184 TG |
105 | #define IRQF_MODIFY_MASK \ |
106 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 107 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
b39898cd | 108 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
e9849777 | 109 | IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY) |
44247184 | 110 | |
8f53f924 TG |
111 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
112 | ||
3b8249e7 TG |
113 | /* |
114 | * Return value for chip->irq_set_affinity() | |
115 | * | |
9df872fa JL |
116 | * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity |
117 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity | |
2cb62547 JL |
118 | * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to |
119 | * support stacked irqchips, which indicates skipping | |
120 | * all descendent irqchips. | |
3b8249e7 TG |
121 | */ |
122 | enum { | |
123 | IRQ_SET_MASK_OK = 0, | |
124 | IRQ_SET_MASK_OK_NOCOPY, | |
2cb62547 | 125 | IRQ_SET_MASK_OK_DONE, |
3b8249e7 TG |
126 | }; |
127 | ||
5b912c10 | 128 | struct msi_desc; |
08a543ad | 129 | struct irq_domain; |
6a6de9ef | 130 | |
ff7dcd44 | 131 | /** |
0d0b4c86 JL |
132 | * struct irq_common_data - per irq data shared by all irqchips |
133 | * @state_use_accessors: status information for irq chip functions. | |
134 | * Use accessor functions to deal with it | |
449e9cae | 135 | * @node: node index useful for balancing |
af7080e0 | 136 | * @handler_data: per-IRQ data for the irq_chip methods |
955bfe59 QY |
137 | * @affinity: IRQ affinity on SMP. If this is an IPI |
138 | * related irq, then this is the mask of the | |
139 | * CPUs to which an IPI can be sent. | |
b237721c | 140 | * @msi_desc: MSI descriptor |
f256c9a0 | 141 | * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. |
0d0b4c86 JL |
142 | */ |
143 | struct irq_common_data { | |
b354286e | 144 | unsigned int __private state_use_accessors; |
449e9cae JL |
145 | #ifdef CONFIG_NUMA |
146 | unsigned int node; | |
147 | #endif | |
af7080e0 | 148 | void *handler_data; |
b237721c | 149 | struct msi_desc *msi_desc; |
9df872fa | 150 | cpumask_var_t affinity; |
f256c9a0 QY |
151 | #ifdef CONFIG_GENERIC_IRQ_IPI |
152 | unsigned int ipi_offset; | |
153 | #endif | |
0d0b4c86 JL |
154 | }; |
155 | ||
156 | /** | |
157 | * struct irq_data - per irq chip data passed down to chip functions | |
966dc736 | 158 | * @mask: precomputed bitmask for accessing the chip registers |
ff7dcd44 | 159 | * @irq: interrupt number |
08a543ad | 160 | * @hwirq: hardware interrupt number, local to the interrupt domain |
0d0b4c86 | 161 | * @common: point to data shared by all irqchips |
ff7dcd44 | 162 | * @chip: low level interrupt hardware access |
08a543ad GL |
163 | * @domain: Interrupt translation domain; responsible for mapping |
164 | * between hwirq number and linux irq number. | |
f8264e34 JL |
165 | * @parent_data: pointer to parent struct irq_data to support hierarchy |
166 | * irq_domain | |
ff7dcd44 TG |
167 | * @chip_data: platform-specific per-chip private data for the chip |
168 | * methods, to allow shared chip implementations | |
ff7dcd44 TG |
169 | */ |
170 | struct irq_data { | |
966dc736 | 171 | u32 mask; |
ff7dcd44 | 172 | unsigned int irq; |
08a543ad | 173 | unsigned long hwirq; |
0d0b4c86 | 174 | struct irq_common_data *common; |
ff7dcd44 | 175 | struct irq_chip *chip; |
08a543ad | 176 | struct irq_domain *domain; |
f8264e34 JL |
177 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
178 | struct irq_data *parent_data; | |
179 | #endif | |
ff7dcd44 | 180 | void *chip_data; |
ff7dcd44 TG |
181 | }; |
182 | ||
f230b6d5 | 183 | /* |
0d0b4c86 | 184 | * Bit masks for irq_common_data.state_use_accessors |
f230b6d5 | 185 | * |
876dbd4c | 186 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 187 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
08d85f3e | 188 | * IRQD_ACTIVATED - Interrupt has already been activated |
a005677b TG |
189 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
190 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 191 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 192 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
193 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
194 | * from suspend | |
e1ef8241 TG |
195 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
196 | * context | |
32f4125e TG |
197 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
198 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
199 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
b76f1674 | 200 | * IRQD_WAKEUP_ARMED - Wakeup mode armed |
fc569712 | 201 | * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU |
9c255583 | 202 | * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel |
1bb04016 | 203 | * IRQD_IRQ_STARTED - Startup state of the interrupt |
f230b6d5 TG |
204 | */ |
205 | enum { | |
876dbd4c | 206 | IRQD_TRIGGER_MASK = 0xf, |
a005677b | 207 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
08d85f3e | 208 | IRQD_ACTIVATED = (1 << 9), |
a005677b TG |
209 | IRQD_NO_BALANCING = (1 << 10), |
210 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 211 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 212 | IRQD_LEVEL = (1 << 13), |
7f94226f | 213 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 214 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 215 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
216 | IRQD_IRQ_MASKED = (1 << 17), |
217 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
b76f1674 | 218 | IRQD_WAKEUP_ARMED = (1 << 19), |
fc569712 | 219 | IRQD_FORWARDED_TO_VCPU = (1 << 20), |
9c255583 | 220 | IRQD_AFFINITY_MANAGED = (1 << 21), |
201d7f47 | 221 | IRQD_IRQ_STARTED = (1 << 22), |
f230b6d5 TG |
222 | }; |
223 | ||
b354286e | 224 | #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) |
0d0b4c86 | 225 | |
f230b6d5 TG |
226 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
227 | { | |
0d0b4c86 | 228 | return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; |
f230b6d5 TG |
229 | } |
230 | ||
a005677b TG |
231 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
232 | { | |
0d0b4c86 | 233 | return __irqd_to_state(d) & IRQD_PER_CPU; |
a005677b TG |
234 | } |
235 | ||
236 | static inline bool irqd_can_balance(struct irq_data *d) | |
237 | { | |
0d0b4c86 | 238 | return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
a005677b TG |
239 | } |
240 | ||
2bdd1055 TG |
241 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
242 | { | |
0d0b4c86 | 243 | return __irqd_to_state(d) & IRQD_AFFINITY_SET; |
2bdd1055 TG |
244 | } |
245 | ||
ee38c04b TG |
246 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
247 | { | |
0d0b4c86 | 248 | __irqd_to_state(d) |= IRQD_AFFINITY_SET; |
ee38c04b TG |
249 | } |
250 | ||
876dbd4c TG |
251 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
252 | { | |
0d0b4c86 | 253 | return __irqd_to_state(d) & IRQD_TRIGGER_MASK; |
876dbd4c TG |
254 | } |
255 | ||
256 | /* | |
257 | * Must only be called inside irq_chip.irq_set_type() functions. | |
258 | */ | |
259 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
260 | { | |
0d0b4c86 JL |
261 | __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; |
262 | __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; | |
876dbd4c TG |
263 | } |
264 | ||
265 | static inline bool irqd_is_level_type(struct irq_data *d) | |
266 | { | |
0d0b4c86 | 267 | return __irqd_to_state(d) & IRQD_LEVEL; |
876dbd4c TG |
268 | } |
269 | ||
7f94226f TG |
270 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
271 | { | |
0d0b4c86 | 272 | return __irqd_to_state(d) & IRQD_WAKEUP_STATE; |
7f94226f TG |
273 | } |
274 | ||
e1ef8241 TG |
275 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
276 | { | |
0d0b4c86 | 277 | return __irqd_to_state(d) & IRQD_MOVE_PCNTXT; |
e1ef8241 TG |
278 | } |
279 | ||
801a0e9a TG |
280 | static inline bool irqd_irq_disabled(struct irq_data *d) |
281 | { | |
0d0b4c86 | 282 | return __irqd_to_state(d) & IRQD_IRQ_DISABLED; |
801a0e9a TG |
283 | } |
284 | ||
32f4125e TG |
285 | static inline bool irqd_irq_masked(struct irq_data *d) |
286 | { | |
0d0b4c86 | 287 | return __irqd_to_state(d) & IRQD_IRQ_MASKED; |
32f4125e TG |
288 | } |
289 | ||
290 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
291 | { | |
0d0b4c86 | 292 | return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; |
32f4125e TG |
293 | } |
294 | ||
b76f1674 TG |
295 | static inline bool irqd_is_wakeup_armed(struct irq_data *d) |
296 | { | |
0d0b4c86 | 297 | return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; |
b76f1674 TG |
298 | } |
299 | ||
fc569712 TG |
300 | static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) |
301 | { | |
302 | return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; | |
303 | } | |
304 | ||
305 | static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) | |
306 | { | |
307 | __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; | |
308 | } | |
309 | ||
310 | static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) | |
311 | { | |
312 | __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; | |
313 | } | |
b76f1674 | 314 | |
9c255583 TG |
315 | static inline bool irqd_affinity_is_managed(struct irq_data *d) |
316 | { | |
317 | return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; | |
318 | } | |
319 | ||
08d85f3e MZ |
320 | static inline bool irqd_is_activated(struct irq_data *d) |
321 | { | |
322 | return __irqd_to_state(d) & IRQD_ACTIVATED; | |
323 | } | |
324 | ||
325 | static inline void irqd_set_activated(struct irq_data *d) | |
326 | { | |
327 | __irqd_to_state(d) |= IRQD_ACTIVATED; | |
328 | } | |
329 | ||
330 | static inline void irqd_clr_activated(struct irq_data *d) | |
331 | { | |
332 | __irqd_to_state(d) &= ~IRQD_ACTIVATED; | |
333 | } | |
334 | ||
201d7f47 TG |
335 | static inline bool irqd_is_started(struct irq_data *d) |
336 | { | |
337 | return __irqd_to_state(d) & IRQD_IRQ_STARTED; | |
338 | } | |
339 | ||
b354286e BF |
340 | #undef __irqd_to_state |
341 | ||
a699e4e4 GL |
342 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
343 | { | |
344 | return d->hwirq; | |
345 | } | |
346 | ||
8fee5c36 | 347 | /** |
6a6de9ef | 348 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 | 349 | * |
be45beb2 | 350 | * @parent_device: pointer to parent device for irqchip |
8fee5c36 | 351 | * @name: name for /proc/interrupts |
f8822657 TG |
352 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
353 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
354 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
355 | * @irq_disable: disable the interrupt | |
356 | * @irq_ack: start of a new interrupt | |
357 | * @irq_mask: mask an interrupt source | |
358 | * @irq_mask_ack: ack and mask an interrupt source | |
359 | * @irq_unmask: unmask an interrupt source | |
360 | * @irq_eoi: end of interrupt | |
361 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
362 | * @irq_retrigger: resend an IRQ to the CPU | |
363 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
364 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
365 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
366 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
367 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
368 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
be9b22b6 BN |
369 | * @irq_suspend: function called from core code on suspend once per |
370 | * chip, when one or more interrupts are installed | |
371 | * @irq_resume: function called from core code on resume once per chip, | |
372 | * when one ore more interrupts are installed | |
cfefd21e | 373 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
d0051816 | 374 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
ab7798ff | 375 | * @irq_print_chip: optional to print special chip info in show_interrupts |
c1bacbae TG |
376 | * @irq_request_resources: optional to request resources before calling |
377 | * any other callback related to this irq | |
378 | * @irq_release_resources: optional to release resources acquired with | |
379 | * irq_request_resources | |
515085ef | 380 | * @irq_compose_msi_msg: optional to compose message content for MSI |
9dde55b7 | 381 | * @irq_write_msi_msg: optional to write message content for MSI |
1b7047ed MZ |
382 | * @irq_get_irqchip_state: return the internal state of an interrupt |
383 | * @irq_set_irqchip_state: set the internal state of a interrupt | |
0a4377de | 384 | * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine |
34dc1ae1 QY |
385 | * @ipi_send_single: send a single IPI to destination cpus |
386 | * @ipi_send_mask: send an IPI to destination cpus in cpumask | |
2bff17ad | 387 | * @flags: chip specific flags |
1da177e4 | 388 | */ |
6a6de9ef | 389 | struct irq_chip { |
be45beb2 | 390 | struct device *parent_device; |
6a6de9ef | 391 | const char *name; |
f8822657 TG |
392 | unsigned int (*irq_startup)(struct irq_data *data); |
393 | void (*irq_shutdown)(struct irq_data *data); | |
394 | void (*irq_enable)(struct irq_data *data); | |
395 | void (*irq_disable)(struct irq_data *data); | |
396 | ||
397 | void (*irq_ack)(struct irq_data *data); | |
398 | void (*irq_mask)(struct irq_data *data); | |
399 | void (*irq_mask_ack)(struct irq_data *data); | |
400 | void (*irq_unmask)(struct irq_data *data); | |
401 | void (*irq_eoi)(struct irq_data *data); | |
402 | ||
403 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
404 | int (*irq_retrigger)(struct irq_data *data); | |
405 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
406 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
407 | ||
408 | void (*irq_bus_lock)(struct irq_data *data); | |
409 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
410 | ||
0fdb4b25 DD |
411 | void (*irq_cpu_online)(struct irq_data *data); |
412 | void (*irq_cpu_offline)(struct irq_data *data); | |
413 | ||
cfefd21e TG |
414 | void (*irq_suspend)(struct irq_data *data); |
415 | void (*irq_resume)(struct irq_data *data); | |
416 | void (*irq_pm_shutdown)(struct irq_data *data); | |
417 | ||
d0051816 TG |
418 | void (*irq_calc_mask)(struct irq_data *data); |
419 | ||
ab7798ff | 420 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
c1bacbae TG |
421 | int (*irq_request_resources)(struct irq_data *data); |
422 | void (*irq_release_resources)(struct irq_data *data); | |
ab7798ff | 423 | |
515085ef | 424 | void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
9dde55b7 | 425 | void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); |
515085ef | 426 | |
1b7047ed MZ |
427 | int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); |
428 | int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); | |
429 | ||
0a4377de JL |
430 | int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); |
431 | ||
34dc1ae1 QY |
432 | void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); |
433 | void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); | |
434 | ||
2bff17ad | 435 | unsigned long flags; |
1da177e4 LT |
436 | }; |
437 | ||
d4d5e089 TG |
438 | /* |
439 | * irq_chip specific flags | |
440 | * | |
77694b40 TG |
441 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
442 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 443 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
444 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
445 | * when irq enabled | |
60f96b41 | 446 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
4f6e4f71 | 447 | * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask |
328a4978 | 448 | * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode |
d4d5e089 TG |
449 | */ |
450 | enum { | |
451 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 452 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 453 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 454 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
60f96b41 | 455 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
dc9b229a | 456 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
328a4978 | 457 | IRQCHIP_EOI_THREADED = (1 << 6), |
d4d5e089 TG |
458 | }; |
459 | ||
e144710b | 460 | #include <linux/irqdesc.h> |
0b8f1efa | 461 | |
34ffdb72 IM |
462 | /* |
463 | * Pick up the arch-dependent methods: | |
464 | */ | |
465 | #include <asm/hw_irq.h> | |
1da177e4 | 466 | |
b683de2b TG |
467 | #ifndef NR_IRQS_LEGACY |
468 | # define NR_IRQS_LEGACY 0 | |
469 | #endif | |
470 | ||
1318a481 TG |
471 | #ifndef ARCH_IRQ_INIT_FLAGS |
472 | # define ARCH_IRQ_INIT_FLAGS 0 | |
473 | #endif | |
474 | ||
c1594b77 | 475 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 476 | |
e144710b | 477 | struct irqaction; |
06fcb0c6 | 478 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 479 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
31d9d9b6 MZ |
480 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
481 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); | |
1da177e4 | 482 | |
0fdb4b25 DD |
483 | extern void irq_cpu_online(void); |
484 | extern void irq_cpu_offline(void); | |
01f8fa4f TG |
485 | extern int irq_set_affinity_locked(struct irq_data *data, |
486 | const struct cpumask *cpumask, bool force); | |
0a4377de | 487 | extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); |
0fdb4b25 | 488 | |
f1e0bb0a YY |
489 | extern void irq_migrate_all_off_this_cpu(void); |
490 | ||
3a3856d0 | 491 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
492 | void irq_move_irq(struct irq_data *data); |
493 | void irq_move_masked_irq(struct irq_data *data); | |
cdd16365 | 494 | bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear); |
e144710b | 495 | #else |
a439520f TG |
496 | static inline void irq_move_irq(struct irq_data *data) { } |
497 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
cdd16365 TG |
498 | static inline bool irq_fixup_move_pending(struct irq_desc *desc, bool fclear) |
499 | { | |
500 | return false; | |
501 | } | |
e144710b | 502 | #endif |
54d5d424 | 503 | |
1da177e4 | 504 | extern int no_irq_affinity; |
1da177e4 | 505 | |
293a7a0a TG |
506 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
507 | int irq_set_parent(int irq, int parent_irq); | |
508 | #else | |
509 | static inline int irq_set_parent(int irq, int parent_irq) | |
510 | { | |
511 | return 0; | |
512 | } | |
513 | #endif | |
514 | ||
6a6de9ef TG |
515 | /* |
516 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 517 | * callable via desc->handle_irq() |
6a6de9ef | 518 | */ |
bd0b9ac4 TG |
519 | extern void handle_level_irq(struct irq_desc *desc); |
520 | extern void handle_fasteoi_irq(struct irq_desc *desc); | |
521 | extern void handle_edge_irq(struct irq_desc *desc); | |
522 | extern void handle_edge_eoi_irq(struct irq_desc *desc); | |
523 | extern void handle_simple_irq(struct irq_desc *desc); | |
edd14cfe | 524 | extern void handle_untracked_irq(struct irq_desc *desc); |
bd0b9ac4 TG |
525 | extern void handle_percpu_irq(struct irq_desc *desc); |
526 | extern void handle_percpu_devid_irq(struct irq_desc *desc); | |
527 | extern void handle_bad_irq(struct irq_desc *desc); | |
31b47cf7 | 528 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 529 | |
515085ef | 530 | extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); |
be45beb2 JH |
531 | extern int irq_chip_pm_get(struct irq_data *data); |
532 | extern int irq_chip_pm_put(struct irq_data *data); | |
85f08c17 | 533 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
3cfeffc2 SA |
534 | extern void irq_chip_enable_parent(struct irq_data *data); |
535 | extern void irq_chip_disable_parent(struct irq_data *data); | |
85f08c17 JL |
536 | extern void irq_chip_ack_parent(struct irq_data *data); |
537 | extern int irq_chip_retrigger_hierarchy(struct irq_data *data); | |
56e8abab YC |
538 | extern void irq_chip_mask_parent(struct irq_data *data); |
539 | extern void irq_chip_unmask_parent(struct irq_data *data); | |
540 | extern void irq_chip_eoi_parent(struct irq_data *data); | |
541 | extern int irq_chip_set_affinity_parent(struct irq_data *data, | |
542 | const struct cpumask *dest, | |
543 | bool force); | |
08b55e2a | 544 | extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); |
0a4377de JL |
545 | extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, |
546 | void *vcpu_info); | |
b7560de1 | 547 | extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); |
85f08c17 JL |
548 | #endif |
549 | ||
6a6de9ef | 550 | /* Handling of unhandled and spurious interrupts: */ |
0dcdbc97 | 551 | extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); |
1da177e4 | 552 | |
a4633adc | 553 | |
6a6de9ef TG |
554 | /* Enable/disable irq debugging output: */ |
555 | extern int noirqdebug_setup(char *str); | |
556 | ||
557 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
558 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
559 | ||
f8b5473f | 560 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 561 | extern struct irq_chip no_irq_chip; |
f8b5473f | 562 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 563 | |
145fc655 | 564 | extern void |
3836ca08 | 565 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
566 | irq_flow_handler_t handle, const char *name); |
567 | ||
3836ca08 TG |
568 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
569 | irq_flow_handler_t handle) | |
570 | { | |
571 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
572 | } | |
573 | ||
31d9d9b6 | 574 | extern int irq_set_percpu_devid(unsigned int irq); |
222df54f MZ |
575 | extern int irq_set_percpu_devid_partition(unsigned int irq, |
576 | const struct cpumask *affinity); | |
577 | extern int irq_get_percpu_devid_partition(unsigned int irq, | |
578 | struct cpumask *affinity); | |
31d9d9b6 | 579 | |
6a6de9ef | 580 | extern void |
3836ca08 | 581 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 582 | const char *name); |
1da177e4 | 583 | |
6a6de9ef | 584 | static inline void |
3836ca08 | 585 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 586 | { |
3836ca08 | 587 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
588 | } |
589 | ||
590 | /* | |
591 | * Set a highlevel chained flow handler for a given IRQ. | |
592 | * (a chained handler is automatically enabled and set to | |
7f1b1244 | 593 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
6a6de9ef TG |
594 | */ |
595 | static inline void | |
3836ca08 | 596 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 597 | { |
3836ca08 | 598 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
599 | } |
600 | ||
3b0f95be RK |
601 | /* |
602 | * Set a highlevel chained flow handler and its data for a given IRQ. | |
603 | * (a chained handler is automatically enabled and set to | |
604 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) | |
605 | */ | |
606 | void | |
607 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
608 | void *data); | |
609 | ||
44247184 TG |
610 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
611 | ||
612 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
613 | { | |
614 | irq_modify_status(irq, 0, set); | |
615 | } | |
616 | ||
617 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
618 | { | |
619 | irq_modify_status(irq, clr, 0); | |
620 | } | |
621 | ||
a0cd9ca2 | 622 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
623 | { |
624 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
625 | } | |
626 | ||
a0cd9ca2 | 627 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
628 | { |
629 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
630 | } | |
46f4f8f6 | 631 | |
7f1b1244 PM |
632 | static inline void irq_set_nothread(unsigned int irq) |
633 | { | |
634 | irq_modify_status(irq, 0, IRQ_NOTHREAD); | |
635 | } | |
636 | ||
637 | static inline void irq_set_thread(unsigned int irq) | |
638 | { | |
639 | irq_modify_status(irq, IRQ_NOTHREAD, 0); | |
640 | } | |
641 | ||
6f91a52d TG |
642 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
643 | { | |
644 | if (nest) | |
645 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
646 | else | |
647 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
648 | } | |
649 | ||
31d9d9b6 MZ |
650 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
651 | { | |
652 | irq_set_status_flags(irq, | |
653 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | | |
654 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); | |
655 | } | |
656 | ||
3a16d713 | 657 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
658 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
659 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
660 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
661 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
662 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
51906e77 AG |
663 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
664 | struct msi_desc *entry); | |
f303a6dd | 665 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 666 | |
a0cd9ca2 | 667 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
668 | { |
669 | struct irq_data *d = irq_get_irq_data(irq); | |
670 | return d ? d->chip : NULL; | |
671 | } | |
672 | ||
673 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
674 | { | |
675 | return d->chip; | |
676 | } | |
677 | ||
a0cd9ca2 | 678 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
679 | { |
680 | struct irq_data *d = irq_get_irq_data(irq); | |
681 | return d ? d->chip_data : NULL; | |
682 | } | |
683 | ||
684 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
685 | { | |
686 | return d->chip_data; | |
687 | } | |
688 | ||
a0cd9ca2 | 689 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
690 | { |
691 | struct irq_data *d = irq_get_irq_data(irq); | |
af7080e0 | 692 | return d ? d->common->handler_data : NULL; |
f303a6dd TG |
693 | } |
694 | ||
a0cd9ca2 | 695 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd | 696 | { |
af7080e0 | 697 | return d->common->handler_data; |
f303a6dd TG |
698 | } |
699 | ||
a0cd9ca2 | 700 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
701 | { |
702 | struct irq_data *d = irq_get_irq_data(irq); | |
b237721c | 703 | return d ? d->common->msi_desc : NULL; |
f303a6dd TG |
704 | } |
705 | ||
c391f262 | 706 | static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) |
f303a6dd | 707 | { |
b237721c | 708 | return d->common->msi_desc; |
f303a6dd TG |
709 | } |
710 | ||
1f6236bf JMC |
711 | static inline u32 irq_get_trigger_type(unsigned int irq) |
712 | { | |
713 | struct irq_data *d = irq_get_irq_data(irq); | |
714 | return d ? irqd_get_trigger_type(d) : 0; | |
715 | } | |
716 | ||
449e9cae | 717 | static inline int irq_common_data_get_node(struct irq_common_data *d) |
6783011b | 718 | { |
449e9cae | 719 | #ifdef CONFIG_NUMA |
6783011b | 720 | return d->node; |
449e9cae JL |
721 | #else |
722 | return 0; | |
723 | #endif | |
724 | } | |
725 | ||
726 | static inline int irq_data_get_node(struct irq_data *d) | |
727 | { | |
728 | return irq_common_data_get_node(d->common); | |
6783011b JL |
729 | } |
730 | ||
c64301a2 JL |
731 | static inline struct cpumask *irq_get_affinity_mask(int irq) |
732 | { | |
733 | struct irq_data *d = irq_get_irq_data(irq); | |
734 | ||
9df872fa | 735 | return d ? d->common->affinity : NULL; |
c64301a2 JL |
736 | } |
737 | ||
738 | static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) | |
739 | { | |
9df872fa | 740 | return d->common->affinity; |
c64301a2 JL |
741 | } |
742 | ||
62a08ae2 TG |
743 | unsigned int arch_dynirq_lower_bound(unsigned int from); |
744 | ||
b6873807 | 745 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
06ee6d57 | 746 | struct module *owner, const struct cpumask *affinity); |
b6873807 | 747 | |
2b5e7730 BG |
748 | int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, |
749 | unsigned int cnt, int node, struct module *owner, | |
750 | const struct cpumask *affinity); | |
751 | ||
ec53cf23 PG |
752 | /* use macros to avoid needing export.h for THIS_MODULE */ |
753 | #define irq_alloc_descs(irq, from, cnt, node) \ | |
06ee6d57 | 754 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) |
b6873807 | 755 | |
ec53cf23 PG |
756 | #define irq_alloc_desc(node) \ |
757 | irq_alloc_descs(-1, 0, 1, node) | |
1f5a5b87 | 758 | |
ec53cf23 PG |
759 | #define irq_alloc_desc_at(at, node) \ |
760 | irq_alloc_descs(at, at, 1, node) | |
1f5a5b87 | 761 | |
ec53cf23 PG |
762 | #define irq_alloc_desc_from(from, node) \ |
763 | irq_alloc_descs(-1, from, 1, node) | |
1f5a5b87 | 764 | |
51906e77 AG |
765 | #define irq_alloc_descs_from(from, cnt, node) \ |
766 | irq_alloc_descs(-1, from, cnt, node) | |
767 | ||
2b5e7730 BG |
768 | #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ |
769 | __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) | |
770 | ||
771 | #define devm_irq_alloc_desc(dev, node) \ | |
772 | devm_irq_alloc_descs(dev, -1, 0, 1, node) | |
773 | ||
774 | #define devm_irq_alloc_desc_at(dev, at, node) \ | |
775 | devm_irq_alloc_descs(dev, at, at, 1, node) | |
776 | ||
777 | #define devm_irq_alloc_desc_from(dev, from, node) \ | |
778 | devm_irq_alloc_descs(dev, -1, from, 1, node) | |
779 | ||
780 | #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ | |
781 | devm_irq_alloc_descs(dev, -1, from, cnt, node) | |
782 | ||
ec53cf23 | 783 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
1f5a5b87 TG |
784 | static inline void irq_free_desc(unsigned int irq) |
785 | { | |
786 | irq_free_descs(irq, 1); | |
787 | } | |
788 | ||
7b6ef126 TG |
789 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
790 | unsigned int irq_alloc_hwirqs(int cnt, int node); | |
791 | static inline unsigned int irq_alloc_hwirq(int node) | |
792 | { | |
793 | return irq_alloc_hwirqs(1, node); | |
794 | } | |
795 | void irq_free_hwirqs(unsigned int from, int cnt); | |
796 | static inline void irq_free_hwirq(unsigned int irq) | |
797 | { | |
798 | return irq_free_hwirqs(irq, 1); | |
799 | } | |
800 | int arch_setup_hwirq(unsigned int irq, int node); | |
801 | void arch_teardown_hwirq(unsigned int irq); | |
802 | #endif | |
803 | ||
c940e01c TG |
804 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
805 | void irq_init_desc(unsigned int irq); | |
806 | #endif | |
807 | ||
7d828062 TG |
808 | /** |
809 | * struct irq_chip_regs - register offsets for struct irq_gci | |
810 | * @enable: Enable register offset to reg_base | |
811 | * @disable: Disable register offset to reg_base | |
812 | * @mask: Mask register offset to reg_base | |
813 | * @ack: Ack register offset to reg_base | |
814 | * @eoi: Eoi register offset to reg_base | |
815 | * @type: Type configuration register offset to reg_base | |
816 | * @polarity: Polarity configuration register offset to reg_base | |
817 | */ | |
818 | struct irq_chip_regs { | |
819 | unsigned long enable; | |
820 | unsigned long disable; | |
821 | unsigned long mask; | |
822 | unsigned long ack; | |
823 | unsigned long eoi; | |
824 | unsigned long type; | |
825 | unsigned long polarity; | |
826 | }; | |
827 | ||
828 | /** | |
829 | * struct irq_chip_type - Generic interrupt chip instance for a flow type | |
830 | * @chip: The real interrupt chip which provides the callbacks | |
831 | * @regs: Register offsets for this chip | |
832 | * @handler: Flow handler associated with this chip | |
833 | * @type: Chip can handle these flow types | |
899f0e66 GF |
834 | * @mask_cache_priv: Cached mask register private to the chip type |
835 | * @mask_cache: Pointer to cached mask register | |
7d828062 TG |
836 | * |
837 | * A irq_generic_chip can have several instances of irq_chip_type when | |
838 | * it requires different functions and register offsets for different | |
839 | * flow types. | |
840 | */ | |
841 | struct irq_chip_type { | |
842 | struct irq_chip chip; | |
843 | struct irq_chip_regs regs; | |
844 | irq_flow_handler_t handler; | |
845 | u32 type; | |
899f0e66 GF |
846 | u32 mask_cache_priv; |
847 | u32 *mask_cache; | |
7d828062 TG |
848 | }; |
849 | ||
850 | /** | |
851 | * struct irq_chip_generic - Generic irq chip data structure | |
852 | * @lock: Lock to protect register and cache data access | |
853 | * @reg_base: Register base address (virtual) | |
2b280376 KC |
854 | * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) |
855 | * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) | |
be9b22b6 BN |
856 | * @suspend: Function called from core code on suspend once per |
857 | * chip; can be useful instead of irq_chip::suspend to | |
858 | * handle chip details even when no interrupts are in use | |
859 | * @resume: Function called from core code on resume once per chip; | |
860 | * can be useful instead of irq_chip::suspend to handle | |
861 | * chip details even when no interrupts are in use | |
7d828062 TG |
862 | * @irq_base: Interrupt base nr for this chip |
863 | * @irq_cnt: Number of interrupts handled by this chip | |
899f0e66 | 864 | * @mask_cache: Cached mask register shared between all chip types |
7d828062 TG |
865 | * @type_cache: Cached type register |
866 | * @polarity_cache: Cached polarity register | |
867 | * @wake_enabled: Interrupt can wakeup from suspend | |
868 | * @wake_active: Interrupt is marked as an wakeup from suspend source | |
869 | * @num_ct: Number of available irq_chip_type instances (usually 1) | |
870 | * @private: Private data for non generic chip callbacks | |
088f40b7 | 871 | * @installed: bitfield to denote installed interrupts |
e8bd834f | 872 | * @unused: bitfield to denote unused interrupts |
088f40b7 | 873 | * @domain: irq domain pointer |
cfefd21e | 874 | * @list: List head for keeping track of instances |
7d828062 TG |
875 | * @chip_types: Array of interrupt irq_chip_types |
876 | * | |
877 | * Note, that irq_chip_generic can have multiple irq_chip_type | |
878 | * implementations which can be associated to a particular irq line of | |
879 | * an irq_chip_generic instance. That allows to share and protect | |
880 | * state in an irq_chip_generic instance when we need to implement | |
881 | * different flow mechanisms (level/edge) for it. | |
882 | */ | |
883 | struct irq_chip_generic { | |
884 | raw_spinlock_t lock; | |
885 | void __iomem *reg_base; | |
2b280376 KC |
886 | u32 (*reg_readl)(void __iomem *addr); |
887 | void (*reg_writel)(u32 val, void __iomem *addr); | |
be9b22b6 BN |
888 | void (*suspend)(struct irq_chip_generic *gc); |
889 | void (*resume)(struct irq_chip_generic *gc); | |
7d828062 TG |
890 | unsigned int irq_base; |
891 | unsigned int irq_cnt; | |
892 | u32 mask_cache; | |
893 | u32 type_cache; | |
894 | u32 polarity_cache; | |
895 | u32 wake_enabled; | |
896 | u32 wake_active; | |
897 | unsigned int num_ct; | |
898 | void *private; | |
088f40b7 | 899 | unsigned long installed; |
e8bd834f | 900 | unsigned long unused; |
088f40b7 | 901 | struct irq_domain *domain; |
cfefd21e | 902 | struct list_head list; |
7d828062 TG |
903 | struct irq_chip_type chip_types[0]; |
904 | }; | |
905 | ||
906 | /** | |
907 | * enum irq_gc_flags - Initialization flags for generic irq chips | |
908 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg | |
909 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for | |
910 | * irq chips which need to call irq_set_wake() on | |
911 | * the parent irq. Usually GPIO implementations | |
af80b0fe | 912 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
966dc736 | 913 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
b7905595 | 914 | * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) |
7d828062 TG |
915 | */ |
916 | enum irq_gc_flags { | |
917 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, | |
918 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, | |
af80b0fe | 919 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
966dc736 | 920 | IRQ_GC_NO_MASK = 1 << 3, |
b7905595 | 921 | IRQ_GC_BE_IO = 1 << 4, |
7d828062 TG |
922 | }; |
923 | ||
088f40b7 TG |
924 | /* |
925 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains | |
926 | * @irqs_per_chip: Number of interrupts per chip | |
927 | * @num_chips: Number of chips | |
928 | * @irq_flags_to_set: IRQ* flags to set on irq setup | |
929 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup | |
930 | * @gc_flags: Generic chip specific setup flags | |
931 | * @gc: Array of pointers to generic interrupt chips | |
932 | */ | |
933 | struct irq_domain_chip_generic { | |
934 | unsigned int irqs_per_chip; | |
935 | unsigned int num_chips; | |
936 | unsigned int irq_flags_to_clear; | |
937 | unsigned int irq_flags_to_set; | |
938 | enum irq_gc_flags gc_flags; | |
939 | struct irq_chip_generic *gc[0]; | |
940 | }; | |
941 | ||
7d828062 TG |
942 | /* Generic chip callback functions */ |
943 | void irq_gc_noop(struct irq_data *d); | |
944 | void irq_gc_mask_disable_reg(struct irq_data *d); | |
945 | void irq_gc_mask_set_bit(struct irq_data *d); | |
946 | void irq_gc_mask_clr_bit(struct irq_data *d); | |
947 | void irq_gc_unmask_enable_reg(struct irq_data *d); | |
659fb32d SG |
948 | void irq_gc_ack_set_bit(struct irq_data *d); |
949 | void irq_gc_ack_clr_bit(struct irq_data *d); | |
7d828062 TG |
950 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
951 | void irq_gc_eoi(struct irq_data *d); | |
952 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); | |
953 | ||
954 | /* Setup functions for irq_chip_generic */ | |
a5152c8a BB |
955 | int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
956 | irq_hw_number_t hw_irq); | |
7d828062 TG |
957 | struct irq_chip_generic * |
958 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, | |
959 | void __iomem *reg_base, irq_flow_handler_t handler); | |
960 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, | |
961 | enum irq_gc_flags flags, unsigned int clr, | |
962 | unsigned int set); | |
963 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); | |
cfefd21e TG |
964 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
965 | unsigned int clr, unsigned int set); | |
7d828062 | 966 | |
1c3e3630 BG |
967 | struct irq_chip_generic * |
968 | devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, | |
969 | unsigned int irq_base, void __iomem *reg_base, | |
970 | irq_flow_handler_t handler); | |
30fd8fc5 BG |
971 | int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, |
972 | u32 msk, enum irq_gc_flags flags, | |
973 | unsigned int clr, unsigned int set); | |
1c3e3630 | 974 | |
088f40b7 | 975 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
088f40b7 | 976 | |
f88eecfe SF |
977 | int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, |
978 | int num_ct, const char *name, | |
979 | irq_flow_handler_t handler, | |
980 | unsigned int clr, unsigned int set, | |
981 | enum irq_gc_flags flags); | |
982 | ||
983 | #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ | |
984 | handler, clr, set, flags) \ | |
985 | ({ \ | |
986 | MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ | |
987 | __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ | |
988 | handler, clr, set, flags); \ | |
989 | }) | |
088f40b7 | 990 | |
707188f5 BG |
991 | static inline void irq_free_generic_chip(struct irq_chip_generic *gc) |
992 | { | |
993 | kfree(gc); | |
994 | } | |
995 | ||
32bb6cbb BG |
996 | static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, |
997 | u32 msk, unsigned int clr, | |
998 | unsigned int set) | |
999 | { | |
1000 | irq_remove_generic_chip(gc, msk, clr, set); | |
1001 | irq_free_generic_chip(gc); | |
1002 | } | |
1003 | ||
7d828062 TG |
1004 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
1005 | { | |
1006 | return container_of(d->chip, struct irq_chip_type, chip); | |
1007 | } | |
1008 | ||
1009 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) | |
1010 | ||
1011 | #ifdef CONFIG_SMP | |
1012 | static inline void irq_gc_lock(struct irq_chip_generic *gc) | |
1013 | { | |
1014 | raw_spin_lock(&gc->lock); | |
1015 | } | |
1016 | ||
1017 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) | |
1018 | { | |
1019 | raw_spin_unlock(&gc->lock); | |
1020 | } | |
1021 | #else | |
1022 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } | |
1023 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } | |
1024 | #endif | |
1025 | ||
ebf9ff75 BB |
1026 | /* |
1027 | * The irqsave variants are for usage in non interrupt code. Do not use | |
1028 | * them in irq_chip callbacks. Use irq_gc_lock() instead. | |
1029 | */ | |
1030 | #define irq_gc_lock_irqsave(gc, flags) \ | |
1031 | raw_spin_lock_irqsave(&(gc)->lock, flags) | |
1032 | ||
1033 | #define irq_gc_unlock_irqrestore(gc, flags) \ | |
1034 | raw_spin_unlock_irqrestore(&(gc)->lock, flags) | |
1035 | ||
332fd7c4 KC |
1036 | static inline void irq_reg_writel(struct irq_chip_generic *gc, |
1037 | u32 val, int reg_offset) | |
1038 | { | |
2b280376 KC |
1039 | if (gc->reg_writel) |
1040 | gc->reg_writel(val, gc->reg_base + reg_offset); | |
1041 | else | |
1042 | writel(val, gc->reg_base + reg_offset); | |
332fd7c4 KC |
1043 | } |
1044 | ||
1045 | static inline u32 irq_reg_readl(struct irq_chip_generic *gc, | |
1046 | int reg_offset) | |
1047 | { | |
2b280376 KC |
1048 | if (gc->reg_readl) |
1049 | return gc->reg_readl(gc->reg_base + reg_offset); | |
1050 | else | |
1051 | return readl(gc->reg_base + reg_offset); | |
332fd7c4 KC |
1052 | } |
1053 | ||
d17bf24e QY |
1054 | /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ |
1055 | #define INVALID_HWIRQ (~0UL) | |
f9bce791 | 1056 | irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); |
3b8e29a8 QY |
1057 | int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); |
1058 | int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); | |
1059 | int ipi_send_single(unsigned int virq, unsigned int cpu); | |
1060 | int ipi_send_mask(unsigned int virq, const struct cpumask *dest); | |
d17bf24e | 1061 | |
06fcb0c6 | 1062 | #endif /* _LINUX_IRQ_H */ |