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IB/mlx5: Report mlx5 enhanced multi packet WQE capability
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 241 MLX5_CMD_OP_MAX
e281682b
SM		 242};
243
244struct mlx5_ifc_flow_table_fields_supported_bits {
245 u8 outer_dmac[0x1];
246 u8 outer_smac[0x1];
247 u8 outer_ether_type[0x1];
19cc7524 248 u8 outer_ip_version[0x1];
e281682b
SM		 249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
a8ade55f 252 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
b4ff3a36 256 u8 reserved_at_b[0x1];
e281682b
SM		 257 u8 outer_sip[0x1];
258 u8 outer_dip[0x1];
259 u8 outer_frag[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
b4ff3a36 271 u8 reserved_at_1a[0x5];
e281682b
SM		 272 u8 source_eswitch_port[0x1];
273
274 u8 inner_dmac[0x1];
275 u8 inner_smac[0x1];
276 u8 inner_ether_type[0x1];
19cc7524 277 u8 inner_ip_version[0x1];
e281682b
SM		 278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
b4ff3a36 281 u8 reserved_at_27[0x1];
e281682b
SM		 282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
b4ff3a36 285 u8 reserved_at_2b[0x1];
e281682b
SM		 286 u8 inner_sip[0x1];
287 u8 inner_dip[0x1];
288 u8 inner_frag[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
b4ff3a36 297 u8 reserved_at_37[0x9];
a550ddfc
YH		 298 u8 reserved_at_40[0x1a];
299 u8 bth_dst_qp[0x1];
e281682b 300
a550ddfc 301 u8 reserved_at_5b[0x25];
e281682b
SM		 302};
303
304struct mlx5_ifc_flow_table_prop_layout_bits {
305 u8 ft_support[0x1];
9dc0b289
AV		 306 u8 reserved_at_1[0x1];
307 u8 flow_counter[0x1];
26a81453 308 u8 flow_modify_en[0x1];
2cc43b49 309 u8 modify_root[0x1];
34a40e68
MG		 310 u8 identified_miss_table_mode[0x1];
311 u8 flow_table_modify[0x1];
7adbde20
HHZ		 312 u8 encap[0x1];
313 u8 decap[0x1];
314 u8 reserved_at_9[0x17];
e281682b 315
b4ff3a36 316 u8 reserved_at_20[0x2];
e281682b 317 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 318 u8 log_max_modify_header_context[0x8];
319 u8 max_modify_header_actions[0x8];
e281682b
SM		 320 u8 max_ft_level[0x8];
321
b4ff3a36 322 u8 reserved_at_40[0x20];
e281682b 323
b4ff3a36 324 u8 reserved_at_60[0x18];
e281682b
SM		 325 u8 log_max_ft_num[0x8];
326
b4ff3a36 327 u8 reserved_at_80[0x18];
e281682b
SM		 328 u8 log_max_destination[0x8];
329
b4ff3a36 330 u8 reserved_at_a0[0x18];
e281682b
SM		 331 u8 log_max_flow[0x8];
332
b4ff3a36 333 u8 reserved_at_c0[0x40];
e281682b
SM		 334
335 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
336
337 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
338};
339
340struct mlx5_ifc_odp_per_transport_service_cap_bits {
341 u8 send[0x1];
342 u8 receive[0x1];
343 u8 write[0x1];
344 u8 read[0x1];
17d2f88f 345 u8 atomic[0x1];
e281682b 346 u8 srq_receive[0x1];
b4ff3a36 347 u8 reserved_at_6[0x1a];
e281682b
SM		 348};
349
b4d1f032 350struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 351 u8 reserved_at_0[0x60];
b4d1f032
MG		 352
353 u8 ipv4[0x20];
354};
355
356struct mlx5_ifc_ipv6_layout_bits {
357 u8 ipv6[16][0x8];
358};
359
360union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
361 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
362 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 363 u8 reserved_at_0[0x80];
b4d1f032
MG		 364};
365
e281682b
SM		 366struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
367 u8 smac_47_16[0x20];
368
369 u8 smac_15_0[0x10];
370 u8 ethertype[0x10];
371
372 u8 dmac_47_16[0x20];
373
374 u8 dmac_15_0[0x10];
375 u8 first_prio[0x3];
376 u8 first_cfi[0x1];
377 u8 first_vid[0xc];
378
379 u8 ip_protocol[0x8];
380 u8 ip_dscp[0x6];
381 u8 ip_ecn[0x2];
10543365
MHY		 382 u8 cvlan_tag[0x1];
383 u8 svlan_tag[0x1];
e281682b 384 u8 frag[0x1];
19cc7524 385 u8 ip_version[0x4];
e281682b
SM		 386 u8 tcp_flags[0x9];
387
388 u8 tcp_sport[0x10];
389 u8 tcp_dport[0x10];
390
a8ade55f
OG		 391 u8 reserved_at_c0[0x18];
392 u8 ttl_hoplimit[0x8];
e281682b
SM		 393
394 u8 udp_sport[0x10];
395 u8 udp_dport[0x10];
396
b4d1f032 397 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 398
b4d1f032 399 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 400};
401
402struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 403 u8 reserved_at_0[0x8];
404 u8 source_sqn[0x18];
e281682b 405
b4ff3a36 406 u8 reserved_at_20[0x10];
e281682b
SM		 407 u8 source_port[0x10];
408
409 u8 outer_second_prio[0x3];
410 u8 outer_second_cfi[0x1];
411 u8 outer_second_vid[0xc];
412 u8 inner_second_prio[0x3];
413 u8 inner_second_cfi[0x1];
414 u8 inner_second_vid[0xc];
415
10543365
MHY		 416 u8 outer_second_cvlan_tag[0x1];
417 u8 inner_second_cvlan_tag[0x1];
418 u8 outer_second_svlan_tag[0x1];
419 u8 inner_second_svlan_tag[0x1];
420 u8 reserved_at_64[0xc];
e281682b
SM		 421 u8 gre_protocol[0x10];
422
423 u8 gre_key_h[0x18];
424 u8 gre_key_l[0x8];
425
426 u8 vxlan_vni[0x18];
b4ff3a36 427 u8 reserved_at_b8[0x8];
e281682b 428
b4ff3a36 429 u8 reserved_at_c0[0x20];
e281682b 430
b4ff3a36 431 u8 reserved_at_e0[0xc];
e281682b
SM		 432 u8 outer_ipv6_flow_label[0x14];
433
b4ff3a36 434 u8 reserved_at_100[0xc];
e281682b
SM		 435 u8 inner_ipv6_flow_label[0x14];
436
a550ddfc
YH		 437 u8 reserved_at_120[0x28];
438 u8 bth_dst_qp[0x18];
439 u8 reserved_at_160[0xa0];
e281682b
SM		 440};
441
442struct mlx5_ifc_cmd_pas_bits {
443 u8 pa_h[0x20];
444
445 u8 pa_l[0x14];
b4ff3a36 446 u8 reserved_at_34[0xc];
e281682b
SM		 447};
448
449struct mlx5_ifc_uint64_bits {
450 u8 hi[0x20];
451
452 u8 lo[0x20];
453};
454
455enum {
456 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
457 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
458 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
459 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
460 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
461 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
462 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
463 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
464 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
465 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
466};
467
468struct mlx5_ifc_ads_bits {
469 u8 fl[0x1];
470 u8 free_ar[0x1];
b4ff3a36 471 u8 reserved_at_2[0xe];
e281682b
SM		 472 u8 pkey_index[0x10];
473
b4ff3a36 474 u8 reserved_at_20[0x8];
e281682b
SM		 475 u8 grh[0x1];
476 u8 mlid[0x7];
477 u8 rlid[0x10];
478
479 u8 ack_timeout[0x5];
b4ff3a36 480 u8 reserved_at_45[0x3];
e281682b 481 u8 src_addr_index[0x8];
b4ff3a36 482 u8 reserved_at_50[0x4];
e281682b
SM		 483 u8 stat_rate[0x4];
484 u8 hop_limit[0x8];
485
b4ff3a36 486 u8 reserved_at_60[0x4];
e281682b
SM		 487 u8 tclass[0x8];
488 u8 flow_label[0x14];
489
490 u8 rgid_rip[16][0x8];
491
b4ff3a36 492 u8 reserved_at_100[0x4];
e281682b
SM		 493 u8 f_dscp[0x1];
494 u8 f_ecn[0x1];
b4ff3a36 495 u8 reserved_at_106[0x1];
e281682b
SM		 496 u8 f_eth_prio[0x1];
497 u8 ecn[0x2];
498 u8 dscp[0x6];
499 u8 udp_sport[0x10];
500
501 u8 dei_cfi[0x1];
502 u8 eth_prio[0x3];
503 u8 sl[0x4];
504 u8 port[0x8];
505 u8 rmac_47_32[0x10];
506
507 u8 rmac_31_0[0x20];
508};
509
510struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 511 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 512 u8 nic_rx_multi_path_tirs_fts[0x1];
513 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
514 u8 reserved_at_3[0x1fd];
e281682b
SM		 515
516 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
517
b4ff3a36 518 u8 reserved_at_400[0x200];
e281682b
SM		 519
520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
521
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
523
b4ff3a36 524 u8 reserved_at_a00[0x200];
e281682b
SM		 525
526 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
527
b4ff3a36 528 u8 reserved_at_e00[0x7200];
e281682b
SM		 529};
530
495716b1 531struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 532 u8 reserved_at_0[0x200];
495716b1
SM		 533
534 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
535
536 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
537
538 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
539
b4ff3a36 540 u8 reserved_at_800[0x7800];
495716b1
SM		 541};
542
d6666753
SM		 543struct mlx5_ifc_e_switch_cap_bits {
544 u8 vport_svlan_strip[0x1];
545 u8 vport_cvlan_strip[0x1];
546 u8 vport_svlan_insert[0x1];
547 u8 vport_cvlan_insert_if_not_exist[0x1];
548 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 549 u8 reserved_at_5[0x19];
550 u8 nic_vport_node_guid_modify[0x1];
551 u8 nic_vport_port_guid_modify[0x1];
d6666753 552
7adbde20
HHZ		 553 u8 vxlan_encap_decap[0x1];
554 u8 nvgre_encap_decap[0x1];
555 u8 reserved_at_22[0x9];
556 u8 log_max_encap_headers[0x5];
557 u8 reserved_2b[0x6];
558 u8 max_encap_header_size[0xa];
559
560 u8 reserved_40[0x7c0];
561
d6666753
SM		 562};
563
7486216b
SM		 564struct mlx5_ifc_qos_cap_bits {
565 u8 packet_pacing[0x1];
813f8540 566 u8 esw_scheduling[0x1];
c9497c98
MHY		 567 u8 esw_bw_share[0x1];
568 u8 esw_rate_limit[0x1];
569 u8 reserved_at_4[0x1c];
813f8540
MHY		 570
571 u8 reserved_at_20[0x20];
572
7486216b 573 u8 packet_pacing_max_rate[0x20];
813f8540 574
7486216b 575 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 576
577 u8 reserved_at_80[0x10];
7486216b 578 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 579
580 u8 esw_element_type[0x10];
581 u8 esw_tsar_type[0x10];
582
583 u8 reserved_at_c0[0x10];
584 u8 max_qos_para_vport[0x10];
585
586 u8 max_tsar_bw_share[0x20];
587
588 u8 reserved_at_100[0x700];
7486216b
SM		 589};
590
e281682b
SM		 591struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
592 u8 csum_cap[0x1];
593 u8 vlan_cap[0x1];
594 u8 lro_cap[0x1];
595 u8 lro_psh_flag[0x1];
596 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 597 u8 reserved_at_5[0x2];
598 u8 wqe_vlan_insert[0x1];
66189961 599 u8 self_lb_en_modifiable[0x1];
b4ff3a36 600 u8 reserved_at_9[0x2];
e281682b 601 u8 max_lso_cap[0x5];
c226dc22 602 u8 multi_pkt_send_wqe[0x2];
cff92d7c 603 u8 wqe_inline_mode[0x2];
e281682b 604 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 605 u8 reg_umr_sq[0x1];
606 u8 scatter_fcs[0x1];
050da902 607 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 608 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 609 u8 reserved_at_1c[0x2];
e281682b
SM		 610 u8 tunnel_statless_gre[0x1];
611 u8 tunnel_stateless_vxlan[0x1];
612
547eede0
IT		 613 u8 swp[0x1];
614 u8 swp_csum[0x1];
615 u8 swp_lso[0x1];
616 u8 reserved_at_23[0x1d];
e281682b 617
b4ff3a36 618 u8 reserved_at_40[0x10];
e281682b
SM		 619 u8 lro_min_mss_size[0x10];
620
b4ff3a36 621 u8 reserved_at_60[0x120];
e281682b
SM		 622
623 u8 lro_timer_supported_periods[4][0x20];
624
b4ff3a36 625 u8 reserved_at_200[0x600];
e281682b
SM		 626};
627
628struct mlx5_ifc_roce_cap_bits {
629 u8 roce_apm[0x1];
b4ff3a36 630 u8 reserved_at_1[0x1f];
e281682b 631
b4ff3a36 632 u8 reserved_at_20[0x60];
e281682b 633
b4ff3a36 634 u8 reserved_at_80[0xc];
e281682b 635 u8 l3_type[0x4];
b4ff3a36 636 u8 reserved_at_90[0x8];
e281682b
SM		 637 u8 roce_version[0x8];
638
b4ff3a36 639 u8 reserved_at_a0[0x10];
e281682b
SM		 640 u8 r_roce_dest_udp_port[0x10];
641
642 u8 r_roce_max_src_udp_port[0x10];
643 u8 r_roce_min_src_udp_port[0x10];
644
b4ff3a36 645 u8 reserved_at_e0[0x10];
e281682b
SM		 646 u8 roce_address_table_size[0x10];
647
b4ff3a36 648 u8 reserved_at_100[0x700];
e281682b
SM		 649};
650
651enum {
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
661};
662
663enum {
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
665 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
666 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
673};
674
675struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 676 u8 reserved_at_0[0x40];
e281682b 677
bd10838a 678 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 679 u8 reserved_at_42[0x4];
bd10838a 680 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 681
b4ff3a36 682 u8 reserved_at_47[0x19];
e281682b 683
b4ff3a36 684 u8 reserved_at_60[0x20];
e281682b 685
b4ff3a36 686 u8 reserved_at_80[0x10];
f91e6d89 687 u8 atomic_operations[0x10];
e281682b 688
b4ff3a36 689 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 690 u8 atomic_size_qp[0x10];
691
b4ff3a36 692 u8 reserved_at_c0[0x10];
e281682b
SM		 693 u8 atomic_size_dc[0x10];
694
b4ff3a36 695 u8 reserved_at_e0[0x720];
e281682b
SM		 696};
697
698struct mlx5_ifc_odp_cap_bits {
b4ff3a36 699 u8 reserved_at_0[0x40];
e281682b
SM		 700
701 u8 sig[0x1];
b4ff3a36 702 u8 reserved_at_41[0x1f];
e281682b 703
b4ff3a36 704 u8 reserved_at_60[0x20];
e281682b
SM		 705
706 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
707
708 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
709
710 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
711
b4ff3a36 712 u8 reserved_at_e0[0x720];
e281682b
SM		 713};
714
3f0393a5
SG		 715struct mlx5_ifc_calc_op {
716 u8 reserved_at_0[0x10];
717 u8 reserved_at_10[0x9];
718 u8 op_swap_endianness[0x1];
719 u8 op_min[0x1];
720 u8 op_xor[0x1];
721 u8 op_or[0x1];
722 u8 op_and[0x1];
723 u8 op_max[0x1];
724 u8 op_add[0x1];
725};
726
727struct mlx5_ifc_vector_calc_cap_bits {
728 u8 calc_matrix[0x1];
729 u8 reserved_at_1[0x1f];
730 u8 reserved_at_20[0x8];
731 u8 max_vec_count[0x8];
732 u8 reserved_at_30[0xd];
733 u8 max_chunk_size[0x3];
734 struct mlx5_ifc_calc_op calc0;
735 struct mlx5_ifc_calc_op calc1;
736 struct mlx5_ifc_calc_op calc2;
737 struct mlx5_ifc_calc_op calc3;
738
739 u8 reserved_at_e0[0x720];
740};
741
e281682b
SM		 742enum {
743 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
744 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 745 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 746};
747
748enum {
749 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
750 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
751};
752
753enum {
754 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
755 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
756 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
757 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
758 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
759};
760
761enum {
762 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
763 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
764 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
765 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
766 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
768};
769
770enum {
771 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
772 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
773};
774
775enum {
776 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
777 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
778 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
779};
780
781enum {
782 MLX5_CAP_PORT_TYPE_IB = 0x0,
783 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 784};
785
1410a90a
MG		 786enum {
787 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
788 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
789 MLX5_CAP_UMR_FENCE_NONE = 0x2,
790};
791
b775516b 792struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 793 u8 reserved_at_0[0x80];
b775516b
EC		 794
795 u8 log_max_srq_sz[0x8];
796 u8 log_max_qp_sz[0x8];
b4ff3a36 797 u8 reserved_at_90[0xb];
b775516b
EC		 798 u8 log_max_qp[0x5];
799
b4ff3a36 800 u8 reserved_at_a0[0xb];
e281682b 801 u8 log_max_srq[0x5];
b4ff3a36 802 u8 reserved_at_b0[0x10];
b775516b 803
b4ff3a36 804 u8 reserved_at_c0[0x8];
b775516b 805 u8 log_max_cq_sz[0x8];
b4ff3a36 806 u8 reserved_at_d0[0xb];
b775516b
EC		 807 u8 log_max_cq[0x5];
808
809 u8 log_max_eq_sz[0x8];
b4ff3a36 810 u8 reserved_at_e8[0x2];
b775516b 811 u8 log_max_mkey[0x6];
b4ff3a36 812 u8 reserved_at_f0[0xc];
b775516b
EC		 813 u8 log_max_eq[0x4];
814
815 u8 max_indirection[0x8];
bcda1aca 816 u8 fixed_buffer_size[0x1];
b775516b 817 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 818 u8 force_teardown[0x1];
819 u8 reserved_at_111[0x1];
b775516b 820 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 821 u8 umr_extended_translation_offset[0x1];
822 u8 null_mkey[0x1];
b775516b
EC		 823 u8 log_max_klm_list_size[0x6];
824
b4ff3a36 825 u8 reserved_at_120[0xa];
b775516b 826 u8 log_max_ra_req_dc[0x6];
b4ff3a36 827 u8 reserved_at_130[0xa];
b775516b
EC		 828 u8 log_max_ra_res_dc[0x6];
829
b4ff3a36 830 u8 reserved_at_140[0xa];
b775516b 831 u8 log_max_ra_req_qp[0x6];
b4ff3a36 832 u8 reserved_at_150[0xa];
b775516b
EC		 833 u8 log_max_ra_res_qp[0x6];
834
f32f5bd2 835 u8 end_pad[0x1];
b775516b
EC		 836 u8 cc_query_allowed[0x1];
837 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 838 u8 start_pad[0x1];
839 u8 cache_line_128byte[0x1];
137ffd15 840 u8 reserved_at_165[0xb];
e281682b 841 u8 gid_table_size[0x10];
b775516b 842
e281682b
SM		 843 u8 out_of_seq_cnt[0x1];
844 u8 vport_counters[0x1];
7486216b 845 u8 retransmission_q_counters[0x1];
83b502a1
AV		 846 u8 reserved_at_183[0x1];
847 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 848 u8 rq_delay_drop[0x1];
b775516b
EC		 849 u8 max_qp_cnt[0xa];
850 u8 pkey_table_size[0x10];
851
e281682b
SM		 852 u8 vport_group_manager[0x1];
853 u8 vhca_group_manager[0x1];
854 u8 ib_virt[0x1];
855 u8 eth_virt[0x1];
b4ff3a36 856 u8 reserved_at_1a4[0x1];
e281682b
SM		 857 u8 ets[0x1];
858 u8 nic_flow_table[0x1];
54f0a411 859 u8 eswitch_flow_table[0x1];
e1c9c62b 860 u8 early_vf_enable[0x1];
cfdcbcea
GP		 861 u8 mcam_reg[0x1];
862 u8 pcam_reg[0x1];
b775516b 863 u8 local_ca_ack_delay[0x5];
4ce3bf2f 864 u8 port_module_event[0x1];
58dcb60a 865 u8 enhanced_error_q_counters[0x1];
7d5e1423 866 u8 ports_check[0x1];
7b13558f 867 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 868 u8 disable_link_up[0x1];
869 u8 beacon_led[0x1];
e281682b 870 u8 port_type[0x2];
b775516b
EC		 871 u8 num_ports[0x8];
872
f9a1ef72
EE		 873 u8 reserved_at_1c0[0x1];
874 u8 pps[0x1];
875 u8 pps_modify[0x1];
b775516b 876 u8 log_max_msg[0x5];
e1c9c62b 877 u8 reserved_at_1c8[0x4];
4f3961ee 878 u8 max_tc[0x4];
7486216b
SM		 879 u8 reserved_at_1d0[0x1];
880 u8 dcbx[0x1];
246ac981
MG		 881 u8 general_notification_event[0x1];
882 u8 reserved_at_1d3[0x2];
e29341fb 883 u8 fpga[0x1];
928cfe87
TT		 884 u8 rol_s[0x1];
885 u8 rol_g[0x1];
e1c9c62b 886 u8 reserved_at_1d8[0x1];
928cfe87
TT		 887 u8 wol_s[0x1];
888 u8 wol_g[0x1];
889 u8 wol_a[0x1];
890 u8 wol_b[0x1];
891 u8 wol_m[0x1];
892 u8 wol_u[0x1];
893 u8 wol_p[0x1];
b775516b
EC		 894
895 u8 stat_rate_support[0x10];
e1c9c62b 896 u8 reserved_at_1f0[0xc];
e281682b 897 u8 cqe_version[0x4];
b775516b 898
e281682b 899 u8 compact_address_vector[0x1];
7d5e1423 900 u8 striding_rq[0x1];
500a3d0d
ES		 901 u8 reserved_at_202[0x1];
902 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 903 u8 ipoib_basic_offloads[0x1];
1410a90a
MG		 904 u8 reserved_at_205[0x5];
905 u8 umr_fence[0x2];
906 u8 reserved_at_20c[0x3];
e281682b 907 u8 drain_sigerr[0x1];
b775516b
EC		 908 u8 cmdif_checksum[0x2];
909 u8 sigerr_cqe[0x1];
e1c9c62b 910 u8 reserved_at_213[0x1];
b775516b
EC		 911 u8 wq_signature[0x1];
912 u8 sctr_data_cqe[0x1];
e1c9c62b 913 u8 reserved_at_216[0x1];
b775516b
EC		 914 u8 sho[0x1];
915 u8 tph[0x1];
916 u8 rf[0x1];
e281682b 917 u8 dct[0x1];
7486216b 918 u8 qos[0x1];
e281682b 919 u8 eth_net_offloads[0x1];
b775516b
EC		 920 u8 roce[0x1];
921 u8 atomic[0x1];
e1c9c62b 922 u8 reserved_at_21f[0x1];
b775516b
EC		 923
924 u8 cq_oi[0x1];
925 u8 cq_resize[0x1];
926 u8 cq_moderation[0x1];
e1c9c62b 927 u8 reserved_at_223[0x3];
e281682b 928 u8 cq_eq_remap[0x1];
b775516b
EC		 929 u8 pg[0x1];
930 u8 block_lb_mc[0x1];
e1c9c62b 931 u8 reserved_at_229[0x1];
e281682b 932 u8 scqe_break_moderation[0x1];
7d5e1423 933 u8 cq_period_start_from_cqe[0x1];
b775516b 934 u8 cd[0x1];
e1c9c62b 935 u8 reserved_at_22d[0x1];
b775516b 936 u8 apm[0x1];
3f0393a5 937 u8 vector_calc[0x1];
7d5e1423 938 u8 umr_ptr_rlky[0x1];
d2370e0a 939 u8 imaicl[0x1];
e1c9c62b 940 u8 reserved_at_232[0x4];
b775516b
EC		 941 u8 qkv[0x1];
942 u8 pkv[0x1];
b11a4f9c
HE		 943 u8 set_deth_sqpn[0x1];
944 u8 reserved_at_239[0x3];
b775516b
EC		 945 u8 xrc[0x1];
946 u8 ud[0x1];
947 u8 uc[0x1];
948 u8 rc[0x1];
949
a6d51b68
EC		 950 u8 uar_4k[0x1];
951 u8 reserved_at_241[0x9];
b775516b 952 u8 uar_sz[0x6];
e1c9c62b 953 u8 reserved_at_250[0x8];
b775516b
EC		 954 u8 log_pg_sz[0x8];
955
956 u8 bf[0x1];
0dbc6fe0 957 u8 driver_version[0x1];
e281682b 958 u8 pad_tx_eth_packet[0x1];
e1c9c62b 959 u8 reserved_at_263[0x8];
b775516b 960 u8 log_bf_reg_size[0x5];
84df61eb
AH		 961
962 u8 reserved_at_270[0xb];
963 u8 lag_master[0x1];
964 u8 num_lag_ports[0x4];
b775516b 965
e1c9c62b 966 u8 reserved_at_280[0x10];
b775516b
EC		 967 u8 max_wqe_sz_sq[0x10];
968
e1c9c62b 969 u8 reserved_at_2a0[0x10];
b775516b
EC		 970 u8 max_wqe_sz_rq[0x10];
971
e1c9c62b 972 u8 reserved_at_2c0[0x10];
b775516b
EC		 973 u8 max_wqe_sz_sq_dc[0x10];
974
e1c9c62b 975 u8 reserved_at_2e0[0x7];
b775516b
EC		 976 u8 max_qp_mcg[0x19];
977
e1c9c62b 978 u8 reserved_at_300[0x18];
b775516b
EC		 979 u8 log_max_mcg[0x8];
980
e1c9c62b 981 u8 reserved_at_320[0x3];
e281682b 982 u8 log_max_transport_domain[0x5];
e1c9c62b 983 u8 reserved_at_328[0x3];
b775516b 984 u8 log_max_pd[0x5];
e1c9c62b 985 u8 reserved_at_330[0xb];
b775516b
EC		 986 u8 log_max_xrcd[0x5];
987
a351a1b0
AV		 988 u8 reserved_at_340[0x8];
989 u8 log_max_flow_counter_bulk[0x8];
990 u8 max_flow_counter[0x10];
991
b775516b 992
e1c9c62b 993 u8 reserved_at_360[0x3];
b775516b 994 u8 log_max_rq[0x5];
e1c9c62b 995 u8 reserved_at_368[0x3];
b775516b 996 u8 log_max_sq[0x5];
e1c9c62b 997 u8 reserved_at_370[0x3];
b775516b 998 u8 log_max_tir[0x5];
e1c9c62b 999 u8 reserved_at_378[0x3];
b775516b
EC		 1000 u8 log_max_tis[0x5];
1001
e281682b 1002 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1003 u8 reserved_at_381[0x2];
e281682b 1004 u8 log_max_rmp[0x5];
e1c9c62b 1005 u8 reserved_at_388[0x3];
e281682b 1006 u8 log_max_rqt[0x5];
e1c9c62b 1007 u8 reserved_at_390[0x3];
e281682b 1008 u8 log_max_rqt_size[0x5];
e1c9c62b 1009 u8 reserved_at_398[0x3];
b775516b
EC		 1010 u8 log_max_tis_per_sq[0x5];
1011
e1c9c62b 1012 u8 reserved_at_3a0[0x3];
e281682b 1013 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1014 u8 reserved_at_3a8[0x3];
e281682b 1015 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1016 u8 reserved_at_3b0[0x3];
e281682b 1017 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1018 u8 reserved_at_3b8[0x3];
e281682b
SM		 1019 u8 log_min_stride_sz_sq[0x5];
1020
e1c9c62b 1021 u8 reserved_at_3c0[0x1b];
e281682b
SM		 1022 u8 log_max_wq_sz[0x5];
1023
54f0a411 1024 u8 nic_vport_change_event[0x1];
bded747b
HN		 1025 u8 disable_local_lb[0x1];
1026 u8 reserved_at_3e2[0x9];
54f0a411 1027 u8 log_max_vlan_list[0x5];
e1c9c62b 1028 u8 reserved_at_3f0[0x3];
54f0a411 1029 u8 log_max_current_mc_list[0x5];
e1c9c62b 1030 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1031 u8 log_max_current_uc_list[0x5];
1032
e1c9c62b 1033 u8 reserved_at_400[0x80];
54f0a411 1034
e1c9c62b 1035 u8 reserved_at_480[0x3];
e281682b 1036 u8 log_max_l2_table[0x5];
e1c9c62b 1037 u8 reserved_at_488[0x8];
b775516b
EC		 1038 u8 log_uar_page_sz[0x10];
1039
e1c9c62b 1040 u8 reserved_at_4a0[0x20];
048ccca8 1041 u8 device_frequency_mhz[0x20];
b0844444 1042 u8 device_frequency_khz[0x20];
e1c9c62b 1043
a6d51b68
EC		 1044 u8 reserved_at_500[0x20];
1045 u8 num_of_uars_per_page[0x20];
1046 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1047
1048 u8 reserved_at_580[0x3f];
7d5e1423 1049 u8 cqe_compression[0x1];
b775516b 1050
7d5e1423
SM		 1051 u8 cqe_compression_timeout[0x10];
1052 u8 cqe_compression_max_num[0x10];
b775516b 1053
7486216b
SM		 1054 u8 reserved_at_5e0[0x10];
1055 u8 tag_matching[0x1];
1056 u8 rndv_offload_rc[0x1];
1057 u8 rndv_offload_dc[0x1];
1058 u8 log_tag_matching_list_sz[0x5];
7b13558f 1059 u8 reserved_at_5f8[0x3];
7486216b
SM		 1060 u8 log_max_xrq[0x5];
1061
7b13558f 1062 u8 reserved_at_600[0x200];
b775516b
EC		 1063};
1064
81848731
SM		 1065enum mlx5_flow_destination_type {
1066 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1067 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1068 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1069
1070 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1071};
b775516b 1072
e281682b
SM		 1073struct mlx5_ifc_dest_format_struct_bits {
1074 u8 destination_type[0x8];
1075 u8 destination_id[0x18];
b775516b 1076
b4ff3a36 1077 u8 reserved_at_20[0x20];
e281682b
SM		 1078};
1079
9dc0b289 1080struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1081 u8 clear[0x1];
1082 u8 num_of_counters[0xf];
9dc0b289
AV		 1083 u8 flow_counter_id[0x10];
1084
1085 u8 reserved_at_20[0x20];
1086};
1087
1088union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1089 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1090 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1091 u8 reserved_at_0[0x40];
1092};
1093
e281682b
SM		 1094struct mlx5_ifc_fte_match_param_bits {
1095 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1096
1097 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1098
1099 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1100
b4ff3a36 1101 u8 reserved_at_600[0xa00];
b775516b
EC		 1102};
1103
e281682b
SM		 1104enum {
1105 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1106 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1107 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1108 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1109 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1110};
b775516b 1111
e281682b
SM		 1112struct mlx5_ifc_rx_hash_field_select_bits {
1113 u8 l3_prot_type[0x1];
1114 u8 l4_prot_type[0x1];
1115 u8 selected_fields[0x1e];
1116};
b775516b 1117
e281682b
SM		 1118enum {
1119 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1120 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1121};
1122
e281682b
SM		 1123enum {
1124 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1125 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1126};
1127
1128struct mlx5_ifc_wq_bits {
1129 u8 wq_type[0x4];
1130 u8 wq_signature[0x1];
1131 u8 end_padding_mode[0x2];
1132 u8 cd_slave[0x1];
b4ff3a36 1133 u8 reserved_at_8[0x18];
b775516b 1134
e281682b
SM		 1135 u8 hds_skip_first_sge[0x1];
1136 u8 log2_hds_buf_size[0x3];
b4ff3a36 1137 u8 reserved_at_24[0x7];
e281682b
SM		 1138 u8 page_offset[0x5];
1139 u8 lwm[0x10];
b775516b 1140
b4ff3a36 1141 u8 reserved_at_40[0x8];
e281682b
SM		 1142 u8 pd[0x18];
1143
b4ff3a36 1144 u8 reserved_at_60[0x8];
e281682b
SM		 1145 u8 uar_page[0x18];
1146
1147 u8 dbr_addr[0x40];
1148
1149 u8 hw_counter[0x20];
1150
1151 u8 sw_counter[0x20];
1152
b4ff3a36 1153 u8 reserved_at_100[0xc];
e281682b 1154 u8 log_wq_stride[0x4];
b4ff3a36 1155 u8 reserved_at_110[0x3];
e281682b 1156 u8 log_wq_pg_sz[0x5];
b4ff3a36 1157 u8 reserved_at_118[0x3];
e281682b
SM		 1158 u8 log_wq_sz[0x5];
1159
7d5e1423
SM		 1160 u8 reserved_at_120[0x15];
1161 u8 log_wqe_num_of_strides[0x3];
1162 u8 two_byte_shift_en[0x1];
1163 u8 reserved_at_139[0x4];
1164 u8 log_wqe_stride_size[0x3];
1165
1166 u8 reserved_at_140[0x4c0];
b775516b 1167
e281682b 1168 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1169};
1170
e281682b 1171struct mlx5_ifc_rq_num_bits {
b4ff3a36 1172 u8 reserved_at_0[0x8];
e281682b
SM		 1173 u8 rq_num[0x18];
1174};
b775516b 1175
e281682b 1176struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1177 u8 reserved_at_0[0x10];
e281682b 1178 u8 mac_addr_47_32[0x10];
b775516b 1179
e281682b
SM		 1180 u8 mac_addr_31_0[0x20];
1181};
1182
c0046cf7 1183struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1184 u8 reserved_at_0[0x14];
c0046cf7
SM		 1185 u8 vlan[0x0c];
1186
b4ff3a36 1187 u8 reserved_at_20[0x20];
c0046cf7
SM		 1188};
1189
e281682b 1190struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1191 u8 reserved_at_0[0xa0];
e281682b
SM		 1192
1193 u8 min_time_between_cnps[0x20];
1194
b4ff3a36 1195 u8 reserved_at_c0[0x12];
e281682b 1196 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1197 u8 reserved_at_d8[0x4];
1198 u8 cnp_prio_mode[0x1];
e281682b
SM		 1199 u8 cnp_802p_prio[0x3];
1200
b4ff3a36 1201 u8 reserved_at_e0[0x720];
e281682b
SM		 1202};
1203
1204struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1205 u8 reserved_at_0[0x60];
e281682b 1206
b4ff3a36 1207 u8 reserved_at_60[0x4];
e281682b 1208 u8 clamp_tgt_rate[0x1];
b4ff3a36 1209 u8 reserved_at_65[0x3];
e281682b 1210 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1211 u8 reserved_at_69[0x17];
e281682b 1212
b4ff3a36 1213 u8 reserved_at_80[0x20];
e281682b
SM		 1214
1215 u8 rpg_time_reset[0x20];
1216
1217 u8 rpg_byte_reset[0x20];
1218
1219 u8 rpg_threshold[0x20];
1220
1221 u8 rpg_max_rate[0x20];
1222
1223 u8 rpg_ai_rate[0x20];
1224
1225 u8 rpg_hai_rate[0x20];
1226
1227 u8 rpg_gd[0x20];
1228
1229 u8 rpg_min_dec_fac[0x20];
1230
1231 u8 rpg_min_rate[0x20];
1232
b4ff3a36 1233 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1234
1235 u8 rate_to_set_on_first_cnp[0x20];
1236
1237 u8 dce_tcp_g[0x20];
1238
1239 u8 dce_tcp_rtt[0x20];
1240
1241 u8 rate_reduce_monitor_period[0x20];
1242
b4ff3a36 1243 u8 reserved_at_320[0x20];
e281682b
SM		 1244
1245 u8 initial_alpha_value[0x20];
1246
b4ff3a36 1247 u8 reserved_at_360[0x4a0];
e281682b
SM		 1248};
1249
1250struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1251 u8 reserved_at_0[0x80];
e281682b
SM		 1252
1253 u8 rppp_max_rps[0x20];
1254
1255 u8 rpg_time_reset[0x20];
1256
1257 u8 rpg_byte_reset[0x20];
1258
1259 u8 rpg_threshold[0x20];
1260
1261 u8 rpg_max_rate[0x20];
1262
1263 u8 rpg_ai_rate[0x20];
1264
1265 u8 rpg_hai_rate[0x20];
1266
1267 u8 rpg_gd[0x20];
1268
1269 u8 rpg_min_dec_fac[0x20];
1270
1271 u8 rpg_min_rate[0x20];
1272
b4ff3a36 1273 u8 reserved_at_1c0[0x640];
e281682b
SM		 1274};
1275
1276enum {
1277 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1278 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1279 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1280};
1281
1282struct mlx5_ifc_resize_field_select_bits {
1283 u8 resize_field_select[0x20];
1284};
1285
1286enum {
1287 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1288 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1289 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1290 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1291};
1292
1293struct mlx5_ifc_modify_field_select_bits {
1294 u8 modify_field_select[0x20];
1295};
1296
1297struct mlx5_ifc_field_select_r_roce_np_bits {
1298 u8 field_select_r_roce_np[0x20];
1299};
1300
1301struct mlx5_ifc_field_select_r_roce_rp_bits {
1302 u8 field_select_r_roce_rp[0x20];
1303};
1304
1305enum {
1306 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1307 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1308 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1309 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1310 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1316};
1317
1318struct mlx5_ifc_field_select_802_1qau_rp_bits {
1319 u8 field_select_8021qaurp[0x20];
1320};
1321
1322struct mlx5_ifc_phys_layer_cntrs_bits {
1323 u8 time_since_last_clear_high[0x20];
1324
1325 u8 time_since_last_clear_low[0x20];
1326
1327 u8 symbol_errors_high[0x20];
1328
1329 u8 symbol_errors_low[0x20];
1330
1331 u8 sync_headers_errors_high[0x20];
1332
1333 u8 sync_headers_errors_low[0x20];
1334
1335 u8 edpl_bip_errors_lane0_high[0x20];
1336
1337 u8 edpl_bip_errors_lane0_low[0x20];
1338
1339 u8 edpl_bip_errors_lane1_high[0x20];
1340
1341 u8 edpl_bip_errors_lane1_low[0x20];
1342
1343 u8 edpl_bip_errors_lane2_high[0x20];
1344
1345 u8 edpl_bip_errors_lane2_low[0x20];
1346
1347 u8 edpl_bip_errors_lane3_high[0x20];
1348
1349 u8 edpl_bip_errors_lane3_low[0x20];
1350
1351 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1352
1353 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1354
1355 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1356
1357 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1358
1359 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1360
1361 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1362
1363 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1364
1365 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1366
1367 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1368
1369 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1370
1371 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1372
1373 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1374
1375 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1376
1377 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1378
1379 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1380
1381 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1382
1383 u8 rs_fec_corrected_blocks_high[0x20];
1384
1385 u8 rs_fec_corrected_blocks_low[0x20];
1386
1387 u8 rs_fec_uncorrectable_blocks_high[0x20];
1388
1389 u8 rs_fec_uncorrectable_blocks_low[0x20];
1390
1391 u8 rs_fec_no_errors_blocks_high[0x20];
1392
1393 u8 rs_fec_no_errors_blocks_low[0x20];
1394
1395 u8 rs_fec_single_error_blocks_high[0x20];
1396
1397 u8 rs_fec_single_error_blocks_low[0x20];
1398
1399 u8 rs_fec_corrected_symbols_total_high[0x20];
1400
1401 u8 rs_fec_corrected_symbols_total_low[0x20];
1402
1403 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1404
1405 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1406
1407 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1408
1409 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1410
1411 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1412
1413 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1414
1415 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1416
1417 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1418
1419 u8 link_down_events[0x20];
1420
1421 u8 successful_recovery_events[0x20];
1422
b4ff3a36 1423 u8 reserved_at_640[0x180];
e281682b
SM		 1424};
1425
d8dc0508
GP		 1426struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1427 u8 time_since_last_clear_high[0x20];
1428
1429 u8 time_since_last_clear_low[0x20];
1430
1431 u8 phy_received_bits_high[0x20];
1432
1433 u8 phy_received_bits_low[0x20];
1434
1435 u8 phy_symbol_errors_high[0x20];
1436
1437 u8 phy_symbol_errors_low[0x20];
1438
1439 u8 phy_corrected_bits_high[0x20];
1440
1441 u8 phy_corrected_bits_low[0x20];
1442
1443 u8 phy_corrected_bits_lane0_high[0x20];
1444
1445 u8 phy_corrected_bits_lane0_low[0x20];
1446
1447 u8 phy_corrected_bits_lane1_high[0x20];
1448
1449 u8 phy_corrected_bits_lane1_low[0x20];
1450
1451 u8 phy_corrected_bits_lane2_high[0x20];
1452
1453 u8 phy_corrected_bits_lane2_low[0x20];
1454
1455 u8 phy_corrected_bits_lane3_high[0x20];
1456
1457 u8 phy_corrected_bits_lane3_low[0x20];
1458
1459 u8 reserved_at_200[0x5c0];
1460};
1461
1c64bf6f
MY		 1462struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1463 u8 symbol_error_counter[0x10];
1464
1465 u8 link_error_recovery_counter[0x8];
1466
1467 u8 link_downed_counter[0x8];
1468
1469 u8 port_rcv_errors[0x10];
1470
1471 u8 port_rcv_remote_physical_errors[0x10];
1472
1473 u8 port_rcv_switch_relay_errors[0x10];
1474
1475 u8 port_xmit_discards[0x10];
1476
1477 u8 port_xmit_constraint_errors[0x8];
1478
1479 u8 port_rcv_constraint_errors[0x8];
1480
1481 u8 reserved_at_70[0x8];
1482
1483 u8 link_overrun_errors[0x8];
1484
1485 u8 reserved_at_80[0x10];
1486
1487 u8 vl_15_dropped[0x10];
1488
133bea04
TW		 1489 u8 reserved_at_a0[0x80];
1490
1491 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1492};
1493
e281682b
SM		 1494struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1495 u8 transmit_queue_high[0x20];
1496
1497 u8 transmit_queue_low[0x20];
1498
b4ff3a36 1499 u8 reserved_at_40[0x780];
e281682b
SM		 1500};
1501
1502struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1503 u8 rx_octets_high[0x20];
1504
1505 u8 rx_octets_low[0x20];
1506
b4ff3a36 1507 u8 reserved_at_40[0xc0];
e281682b
SM		 1508
1509 u8 rx_frames_high[0x20];
1510
1511 u8 rx_frames_low[0x20];
1512
1513 u8 tx_octets_high[0x20];
1514
1515 u8 tx_octets_low[0x20];
1516
b4ff3a36 1517 u8 reserved_at_180[0xc0];
e281682b
SM		 1518
1519 u8 tx_frames_high[0x20];
1520
1521 u8 tx_frames_low[0x20];
1522
1523 u8 rx_pause_high[0x20];
1524
1525 u8 rx_pause_low[0x20];
1526
1527 u8 rx_pause_duration_high[0x20];
1528
1529 u8 rx_pause_duration_low[0x20];
1530
1531 u8 tx_pause_high[0x20];
1532
1533 u8 tx_pause_low[0x20];
1534
1535 u8 tx_pause_duration_high[0x20];
1536
1537 u8 tx_pause_duration_low[0x20];
1538
1539 u8 rx_pause_transition_high[0x20];
1540
1541 u8 rx_pause_transition_low[0x20];
1542
b4ff3a36 1543 u8 reserved_at_3c0[0x400];
e281682b
SM		 1544};
1545
1546struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1547 u8 port_transmit_wait_high[0x20];
1548
1549 u8 port_transmit_wait_low[0x20];
1550
b4ff3a36 1551 u8 reserved_at_40[0x780];
e281682b
SM		 1552};
1553
1554struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1555 u8 dot3stats_alignment_errors_high[0x20];
1556
1557 u8 dot3stats_alignment_errors_low[0x20];
1558
1559 u8 dot3stats_fcs_errors_high[0x20];
1560
1561 u8 dot3stats_fcs_errors_low[0x20];
1562
1563 u8 dot3stats_single_collision_frames_high[0x20];
1564
1565 u8 dot3stats_single_collision_frames_low[0x20];
1566
1567 u8 dot3stats_multiple_collision_frames_high[0x20];
1568
1569 u8 dot3stats_multiple_collision_frames_low[0x20];
1570
1571 u8 dot3stats_sqe_test_errors_high[0x20];
1572
1573 u8 dot3stats_sqe_test_errors_low[0x20];
1574
1575 u8 dot3stats_deferred_transmissions_high[0x20];
1576
1577 u8 dot3stats_deferred_transmissions_low[0x20];
1578
1579 u8 dot3stats_late_collisions_high[0x20];
1580
1581 u8 dot3stats_late_collisions_low[0x20];
1582
1583 u8 dot3stats_excessive_collisions_high[0x20];
1584
1585 u8 dot3stats_excessive_collisions_low[0x20];
1586
1587 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1588
1589 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1590
1591 u8 dot3stats_carrier_sense_errors_high[0x20];
1592
1593 u8 dot3stats_carrier_sense_errors_low[0x20];
1594
1595 u8 dot3stats_frame_too_longs_high[0x20];
1596
1597 u8 dot3stats_frame_too_longs_low[0x20];
1598
1599 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1600
1601 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1602
1603 u8 dot3stats_symbol_errors_high[0x20];
1604
1605 u8 dot3stats_symbol_errors_low[0x20];
1606
1607 u8 dot3control_in_unknown_opcodes_high[0x20];
1608
1609 u8 dot3control_in_unknown_opcodes_low[0x20];
1610
1611 u8 dot3in_pause_frames_high[0x20];
1612
1613 u8 dot3in_pause_frames_low[0x20];
1614
1615 u8 dot3out_pause_frames_high[0x20];
1616
1617 u8 dot3out_pause_frames_low[0x20];
1618
b4ff3a36 1619 u8 reserved_at_400[0x3c0];
e281682b
SM		 1620};
1621
1622struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1623 u8 ether_stats_drop_events_high[0x20];
1624
1625 u8 ether_stats_drop_events_low[0x20];
1626
1627 u8 ether_stats_octets_high[0x20];
1628
1629 u8 ether_stats_octets_low[0x20];
1630
1631 u8 ether_stats_pkts_high[0x20];
1632
1633 u8 ether_stats_pkts_low[0x20];
1634
1635 u8 ether_stats_broadcast_pkts_high[0x20];
1636
1637 u8 ether_stats_broadcast_pkts_low[0x20];
1638
1639 u8 ether_stats_multicast_pkts_high[0x20];
1640
1641 u8 ether_stats_multicast_pkts_low[0x20];
1642
1643 u8 ether_stats_crc_align_errors_high[0x20];
1644
1645 u8 ether_stats_crc_align_errors_low[0x20];
1646
1647 u8 ether_stats_undersize_pkts_high[0x20];
1648
1649 u8 ether_stats_undersize_pkts_low[0x20];
1650
1651 u8 ether_stats_oversize_pkts_high[0x20];
1652
1653 u8 ether_stats_oversize_pkts_low[0x20];
1654
1655 u8 ether_stats_fragments_high[0x20];
1656
1657 u8 ether_stats_fragments_low[0x20];
1658
1659 u8 ether_stats_jabbers_high[0x20];
1660
1661 u8 ether_stats_jabbers_low[0x20];
1662
1663 u8 ether_stats_collisions_high[0x20];
1664
1665 u8 ether_stats_collisions_low[0x20];
1666
1667 u8 ether_stats_pkts64octets_high[0x20];
1668
1669 u8 ether_stats_pkts64octets_low[0x20];
1670
1671 u8 ether_stats_pkts65to127octets_high[0x20];
1672
1673 u8 ether_stats_pkts65to127octets_low[0x20];
1674
1675 u8 ether_stats_pkts128to255octets_high[0x20];
1676
1677 u8 ether_stats_pkts128to255octets_low[0x20];
1678
1679 u8 ether_stats_pkts256to511octets_high[0x20];
1680
1681 u8 ether_stats_pkts256to511octets_low[0x20];
1682
1683 u8 ether_stats_pkts512to1023octets_high[0x20];
1684
1685 u8 ether_stats_pkts512to1023octets_low[0x20];
1686
1687 u8 ether_stats_pkts1024to1518octets_high[0x20];
1688
1689 u8 ether_stats_pkts1024to1518octets_low[0x20];
1690
1691 u8 ether_stats_pkts1519to2047octets_high[0x20];
1692
1693 u8 ether_stats_pkts1519to2047octets_low[0x20];
1694
1695 u8 ether_stats_pkts2048to4095octets_high[0x20];
1696
1697 u8 ether_stats_pkts2048to4095octets_low[0x20];
1698
1699 u8 ether_stats_pkts4096to8191octets_high[0x20];
1700
1701 u8 ether_stats_pkts4096to8191octets_low[0x20];
1702
1703 u8 ether_stats_pkts8192to10239octets_high[0x20];
1704
1705 u8 ether_stats_pkts8192to10239octets_low[0x20];
1706
b4ff3a36 1707 u8 reserved_at_540[0x280];
e281682b
SM		 1708};
1709
1710struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1711 u8 if_in_octets_high[0x20];
1712
1713 u8 if_in_octets_low[0x20];
1714
1715 u8 if_in_ucast_pkts_high[0x20];
1716
1717 u8 if_in_ucast_pkts_low[0x20];
1718
1719 u8 if_in_discards_high[0x20];
1720
1721 u8 if_in_discards_low[0x20];
1722
1723 u8 if_in_errors_high[0x20];
1724
1725 u8 if_in_errors_low[0x20];
1726
1727 u8 if_in_unknown_protos_high[0x20];
1728
1729 u8 if_in_unknown_protos_low[0x20];
1730
1731 u8 if_out_octets_high[0x20];
1732
1733 u8 if_out_octets_low[0x20];
1734
1735 u8 if_out_ucast_pkts_high[0x20];
1736
1737 u8 if_out_ucast_pkts_low[0x20];
1738
1739 u8 if_out_discards_high[0x20];
1740
1741 u8 if_out_discards_low[0x20];
1742
1743 u8 if_out_errors_high[0x20];
1744
1745 u8 if_out_errors_low[0x20];
1746
1747 u8 if_in_multicast_pkts_high[0x20];
1748
1749 u8 if_in_multicast_pkts_low[0x20];
1750
1751 u8 if_in_broadcast_pkts_high[0x20];
1752
1753 u8 if_in_broadcast_pkts_low[0x20];
1754
1755 u8 if_out_multicast_pkts_high[0x20];
1756
1757 u8 if_out_multicast_pkts_low[0x20];
1758
1759 u8 if_out_broadcast_pkts_high[0x20];
1760
1761 u8 if_out_broadcast_pkts_low[0x20];
1762
b4ff3a36 1763 u8 reserved_at_340[0x480];
e281682b
SM		 1764};
1765
1766struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1767 u8 a_frames_transmitted_ok_high[0x20];
1768
1769 u8 a_frames_transmitted_ok_low[0x20];
1770
1771 u8 a_frames_received_ok_high[0x20];
1772
1773 u8 a_frames_received_ok_low[0x20];
1774
1775 u8 a_frame_check_sequence_errors_high[0x20];
1776
1777 u8 a_frame_check_sequence_errors_low[0x20];
1778
1779 u8 a_alignment_errors_high[0x20];
1780
1781 u8 a_alignment_errors_low[0x20];
1782
1783 u8 a_octets_transmitted_ok_high[0x20];
1784
1785 u8 a_octets_transmitted_ok_low[0x20];
1786
1787 u8 a_octets_received_ok_high[0x20];
1788
1789 u8 a_octets_received_ok_low[0x20];
1790
1791 u8 a_multicast_frames_xmitted_ok_high[0x20];
1792
1793 u8 a_multicast_frames_xmitted_ok_low[0x20];
1794
1795 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1796
1797 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1798
1799 u8 a_multicast_frames_received_ok_high[0x20];
1800
1801 u8 a_multicast_frames_received_ok_low[0x20];
1802
1803 u8 a_broadcast_frames_received_ok_high[0x20];
1804
1805 u8 a_broadcast_frames_received_ok_low[0x20];
1806
1807 u8 a_in_range_length_errors_high[0x20];
1808
1809 u8 a_in_range_length_errors_low[0x20];
1810
1811 u8 a_out_of_range_length_field_high[0x20];
1812
1813 u8 a_out_of_range_length_field_low[0x20];
1814
1815 u8 a_frame_too_long_errors_high[0x20];
1816
1817 u8 a_frame_too_long_errors_low[0x20];
1818
1819 u8 a_symbol_error_during_carrier_high[0x20];
1820
1821 u8 a_symbol_error_during_carrier_low[0x20];
1822
1823 u8 a_mac_control_frames_transmitted_high[0x20];
1824
1825 u8 a_mac_control_frames_transmitted_low[0x20];
1826
1827 u8 a_mac_control_frames_received_high[0x20];
1828
1829 u8 a_mac_control_frames_received_low[0x20];
1830
1831 u8 a_unsupported_opcodes_received_high[0x20];
1832
1833 u8 a_unsupported_opcodes_received_low[0x20];
1834
1835 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1836
1837 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1838
1839 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1840
1841 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1842
b4ff3a36 1843 u8 reserved_at_4c0[0x300];
e281682b
SM		 1844};
1845
8ed1a630
GP		 1846struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1847 u8 life_time_counter_high[0x20];
1848
1849 u8 life_time_counter_low[0x20];
1850
1851 u8 rx_errors[0x20];
1852
1853 u8 tx_errors[0x20];
1854
1855 u8 l0_to_recovery_eieos[0x20];
1856
1857 u8 l0_to_recovery_ts[0x20];
1858
1859 u8 l0_to_recovery_framing[0x20];
1860
1861 u8 l0_to_recovery_retrain[0x20];
1862
1863 u8 crc_error_dllp[0x20];
1864
1865 u8 crc_error_tlp[0x20];
1866
1867 u8 reserved_at_140[0x680];
1868};
1869
e281682b
SM		 1870struct mlx5_ifc_cmd_inter_comp_event_bits {
1871 u8 command_completion_vector[0x20];
1872
b4ff3a36 1873 u8 reserved_at_20[0xc0];
e281682b
SM		 1874};
1875
1876struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1877 u8 reserved_at_0[0x18];
e281682b 1878 u8 port_num[0x1];
b4ff3a36 1879 u8 reserved_at_19[0x3];
e281682b
SM		 1880 u8 vl[0x4];
1881
b4ff3a36 1882 u8 reserved_at_20[0xa0];
e281682b
SM		 1883};
1884
1885struct mlx5_ifc_db_bf_congestion_event_bits {
1886 u8 event_subtype[0x8];
b4ff3a36 1887 u8 reserved_at_8[0x8];
e281682b 1888 u8 congestion_level[0x8];
b4ff3a36 1889 u8 reserved_at_18[0x8];
e281682b 1890
b4ff3a36 1891 u8 reserved_at_20[0xa0];
e281682b
SM		 1892};
1893
1894struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1895 u8 reserved_at_0[0x60];
e281682b
SM		 1896
1897 u8 gpio_event_hi[0x20];
1898
1899 u8 gpio_event_lo[0x20];
1900
b4ff3a36 1901 u8 reserved_at_a0[0x40];
e281682b
SM		 1902};
1903
1904struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1905 u8 reserved_at_0[0x40];
e281682b
SM		 1906
1907 u8 port_num[0x4];
b4ff3a36 1908 u8 reserved_at_44[0x1c];
e281682b 1909
b4ff3a36 1910 u8 reserved_at_60[0x80];
e281682b
SM		 1911};
1912
1913struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1914 u8 reserved_at_0[0xe0];
e281682b
SM		 1915};
1916
1917enum {
1918 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1919 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1920};
1921
1922struct mlx5_ifc_cq_error_bits {
b4ff3a36 1923 u8 reserved_at_0[0x8];
e281682b
SM		 1924 u8 cqn[0x18];
1925
b4ff3a36 1926 u8 reserved_at_20[0x20];
e281682b 1927
b4ff3a36 1928 u8 reserved_at_40[0x18];
e281682b
SM		 1929 u8 syndrome[0x8];
1930
b4ff3a36 1931 u8 reserved_at_60[0x80];
e281682b
SM		 1932};
1933
1934struct mlx5_ifc_rdma_page_fault_event_bits {
1935 u8 bytes_committed[0x20];
1936
1937 u8 r_key[0x20];
1938
b4ff3a36 1939 u8 reserved_at_40[0x10];
e281682b
SM		 1940 u8 packet_len[0x10];
1941
1942 u8 rdma_op_len[0x20];
1943
1944 u8 rdma_va[0x40];
1945
b4ff3a36 1946 u8 reserved_at_c0[0x5];
e281682b
SM		 1947 u8 rdma[0x1];
1948 u8 write[0x1];
1949 u8 requestor[0x1];
1950 u8 qp_number[0x18];
1951};
1952
1953struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1954 u8 bytes_committed[0x20];
1955
b4ff3a36 1956 u8 reserved_at_20[0x10];
e281682b
SM		 1957 u8 wqe_index[0x10];
1958
b4ff3a36 1959 u8 reserved_at_40[0x10];
e281682b
SM		 1960 u8 len[0x10];
1961
b4ff3a36 1962 u8 reserved_at_60[0x60];
e281682b 1963
b4ff3a36 1964 u8 reserved_at_c0[0x5];
e281682b
SM		 1965 u8 rdma[0x1];
1966 u8 write_read[0x1];
1967 u8 requestor[0x1];
1968 u8 qpn[0x18];
1969};
1970
1971struct mlx5_ifc_qp_events_bits {
b4ff3a36 1972 u8 reserved_at_0[0xa0];
e281682b
SM		 1973
1974 u8 type[0x8];
b4ff3a36 1975 u8 reserved_at_a8[0x18];
e281682b 1976
b4ff3a36 1977 u8 reserved_at_c0[0x8];
e281682b
SM		 1978 u8 qpn_rqn_sqn[0x18];
1979};
1980
1981struct mlx5_ifc_dct_events_bits {
b4ff3a36 1982 u8 reserved_at_0[0xc0];
e281682b 1983
b4ff3a36 1984 u8 reserved_at_c0[0x8];
e281682b
SM		 1985 u8 dct_number[0x18];
1986};
1987
1988struct mlx5_ifc_comp_event_bits {
b4ff3a36 1989 u8 reserved_at_0[0xc0];
e281682b 1990
b4ff3a36 1991 u8 reserved_at_c0[0x8];
e281682b
SM		 1992 u8 cq_number[0x18];
1993};
1994
1995enum {
1996 MLX5_QPC_STATE_RST = 0x0,
1997 MLX5_QPC_STATE_INIT = 0x1,
1998 MLX5_QPC_STATE_RTR = 0x2,
1999 MLX5_QPC_STATE_RTS = 0x3,
2000 MLX5_QPC_STATE_SQER = 0x4,
2001 MLX5_QPC_STATE_ERR = 0x6,
2002 MLX5_QPC_STATE_SQD = 0x7,
2003 MLX5_QPC_STATE_SUSPENDED = 0x9,
2004};
2005
2006enum {
2007 MLX5_QPC_ST_RC = 0x0,
2008 MLX5_QPC_ST_UC = 0x1,
2009 MLX5_QPC_ST_UD = 0x2,
2010 MLX5_QPC_ST_XRC = 0x3,
2011 MLX5_QPC_ST_DCI = 0x5,
2012 MLX5_QPC_ST_QP0 = 0x7,
2013 MLX5_QPC_ST_QP1 = 0x8,
2014 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2015 MLX5_QPC_ST_REG_UMR = 0xc,
2016};
2017
2018enum {
2019 MLX5_QPC_PM_STATE_ARMED = 0x0,
2020 MLX5_QPC_PM_STATE_REARM = 0x1,
2021 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2022 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2023};
2024
2025enum {
2026 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2027 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2028};
2029
2030enum {
2031 MLX5_QPC_MTU_256_BYTES = 0x1,
2032 MLX5_QPC_MTU_512_BYTES = 0x2,
2033 MLX5_QPC_MTU_1K_BYTES = 0x3,
2034 MLX5_QPC_MTU_2K_BYTES = 0x4,
2035 MLX5_QPC_MTU_4K_BYTES = 0x5,
2036 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2037};
2038
2039enum {
2040 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2041 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2042 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2043 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2044 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2045 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2046 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2047 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2048};
2049
2050enum {
2051 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2052 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2053 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2054};
2055
2056enum {
2057 MLX5_QPC_CS_RES_DISABLE = 0x0,
2058 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2059 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2060};
2061
2062struct mlx5_ifc_qpc_bits {
2063 u8 state[0x4];
84df61eb 2064 u8 lag_tx_port_affinity[0x4];
e281682b 2065 u8 st[0x8];
b4ff3a36 2066 u8 reserved_at_10[0x3];
e281682b 2067 u8 pm_state[0x2];
b4ff3a36 2068 u8 reserved_at_15[0x7];
e281682b 2069 u8 end_padding_mode[0x2];
b4ff3a36 2070 u8 reserved_at_1e[0x2];
e281682b
SM		 2071
2072 u8 wq_signature[0x1];
2073 u8 block_lb_mc[0x1];
2074 u8 atomic_like_write_en[0x1];
2075 u8 latency_sensitive[0x1];
b4ff3a36 2076 u8 reserved_at_24[0x1];
e281682b 2077 u8 drain_sigerr[0x1];
b4ff3a36 2078 u8 reserved_at_26[0x2];
e281682b
SM		 2079 u8 pd[0x18];
2080
2081 u8 mtu[0x3];
2082 u8 log_msg_max[0x5];
b4ff3a36 2083 u8 reserved_at_48[0x1];
e281682b
SM		 2084 u8 log_rq_size[0x4];
2085 u8 log_rq_stride[0x3];
2086 u8 no_sq[0x1];
2087 u8 log_sq_size[0x4];
b4ff3a36 2088 u8 reserved_at_55[0x6];
e281682b 2089 u8 rlky[0x1];
1015c2e8 2090 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2091
2092 u8 counter_set_id[0x8];
2093 u8 uar_page[0x18];
2094
b4ff3a36 2095 u8 reserved_at_80[0x8];
e281682b
SM		 2096 u8 user_index[0x18];
2097
b4ff3a36 2098 u8 reserved_at_a0[0x3];
e281682b
SM		 2099 u8 log_page_size[0x5];
2100 u8 remote_qpn[0x18];
2101
2102 struct mlx5_ifc_ads_bits primary_address_path;
2103
2104 struct mlx5_ifc_ads_bits secondary_address_path;
2105
2106 u8 log_ack_req_freq[0x4];
b4ff3a36 2107 u8 reserved_at_384[0x4];
e281682b 2108 u8 log_sra_max[0x3];
b4ff3a36 2109 u8 reserved_at_38b[0x2];
e281682b
SM		 2110 u8 retry_count[0x3];
2111 u8 rnr_retry[0x3];
b4ff3a36 2112 u8 reserved_at_393[0x1];
e281682b
SM		 2113 u8 fre[0x1];
2114 u8 cur_rnr_retry[0x3];
2115 u8 cur_retry_count[0x3];
b4ff3a36 2116 u8 reserved_at_39b[0x5];
e281682b 2117
b4ff3a36 2118 u8 reserved_at_3a0[0x20];
e281682b 2119
b4ff3a36 2120 u8 reserved_at_3c0[0x8];
e281682b
SM		 2121 u8 next_send_psn[0x18];
2122
b4ff3a36 2123 u8 reserved_at_3e0[0x8];
e281682b
SM		 2124 u8 cqn_snd[0x18];
2125
09a7d9ec
SM		 2126 u8 reserved_at_400[0x8];
2127 u8 deth_sqpn[0x18];
2128
2129 u8 reserved_at_420[0x20];
e281682b 2130
b4ff3a36 2131 u8 reserved_at_440[0x8];
e281682b
SM		 2132 u8 last_acked_psn[0x18];
2133
b4ff3a36 2134 u8 reserved_at_460[0x8];
e281682b
SM		 2135 u8 ssn[0x18];
2136
b4ff3a36 2137 u8 reserved_at_480[0x8];
e281682b 2138 u8 log_rra_max[0x3];
b4ff3a36 2139 u8 reserved_at_48b[0x1];
e281682b
SM		 2140 u8 atomic_mode[0x4];
2141 u8 rre[0x1];
2142 u8 rwe[0x1];
2143 u8 rae[0x1];
b4ff3a36 2144 u8 reserved_at_493[0x1];
e281682b 2145 u8 page_offset[0x6];
b4ff3a36 2146 u8 reserved_at_49a[0x3];
e281682b
SM		 2147 u8 cd_slave_receive[0x1];
2148 u8 cd_slave_send[0x1];
2149 u8 cd_master[0x1];
2150
b4ff3a36 2151 u8 reserved_at_4a0[0x3];
e281682b
SM		 2152 u8 min_rnr_nak[0x5];
2153 u8 next_rcv_psn[0x18];
2154
b4ff3a36 2155 u8 reserved_at_4c0[0x8];
e281682b
SM		 2156 u8 xrcd[0x18];
2157
b4ff3a36 2158 u8 reserved_at_4e0[0x8];
e281682b
SM		 2159 u8 cqn_rcv[0x18];
2160
2161 u8 dbr_addr[0x40];
2162
2163 u8 q_key[0x20];
2164
b4ff3a36 2165 u8 reserved_at_560[0x5];
e281682b 2166 u8 rq_type[0x3];
7486216b 2167 u8 srqn_rmpn_xrqn[0x18];
e281682b 2168
b4ff3a36 2169 u8 reserved_at_580[0x8];
e281682b
SM		 2170 u8 rmsn[0x18];
2171
2172 u8 hw_sq_wqebb_counter[0x10];
2173 u8 sw_sq_wqebb_counter[0x10];
2174
2175 u8 hw_rq_counter[0x20];
2176
2177 u8 sw_rq_counter[0x20];
2178
b4ff3a36 2179 u8 reserved_at_600[0x20];
e281682b 2180
b4ff3a36 2181 u8 reserved_at_620[0xf];
e281682b
SM		 2182 u8 cgs[0x1];
2183 u8 cs_req[0x8];
2184 u8 cs_res[0x8];
2185
2186 u8 dc_access_key[0x40];
2187
b4ff3a36 2188 u8 reserved_at_680[0xc0];
e281682b
SM		 2189};
2190
2191struct mlx5_ifc_roce_addr_layout_bits {
2192 u8 source_l3_address[16][0x8];
2193
b4ff3a36 2194 u8 reserved_at_80[0x3];
e281682b
SM		 2195 u8 vlan_valid[0x1];
2196 u8 vlan_id[0xc];
2197 u8 source_mac_47_32[0x10];
2198
2199 u8 source_mac_31_0[0x20];
2200
b4ff3a36 2201 u8 reserved_at_c0[0x14];
e281682b
SM		 2202 u8 roce_l3_type[0x4];
2203 u8 roce_version[0x8];
2204
b4ff3a36 2205 u8 reserved_at_e0[0x20];
e281682b
SM		 2206};
2207
2208union mlx5_ifc_hca_cap_union_bits {
2209 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2210 struct mlx5_ifc_odp_cap_bits odp_cap;
2211 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2212 struct mlx5_ifc_roce_cap_bits roce_cap;
2213 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2214 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2215 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2216 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2217 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2218 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2219 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2220 u8 reserved_at_0[0x8000];
e281682b
SM		 2221};
2222
2223enum {
2224 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2225 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2226 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2227 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2228 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2229 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2230 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
e281682b
SM		 2231};
2232
2233struct mlx5_ifc_flow_context_bits {
b4ff3a36 2234 u8 reserved_at_0[0x20];
e281682b
SM		 2235
2236 u8 group_id[0x20];
2237
b4ff3a36 2238 u8 reserved_at_40[0x8];
e281682b
SM		 2239 u8 flow_tag[0x18];
2240
b4ff3a36 2241 u8 reserved_at_60[0x10];
e281682b
SM		 2242 u8 action[0x10];
2243
b4ff3a36 2244 u8 reserved_at_80[0x8];
e281682b
SM		 2245 u8 destination_list_size[0x18];
2246
9dc0b289
AV		 2247 u8 reserved_at_a0[0x8];
2248 u8 flow_counter_list_size[0x18];
2249
7adbde20
HHZ		 2250 u8 encap_id[0x20];
2251
2a69cb9f
OG		 2252 u8 modify_header_id[0x20];
2253
2254 u8 reserved_at_100[0x100];
e281682b
SM		 2255
2256 struct mlx5_ifc_fte_match_param_bits match_value;
2257
b4ff3a36 2258 u8 reserved_at_1200[0x600];
e281682b 2259
9dc0b289 2260 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2261};
2262
2263enum {
2264 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2265 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2266};
2267
2268struct mlx5_ifc_xrc_srqc_bits {
2269 u8 state[0x4];
2270 u8 log_xrc_srq_size[0x4];
b4ff3a36 2271 u8 reserved_at_8[0x18];
e281682b
SM		 2272
2273 u8 wq_signature[0x1];
2274 u8 cont_srq[0x1];
b4ff3a36 2275 u8 reserved_at_22[0x1];
e281682b
SM		 2276 u8 rlky[0x1];
2277 u8 basic_cyclic_rcv_wqe[0x1];
2278 u8 log_rq_stride[0x3];
2279 u8 xrcd[0x18];
2280
2281 u8 page_offset[0x6];
b4ff3a36 2282 u8 reserved_at_46[0x2];
e281682b
SM		 2283 u8 cqn[0x18];
2284
b4ff3a36 2285 u8 reserved_at_60[0x20];
e281682b
SM		 2286
2287 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2288 u8 reserved_at_81[0x1];
e281682b
SM		 2289 u8 log_page_size[0x6];
2290 u8 user_index[0x18];
2291
b4ff3a36 2292 u8 reserved_at_a0[0x20];
e281682b 2293
b4ff3a36 2294 u8 reserved_at_c0[0x8];
e281682b
SM		 2295 u8 pd[0x18];
2296
2297 u8 lwm[0x10];
2298 u8 wqe_cnt[0x10];
2299
b4ff3a36 2300 u8 reserved_at_100[0x40];
e281682b
SM		 2301
2302 u8 db_record_addr_h[0x20];
2303
2304 u8 db_record_addr_l[0x1e];
b4ff3a36 2305 u8 reserved_at_17e[0x2];
e281682b 2306
b4ff3a36 2307 u8 reserved_at_180[0x80];
e281682b
SM		 2308};
2309
2310struct mlx5_ifc_traffic_counter_bits {
2311 u8 packets[0x40];
2312
2313 u8 octets[0x40];
2314};
2315
2316struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2317 u8 strict_lag_tx_port_affinity[0x1];
2318 u8 reserved_at_1[0x3];
2319 u8 lag_tx_port_affinity[0x04];
2320
2321 u8 reserved_at_8[0x4];
e281682b 2322 u8 prio[0x4];
b4ff3a36 2323 u8 reserved_at_10[0x10];
e281682b 2324
b4ff3a36 2325 u8 reserved_at_20[0x100];
e281682b 2326
b4ff3a36 2327 u8 reserved_at_120[0x8];
e281682b
SM		 2328 u8 transport_domain[0x18];
2329
500a3d0d
ES		 2330 u8 reserved_at_140[0x8];
2331 u8 underlay_qpn[0x18];
2332 u8 reserved_at_160[0x3a0];
e281682b
SM		 2333};
2334
2335enum {
2336 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2337 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2338};
2339
2340enum {
2341 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2342 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2343};
2344
2345enum {
2be6967c
SM		 2346 MLX5_RX_HASH_FN_NONE = 0x0,
2347 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2348 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2349};
2350
2351enum {
2352 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2353 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2354};
2355
2356struct mlx5_ifc_tirc_bits {
b4ff3a36 2357 u8 reserved_at_0[0x20];
e281682b
SM		 2358
2359 u8 disp_type[0x4];
b4ff3a36 2360 u8 reserved_at_24[0x1c];
e281682b 2361
b4ff3a36 2362 u8 reserved_at_40[0x40];
e281682b 2363
b4ff3a36 2364 u8 reserved_at_80[0x4];
e281682b
SM		 2365 u8 lro_timeout_period_usecs[0x10];
2366 u8 lro_enable_mask[0x4];
2367 u8 lro_max_ip_payload_size[0x8];
2368
b4ff3a36 2369 u8 reserved_at_a0[0x40];
e281682b 2370
b4ff3a36 2371 u8 reserved_at_e0[0x8];
e281682b
SM		 2372 u8 inline_rqn[0x18];
2373
2374 u8 rx_hash_symmetric[0x1];
b4ff3a36 2375 u8 reserved_at_101[0x1];
e281682b 2376 u8 tunneled_offload_en[0x1];
b4ff3a36 2377 u8 reserved_at_103[0x5];
e281682b
SM		 2378 u8 indirect_table[0x18];
2379
2380 u8 rx_hash_fn[0x4];
b4ff3a36 2381 u8 reserved_at_124[0x2];
e281682b
SM		 2382 u8 self_lb_block[0x2];
2383 u8 transport_domain[0x18];
2384
2385 u8 rx_hash_toeplitz_key[10][0x20];
2386
2387 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2388
2389 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2390
b4ff3a36 2391 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2392};
2393
2394enum {
2395 MLX5_SRQC_STATE_GOOD = 0x0,
2396 MLX5_SRQC_STATE_ERROR = 0x1,
2397};
2398
2399struct mlx5_ifc_srqc_bits {
2400 u8 state[0x4];
2401 u8 log_srq_size[0x4];
b4ff3a36 2402 u8 reserved_at_8[0x18];
e281682b
SM		 2403
2404 u8 wq_signature[0x1];
2405 u8 cont_srq[0x1];
b4ff3a36 2406 u8 reserved_at_22[0x1];
e281682b 2407 u8 rlky[0x1];
b4ff3a36 2408 u8 reserved_at_24[0x1];
e281682b
SM		 2409 u8 log_rq_stride[0x3];
2410 u8 xrcd[0x18];
2411
2412 u8 page_offset[0x6];
b4ff3a36 2413 u8 reserved_at_46[0x2];
e281682b
SM		 2414 u8 cqn[0x18];
2415
b4ff3a36 2416 u8 reserved_at_60[0x20];
e281682b 2417
b4ff3a36 2418 u8 reserved_at_80[0x2];
e281682b 2419 u8 log_page_size[0x6];
b4ff3a36 2420 u8 reserved_at_88[0x18];
e281682b 2421
b4ff3a36 2422 u8 reserved_at_a0[0x20];
e281682b 2423
b4ff3a36 2424 u8 reserved_at_c0[0x8];
e281682b
SM		 2425 u8 pd[0x18];
2426
2427 u8 lwm[0x10];
2428 u8 wqe_cnt[0x10];
2429
b4ff3a36 2430 u8 reserved_at_100[0x40];
e281682b 2431
01949d01 2432 u8 dbr_addr[0x40];
e281682b 2433
b4ff3a36 2434 u8 reserved_at_180[0x80];
e281682b
SM		 2435};
2436
2437enum {
2438 MLX5_SQC_STATE_RST = 0x0,
2439 MLX5_SQC_STATE_RDY = 0x1,
2440 MLX5_SQC_STATE_ERR = 0x3,
2441};
2442
2443struct mlx5_ifc_sqc_bits {
2444 u8 rlky[0x1];
2445 u8 cd_master[0x1];
2446 u8 fre[0x1];
2447 u8 flush_in_error_en[0x1];
795b609c 2448 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2449 u8 min_wqe_inline_mode[0x3];
e281682b 2450 u8 state[0x4];
7d5e1423 2451 u8 reg_umr[0x1];
547eede0
IT		 2452 u8 allow_swp[0x1];
2453 u8 reserved_at_e[0x12];
e281682b 2454
b4ff3a36 2455 u8 reserved_at_20[0x8];
e281682b
SM		 2456 u8 user_index[0x18];
2457
b4ff3a36 2458 u8 reserved_at_40[0x8];
e281682b
SM		 2459 u8 cqn[0x18];
2460
7486216b 2461 u8 reserved_at_60[0x90];
e281682b 2462
7486216b 2463 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2464 u8 tis_lst_sz[0x10];
b4ff3a36 2465 u8 reserved_at_110[0x10];
e281682b 2466
b4ff3a36 2467 u8 reserved_at_120[0x40];
e281682b 2468
b4ff3a36 2469 u8 reserved_at_160[0x8];
e281682b
SM		 2470 u8 tis_num_0[0x18];
2471
2472 struct mlx5_ifc_wq_bits wq;
2473};
2474
813f8540
MHY		 2475enum {
2476 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2477 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2478 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2479 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2480};
2481
2482struct mlx5_ifc_scheduling_context_bits {
2483 u8 element_type[0x8];
2484 u8 reserved_at_8[0x18];
2485
2486 u8 element_attributes[0x20];
2487
2488 u8 parent_element_id[0x20];
2489
2490 u8 reserved_at_60[0x40];
2491
2492 u8 bw_share[0x20];
2493
2494 u8 max_average_bw[0x20];
2495
2496 u8 reserved_at_e0[0x120];
2497};
2498
e281682b 2499struct mlx5_ifc_rqtc_bits {
b4ff3a36 2500 u8 reserved_at_0[0xa0];
e281682b 2501
b4ff3a36 2502 u8 reserved_at_a0[0x10];
e281682b
SM		 2503 u8 rqt_max_size[0x10];
2504
b4ff3a36 2505 u8 reserved_at_c0[0x10];
e281682b
SM		 2506 u8 rqt_actual_size[0x10];
2507
b4ff3a36 2508 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2509
2510 struct mlx5_ifc_rq_num_bits rq_num[0];
2511};
2512
2513enum {
2514 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2515 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2516};
2517
2518enum {
2519 MLX5_RQC_STATE_RST = 0x0,
2520 MLX5_RQC_STATE_RDY = 0x1,
2521 MLX5_RQC_STATE_ERR = 0x3,
2522};
2523
2524struct mlx5_ifc_rqc_bits {
2525 u8 rlky[0x1];
03404e8a 2526 u8 delay_drop_en[0x1];
7d5e1423 2527 u8 scatter_fcs[0x1];
e281682b
SM		 2528 u8 vsd[0x1];
2529 u8 mem_rq_type[0x4];
2530 u8 state[0x4];
b4ff3a36 2531 u8 reserved_at_c[0x1];
e281682b 2532 u8 flush_in_error_en[0x1];
b4ff3a36 2533 u8 reserved_at_e[0x12];
e281682b 2534
b4ff3a36 2535 u8 reserved_at_20[0x8];
e281682b
SM		 2536 u8 user_index[0x18];
2537
b4ff3a36 2538 u8 reserved_at_40[0x8];
e281682b
SM		 2539 u8 cqn[0x18];
2540
2541 u8 counter_set_id[0x8];
b4ff3a36 2542 u8 reserved_at_68[0x18];
e281682b 2543
b4ff3a36 2544 u8 reserved_at_80[0x8];
e281682b
SM		 2545 u8 rmpn[0x18];
2546
b4ff3a36 2547 u8 reserved_at_a0[0xe0];
e281682b
SM		 2548
2549 struct mlx5_ifc_wq_bits wq;
2550};
2551
2552enum {
2553 MLX5_RMPC_STATE_RDY = 0x1,
2554 MLX5_RMPC_STATE_ERR = 0x3,
2555};
2556
2557struct mlx5_ifc_rmpc_bits {
b4ff3a36 2558 u8 reserved_at_0[0x8];
e281682b 2559 u8 state[0x4];
b4ff3a36 2560 u8 reserved_at_c[0x14];
e281682b
SM		 2561
2562 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2563 u8 reserved_at_21[0x1f];
e281682b 2564
b4ff3a36 2565 u8 reserved_at_40[0x140];
e281682b
SM		 2566
2567 struct mlx5_ifc_wq_bits wq;
2568};
2569
e281682b 2570struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2571 u8 reserved_at_0[0x5];
2572 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2573 u8 reserved_at_8[0x15];
2574 u8 disable_mc_local_lb[0x1];
2575 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2576 u8 roce_en[0x1];
2577
d82b7318 2578 u8 arm_change_event[0x1];
b4ff3a36 2579 u8 reserved_at_21[0x1a];
d82b7318
SM		 2580 u8 event_on_mtu[0x1];
2581 u8 event_on_promisc_change[0x1];
2582 u8 event_on_vlan_change[0x1];
2583 u8 event_on_mc_address_change[0x1];
2584 u8 event_on_uc_address_change[0x1];
e281682b 2585
b4ff3a36 2586 u8 reserved_at_40[0xf0];
d82b7318
SM		 2587
2588 u8 mtu[0x10];
2589
9efa7525
AS		 2590 u8 system_image_guid[0x40];
2591 u8 port_guid[0x40];
2592 u8 node_guid[0x40];
2593
b4ff3a36 2594 u8 reserved_at_200[0x140];
9efa7525 2595 u8 qkey_violation_counter[0x10];
b4ff3a36 2596 u8 reserved_at_350[0x430];
d82b7318
SM		 2597
2598 u8 promisc_uc[0x1];
2599 u8 promisc_mc[0x1];
2600 u8 promisc_all[0x1];
b4ff3a36 2601 u8 reserved_at_783[0x2];
e281682b 2602 u8 allowed_list_type[0x3];
b4ff3a36 2603 u8 reserved_at_788[0xc];
e281682b
SM		 2604 u8 allowed_list_size[0xc];
2605
2606 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2607
b4ff3a36 2608 u8 reserved_at_7e0[0x20];
e281682b
SM		 2609
2610 u8 current_uc_mac_address[0][0x40];
2611};
2612
2613enum {
2614 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2615 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2616 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2617 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2618};
2619
2620struct mlx5_ifc_mkc_bits {
b4ff3a36 2621 u8 reserved_at_0[0x1];
e281682b 2622 u8 free[0x1];
b4ff3a36 2623 u8 reserved_at_2[0xd];
e281682b
SM		 2624 u8 small_fence_on_rdma_read_response[0x1];
2625 u8 umr_en[0x1];
2626 u8 a[0x1];
2627 u8 rw[0x1];
2628 u8 rr[0x1];
2629 u8 lw[0x1];
2630 u8 lr[0x1];
2631 u8 access_mode[0x2];
b4ff3a36 2632 u8 reserved_at_18[0x8];
e281682b
SM		 2633
2634 u8 qpn[0x18];
2635 u8 mkey_7_0[0x8];
2636
b4ff3a36 2637 u8 reserved_at_40[0x20];
e281682b
SM		 2638
2639 u8 length64[0x1];
2640 u8 bsf_en[0x1];
2641 u8 sync_umr[0x1];
b4ff3a36 2642 u8 reserved_at_63[0x2];
e281682b 2643 u8 expected_sigerr_count[0x1];
b4ff3a36 2644 u8 reserved_at_66[0x1];
e281682b
SM		 2645 u8 en_rinval[0x1];
2646 u8 pd[0x18];
2647
2648 u8 start_addr[0x40];
2649
2650 u8 len[0x40];
2651
2652 u8 bsf_octword_size[0x20];
2653
b4ff3a36 2654 u8 reserved_at_120[0x80];
e281682b
SM		 2655
2656 u8 translations_octword_size[0x20];
2657
b4ff3a36 2658 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2659 u8 log_page_size[0x5];
2660
b4ff3a36 2661 u8 reserved_at_1e0[0x20];
e281682b
SM		 2662};
2663
2664struct mlx5_ifc_pkey_bits {
b4ff3a36 2665 u8 reserved_at_0[0x10];
e281682b
SM		 2666 u8 pkey[0x10];
2667};
2668
2669struct mlx5_ifc_array128_auto_bits {
2670 u8 array128_auto[16][0x8];
2671};
2672
2673struct mlx5_ifc_hca_vport_context_bits {
2674 u8 field_select[0x20];
2675
b4ff3a36 2676 u8 reserved_at_20[0xe0];
e281682b
SM		 2677
2678 u8 sm_virt_aware[0x1];
2679 u8 has_smi[0x1];
2680 u8 has_raw[0x1];
2681 u8 grh_required[0x1];
b4ff3a36 2682 u8 reserved_at_104[0xc];
707c4602
MD		 2683 u8 port_physical_state[0x4];
2684 u8 vport_state_policy[0x4];
2685 u8 port_state[0x4];
e281682b
SM		 2686 u8 vport_state[0x4];
2687
b4ff3a36 2688 u8 reserved_at_120[0x20];
707c4602
MD		 2689
2690 u8 system_image_guid[0x40];
e281682b
SM		 2691
2692 u8 port_guid[0x40];
2693
2694 u8 node_guid[0x40];
2695
2696 u8 cap_mask1[0x20];
2697
2698 u8 cap_mask1_field_select[0x20];
2699
2700 u8 cap_mask2[0x20];
2701
2702 u8 cap_mask2_field_select[0x20];
2703
b4ff3a36 2704 u8 reserved_at_280[0x80];
e281682b
SM		 2705
2706 u8 lid[0x10];
b4ff3a36 2707 u8 reserved_at_310[0x4];
e281682b
SM		 2708 u8 init_type_reply[0x4];
2709 u8 lmc[0x3];
2710 u8 subnet_timeout[0x5];
2711
2712 u8 sm_lid[0x10];
2713 u8 sm_sl[0x4];
b4ff3a36 2714 u8 reserved_at_334[0xc];
e281682b
SM		 2715
2716 u8 qkey_violation_counter[0x10];
2717 u8 pkey_violation_counter[0x10];
2718
b4ff3a36 2719 u8 reserved_at_360[0xca0];
e281682b
SM		 2720};
2721
d6666753 2722struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2723 u8 reserved_at_0[0x3];
d6666753
SM		 2724 u8 vport_svlan_strip[0x1];
2725 u8 vport_cvlan_strip[0x1];
2726 u8 vport_svlan_insert[0x1];
2727 u8 vport_cvlan_insert[0x2];
b4ff3a36 2728 u8 reserved_at_8[0x18];
d6666753 2729
b4ff3a36 2730 u8 reserved_at_20[0x20];
d6666753
SM		 2731
2732 u8 svlan_cfi[0x1];
2733 u8 svlan_pcp[0x3];
2734 u8 svlan_id[0xc];
2735 u8 cvlan_cfi[0x1];
2736 u8 cvlan_pcp[0x3];
2737 u8 cvlan_id[0xc];
2738
b4ff3a36 2739 u8 reserved_at_60[0x7a0];
d6666753
SM		 2740};
2741
e281682b
SM		 2742enum {
2743 MLX5_EQC_STATUS_OK = 0x0,
2744 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2745};
2746
2747enum {
2748 MLX5_EQC_ST_ARMED = 0x9,
2749 MLX5_EQC_ST_FIRED = 0xa,
2750};
2751
2752struct mlx5_ifc_eqc_bits {
2753 u8 status[0x4];
b4ff3a36 2754 u8 reserved_at_4[0x9];
e281682b
SM		 2755 u8 ec[0x1];
2756 u8 oi[0x1];
b4ff3a36 2757 u8 reserved_at_f[0x5];
e281682b 2758 u8 st[0x4];
b4ff3a36 2759 u8 reserved_at_18[0x8];
e281682b 2760
b4ff3a36 2761 u8 reserved_at_20[0x20];
e281682b 2762
b4ff3a36 2763 u8 reserved_at_40[0x14];
e281682b 2764 u8 page_offset[0x6];
b4ff3a36 2765 u8 reserved_at_5a[0x6];
e281682b 2766
b4ff3a36 2767 u8 reserved_at_60[0x3];
e281682b
SM		 2768 u8 log_eq_size[0x5];
2769 u8 uar_page[0x18];
2770
b4ff3a36 2771 u8 reserved_at_80[0x20];
e281682b 2772
b4ff3a36 2773 u8 reserved_at_a0[0x18];
e281682b
SM		 2774 u8 intr[0x8];
2775
b4ff3a36 2776 u8 reserved_at_c0[0x3];
e281682b 2777 u8 log_page_size[0x5];
b4ff3a36 2778 u8 reserved_at_c8[0x18];
e281682b 2779
b4ff3a36 2780 u8 reserved_at_e0[0x60];
e281682b 2781
b4ff3a36 2782 u8 reserved_at_140[0x8];
e281682b
SM		 2783 u8 consumer_counter[0x18];
2784
b4ff3a36 2785 u8 reserved_at_160[0x8];
e281682b
SM		 2786 u8 producer_counter[0x18];
2787
b4ff3a36 2788 u8 reserved_at_180[0x80];
e281682b
SM		 2789};
2790
2791enum {
2792 MLX5_DCTC_STATE_ACTIVE = 0x0,
2793 MLX5_DCTC_STATE_DRAINING = 0x1,
2794 MLX5_DCTC_STATE_DRAINED = 0x2,
2795};
2796
2797enum {
2798 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2799 MLX5_DCTC_CS_RES_NA = 0x1,
2800 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2801};
2802
2803enum {
2804 MLX5_DCTC_MTU_256_BYTES = 0x1,
2805 MLX5_DCTC_MTU_512_BYTES = 0x2,
2806 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2807 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2808 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2809};
2810
2811struct mlx5_ifc_dctc_bits {
b4ff3a36 2812 u8 reserved_at_0[0x4];
e281682b 2813 u8 state[0x4];
b4ff3a36 2814 u8 reserved_at_8[0x18];
e281682b 2815
b4ff3a36 2816 u8 reserved_at_20[0x8];
e281682b
SM		 2817 u8 user_index[0x18];
2818
b4ff3a36 2819 u8 reserved_at_40[0x8];
e281682b
SM		 2820 u8 cqn[0x18];
2821
2822 u8 counter_set_id[0x8];
2823 u8 atomic_mode[0x4];
2824 u8 rre[0x1];
2825 u8 rwe[0x1];
2826 u8 rae[0x1];
2827 u8 atomic_like_write_en[0x1];
2828 u8 latency_sensitive[0x1];
2829 u8 rlky[0x1];
2830 u8 free_ar[0x1];
b4ff3a36 2831 u8 reserved_at_73[0xd];
e281682b 2832
b4ff3a36 2833 u8 reserved_at_80[0x8];
e281682b 2834 u8 cs_res[0x8];
b4ff3a36 2835 u8 reserved_at_90[0x3];
e281682b 2836 u8 min_rnr_nak[0x5];
b4ff3a36 2837 u8 reserved_at_98[0x8];
e281682b 2838
b4ff3a36 2839 u8 reserved_at_a0[0x8];
7486216b 2840 u8 srqn_xrqn[0x18];
e281682b 2841
b4ff3a36 2842 u8 reserved_at_c0[0x8];
e281682b
SM		 2843 u8 pd[0x18];
2844
2845 u8 tclass[0x8];
b4ff3a36 2846 u8 reserved_at_e8[0x4];
e281682b
SM		 2847 u8 flow_label[0x14];
2848
2849 u8 dc_access_key[0x40];
2850
b4ff3a36 2851 u8 reserved_at_140[0x5];
e281682b
SM		 2852 u8 mtu[0x3];
2853 u8 port[0x8];
2854 u8 pkey_index[0x10];
2855
b4ff3a36 2856 u8 reserved_at_160[0x8];
e281682b 2857 u8 my_addr_index[0x8];
b4ff3a36 2858 u8 reserved_at_170[0x8];
e281682b
SM		 2859 u8 hop_limit[0x8];
2860
2861 u8 dc_access_key_violation_count[0x20];
2862
b4ff3a36 2863 u8 reserved_at_1a0[0x14];
e281682b
SM		 2864 u8 dei_cfi[0x1];
2865 u8 eth_prio[0x3];
2866 u8 ecn[0x2];
2867 u8 dscp[0x6];
2868
b4ff3a36 2869 u8 reserved_at_1c0[0x40];
e281682b
SM		 2870};
2871
2872enum {
2873 MLX5_CQC_STATUS_OK = 0x0,
2874 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2875 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2876};
2877
2878enum {
2879 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2880 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2881};
2882
2883enum {
2884 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2885 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2886 MLX5_CQC_ST_FIRED = 0xa,
2887};
2888
7d5e1423
SM		 2889enum {
2890 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2891 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2892 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2893};
2894
e281682b
SM		 2895struct mlx5_ifc_cqc_bits {
2896 u8 status[0x4];
b4ff3a36 2897 u8 reserved_at_4[0x4];
e281682b
SM		 2898 u8 cqe_sz[0x3];
2899 u8 cc[0x1];
b4ff3a36 2900 u8 reserved_at_c[0x1];
e281682b
SM		 2901 u8 scqe_break_moderation_en[0x1];
2902 u8 oi[0x1];
7d5e1423
SM		 2903 u8 cq_period_mode[0x2];
2904 u8 cqe_comp_en[0x1];
e281682b
SM		 2905 u8 mini_cqe_res_format[0x2];
2906 u8 st[0x4];
b4ff3a36 2907 u8 reserved_at_18[0x8];
e281682b 2908
b4ff3a36 2909 u8 reserved_at_20[0x20];
e281682b 2910
b4ff3a36 2911 u8 reserved_at_40[0x14];
e281682b 2912 u8 page_offset[0x6];
b4ff3a36 2913 u8 reserved_at_5a[0x6];
e281682b 2914
b4ff3a36 2915 u8 reserved_at_60[0x3];
e281682b
SM		 2916 u8 log_cq_size[0x5];
2917 u8 uar_page[0x18];
2918
b4ff3a36 2919 u8 reserved_at_80[0x4];
e281682b
SM		 2920 u8 cq_period[0xc];
2921 u8 cq_max_count[0x10];
2922
b4ff3a36 2923 u8 reserved_at_a0[0x18];
e281682b
SM		 2924 u8 c_eqn[0x8];
2925
b4ff3a36 2926 u8 reserved_at_c0[0x3];
e281682b 2927 u8 log_page_size[0x5];
b4ff3a36 2928 u8 reserved_at_c8[0x18];
e281682b 2929
b4ff3a36 2930 u8 reserved_at_e0[0x20];
e281682b 2931
b4ff3a36 2932 u8 reserved_at_100[0x8];
e281682b
SM		 2933 u8 last_notified_index[0x18];
2934
b4ff3a36 2935 u8 reserved_at_120[0x8];
e281682b
SM		 2936 u8 last_solicit_index[0x18];
2937
b4ff3a36 2938 u8 reserved_at_140[0x8];
e281682b
SM		 2939 u8 consumer_counter[0x18];
2940
b4ff3a36 2941 u8 reserved_at_160[0x8];
e281682b
SM		 2942 u8 producer_counter[0x18];
2943
b4ff3a36 2944 u8 reserved_at_180[0x40];
e281682b
SM		 2945
2946 u8 dbr_addr[0x40];
2947};
2948
2949union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2950 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2951 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2952 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2953 u8 reserved_at_0[0x800];
e281682b
SM		 2954};
2955
2956struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2957 u8 reserved_at_0[0xc0];
e281682b 2958
b4ff3a36 2959 u8 reserved_at_c0[0x8];
211e6c80
MD		 2960 u8 ieee_vendor_id[0x18];
2961
b4ff3a36 2962 u8 reserved_at_e0[0x10];
e281682b
SM		 2963 u8 vsd_vendor_id[0x10];
2964
2965 u8 vsd[208][0x8];
2966
2967 u8 vsd_contd_psid[16][0x8];
2968};
2969
7486216b
SM		 2970enum {
2971 MLX5_XRQC_STATE_GOOD = 0x0,
2972 MLX5_XRQC_STATE_ERROR = 0x1,
2973};
2974
2975enum {
2976 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2977 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2978};
2979
2980enum {
2981 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2982};
2983
2984struct mlx5_ifc_tag_matching_topology_context_bits {
2985 u8 log_matching_list_sz[0x4];
2986 u8 reserved_at_4[0xc];
2987 u8 append_next_index[0x10];
2988
2989 u8 sw_phase_cnt[0x10];
2990 u8 hw_phase_cnt[0x10];
2991
2992 u8 reserved_at_40[0x40];
2993};
2994
2995struct mlx5_ifc_xrqc_bits {
2996 u8 state[0x4];
2997 u8 rlkey[0x1];
2998 u8 reserved_at_5[0xf];
2999 u8 topology[0x4];
3000 u8 reserved_at_18[0x4];
3001 u8 offload[0x4];
3002
3003 u8 reserved_at_20[0x8];
3004 u8 user_index[0x18];
3005
3006 u8 reserved_at_40[0x8];
3007 u8 cqn[0x18];
3008
3009 u8 reserved_at_60[0xa0];
3010
3011 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3012
5579e151 3013 u8 reserved_at_180[0x880];
7486216b
SM		 3014
3015 struct mlx5_ifc_wq_bits wq;
3016};
3017
e281682b
SM		 3018union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3019 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3020 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3021 u8 reserved_at_0[0x20];
e281682b
SM		 3022};
3023
3024union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3025 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3026 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3027 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3028 u8 reserved_at_0[0x20];
e281682b
SM		 3029};
3030
3031union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3032 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3033 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3034 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3035 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3036 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3037 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3038 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3039 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3040 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3041 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3042 u8 reserved_at_0[0x7c0];
e281682b
SM		 3043};
3044
8ed1a630
GP		 3045union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3046 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3047 u8 reserved_at_0[0x7c0];
3048};
3049
e281682b
SM		 3050union mlx5_ifc_event_auto_bits {
3051 struct mlx5_ifc_comp_event_bits comp_event;
3052 struct mlx5_ifc_dct_events_bits dct_events;
3053 struct mlx5_ifc_qp_events_bits qp_events;
3054 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3055 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3056 struct mlx5_ifc_cq_error_bits cq_error;
3057 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3058 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3059 struct mlx5_ifc_gpio_event_bits gpio_event;
3060 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3061 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3062 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3063 u8 reserved_at_0[0xe0];
e281682b
SM		 3064};
3065
3066struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3067 u8 reserved_at_0[0x100];
e281682b
SM		 3068
3069 u8 assert_existptr[0x20];
3070
3071 u8 assert_callra[0x20];
3072
b4ff3a36 3073 u8 reserved_at_140[0x40];
e281682b
SM		 3074
3075 u8 fw_version[0x20];
3076
3077 u8 hw_id[0x20];
3078
b4ff3a36 3079 u8 reserved_at_1c0[0x20];
e281682b
SM		 3080
3081 u8 irisc_index[0x8];
3082 u8 synd[0x8];
3083 u8 ext_synd[0x10];
3084};
3085
3086struct mlx5_ifc_register_loopback_control_bits {
3087 u8 no_lb[0x1];
b4ff3a36 3088 u8 reserved_at_1[0x7];
e281682b 3089 u8 port[0x8];
b4ff3a36 3090 u8 reserved_at_10[0x10];
e281682b 3091
b4ff3a36 3092 u8 reserved_at_20[0x60];
e281682b
SM		 3093};
3094
813f8540
MHY		 3095struct mlx5_ifc_vport_tc_element_bits {
3096 u8 traffic_class[0x4];
3097 u8 reserved_at_4[0xc];
3098 u8 vport_number[0x10];
3099};
3100
3101struct mlx5_ifc_vport_element_bits {
3102 u8 reserved_at_0[0x10];
3103 u8 vport_number[0x10];
3104};
3105
3106enum {
3107 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3108 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3109 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3110};
3111
3112struct mlx5_ifc_tsar_element_bits {
3113 u8 reserved_at_0[0x8];
3114 u8 tsar_type[0x8];
3115 u8 reserved_at_10[0x10];
3116};
3117
8812c24d
MD		 3118enum {
3119 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3120 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3121};
3122
e281682b
SM		 3123struct mlx5_ifc_teardown_hca_out_bits {
3124 u8 status[0x8];
b4ff3a36 3125 u8 reserved_at_8[0x18];
e281682b
SM		 3126
3127 u8 syndrome[0x20];
3128
8812c24d
MD		 3129 u8 reserved_at_40[0x3f];
3130
3131 u8 force_state[0x1];
e281682b
SM		 3132};
3133
3134enum {
3135 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3136 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3137};
3138
3139struct mlx5_ifc_teardown_hca_in_bits {
3140 u8 opcode[0x10];
b4ff3a36 3141 u8 reserved_at_10[0x10];
e281682b 3142
b4ff3a36 3143 u8 reserved_at_20[0x10];
e281682b
SM		 3144 u8 op_mod[0x10];
3145
b4ff3a36 3146 u8 reserved_at_40[0x10];
e281682b
SM		 3147 u8 profile[0x10];
3148
b4ff3a36 3149 u8 reserved_at_60[0x20];
e281682b
SM		 3150};
3151
3152struct mlx5_ifc_sqerr2rts_qp_out_bits {
3153 u8 status[0x8];
b4ff3a36 3154 u8 reserved_at_8[0x18];
e281682b
SM		 3155
3156 u8 syndrome[0x20];
3157
b4ff3a36 3158 u8 reserved_at_40[0x40];
e281682b
SM		 3159};
3160
3161struct mlx5_ifc_sqerr2rts_qp_in_bits {
3162 u8 opcode[0x10];
b4ff3a36 3163 u8 reserved_at_10[0x10];
e281682b 3164
b4ff3a36 3165 u8 reserved_at_20[0x10];
e281682b
SM		 3166 u8 op_mod[0x10];
3167
b4ff3a36 3168 u8 reserved_at_40[0x8];
e281682b
SM		 3169 u8 qpn[0x18];
3170
b4ff3a36 3171 u8 reserved_at_60[0x20];
e281682b
SM		 3172
3173 u8 opt_param_mask[0x20];
3174
b4ff3a36 3175 u8 reserved_at_a0[0x20];
e281682b
SM		 3176
3177 struct mlx5_ifc_qpc_bits qpc;
3178
b4ff3a36 3179 u8 reserved_at_800[0x80];
e281682b
SM		 3180};
3181
3182struct mlx5_ifc_sqd2rts_qp_out_bits {
3183 u8 status[0x8];
b4ff3a36 3184 u8 reserved_at_8[0x18];
e281682b
SM		 3185
3186 u8 syndrome[0x20];
3187
b4ff3a36 3188 u8 reserved_at_40[0x40];
e281682b
SM		 3189};
3190
3191struct mlx5_ifc_sqd2rts_qp_in_bits {
3192 u8 opcode[0x10];
b4ff3a36 3193 u8 reserved_at_10[0x10];
e281682b 3194
b4ff3a36 3195 u8 reserved_at_20[0x10];
e281682b
SM		 3196 u8 op_mod[0x10];
3197
b4ff3a36 3198 u8 reserved_at_40[0x8];
e281682b
SM		 3199 u8 qpn[0x18];
3200
b4ff3a36 3201 u8 reserved_at_60[0x20];
e281682b
SM		 3202
3203 u8 opt_param_mask[0x20];
3204
b4ff3a36 3205 u8 reserved_at_a0[0x20];
e281682b
SM		 3206
3207 struct mlx5_ifc_qpc_bits qpc;
3208
b4ff3a36 3209 u8 reserved_at_800[0x80];
e281682b
SM		 3210};
3211
3212struct mlx5_ifc_set_roce_address_out_bits {
3213 u8 status[0x8];
b4ff3a36 3214 u8 reserved_at_8[0x18];
e281682b
SM		 3215
3216 u8 syndrome[0x20];
3217
b4ff3a36 3218 u8 reserved_at_40[0x40];
e281682b
SM		 3219};
3220
3221struct mlx5_ifc_set_roce_address_in_bits {
3222 u8 opcode[0x10];
b4ff3a36 3223 u8 reserved_at_10[0x10];
e281682b 3224
b4ff3a36 3225 u8 reserved_at_20[0x10];
e281682b
SM		 3226 u8 op_mod[0x10];
3227
3228 u8 roce_address_index[0x10];
b4ff3a36 3229 u8 reserved_at_50[0x10];
e281682b 3230
b4ff3a36 3231 u8 reserved_at_60[0x20];
e281682b
SM		 3232
3233 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3234};
3235
3236struct mlx5_ifc_set_mad_demux_out_bits {
3237 u8 status[0x8];
b4ff3a36 3238 u8 reserved_at_8[0x18];
e281682b
SM		 3239
3240 u8 syndrome[0x20];
3241
b4ff3a36 3242 u8 reserved_at_40[0x40];
e281682b
SM		 3243};
3244
3245enum {
3246 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3247 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3248};
3249
3250struct mlx5_ifc_set_mad_demux_in_bits {
3251 u8 opcode[0x10];
b4ff3a36 3252 u8 reserved_at_10[0x10];
e281682b 3253
b4ff3a36 3254 u8 reserved_at_20[0x10];
e281682b
SM		 3255 u8 op_mod[0x10];
3256
b4ff3a36 3257 u8 reserved_at_40[0x20];
e281682b 3258
b4ff3a36 3259 u8 reserved_at_60[0x6];
e281682b 3260 u8 demux_mode[0x2];
b4ff3a36 3261 u8 reserved_at_68[0x18];
e281682b
SM		 3262};
3263
3264struct mlx5_ifc_set_l2_table_entry_out_bits {
3265 u8 status[0x8];
b4ff3a36 3266 u8 reserved_at_8[0x18];
e281682b
SM		 3267
3268 u8 syndrome[0x20];
3269
b4ff3a36 3270 u8 reserved_at_40[0x40];
e281682b
SM		 3271};
3272
3273struct mlx5_ifc_set_l2_table_entry_in_bits {
3274 u8 opcode[0x10];
b4ff3a36 3275 u8 reserved_at_10[0x10];
e281682b 3276
b4ff3a36 3277 u8 reserved_at_20[0x10];
e281682b
SM		 3278 u8 op_mod[0x10];
3279
b4ff3a36 3280 u8 reserved_at_40[0x60];
e281682b 3281
b4ff3a36 3282 u8 reserved_at_a0[0x8];
e281682b
SM		 3283 u8 table_index[0x18];
3284
b4ff3a36 3285 u8 reserved_at_c0[0x20];
e281682b 3286
b4ff3a36 3287 u8 reserved_at_e0[0x13];
e281682b
SM		 3288 u8 vlan_valid[0x1];
3289 u8 vlan[0xc];
3290
3291 struct mlx5_ifc_mac_address_layout_bits mac_address;
3292
b4ff3a36 3293 u8 reserved_at_140[0xc0];
e281682b
SM		 3294};
3295
3296struct mlx5_ifc_set_issi_out_bits {
3297 u8 status[0x8];
b4ff3a36 3298 u8 reserved_at_8[0x18];
e281682b
SM		 3299
3300 u8 syndrome[0x20];
3301
b4ff3a36 3302 u8 reserved_at_40[0x40];
e281682b
SM		 3303};
3304
3305struct mlx5_ifc_set_issi_in_bits {
3306 u8 opcode[0x10];
b4ff3a36 3307 u8 reserved_at_10[0x10];
e281682b 3308
b4ff3a36 3309 u8 reserved_at_20[0x10];
e281682b
SM		 3310 u8 op_mod[0x10];
3311
b4ff3a36 3312 u8 reserved_at_40[0x10];
e281682b
SM		 3313 u8 current_issi[0x10];
3314
b4ff3a36 3315 u8 reserved_at_60[0x20];
e281682b
SM		 3316};
3317
3318struct mlx5_ifc_set_hca_cap_out_bits {
3319 u8 status[0x8];
b4ff3a36 3320 u8 reserved_at_8[0x18];
e281682b
SM		 3321
3322 u8 syndrome[0x20];
3323
b4ff3a36 3324 u8 reserved_at_40[0x40];
e281682b
SM		 3325};
3326
3327struct mlx5_ifc_set_hca_cap_in_bits {
3328 u8 opcode[0x10];
b4ff3a36 3329 u8 reserved_at_10[0x10];
e281682b 3330
b4ff3a36 3331 u8 reserved_at_20[0x10];
e281682b
SM		 3332 u8 op_mod[0x10];
3333
b4ff3a36 3334 u8 reserved_at_40[0x40];
e281682b
SM		 3335
3336 union mlx5_ifc_hca_cap_union_bits capability;
3337};
3338
26a81453
MG		 3339enum {
3340 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3341 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3342 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3343 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3344};
3345
e281682b
SM		 3346struct mlx5_ifc_set_fte_out_bits {
3347 u8 status[0x8];
b4ff3a36 3348 u8 reserved_at_8[0x18];
e281682b
SM		 3349
3350 u8 syndrome[0x20];
3351
b4ff3a36 3352 u8 reserved_at_40[0x40];
e281682b
SM		 3353};
3354
3355struct mlx5_ifc_set_fte_in_bits {
3356 u8 opcode[0x10];
b4ff3a36 3357 u8 reserved_at_10[0x10];
e281682b 3358
b4ff3a36 3359 u8 reserved_at_20[0x10];
e281682b
SM		 3360 u8 op_mod[0x10];
3361
7d5e1423
SM		 3362 u8 other_vport[0x1];
3363 u8 reserved_at_41[0xf];
3364 u8 vport_number[0x10];
3365
3366 u8 reserved_at_60[0x20];
e281682b
SM		 3367
3368 u8 table_type[0x8];
b4ff3a36 3369 u8 reserved_at_88[0x18];
e281682b 3370
b4ff3a36 3371 u8 reserved_at_a0[0x8];
e281682b
SM		 3372 u8 table_id[0x18];
3373
b4ff3a36 3374 u8 reserved_at_c0[0x18];
26a81453
MG		 3375 u8 modify_enable_mask[0x8];
3376
b4ff3a36 3377 u8 reserved_at_e0[0x20];
e281682b
SM		 3378
3379 u8 flow_index[0x20];
3380
b4ff3a36 3381 u8 reserved_at_120[0xe0];
e281682b
SM		 3382
3383 struct mlx5_ifc_flow_context_bits flow_context;
3384};
3385
3386struct mlx5_ifc_rts2rts_qp_out_bits {
3387 u8 status[0x8];
b4ff3a36 3388 u8 reserved_at_8[0x18];
e281682b
SM		 3389
3390 u8 syndrome[0x20];
3391
b4ff3a36 3392 u8 reserved_at_40[0x40];
e281682b
SM		 3393};
3394
3395struct mlx5_ifc_rts2rts_qp_in_bits {
3396 u8 opcode[0x10];
b4ff3a36 3397 u8 reserved_at_10[0x10];
e281682b 3398
b4ff3a36 3399 u8 reserved_at_20[0x10];
e281682b
SM		 3400 u8 op_mod[0x10];
3401
b4ff3a36 3402 u8 reserved_at_40[0x8];
e281682b
SM		 3403 u8 qpn[0x18];
3404
b4ff3a36 3405 u8 reserved_at_60[0x20];
e281682b
SM		 3406
3407 u8 opt_param_mask[0x20];
3408
b4ff3a36 3409 u8 reserved_at_a0[0x20];
e281682b
SM		 3410
3411 struct mlx5_ifc_qpc_bits qpc;
3412
b4ff3a36 3413 u8 reserved_at_800[0x80];
e281682b
SM		 3414};
3415
3416struct mlx5_ifc_rtr2rts_qp_out_bits {
3417 u8 status[0x8];
b4ff3a36 3418 u8 reserved_at_8[0x18];
e281682b
SM		 3419
3420 u8 syndrome[0x20];
3421
b4ff3a36 3422 u8 reserved_at_40[0x40];
e281682b
SM		 3423};
3424
3425struct mlx5_ifc_rtr2rts_qp_in_bits {
3426 u8 opcode[0x10];
b4ff3a36 3427 u8 reserved_at_10[0x10];
e281682b 3428
b4ff3a36 3429 u8 reserved_at_20[0x10];
e281682b
SM		 3430 u8 op_mod[0x10];
3431
b4ff3a36 3432 u8 reserved_at_40[0x8];
e281682b
SM		 3433 u8 qpn[0x18];
3434
b4ff3a36 3435 u8 reserved_at_60[0x20];
e281682b
SM		 3436
3437 u8 opt_param_mask[0x20];
3438
b4ff3a36 3439 u8 reserved_at_a0[0x20];
e281682b
SM		 3440
3441 struct mlx5_ifc_qpc_bits qpc;
3442
b4ff3a36 3443 u8 reserved_at_800[0x80];
e281682b
SM		 3444};
3445
3446struct mlx5_ifc_rst2init_qp_out_bits {
3447 u8 status[0x8];
b4ff3a36 3448 u8 reserved_at_8[0x18];
e281682b
SM		 3449
3450 u8 syndrome[0x20];
3451
b4ff3a36 3452 u8 reserved_at_40[0x40];
e281682b
SM		 3453};
3454
3455struct mlx5_ifc_rst2init_qp_in_bits {
3456 u8 opcode[0x10];
b4ff3a36 3457 u8 reserved_at_10[0x10];
e281682b 3458
b4ff3a36 3459 u8 reserved_at_20[0x10];
e281682b
SM		 3460 u8 op_mod[0x10];
3461
b4ff3a36 3462 u8 reserved_at_40[0x8];
e281682b
SM		 3463 u8 qpn[0x18];
3464
b4ff3a36 3465 u8 reserved_at_60[0x20];
e281682b
SM		 3466
3467 u8 opt_param_mask[0x20];
3468
b4ff3a36 3469 u8 reserved_at_a0[0x20];
e281682b
SM		 3470
3471 struct mlx5_ifc_qpc_bits qpc;
3472
b4ff3a36 3473 u8 reserved_at_800[0x80];
e281682b
SM		 3474};
3475
7486216b
SM		 3476struct mlx5_ifc_query_xrq_out_bits {
3477 u8 status[0x8];
3478 u8 reserved_at_8[0x18];
3479
3480 u8 syndrome[0x20];
3481
3482 u8 reserved_at_40[0x40];
3483
3484 struct mlx5_ifc_xrqc_bits xrq_context;
3485};
3486
3487struct mlx5_ifc_query_xrq_in_bits {
3488 u8 opcode[0x10];
3489 u8 reserved_at_10[0x10];
3490
3491 u8 reserved_at_20[0x10];
3492 u8 op_mod[0x10];
3493
3494 u8 reserved_at_40[0x8];
3495 u8 xrqn[0x18];
3496
3497 u8 reserved_at_60[0x20];
3498};
3499
e281682b
SM		 3500struct mlx5_ifc_query_xrc_srq_out_bits {
3501 u8 status[0x8];
b4ff3a36 3502 u8 reserved_at_8[0x18];
e281682b
SM		 3503
3504 u8 syndrome[0x20];
3505
b4ff3a36 3506 u8 reserved_at_40[0x40];
e281682b
SM		 3507
3508 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3509
b4ff3a36 3510 u8 reserved_at_280[0x600];
e281682b
SM		 3511
3512 u8 pas[0][0x40];
3513};
3514
3515struct mlx5_ifc_query_xrc_srq_in_bits {
3516 u8 opcode[0x10];
b4ff3a36 3517 u8 reserved_at_10[0x10];
e281682b 3518
b4ff3a36 3519 u8 reserved_at_20[0x10];
e281682b
SM		 3520 u8 op_mod[0x10];
3521
b4ff3a36 3522 u8 reserved_at_40[0x8];
e281682b
SM		 3523 u8 xrc_srqn[0x18];
3524
b4ff3a36 3525 u8 reserved_at_60[0x20];
e281682b
SM		 3526};
3527
3528enum {
3529 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3530 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3531};
3532
3533struct mlx5_ifc_query_vport_state_out_bits {
3534 u8 status[0x8];
b4ff3a36 3535 u8 reserved_at_8[0x18];
e281682b
SM		 3536
3537 u8 syndrome[0x20];
3538
b4ff3a36 3539 u8 reserved_at_40[0x20];
e281682b 3540
b4ff3a36 3541 u8 reserved_at_60[0x18];
e281682b
SM		 3542 u8 admin_state[0x4];
3543 u8 state[0x4];
3544};
3545
3546enum {
3547 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3548 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3549};
3550
3551struct mlx5_ifc_query_vport_state_in_bits {
3552 u8 opcode[0x10];
b4ff3a36 3553 u8 reserved_at_10[0x10];
e281682b 3554
b4ff3a36 3555 u8 reserved_at_20[0x10];
e281682b
SM		 3556 u8 op_mod[0x10];
3557
3558 u8 other_vport[0x1];
b4ff3a36 3559 u8 reserved_at_41[0xf];
e281682b
SM		 3560 u8 vport_number[0x10];
3561
b4ff3a36 3562 u8 reserved_at_60[0x20];
e281682b
SM		 3563};
3564
3565struct mlx5_ifc_query_vport_counter_out_bits {
3566 u8 status[0x8];
b4ff3a36 3567 u8 reserved_at_8[0x18];
e281682b
SM		 3568
3569 u8 syndrome[0x20];
3570
b4ff3a36 3571 u8 reserved_at_40[0x40];
e281682b
SM		 3572
3573 struct mlx5_ifc_traffic_counter_bits received_errors;
3574
3575 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3576
3577 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3578
3579 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3580
3581 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3582
3583 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3584
3585 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3586
3587 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3588
3589 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3590
3591 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3592
3593 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3594
3595 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3596
b4ff3a36 3597 u8 reserved_at_680[0xa00];
e281682b
SM		 3598};
3599
3600enum {
3601 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3602};
3603
3604struct mlx5_ifc_query_vport_counter_in_bits {
3605 u8 opcode[0x10];
b4ff3a36 3606 u8 reserved_at_10[0x10];
e281682b 3607
b4ff3a36 3608 u8 reserved_at_20[0x10];
e281682b
SM		 3609 u8 op_mod[0x10];
3610
3611 u8 other_vport[0x1];
b54ba277
MY		 3612 u8 reserved_at_41[0xb];
3613 u8 port_num[0x4];
e281682b
SM		 3614 u8 vport_number[0x10];
3615
b4ff3a36 3616 u8 reserved_at_60[0x60];
e281682b
SM		 3617
3618 u8 clear[0x1];
b4ff3a36 3619 u8 reserved_at_c1[0x1f];
e281682b 3620
b4ff3a36 3621 u8 reserved_at_e0[0x20];
e281682b
SM		 3622};
3623
3624struct mlx5_ifc_query_tis_out_bits {
3625 u8 status[0x8];
b4ff3a36 3626 u8 reserved_at_8[0x18];
e281682b
SM		 3627
3628 u8 syndrome[0x20];
3629
b4ff3a36 3630 u8 reserved_at_40[0x40];
e281682b
SM		 3631
3632 struct mlx5_ifc_tisc_bits tis_context;
3633};
3634
3635struct mlx5_ifc_query_tis_in_bits {
3636 u8 opcode[0x10];
b4ff3a36 3637 u8 reserved_at_10[0x10];
e281682b 3638
b4ff3a36 3639 u8 reserved_at_20[0x10];
e281682b
SM		 3640 u8 op_mod[0x10];
3641
b4ff3a36 3642 u8 reserved_at_40[0x8];
e281682b
SM		 3643 u8 tisn[0x18];
3644
b4ff3a36 3645 u8 reserved_at_60[0x20];
e281682b
SM		 3646};
3647
3648struct mlx5_ifc_query_tir_out_bits {
3649 u8 status[0x8];
b4ff3a36 3650 u8 reserved_at_8[0x18];
e281682b
SM		 3651
3652 u8 syndrome[0x20];
3653
b4ff3a36 3654 u8 reserved_at_40[0xc0];
e281682b
SM		 3655
3656 struct mlx5_ifc_tirc_bits tir_context;
3657};
3658
3659struct mlx5_ifc_query_tir_in_bits {
3660 u8 opcode[0x10];
b4ff3a36 3661 u8 reserved_at_10[0x10];
e281682b 3662
b4ff3a36 3663 u8 reserved_at_20[0x10];
e281682b
SM		 3664 u8 op_mod[0x10];
3665
b4ff3a36 3666 u8 reserved_at_40[0x8];
e281682b
SM		 3667 u8 tirn[0x18];
3668
b4ff3a36 3669 u8 reserved_at_60[0x20];
e281682b
SM		 3670};
3671
3672struct mlx5_ifc_query_srq_out_bits {
3673 u8 status[0x8];
b4ff3a36 3674 u8 reserved_at_8[0x18];
e281682b
SM		 3675
3676 u8 syndrome[0x20];
3677
b4ff3a36 3678 u8 reserved_at_40[0x40];
e281682b
SM		 3679
3680 struct mlx5_ifc_srqc_bits srq_context_entry;
3681
b4ff3a36 3682 u8 reserved_at_280[0x600];
e281682b
SM		 3683
3684 u8 pas[0][0x40];
3685};
3686
3687struct mlx5_ifc_query_srq_in_bits {
3688 u8 opcode[0x10];
b4ff3a36 3689 u8 reserved_at_10[0x10];
e281682b 3690
b4ff3a36 3691 u8 reserved_at_20[0x10];
e281682b
SM		 3692 u8 op_mod[0x10];
3693
b4ff3a36 3694 u8 reserved_at_40[0x8];
e281682b
SM		 3695 u8 srqn[0x18];
3696
b4ff3a36 3697 u8 reserved_at_60[0x20];
e281682b
SM		 3698};
3699
3700struct mlx5_ifc_query_sq_out_bits {
3701 u8 status[0x8];
b4ff3a36 3702 u8 reserved_at_8[0x18];
e281682b
SM		 3703
3704 u8 syndrome[0x20];
3705
b4ff3a36 3706 u8 reserved_at_40[0xc0];
e281682b
SM		 3707
3708 struct mlx5_ifc_sqc_bits sq_context;
3709};
3710
3711struct mlx5_ifc_query_sq_in_bits {
3712 u8 opcode[0x10];
b4ff3a36 3713 u8 reserved_at_10[0x10];
e281682b 3714
b4ff3a36 3715 u8 reserved_at_20[0x10];
e281682b
SM		 3716 u8 op_mod[0x10];
3717
b4ff3a36 3718 u8 reserved_at_40[0x8];
e281682b
SM		 3719 u8 sqn[0x18];
3720
b4ff3a36 3721 u8 reserved_at_60[0x20];
e281682b
SM		 3722};
3723
3724struct mlx5_ifc_query_special_contexts_out_bits {
3725 u8 status[0x8];
b4ff3a36 3726 u8 reserved_at_8[0x18];
e281682b
SM		 3727
3728 u8 syndrome[0x20];
3729
ec22eb53 3730 u8 dump_fill_mkey[0x20];
e281682b
SM		 3731
3732 u8 resd_lkey[0x20];
bcda1aca
AK		 3733
3734 u8 null_mkey[0x20];
3735
3736 u8 reserved_at_a0[0x60];
e281682b
SM		 3737};
3738
3739struct mlx5_ifc_query_special_contexts_in_bits {
3740 u8 opcode[0x10];
b4ff3a36 3741 u8 reserved_at_10[0x10];
e281682b 3742
b4ff3a36 3743 u8 reserved_at_20[0x10];
e281682b
SM		 3744 u8 op_mod[0x10];
3745
b4ff3a36 3746 u8 reserved_at_40[0x40];
e281682b
SM		 3747};
3748
813f8540
MHY		 3749struct mlx5_ifc_query_scheduling_element_out_bits {
3750 u8 opcode[0x10];
3751 u8 reserved_at_10[0x10];
3752
3753 u8 reserved_at_20[0x10];
3754 u8 op_mod[0x10];
3755
3756 u8 reserved_at_40[0xc0];
3757
3758 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3759
3760 u8 reserved_at_300[0x100];
3761};
3762
3763enum {
3764 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3765};
3766
3767struct mlx5_ifc_query_scheduling_element_in_bits {
3768 u8 opcode[0x10];
3769 u8 reserved_at_10[0x10];
3770
3771 u8 reserved_at_20[0x10];
3772 u8 op_mod[0x10];
3773
3774 u8 scheduling_hierarchy[0x8];
3775 u8 reserved_at_48[0x18];
3776
3777 u8 scheduling_element_id[0x20];
3778
3779 u8 reserved_at_80[0x180];
3780};
3781
e281682b
SM		 3782struct mlx5_ifc_query_rqt_out_bits {
3783 u8 status[0x8];
b4ff3a36 3784 u8 reserved_at_8[0x18];
e281682b
SM		 3785
3786 u8 syndrome[0x20];
3787
b4ff3a36 3788 u8 reserved_at_40[0xc0];
e281682b
SM		 3789
3790 struct mlx5_ifc_rqtc_bits rqt_context;
3791};
3792
3793struct mlx5_ifc_query_rqt_in_bits {
3794 u8 opcode[0x10];
b4ff3a36 3795 u8 reserved_at_10[0x10];
e281682b 3796
b4ff3a36 3797 u8 reserved_at_20[0x10];
e281682b
SM		 3798 u8 op_mod[0x10];
3799
b4ff3a36 3800 u8 reserved_at_40[0x8];
e281682b
SM		 3801 u8 rqtn[0x18];
3802
b4ff3a36 3803 u8 reserved_at_60[0x20];
e281682b
SM		 3804};
3805
3806struct mlx5_ifc_query_rq_out_bits {
3807 u8 status[0x8];
b4ff3a36 3808 u8 reserved_at_8[0x18];
e281682b
SM		 3809
3810 u8 syndrome[0x20];
3811
b4ff3a36 3812 u8 reserved_at_40[0xc0];
e281682b
SM		 3813
3814 struct mlx5_ifc_rqc_bits rq_context;
3815};
3816
3817struct mlx5_ifc_query_rq_in_bits {
3818 u8 opcode[0x10];
b4ff3a36 3819 u8 reserved_at_10[0x10];
e281682b 3820
b4ff3a36 3821 u8 reserved_at_20[0x10];
e281682b
SM		 3822 u8 op_mod[0x10];
3823
b4ff3a36 3824 u8 reserved_at_40[0x8];
e281682b
SM		 3825 u8 rqn[0x18];
3826
b4ff3a36 3827 u8 reserved_at_60[0x20];
e281682b
SM		 3828};
3829
3830struct mlx5_ifc_query_roce_address_out_bits {
3831 u8 status[0x8];
b4ff3a36 3832 u8 reserved_at_8[0x18];
e281682b
SM		 3833
3834 u8 syndrome[0x20];
3835
b4ff3a36 3836 u8 reserved_at_40[0x40];
e281682b
SM		 3837
3838 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3839};
3840
3841struct mlx5_ifc_query_roce_address_in_bits {
3842 u8 opcode[0x10];
b4ff3a36 3843 u8 reserved_at_10[0x10];
e281682b 3844
b4ff3a36 3845 u8 reserved_at_20[0x10];
e281682b
SM		 3846 u8 op_mod[0x10];
3847
3848 u8 roce_address_index[0x10];
b4ff3a36 3849 u8 reserved_at_50[0x10];
e281682b 3850
b4ff3a36 3851 u8 reserved_at_60[0x20];
e281682b
SM		 3852};
3853
3854struct mlx5_ifc_query_rmp_out_bits {
3855 u8 status[0x8];
b4ff3a36 3856 u8 reserved_at_8[0x18];
e281682b
SM		 3857
3858 u8 syndrome[0x20];
3859
b4ff3a36 3860 u8 reserved_at_40[0xc0];
e281682b
SM		 3861
3862 struct mlx5_ifc_rmpc_bits rmp_context;
3863};
3864
3865struct mlx5_ifc_query_rmp_in_bits {
3866 u8 opcode[0x10];
b4ff3a36 3867 u8 reserved_at_10[0x10];
e281682b 3868
b4ff3a36 3869 u8 reserved_at_20[0x10];
e281682b
SM		 3870 u8 op_mod[0x10];
3871
b4ff3a36 3872 u8 reserved_at_40[0x8];
e281682b
SM		 3873 u8 rmpn[0x18];
3874
b4ff3a36 3875 u8 reserved_at_60[0x20];
e281682b
SM		 3876};
3877
3878struct mlx5_ifc_query_qp_out_bits {
3879 u8 status[0x8];
b4ff3a36 3880 u8 reserved_at_8[0x18];
e281682b
SM		 3881
3882 u8 syndrome[0x20];
3883
b4ff3a36 3884 u8 reserved_at_40[0x40];
e281682b
SM		 3885
3886 u8 opt_param_mask[0x20];
3887
b4ff3a36 3888 u8 reserved_at_a0[0x20];
e281682b
SM		 3889
3890 struct mlx5_ifc_qpc_bits qpc;
3891
b4ff3a36 3892 u8 reserved_at_800[0x80];
e281682b
SM		 3893
3894 u8 pas[0][0x40];
3895};
3896
3897struct mlx5_ifc_query_qp_in_bits {
3898 u8 opcode[0x10];
b4ff3a36 3899 u8 reserved_at_10[0x10];
e281682b 3900
b4ff3a36 3901 u8 reserved_at_20[0x10];
e281682b
SM		 3902 u8 op_mod[0x10];
3903
b4ff3a36 3904 u8 reserved_at_40[0x8];
e281682b
SM		 3905 u8 qpn[0x18];
3906
b4ff3a36 3907 u8 reserved_at_60[0x20];
e281682b
SM		 3908};
3909
3910struct mlx5_ifc_query_q_counter_out_bits {
3911 u8 status[0x8];
b4ff3a36 3912 u8 reserved_at_8[0x18];
e281682b
SM		 3913
3914 u8 syndrome[0x20];
3915
b4ff3a36 3916 u8 reserved_at_40[0x40];
e281682b
SM		 3917
3918 u8 rx_write_requests[0x20];
3919
b4ff3a36 3920 u8 reserved_at_a0[0x20];
e281682b
SM		 3921
3922 u8 rx_read_requests[0x20];
3923
b4ff3a36 3924 u8 reserved_at_e0[0x20];
e281682b
SM		 3925
3926 u8 rx_atomic_requests[0x20];
3927
b4ff3a36 3928 u8 reserved_at_120[0x20];
e281682b
SM		 3929
3930 u8 rx_dct_connect[0x20];
3931
b4ff3a36 3932 u8 reserved_at_160[0x20];
e281682b
SM		 3933
3934 u8 out_of_buffer[0x20];
3935
b4ff3a36 3936 u8 reserved_at_1a0[0x20];
e281682b
SM		 3937
3938 u8 out_of_sequence[0x20];
3939
7486216b
SM		 3940 u8 reserved_at_1e0[0x20];
3941
3942 u8 duplicate_request[0x20];
3943
3944 u8 reserved_at_220[0x20];
3945
3946 u8 rnr_nak_retry_err[0x20];
3947
3948 u8 reserved_at_260[0x20];
3949
3950 u8 packet_seq_err[0x20];
3951
3952 u8 reserved_at_2a0[0x20];
3953
3954 u8 implied_nak_seq_err[0x20];
3955
3956 u8 reserved_at_2e0[0x20];
3957
3958 u8 local_ack_timeout_err[0x20];
3959
58dcb60a
PP		 3960 u8 reserved_at_320[0xa0];
3961
3962 u8 resp_local_length_error[0x20];
3963
3964 u8 req_local_length_error[0x20];
3965
3966 u8 resp_local_qp_error[0x20];
3967
3968 u8 local_operation_error[0x20];
3969
3970 u8 resp_local_protection[0x20];
3971
3972 u8 req_local_protection[0x20];
3973
3974 u8 resp_cqe_error[0x20];
3975
3976 u8 req_cqe_error[0x20];
3977
3978 u8 req_mw_binding[0x20];
3979
3980 u8 req_bad_response[0x20];
3981
3982 u8 req_remote_invalid_request[0x20];
3983
3984 u8 resp_remote_invalid_request[0x20];
3985
3986 u8 req_remote_access_errors[0x20];
3987
3988 u8 resp_remote_access_errors[0x20];
3989
3990 u8 req_remote_operation_errors[0x20];
3991
3992 u8 req_transport_retries_exceeded[0x20];
3993
3994 u8 cq_overflow[0x20];
3995
3996 u8 resp_cqe_flush_error[0x20];
3997
3998 u8 req_cqe_flush_error[0x20];
3999
4000 u8 reserved_at_620[0x1e0];
e281682b
SM		 4001};
4002
4003struct mlx5_ifc_query_q_counter_in_bits {
4004 u8 opcode[0x10];
b4ff3a36 4005 u8 reserved_at_10[0x10];
e281682b 4006
b4ff3a36 4007 u8 reserved_at_20[0x10];
e281682b
SM		 4008 u8 op_mod[0x10];
4009
b4ff3a36 4010 u8 reserved_at_40[0x80];
e281682b
SM		 4011
4012 u8 clear[0x1];
b4ff3a36 4013 u8 reserved_at_c1[0x1f];
e281682b 4014
b4ff3a36 4015 u8 reserved_at_e0[0x18];
e281682b
SM		 4016 u8 counter_set_id[0x8];
4017};
4018
4019struct mlx5_ifc_query_pages_out_bits {
4020 u8 status[0x8];
b4ff3a36 4021 u8 reserved_at_8[0x18];
e281682b
SM		 4022
4023 u8 syndrome[0x20];
4024
b4ff3a36 4025 u8 reserved_at_40[0x10];
e281682b
SM		 4026 u8 function_id[0x10];
4027
4028 u8 num_pages[0x20];
4029};
4030
4031enum {
4032 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4033 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4034 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4035};
4036
4037struct mlx5_ifc_query_pages_in_bits {
4038 u8 opcode[0x10];
b4ff3a36 4039 u8 reserved_at_10[0x10];
e281682b 4040
b4ff3a36 4041 u8 reserved_at_20[0x10];
e281682b
SM		 4042 u8 op_mod[0x10];
4043
b4ff3a36 4044 u8 reserved_at_40[0x10];
e281682b
SM		 4045 u8 function_id[0x10];
4046
b4ff3a36 4047 u8 reserved_at_60[0x20];
e281682b
SM		 4048};
4049
4050struct mlx5_ifc_query_nic_vport_context_out_bits {
4051 u8 status[0x8];
b4ff3a36 4052 u8 reserved_at_8[0x18];
e281682b
SM		 4053
4054 u8 syndrome[0x20];
4055
b4ff3a36 4056 u8 reserved_at_40[0x40];
e281682b
SM		 4057
4058 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4059};
4060
4061struct mlx5_ifc_query_nic_vport_context_in_bits {
4062 u8 opcode[0x10];
b4ff3a36 4063 u8 reserved_at_10[0x10];
e281682b 4064
b4ff3a36 4065 u8 reserved_at_20[0x10];
e281682b
SM		 4066 u8 op_mod[0x10];
4067
4068 u8 other_vport[0x1];
b4ff3a36 4069 u8 reserved_at_41[0xf];
e281682b
SM		 4070 u8 vport_number[0x10];
4071
b4ff3a36 4072 u8 reserved_at_60[0x5];
e281682b 4073 u8 allowed_list_type[0x3];
b4ff3a36 4074 u8 reserved_at_68[0x18];
e281682b
SM		 4075};
4076
4077struct mlx5_ifc_query_mkey_out_bits {
4078 u8 status[0x8];
b4ff3a36 4079 u8 reserved_at_8[0x18];
e281682b
SM		 4080
4081 u8 syndrome[0x20];
4082
b4ff3a36 4083 u8 reserved_at_40[0x40];
e281682b
SM		 4084
4085 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4086
b4ff3a36 4087 u8 reserved_at_280[0x600];
e281682b
SM		 4088
4089 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4090
4091 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4092};
4093
4094struct mlx5_ifc_query_mkey_in_bits {
4095 u8 opcode[0x10];
b4ff3a36 4096 u8 reserved_at_10[0x10];
e281682b 4097
b4ff3a36 4098 u8 reserved_at_20[0x10];
e281682b
SM		 4099 u8 op_mod[0x10];
4100
b4ff3a36 4101 u8 reserved_at_40[0x8];
e281682b
SM		 4102 u8 mkey_index[0x18];
4103
4104 u8 pg_access[0x1];
b4ff3a36 4105 u8 reserved_at_61[0x1f];
e281682b
SM		 4106};
4107
4108struct mlx5_ifc_query_mad_demux_out_bits {
4109 u8 status[0x8];
b4ff3a36 4110 u8 reserved_at_8[0x18];
e281682b
SM		 4111
4112 u8 syndrome[0x20];
4113
b4ff3a36 4114 u8 reserved_at_40[0x40];
e281682b
SM		 4115
4116 u8 mad_dumux_parameters_block[0x20];
4117};
4118
4119struct mlx5_ifc_query_mad_demux_in_bits {
4120 u8 opcode[0x10];
b4ff3a36 4121 u8 reserved_at_10[0x10];
e281682b 4122
b4ff3a36 4123 u8 reserved_at_20[0x10];
e281682b
SM		 4124 u8 op_mod[0x10];
4125
b4ff3a36 4126 u8 reserved_at_40[0x40];
e281682b
SM		 4127};
4128
4129struct mlx5_ifc_query_l2_table_entry_out_bits {
4130 u8 status[0x8];
b4ff3a36 4131 u8 reserved_at_8[0x18];
e281682b
SM		 4132
4133 u8 syndrome[0x20];
4134
b4ff3a36 4135 u8 reserved_at_40[0xa0];
e281682b 4136
b4ff3a36 4137 u8 reserved_at_e0[0x13];
e281682b
SM		 4138 u8 vlan_valid[0x1];
4139 u8 vlan[0xc];
4140
4141 struct mlx5_ifc_mac_address_layout_bits mac_address;
4142
b4ff3a36 4143 u8 reserved_at_140[0xc0];
e281682b
SM		 4144};
4145
4146struct mlx5_ifc_query_l2_table_entry_in_bits {
4147 u8 opcode[0x10];
b4ff3a36 4148 u8 reserved_at_10[0x10];
e281682b 4149
b4ff3a36 4150 u8 reserved_at_20[0x10];
e281682b
SM		 4151 u8 op_mod[0x10];
4152
b4ff3a36 4153 u8 reserved_at_40[0x60];
e281682b 4154
b4ff3a36 4155 u8 reserved_at_a0[0x8];
e281682b
SM		 4156 u8 table_index[0x18];
4157
b4ff3a36 4158 u8 reserved_at_c0[0x140];
e281682b
SM		 4159};
4160
4161struct mlx5_ifc_query_issi_out_bits {
4162 u8 status[0x8];
b4ff3a36 4163 u8 reserved_at_8[0x18];
e281682b
SM		 4164
4165 u8 syndrome[0x20];
4166
b4ff3a36 4167 u8 reserved_at_40[0x10];
e281682b
SM		 4168 u8 current_issi[0x10];
4169
b4ff3a36 4170 u8 reserved_at_60[0xa0];
e281682b 4171
b4ff3a36 4172 u8 reserved_at_100[76][0x8];
e281682b
SM		 4173 u8 supported_issi_dw0[0x20];
4174};
4175
4176struct mlx5_ifc_query_issi_in_bits {
4177 u8 opcode[0x10];
b4ff3a36 4178 u8 reserved_at_10[0x10];
e281682b 4179
b4ff3a36 4180 u8 reserved_at_20[0x10];
e281682b
SM		 4181 u8 op_mod[0x10];
4182
b4ff3a36 4183 u8 reserved_at_40[0x40];
e281682b
SM		 4184};
4185
0dbc6fe0
SM		 4186struct mlx5_ifc_set_driver_version_out_bits {
4187 u8 status[0x8];
4188 u8 reserved_0[0x18];
4189
4190 u8 syndrome[0x20];
4191 u8 reserved_1[0x40];
4192};
4193
4194struct mlx5_ifc_set_driver_version_in_bits {
4195 u8 opcode[0x10];
4196 u8 reserved_0[0x10];
4197
4198 u8 reserved_1[0x10];
4199 u8 op_mod[0x10];
4200
4201 u8 reserved_2[0x40];
4202 u8 driver_version[64][0x8];
4203};
4204
e281682b
SM		 4205struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4206 u8 status[0x8];
b4ff3a36 4207 u8 reserved_at_8[0x18];
e281682b
SM		 4208
4209 u8 syndrome[0x20];
4210
b4ff3a36 4211 u8 reserved_at_40[0x40];
e281682b
SM		 4212
4213 struct mlx5_ifc_pkey_bits pkey[0];
4214};
4215
4216struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4217 u8 opcode[0x10];
b4ff3a36 4218 u8 reserved_at_10[0x10];
e281682b 4219
b4ff3a36 4220 u8 reserved_at_20[0x10];
e281682b
SM		 4221 u8 op_mod[0x10];
4222
4223 u8 other_vport[0x1];
b4ff3a36 4224 u8 reserved_at_41[0xb];
707c4602 4225 u8 port_num[0x4];
e281682b
SM		 4226 u8 vport_number[0x10];
4227
b4ff3a36 4228 u8 reserved_at_60[0x10];
e281682b
SM		 4229 u8 pkey_index[0x10];
4230};
4231
eff901d3
EC		 4232enum {
4233 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4234 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4235 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4236};
4237
e281682b
SM		 4238struct mlx5_ifc_query_hca_vport_gid_out_bits {
4239 u8 status[0x8];
b4ff3a36 4240 u8 reserved_at_8[0x18];
e281682b
SM		 4241
4242 u8 syndrome[0x20];
4243
b4ff3a36 4244 u8 reserved_at_40[0x20];
e281682b
SM		 4245
4246 u8 gids_num[0x10];
b4ff3a36 4247 u8 reserved_at_70[0x10];
e281682b
SM		 4248
4249 struct mlx5_ifc_array128_auto_bits gid[0];
4250};
4251
4252struct mlx5_ifc_query_hca_vport_gid_in_bits {
4253 u8 opcode[0x10];
b4ff3a36 4254 u8 reserved_at_10[0x10];
e281682b 4255
b4ff3a36 4256 u8 reserved_at_20[0x10];
e281682b
SM		 4257 u8 op_mod[0x10];
4258
4259 u8 other_vport[0x1];
b4ff3a36 4260 u8 reserved_at_41[0xb];
707c4602 4261 u8 port_num[0x4];
e281682b
SM		 4262 u8 vport_number[0x10];
4263
b4ff3a36 4264 u8 reserved_at_60[0x10];
e281682b
SM		 4265 u8 gid_index[0x10];
4266};
4267
4268struct mlx5_ifc_query_hca_vport_context_out_bits {
4269 u8 status[0x8];
b4ff3a36 4270 u8 reserved_at_8[0x18];
e281682b
SM		 4271
4272 u8 syndrome[0x20];
4273
b4ff3a36 4274 u8 reserved_at_40[0x40];
e281682b
SM		 4275
4276 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4277};
4278
4279struct mlx5_ifc_query_hca_vport_context_in_bits {
4280 u8 opcode[0x10];
b4ff3a36 4281 u8 reserved_at_10[0x10];
e281682b 4282
b4ff3a36 4283 u8 reserved_at_20[0x10];
e281682b
SM		 4284 u8 op_mod[0x10];
4285
4286 u8 other_vport[0x1];
b4ff3a36 4287 u8 reserved_at_41[0xb];
707c4602 4288 u8 port_num[0x4];
e281682b
SM		 4289 u8 vport_number[0x10];
4290
b4ff3a36 4291 u8 reserved_at_60[0x20];
e281682b
SM		 4292};
4293
4294struct mlx5_ifc_query_hca_cap_out_bits {
4295 u8 status[0x8];
b4ff3a36 4296 u8 reserved_at_8[0x18];
e281682b
SM		 4297
4298 u8 syndrome[0x20];
4299
b4ff3a36 4300 u8 reserved_at_40[0x40];
e281682b
SM		 4301
4302 union mlx5_ifc_hca_cap_union_bits capability;
4303};
4304
4305struct mlx5_ifc_query_hca_cap_in_bits {
4306 u8 opcode[0x10];
b4ff3a36 4307 u8 reserved_at_10[0x10];
e281682b 4308
b4ff3a36 4309 u8 reserved_at_20[0x10];
e281682b
SM		 4310 u8 op_mod[0x10];
4311
b4ff3a36 4312 u8 reserved_at_40[0x40];
e281682b
SM		 4313};
4314
4315struct mlx5_ifc_query_flow_table_out_bits {
4316 u8 status[0x8];
b4ff3a36 4317 u8 reserved_at_8[0x18];
e281682b
SM		 4318
4319 u8 syndrome[0x20];
4320
b4ff3a36 4321 u8 reserved_at_40[0x80];
e281682b 4322
b4ff3a36 4323 u8 reserved_at_c0[0x8];
e281682b 4324 u8 level[0x8];
b4ff3a36 4325 u8 reserved_at_d0[0x8];
e281682b
SM		 4326 u8 log_size[0x8];
4327
b4ff3a36 4328 u8 reserved_at_e0[0x120];
e281682b
SM		 4329};
4330
4331struct mlx5_ifc_query_flow_table_in_bits {
4332 u8 opcode[0x10];
b4ff3a36 4333 u8 reserved_at_10[0x10];
e281682b 4334
b4ff3a36 4335 u8 reserved_at_20[0x10];
e281682b
SM		 4336 u8 op_mod[0x10];
4337
b4ff3a36 4338 u8 reserved_at_40[0x40];
e281682b
SM		 4339
4340 u8 table_type[0x8];
b4ff3a36 4341 u8 reserved_at_88[0x18];
e281682b 4342
b4ff3a36 4343 u8 reserved_at_a0[0x8];
e281682b
SM		 4344 u8 table_id[0x18];
4345
b4ff3a36 4346 u8 reserved_at_c0[0x140];
e281682b
SM		 4347};
4348
4349struct mlx5_ifc_query_fte_out_bits {
4350 u8 status[0x8];
b4ff3a36 4351 u8 reserved_at_8[0x18];
e281682b
SM		 4352
4353 u8 syndrome[0x20];
4354
b4ff3a36 4355 u8 reserved_at_40[0x1c0];
e281682b
SM		 4356
4357 struct mlx5_ifc_flow_context_bits flow_context;
4358};
4359
4360struct mlx5_ifc_query_fte_in_bits {
4361 u8 opcode[0x10];
b4ff3a36 4362 u8 reserved_at_10[0x10];
e281682b 4363
b4ff3a36 4364 u8 reserved_at_20[0x10];
e281682b
SM		 4365 u8 op_mod[0x10];
4366
b4ff3a36 4367 u8 reserved_at_40[0x40];
e281682b
SM		 4368
4369 u8 table_type[0x8];
b4ff3a36 4370 u8 reserved_at_88[0x18];
e281682b 4371
b4ff3a36 4372 u8 reserved_at_a0[0x8];
e281682b
SM		 4373 u8 table_id[0x18];
4374
b4ff3a36 4375 u8 reserved_at_c0[0x40];
e281682b
SM		 4376
4377 u8 flow_index[0x20];
4378
b4ff3a36 4379 u8 reserved_at_120[0xe0];
e281682b
SM		 4380};
4381
4382enum {
4383 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4384 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4385 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4386};
4387
4388struct mlx5_ifc_query_flow_group_out_bits {
4389 u8 status[0x8];
b4ff3a36 4390 u8 reserved_at_8[0x18];
e281682b
SM		 4391
4392 u8 syndrome[0x20];
4393
b4ff3a36 4394 u8 reserved_at_40[0xa0];
e281682b
SM		 4395
4396 u8 start_flow_index[0x20];
4397
b4ff3a36 4398 u8 reserved_at_100[0x20];
e281682b
SM		 4399
4400 u8 end_flow_index[0x20];
4401
b4ff3a36 4402 u8 reserved_at_140[0xa0];
e281682b 4403
b4ff3a36 4404 u8 reserved_at_1e0[0x18];
e281682b
SM		 4405 u8 match_criteria_enable[0x8];
4406
4407 struct mlx5_ifc_fte_match_param_bits match_criteria;
4408
b4ff3a36 4409 u8 reserved_at_1200[0xe00];
e281682b
SM		 4410};
4411
4412struct mlx5_ifc_query_flow_group_in_bits {
4413 u8 opcode[0x10];
b4ff3a36 4414 u8 reserved_at_10[0x10];
e281682b 4415
b4ff3a36 4416 u8 reserved_at_20[0x10];
e281682b
SM		 4417 u8 op_mod[0x10];
4418
b4ff3a36 4419 u8 reserved_at_40[0x40];
e281682b
SM		 4420
4421 u8 table_type[0x8];
b4ff3a36 4422 u8 reserved_at_88[0x18];
e281682b 4423
b4ff3a36 4424 u8 reserved_at_a0[0x8];
e281682b
SM		 4425 u8 table_id[0x18];
4426
4427 u8 group_id[0x20];
4428
b4ff3a36 4429 u8 reserved_at_e0[0x120];
e281682b
SM		 4430};
4431
9dc0b289
AV		 4432struct mlx5_ifc_query_flow_counter_out_bits {
4433 u8 status[0x8];
4434 u8 reserved_at_8[0x18];
4435
4436 u8 syndrome[0x20];
4437
4438 u8 reserved_at_40[0x40];
4439
4440 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4441};
4442
4443struct mlx5_ifc_query_flow_counter_in_bits {
4444 u8 opcode[0x10];
4445 u8 reserved_at_10[0x10];
4446
4447 u8 reserved_at_20[0x10];
4448 u8 op_mod[0x10];
4449
4450 u8 reserved_at_40[0x80];
4451
4452 u8 clear[0x1];
4453 u8 reserved_at_c1[0xf];
4454 u8 num_of_counters[0x10];
4455
4456 u8 reserved_at_e0[0x10];
4457 u8 flow_counter_id[0x10];
4458};
4459
d6666753
SM		 4460struct mlx5_ifc_query_esw_vport_context_out_bits {
4461 u8 status[0x8];
b4ff3a36 4462 u8 reserved_at_8[0x18];
d6666753
SM		 4463
4464 u8 syndrome[0x20];
4465
b4ff3a36 4466 u8 reserved_at_40[0x40];
d6666753
SM		 4467
4468 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4469};
4470
4471struct mlx5_ifc_query_esw_vport_context_in_bits {
4472 u8 opcode[0x10];
b4ff3a36 4473 u8 reserved_at_10[0x10];
d6666753 4474
b4ff3a36 4475 u8 reserved_at_20[0x10];
d6666753
SM		 4476 u8 op_mod[0x10];
4477
4478 u8 other_vport[0x1];
b4ff3a36 4479 u8 reserved_at_41[0xf];
d6666753
SM		 4480 u8 vport_number[0x10];
4481
b4ff3a36 4482 u8 reserved_at_60[0x20];
d6666753
SM		 4483};
4484
4485struct mlx5_ifc_modify_esw_vport_context_out_bits {
4486 u8 status[0x8];
b4ff3a36 4487 u8 reserved_at_8[0x18];
d6666753
SM		 4488
4489 u8 syndrome[0x20];
4490
b4ff3a36 4491 u8 reserved_at_40[0x40];
d6666753
SM		 4492};
4493
4494struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4495 u8 reserved_at_0[0x1c];
d6666753
SM		 4496 u8 vport_cvlan_insert[0x1];
4497 u8 vport_svlan_insert[0x1];
4498 u8 vport_cvlan_strip[0x1];
4499 u8 vport_svlan_strip[0x1];
4500};
4501
4502struct mlx5_ifc_modify_esw_vport_context_in_bits {
4503 u8 opcode[0x10];
b4ff3a36 4504 u8 reserved_at_10[0x10];
d6666753 4505
b4ff3a36 4506 u8 reserved_at_20[0x10];
d6666753
SM		 4507 u8 op_mod[0x10];
4508
4509 u8 other_vport[0x1];
b4ff3a36 4510 u8 reserved_at_41[0xf];
d6666753
SM		 4511 u8 vport_number[0x10];
4512
4513 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4514
4515 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4516};
4517
e281682b
SM		 4518struct mlx5_ifc_query_eq_out_bits {
4519 u8 status[0x8];
b4ff3a36 4520 u8 reserved_at_8[0x18];
e281682b
SM		 4521
4522 u8 syndrome[0x20];
4523
b4ff3a36 4524 u8 reserved_at_40[0x40];
e281682b
SM		 4525
4526 struct mlx5_ifc_eqc_bits eq_context_entry;
4527
b4ff3a36 4528 u8 reserved_at_280[0x40];
e281682b
SM		 4529
4530 u8 event_bitmask[0x40];
4531
b4ff3a36 4532 u8 reserved_at_300[0x580];
e281682b
SM		 4533
4534 u8 pas[0][0x40];
4535};
4536
4537struct mlx5_ifc_query_eq_in_bits {
4538 u8 opcode[0x10];
b4ff3a36 4539 u8 reserved_at_10[0x10];
e281682b 4540
b4ff3a36 4541 u8 reserved_at_20[0x10];
e281682b
SM		 4542 u8 op_mod[0x10];
4543
b4ff3a36 4544 u8 reserved_at_40[0x18];
e281682b
SM		 4545 u8 eq_number[0x8];
4546
b4ff3a36 4547 u8 reserved_at_60[0x20];
e281682b
SM		 4548};
4549
7adbde20
HHZ		 4550struct mlx5_ifc_encap_header_in_bits {
4551 u8 reserved_at_0[0x5];
4552 u8 header_type[0x3];
4553 u8 reserved_at_8[0xe];
4554 u8 encap_header_size[0xa];
4555
4556 u8 reserved_at_20[0x10];
4557 u8 encap_header[2][0x8];
4558
4559 u8 more_encap_header[0][0x8];
4560};
4561
4562struct mlx5_ifc_query_encap_header_out_bits {
4563 u8 status[0x8];
4564 u8 reserved_at_8[0x18];
4565
4566 u8 syndrome[0x20];
4567
4568 u8 reserved_at_40[0xa0];
4569
4570 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4571};
4572
4573struct mlx5_ifc_query_encap_header_in_bits {
4574 u8 opcode[0x10];
4575 u8 reserved_at_10[0x10];
4576
4577 u8 reserved_at_20[0x10];
4578 u8 op_mod[0x10];
4579
4580 u8 encap_id[0x20];
4581
4582 u8 reserved_at_60[0xa0];
4583};
4584
4585struct mlx5_ifc_alloc_encap_header_out_bits {
4586 u8 status[0x8];
4587 u8 reserved_at_8[0x18];
4588
4589 u8 syndrome[0x20];
4590
4591 u8 encap_id[0x20];
4592
4593 u8 reserved_at_60[0x20];
4594};
4595
4596struct mlx5_ifc_alloc_encap_header_in_bits {
4597 u8 opcode[0x10];
4598 u8 reserved_at_10[0x10];
4599
4600 u8 reserved_at_20[0x10];
4601 u8 op_mod[0x10];
4602
4603 u8 reserved_at_40[0xa0];
4604
4605 struct mlx5_ifc_encap_header_in_bits encap_header;
4606};
4607
4608struct mlx5_ifc_dealloc_encap_header_out_bits {
4609 u8 status[0x8];
4610 u8 reserved_at_8[0x18];
4611
4612 u8 syndrome[0x20];
4613
4614 u8 reserved_at_40[0x40];
4615};
4616
4617struct mlx5_ifc_dealloc_encap_header_in_bits {
4618 u8 opcode[0x10];
4619 u8 reserved_at_10[0x10];
4620
4621 u8 reserved_20[0x10];
4622 u8 op_mod[0x10];
4623
4624 u8 encap_id[0x20];
4625
4626 u8 reserved_60[0x20];
4627};
4628
2a69cb9f
OG		 4629struct mlx5_ifc_set_action_in_bits {
4630 u8 action_type[0x4];
4631 u8 field[0xc];
4632 u8 reserved_at_10[0x3];
4633 u8 offset[0x5];
4634 u8 reserved_at_18[0x3];
4635 u8 length[0x5];
4636
4637 u8 data[0x20];
4638};
4639
4640struct mlx5_ifc_add_action_in_bits {
4641 u8 action_type[0x4];
4642 u8 field[0xc];
4643 u8 reserved_at_10[0x10];
4644
4645 u8 data[0x20];
4646};
4647
4648union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4649 struct mlx5_ifc_set_action_in_bits set_action_in;
4650 struct mlx5_ifc_add_action_in_bits add_action_in;
4651 u8 reserved_at_0[0x40];
4652};
4653
4654enum {
4655 MLX5_ACTION_TYPE_SET = 0x1,
4656 MLX5_ACTION_TYPE_ADD = 0x2,
4657};
4658
4659enum {
4660 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4661 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4662 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4663 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4664 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4665 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4666 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4667 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4668 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4669 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4670 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4671 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4672 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4673 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4674 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4675 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4676 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4677 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4678 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4679 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4680 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4681 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4682 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4683};
4684
4685struct mlx5_ifc_alloc_modify_header_context_out_bits {
4686 u8 status[0x8];
4687 u8 reserved_at_8[0x18];
4688
4689 u8 syndrome[0x20];
4690
4691 u8 modify_header_id[0x20];
4692
4693 u8 reserved_at_60[0x20];
4694};
4695
4696struct mlx5_ifc_alloc_modify_header_context_in_bits {
4697 u8 opcode[0x10];
4698 u8 reserved_at_10[0x10];
4699
4700 u8 reserved_at_20[0x10];
4701 u8 op_mod[0x10];
4702
4703 u8 reserved_at_40[0x20];
4704
4705 u8 table_type[0x8];
4706 u8 reserved_at_68[0x10];
4707 u8 num_of_actions[0x8];
4708
4709 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4710};
4711
4712struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4713 u8 status[0x8];
4714 u8 reserved_at_8[0x18];
4715
4716 u8 syndrome[0x20];
4717
4718 u8 reserved_at_40[0x40];
4719};
4720
4721struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4722 u8 opcode[0x10];
4723 u8 reserved_at_10[0x10];
4724
4725 u8 reserved_at_20[0x10];
4726 u8 op_mod[0x10];
4727
4728 u8 modify_header_id[0x20];
4729
4730 u8 reserved_at_60[0x20];
4731};
4732
e281682b
SM		 4733struct mlx5_ifc_query_dct_out_bits {
4734 u8 status[0x8];
b4ff3a36 4735 u8 reserved_at_8[0x18];
e281682b
SM		 4736
4737 u8 syndrome[0x20];
4738
b4ff3a36 4739 u8 reserved_at_40[0x40];
e281682b
SM		 4740
4741 struct mlx5_ifc_dctc_bits dct_context_entry;
4742
b4ff3a36 4743 u8 reserved_at_280[0x180];
e281682b
SM		 4744};
4745
4746struct mlx5_ifc_query_dct_in_bits {
4747 u8 opcode[0x10];
b4ff3a36 4748 u8 reserved_at_10[0x10];
e281682b 4749
b4ff3a36 4750 u8 reserved_at_20[0x10];
e281682b
SM		 4751 u8 op_mod[0x10];
4752
b4ff3a36 4753 u8 reserved_at_40[0x8];
e281682b
SM		 4754 u8 dctn[0x18];
4755
b4ff3a36 4756 u8 reserved_at_60[0x20];
e281682b
SM		 4757};
4758
4759struct mlx5_ifc_query_cq_out_bits {
4760 u8 status[0x8];
b4ff3a36 4761 u8 reserved_at_8[0x18];
e281682b
SM		 4762
4763 u8 syndrome[0x20];
4764
b4ff3a36 4765 u8 reserved_at_40[0x40];
e281682b
SM		 4766
4767 struct mlx5_ifc_cqc_bits cq_context;
4768
b4ff3a36 4769 u8 reserved_at_280[0x600];
e281682b
SM		 4770
4771 u8 pas[0][0x40];
4772};
4773
4774struct mlx5_ifc_query_cq_in_bits {
4775 u8 opcode[0x10];
b4ff3a36 4776 u8 reserved_at_10[0x10];
e281682b 4777
b4ff3a36 4778 u8 reserved_at_20[0x10];
e281682b
SM		 4779 u8 op_mod[0x10];
4780
b4ff3a36 4781 u8 reserved_at_40[0x8];
e281682b
SM		 4782 u8 cqn[0x18];
4783
b4ff3a36 4784 u8 reserved_at_60[0x20];
e281682b
SM		 4785};
4786
4787struct mlx5_ifc_query_cong_status_out_bits {
4788 u8 status[0x8];
b4ff3a36 4789 u8 reserved_at_8[0x18];
e281682b
SM		 4790
4791 u8 syndrome[0x20];
4792
b4ff3a36 4793 u8 reserved_at_40[0x20];
e281682b
SM		 4794
4795 u8 enable[0x1];
4796 u8 tag_enable[0x1];
b4ff3a36 4797 u8 reserved_at_62[0x1e];
e281682b
SM		 4798};
4799
4800struct mlx5_ifc_query_cong_status_in_bits {
4801 u8 opcode[0x10];
b4ff3a36 4802 u8 reserved_at_10[0x10];
e281682b 4803
b4ff3a36 4804 u8 reserved_at_20[0x10];
e281682b
SM		 4805 u8 op_mod[0x10];
4806
b4ff3a36 4807 u8 reserved_at_40[0x18];
e281682b
SM		 4808 u8 priority[0x4];
4809 u8 cong_protocol[0x4];
4810
b4ff3a36 4811 u8 reserved_at_60[0x20];
e281682b
SM		 4812};
4813
4814struct mlx5_ifc_query_cong_statistics_out_bits {
4815 u8 status[0x8];
b4ff3a36 4816 u8 reserved_at_8[0x18];
e281682b
SM		 4817
4818 u8 syndrome[0x20];
4819
b4ff3a36 4820 u8 reserved_at_40[0x40];
e281682b 4821
e1f24a79 4822 u8 rp_cur_flows[0x20];
e281682b
SM		 4823
4824 u8 sum_flows[0x20];
4825
e1f24a79 4826 u8 rp_cnp_ignored_high[0x20];
e281682b 4827
e1f24a79 4828 u8 rp_cnp_ignored_low[0x20];
e281682b 4829
e1f24a79 4830 u8 rp_cnp_handled_high[0x20];
e281682b 4831
e1f24a79 4832 u8 rp_cnp_handled_low[0x20];
e281682b 4833
b4ff3a36 4834 u8 reserved_at_140[0x100];
e281682b
SM		 4835
4836 u8 time_stamp_high[0x20];
4837
4838 u8 time_stamp_low[0x20];
4839
4840 u8 accumulators_period[0x20];
4841
e1f24a79 4842 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 4843
e1f24a79 4844 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 4845
e1f24a79 4846 u8 np_cnp_sent_high[0x20];
e281682b 4847
e1f24a79 4848 u8 np_cnp_sent_low[0x20];
e281682b 4849
b4ff3a36 4850 u8 reserved_at_320[0x560];
e281682b
SM		 4851};
4852
4853struct mlx5_ifc_query_cong_statistics_in_bits {
4854 u8 opcode[0x10];
b4ff3a36 4855 u8 reserved_at_10[0x10];
e281682b 4856
b4ff3a36 4857 u8 reserved_at_20[0x10];
e281682b
SM		 4858 u8 op_mod[0x10];
4859
4860 u8 clear[0x1];
b4ff3a36 4861 u8 reserved_at_41[0x1f];
e281682b 4862
b4ff3a36 4863 u8 reserved_at_60[0x20];
e281682b
SM		 4864};
4865
4866struct mlx5_ifc_query_cong_params_out_bits {
4867 u8 status[0x8];
b4ff3a36 4868 u8 reserved_at_8[0x18];
e281682b
SM		 4869
4870 u8 syndrome[0x20];
4871
b4ff3a36 4872 u8 reserved_at_40[0x40];
e281682b
SM		 4873
4874 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4875};
4876
4877struct mlx5_ifc_query_cong_params_in_bits {
4878 u8 opcode[0x10];
b4ff3a36 4879 u8 reserved_at_10[0x10];
e281682b 4880
b4ff3a36 4881 u8 reserved_at_20[0x10];
e281682b
SM		 4882 u8 op_mod[0x10];
4883
b4ff3a36 4884 u8 reserved_at_40[0x1c];
e281682b
SM		 4885 u8 cong_protocol[0x4];
4886
b4ff3a36 4887 u8 reserved_at_60[0x20];
e281682b
SM		 4888};
4889
4890struct mlx5_ifc_query_adapter_out_bits {
4891 u8 status[0x8];
b4ff3a36 4892 u8 reserved_at_8[0x18];
e281682b
SM		 4893
4894 u8 syndrome[0x20];
4895
b4ff3a36 4896 u8 reserved_at_40[0x40];
e281682b
SM		 4897
4898 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4899};
4900
4901struct mlx5_ifc_query_adapter_in_bits {
4902 u8 opcode[0x10];
b4ff3a36 4903 u8 reserved_at_10[0x10];
e281682b 4904
b4ff3a36 4905 u8 reserved_at_20[0x10];
e281682b
SM		 4906 u8 op_mod[0x10];
4907
b4ff3a36 4908 u8 reserved_at_40[0x40];
e281682b
SM		 4909};
4910
4911struct mlx5_ifc_qp_2rst_out_bits {
4912 u8 status[0x8];
b4ff3a36 4913 u8 reserved_at_8[0x18];
e281682b
SM		 4914
4915 u8 syndrome[0x20];
4916
b4ff3a36 4917 u8 reserved_at_40[0x40];
e281682b
SM		 4918};
4919
4920struct mlx5_ifc_qp_2rst_in_bits {
4921 u8 opcode[0x10];
b4ff3a36 4922 u8 reserved_at_10[0x10];
e281682b 4923
b4ff3a36 4924 u8 reserved_at_20[0x10];
e281682b
SM		 4925 u8 op_mod[0x10];
4926
b4ff3a36 4927 u8 reserved_at_40[0x8];
e281682b
SM		 4928 u8 qpn[0x18];
4929
b4ff3a36 4930 u8 reserved_at_60[0x20];
e281682b
SM		 4931};
4932
4933struct mlx5_ifc_qp_2err_out_bits {
4934 u8 status[0x8];
b4ff3a36 4935 u8 reserved_at_8[0x18];
e281682b
SM		 4936
4937 u8 syndrome[0x20];
4938
b4ff3a36 4939 u8 reserved_at_40[0x40];
e281682b
SM		 4940};
4941
4942struct mlx5_ifc_qp_2err_in_bits {
4943 u8 opcode[0x10];
b4ff3a36 4944 u8 reserved_at_10[0x10];
e281682b 4945
b4ff3a36 4946 u8 reserved_at_20[0x10];
e281682b
SM		 4947 u8 op_mod[0x10];
4948
b4ff3a36 4949 u8 reserved_at_40[0x8];
e281682b
SM		 4950 u8 qpn[0x18];
4951
b4ff3a36 4952 u8 reserved_at_60[0x20];
e281682b
SM		 4953};
4954
4955struct mlx5_ifc_page_fault_resume_out_bits {
4956 u8 status[0x8];
b4ff3a36 4957 u8 reserved_at_8[0x18];
e281682b
SM		 4958
4959 u8 syndrome[0x20];
4960
b4ff3a36 4961 u8 reserved_at_40[0x40];
e281682b
SM		 4962};
4963
4964struct mlx5_ifc_page_fault_resume_in_bits {
4965 u8 opcode[0x10];
b4ff3a36 4966 u8 reserved_at_10[0x10];
e281682b 4967
b4ff3a36 4968 u8 reserved_at_20[0x10];
e281682b
SM		 4969 u8 op_mod[0x10];
4970
4971 u8 error[0x1];
b4ff3a36 4972 u8 reserved_at_41[0x4];
223cdc72
AK		 4973 u8 page_fault_type[0x3];
4974 u8 wq_number[0x18];
e281682b 4975
223cdc72
AK		 4976 u8 reserved_at_60[0x8];
4977 u8 token[0x18];
e281682b
SM		 4978};
4979
4980struct mlx5_ifc_nop_out_bits {
4981 u8 status[0x8];
b4ff3a36 4982 u8 reserved_at_8[0x18];
e281682b
SM		 4983
4984 u8 syndrome[0x20];
4985
b4ff3a36 4986 u8 reserved_at_40[0x40];
e281682b
SM		 4987};
4988
4989struct mlx5_ifc_nop_in_bits {
4990 u8 opcode[0x10];
b4ff3a36 4991 u8 reserved_at_10[0x10];
e281682b 4992
b4ff3a36 4993 u8 reserved_at_20[0x10];
e281682b
SM		 4994 u8 op_mod[0x10];
4995
b4ff3a36 4996 u8 reserved_at_40[0x40];
e281682b
SM		 4997};
4998
4999struct mlx5_ifc_modify_vport_state_out_bits {
5000 u8 status[0x8];
b4ff3a36 5001 u8 reserved_at_8[0x18];
e281682b
SM		 5002
5003 u8 syndrome[0x20];
5004
b4ff3a36 5005 u8 reserved_at_40[0x40];
e281682b
SM		 5006};
5007
5008struct mlx5_ifc_modify_vport_state_in_bits {
5009 u8 opcode[0x10];
b4ff3a36 5010 u8 reserved_at_10[0x10];
e281682b 5011
b4ff3a36 5012 u8 reserved_at_20[0x10];
e281682b
SM		 5013 u8 op_mod[0x10];
5014
5015 u8 other_vport[0x1];
b4ff3a36 5016 u8 reserved_at_41[0xf];
e281682b
SM		 5017 u8 vport_number[0x10];
5018
b4ff3a36 5019 u8 reserved_at_60[0x18];
e281682b 5020 u8 admin_state[0x4];
b4ff3a36 5021 u8 reserved_at_7c[0x4];
e281682b
SM		 5022};
5023
5024struct mlx5_ifc_modify_tis_out_bits {
5025 u8 status[0x8];
b4ff3a36 5026 u8 reserved_at_8[0x18];
e281682b
SM		 5027
5028 u8 syndrome[0x20];
5029
b4ff3a36 5030 u8 reserved_at_40[0x40];
e281682b
SM		 5031};
5032
75850d0b 5033struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5034 u8 reserved_at_0[0x20];
75850d0b 5035
84df61eb
AH		 5036 u8 reserved_at_20[0x1d];
5037 u8 lag_tx_port_affinity[0x1];
5038 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5039 u8 prio[0x1];
5040};
5041
e281682b
SM		 5042struct mlx5_ifc_modify_tis_in_bits {
5043 u8 opcode[0x10];
b4ff3a36 5044 u8 reserved_at_10[0x10];
e281682b 5045
b4ff3a36 5046 u8 reserved_at_20[0x10];
e281682b
SM		 5047 u8 op_mod[0x10];
5048
b4ff3a36 5049 u8 reserved_at_40[0x8];
e281682b
SM		 5050 u8 tisn[0x18];
5051
b4ff3a36 5052 u8 reserved_at_60[0x20];
e281682b 5053
75850d0b 5054 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5055
b4ff3a36 5056 u8 reserved_at_c0[0x40];
e281682b
SM		 5057
5058 struct mlx5_ifc_tisc_bits ctx;
5059};
5060
d9eea403 5061struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5062 u8 reserved_at_0[0x20];
d9eea403 5063
b4ff3a36 5064 u8 reserved_at_20[0x1b];
66189961 5065 u8 self_lb_en[0x1];
bdfc028d
TT		 5066 u8 reserved_at_3c[0x1];
5067 u8 hash[0x1];
5068 u8 reserved_at_3e[0x1];
d9eea403
AS		 5069 u8 lro[0x1];
5070};
5071
e281682b
SM		 5072struct mlx5_ifc_modify_tir_out_bits {
5073 u8 status[0x8];
b4ff3a36 5074 u8 reserved_at_8[0x18];
e281682b
SM		 5075
5076 u8 syndrome[0x20];
5077
b4ff3a36 5078 u8 reserved_at_40[0x40];
e281682b
SM		 5079};
5080
5081struct mlx5_ifc_modify_tir_in_bits {
5082 u8 opcode[0x10];
b4ff3a36 5083 u8 reserved_at_10[0x10];
e281682b 5084
b4ff3a36 5085 u8 reserved_at_20[0x10];
e281682b
SM		 5086 u8 op_mod[0x10];
5087
b4ff3a36 5088 u8 reserved_at_40[0x8];
e281682b
SM		 5089 u8 tirn[0x18];
5090
b4ff3a36 5091 u8 reserved_at_60[0x20];
e281682b 5092
d9eea403 5093 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5094
b4ff3a36 5095 u8 reserved_at_c0[0x40];
e281682b
SM		 5096
5097 struct mlx5_ifc_tirc_bits ctx;
5098};
5099
5100struct mlx5_ifc_modify_sq_out_bits {
5101 u8 status[0x8];
b4ff3a36 5102 u8 reserved_at_8[0x18];
e281682b
SM		 5103
5104 u8 syndrome[0x20];
5105
b4ff3a36 5106 u8 reserved_at_40[0x40];
e281682b
SM		 5107};
5108
5109struct mlx5_ifc_modify_sq_in_bits {
5110 u8 opcode[0x10];
b4ff3a36 5111 u8 reserved_at_10[0x10];
e281682b 5112
b4ff3a36 5113 u8 reserved_at_20[0x10];
e281682b
SM		 5114 u8 op_mod[0x10];
5115
5116 u8 sq_state[0x4];
b4ff3a36 5117 u8 reserved_at_44[0x4];
e281682b
SM		 5118 u8 sqn[0x18];
5119
b4ff3a36 5120 u8 reserved_at_60[0x20];
e281682b
SM		 5121
5122 u8 modify_bitmask[0x40];
5123
b4ff3a36 5124 u8 reserved_at_c0[0x40];
e281682b
SM		 5125
5126 struct mlx5_ifc_sqc_bits ctx;
5127};
5128
813f8540
MHY		 5129struct mlx5_ifc_modify_scheduling_element_out_bits {
5130 u8 status[0x8];
5131 u8 reserved_at_8[0x18];
5132
5133 u8 syndrome[0x20];
5134
5135 u8 reserved_at_40[0x1c0];
5136};
5137
5138enum {
5139 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5140 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5141};
5142
5143struct mlx5_ifc_modify_scheduling_element_in_bits {
5144 u8 opcode[0x10];
5145 u8 reserved_at_10[0x10];
5146
5147 u8 reserved_at_20[0x10];
5148 u8 op_mod[0x10];
5149
5150 u8 scheduling_hierarchy[0x8];
5151 u8 reserved_at_48[0x18];
5152
5153 u8 scheduling_element_id[0x20];
5154
5155 u8 reserved_at_80[0x20];
5156
5157 u8 modify_bitmask[0x20];
5158
5159 u8 reserved_at_c0[0x40];
5160
5161 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5162
5163 u8 reserved_at_300[0x100];
5164};
5165
e281682b
SM		 5166struct mlx5_ifc_modify_rqt_out_bits {
5167 u8 status[0x8];
b4ff3a36 5168 u8 reserved_at_8[0x18];
e281682b
SM		 5169
5170 u8 syndrome[0x20];
5171
b4ff3a36 5172 u8 reserved_at_40[0x40];
e281682b
SM		 5173};
5174
5c50368f 5175struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5176 u8 reserved_at_0[0x20];
5c50368f 5177
b4ff3a36 5178 u8 reserved_at_20[0x1f];
5c50368f
AS		 5179 u8 rqn_list[0x1];
5180};
5181
e281682b
SM		 5182struct mlx5_ifc_modify_rqt_in_bits {
5183 u8 opcode[0x10];
b4ff3a36 5184 u8 reserved_at_10[0x10];
e281682b 5185
b4ff3a36 5186 u8 reserved_at_20[0x10];
e281682b
SM		 5187 u8 op_mod[0x10];
5188
b4ff3a36 5189 u8 reserved_at_40[0x8];
e281682b
SM		 5190 u8 rqtn[0x18];
5191
b4ff3a36 5192 u8 reserved_at_60[0x20];
e281682b 5193
5c50368f 5194 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5195
b4ff3a36 5196 u8 reserved_at_c0[0x40];
e281682b
SM		 5197
5198 struct mlx5_ifc_rqtc_bits ctx;
5199};
5200
5201struct mlx5_ifc_modify_rq_out_bits {
5202 u8 status[0x8];
b4ff3a36 5203 u8 reserved_at_8[0x18];
e281682b
SM		 5204
5205 u8 syndrome[0x20];
5206
b4ff3a36 5207 u8 reserved_at_40[0x40];
e281682b
SM		 5208};
5209
83b502a1
AV		 5210enum {
5211 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5212 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5213 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5214};
5215
e281682b
SM		 5216struct mlx5_ifc_modify_rq_in_bits {
5217 u8 opcode[0x10];
b4ff3a36 5218 u8 reserved_at_10[0x10];
e281682b 5219
b4ff3a36 5220 u8 reserved_at_20[0x10];
e281682b
SM		 5221 u8 op_mod[0x10];
5222
5223 u8 rq_state[0x4];
b4ff3a36 5224 u8 reserved_at_44[0x4];
e281682b
SM		 5225 u8 rqn[0x18];
5226
b4ff3a36 5227 u8 reserved_at_60[0x20];
e281682b
SM		 5228
5229 u8 modify_bitmask[0x40];
5230
b4ff3a36 5231 u8 reserved_at_c0[0x40];
e281682b
SM		 5232
5233 struct mlx5_ifc_rqc_bits ctx;
5234};
5235
5236struct mlx5_ifc_modify_rmp_out_bits {
5237 u8 status[0x8];
b4ff3a36 5238 u8 reserved_at_8[0x18];
e281682b
SM		 5239
5240 u8 syndrome[0x20];
5241
b4ff3a36 5242 u8 reserved_at_40[0x40];
e281682b
SM		 5243};
5244
01949d01 5245struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5246 u8 reserved_at_0[0x20];
01949d01 5247
b4ff3a36 5248 u8 reserved_at_20[0x1f];
01949d01
HA		 5249 u8 lwm[0x1];
5250};
5251
e281682b
SM		 5252struct mlx5_ifc_modify_rmp_in_bits {
5253 u8 opcode[0x10];
b4ff3a36 5254 u8 reserved_at_10[0x10];
e281682b 5255
b4ff3a36 5256 u8 reserved_at_20[0x10];
e281682b
SM		 5257 u8 op_mod[0x10];
5258
5259 u8 rmp_state[0x4];
b4ff3a36 5260 u8 reserved_at_44[0x4];
e281682b
SM		 5261 u8 rmpn[0x18];
5262
b4ff3a36 5263 u8 reserved_at_60[0x20];
e281682b 5264
01949d01 5265 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5266
b4ff3a36 5267 u8 reserved_at_c0[0x40];
e281682b
SM		 5268
5269 struct mlx5_ifc_rmpc_bits ctx;
5270};
5271
5272struct mlx5_ifc_modify_nic_vport_context_out_bits {
5273 u8 status[0x8];
b4ff3a36 5274 u8 reserved_at_8[0x18];
e281682b
SM		 5275
5276 u8 syndrome[0x20];
5277
b4ff3a36 5278 u8 reserved_at_40[0x40];
e281682b
SM		 5279};
5280
5281struct mlx5_ifc_modify_nic_vport_field_select_bits {
bded747b
HN		 5282 u8 reserved_at_0[0x14];
5283 u8 disable_uc_local_lb[0x1];
5284 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5285 u8 node_guid[0x1];
5286 u8 port_guid[0x1];
9def7121 5287 u8 min_inline[0x1];
d82b7318
SM		 5288 u8 mtu[0x1];
5289 u8 change_event[0x1];
5290 u8 promisc[0x1];
e281682b
SM		 5291 u8 permanent_address[0x1];
5292 u8 addresses_list[0x1];
5293 u8 roce_en[0x1];
b4ff3a36 5294 u8 reserved_at_1f[0x1];
e281682b
SM		 5295};
5296
5297struct mlx5_ifc_modify_nic_vport_context_in_bits {
5298 u8 opcode[0x10];
b4ff3a36 5299 u8 reserved_at_10[0x10];
e281682b 5300
b4ff3a36 5301 u8 reserved_at_20[0x10];
e281682b
SM		 5302 u8 op_mod[0x10];
5303
5304 u8 other_vport[0x1];
b4ff3a36 5305 u8 reserved_at_41[0xf];
e281682b
SM		 5306 u8 vport_number[0x10];
5307
5308 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5309
b4ff3a36 5310 u8 reserved_at_80[0x780];
e281682b
SM		 5311
5312 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5313};
5314
5315struct mlx5_ifc_modify_hca_vport_context_out_bits {
5316 u8 status[0x8];
b4ff3a36 5317 u8 reserved_at_8[0x18];
e281682b
SM		 5318
5319 u8 syndrome[0x20];
5320
b4ff3a36 5321 u8 reserved_at_40[0x40];
e281682b
SM		 5322};
5323
5324struct mlx5_ifc_modify_hca_vport_context_in_bits {
5325 u8 opcode[0x10];
b4ff3a36 5326 u8 reserved_at_10[0x10];
e281682b 5327
b4ff3a36 5328 u8 reserved_at_20[0x10];
e281682b
SM		 5329 u8 op_mod[0x10];
5330
5331 u8 other_vport[0x1];
b4ff3a36 5332 u8 reserved_at_41[0xb];
707c4602 5333 u8 port_num[0x4];
e281682b
SM		 5334 u8 vport_number[0x10];
5335
b4ff3a36 5336 u8 reserved_at_60[0x20];
e281682b
SM		 5337
5338 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5339};
5340
5341struct mlx5_ifc_modify_cq_out_bits {
5342 u8 status[0x8];
b4ff3a36 5343 u8 reserved_at_8[0x18];
e281682b
SM		 5344
5345 u8 syndrome[0x20];
5346
b4ff3a36 5347 u8 reserved_at_40[0x40];
e281682b
SM		 5348};
5349
5350enum {
5351 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5352 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5353};
5354
5355struct mlx5_ifc_modify_cq_in_bits {
5356 u8 opcode[0x10];
b4ff3a36 5357 u8 reserved_at_10[0x10];
e281682b 5358
b4ff3a36 5359 u8 reserved_at_20[0x10];
e281682b
SM		 5360 u8 op_mod[0x10];
5361
b4ff3a36 5362 u8 reserved_at_40[0x8];
e281682b
SM		 5363 u8 cqn[0x18];
5364
5365 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5366
5367 struct mlx5_ifc_cqc_bits cq_context;
5368
b4ff3a36 5369 u8 reserved_at_280[0x600];
e281682b
SM		 5370
5371 u8 pas[0][0x40];
5372};
5373
5374struct mlx5_ifc_modify_cong_status_out_bits {
5375 u8 status[0x8];
b4ff3a36 5376 u8 reserved_at_8[0x18];
e281682b
SM		 5377
5378 u8 syndrome[0x20];
5379
b4ff3a36 5380 u8 reserved_at_40[0x40];
e281682b
SM		 5381};
5382
5383struct mlx5_ifc_modify_cong_status_in_bits {
5384 u8 opcode[0x10];
b4ff3a36 5385 u8 reserved_at_10[0x10];
e281682b 5386
b4ff3a36 5387 u8 reserved_at_20[0x10];
e281682b
SM		 5388 u8 op_mod[0x10];
5389
b4ff3a36 5390 u8 reserved_at_40[0x18];
e281682b
SM		 5391 u8 priority[0x4];
5392 u8 cong_protocol[0x4];
5393
5394 u8 enable[0x1];
5395 u8 tag_enable[0x1];
b4ff3a36 5396 u8 reserved_at_62[0x1e];
e281682b
SM		 5397};
5398
5399struct mlx5_ifc_modify_cong_params_out_bits {
5400 u8 status[0x8];
b4ff3a36 5401 u8 reserved_at_8[0x18];
e281682b
SM		 5402
5403 u8 syndrome[0x20];
5404
b4ff3a36 5405 u8 reserved_at_40[0x40];
e281682b
SM		 5406};
5407
5408struct mlx5_ifc_modify_cong_params_in_bits {
5409 u8 opcode[0x10];
b4ff3a36 5410 u8 reserved_at_10[0x10];
e281682b 5411
b4ff3a36 5412 u8 reserved_at_20[0x10];
e281682b
SM		 5413 u8 op_mod[0x10];
5414
b4ff3a36 5415 u8 reserved_at_40[0x1c];
e281682b
SM		 5416 u8 cong_protocol[0x4];
5417
5418 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5419
b4ff3a36 5420 u8 reserved_at_80[0x80];
e281682b
SM		 5421
5422 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5423};
5424
5425struct mlx5_ifc_manage_pages_out_bits {
5426 u8 status[0x8];
b4ff3a36 5427 u8 reserved_at_8[0x18];
e281682b
SM		 5428
5429 u8 syndrome[0x20];
5430
5431 u8 output_num_entries[0x20];
5432
b4ff3a36 5433 u8 reserved_at_60[0x20];
e281682b
SM		 5434
5435 u8 pas[0][0x40];
5436};
5437
5438enum {
5439 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5440 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5441 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5442};
5443
5444struct mlx5_ifc_manage_pages_in_bits {
5445 u8 opcode[0x10];
b4ff3a36 5446 u8 reserved_at_10[0x10];
e281682b 5447
b4ff3a36 5448 u8 reserved_at_20[0x10];
e281682b
SM		 5449 u8 op_mod[0x10];
5450
b4ff3a36 5451 u8 reserved_at_40[0x10];
e281682b
SM		 5452 u8 function_id[0x10];
5453
5454 u8 input_num_entries[0x20];
5455
5456 u8 pas[0][0x40];
5457};
5458
5459struct mlx5_ifc_mad_ifc_out_bits {
5460 u8 status[0x8];
b4ff3a36 5461 u8 reserved_at_8[0x18];
e281682b
SM		 5462
5463 u8 syndrome[0x20];
5464
b4ff3a36 5465 u8 reserved_at_40[0x40];
e281682b
SM		 5466
5467 u8 response_mad_packet[256][0x8];
5468};
5469
5470struct mlx5_ifc_mad_ifc_in_bits {
5471 u8 opcode[0x10];
b4ff3a36 5472 u8 reserved_at_10[0x10];
e281682b 5473
b4ff3a36 5474 u8 reserved_at_20[0x10];
e281682b
SM		 5475 u8 op_mod[0x10];
5476
5477 u8 remote_lid[0x10];
b4ff3a36 5478 u8 reserved_at_50[0x8];
e281682b
SM		 5479 u8 port[0x8];
5480
b4ff3a36 5481 u8 reserved_at_60[0x20];
e281682b
SM		 5482
5483 u8 mad[256][0x8];
5484};
5485
5486struct mlx5_ifc_init_hca_out_bits {
5487 u8 status[0x8];
b4ff3a36 5488 u8 reserved_at_8[0x18];
e281682b
SM		 5489
5490 u8 syndrome[0x20];
5491
b4ff3a36 5492 u8 reserved_at_40[0x40];
e281682b
SM		 5493};
5494
5495struct mlx5_ifc_init_hca_in_bits {
5496 u8 opcode[0x10];
b4ff3a36 5497 u8 reserved_at_10[0x10];
e281682b 5498
b4ff3a36 5499 u8 reserved_at_20[0x10];
e281682b
SM		 5500 u8 op_mod[0x10];
5501
b4ff3a36 5502 u8 reserved_at_40[0x40];
e281682b
SM		 5503};
5504
5505struct mlx5_ifc_init2rtr_qp_out_bits {
5506 u8 status[0x8];
b4ff3a36 5507 u8 reserved_at_8[0x18];
e281682b
SM		 5508
5509 u8 syndrome[0x20];
5510
b4ff3a36 5511 u8 reserved_at_40[0x40];
e281682b
SM		 5512};
5513
5514struct mlx5_ifc_init2rtr_qp_in_bits {
5515 u8 opcode[0x10];
b4ff3a36 5516 u8 reserved_at_10[0x10];
e281682b 5517
b4ff3a36 5518 u8 reserved_at_20[0x10];
e281682b
SM		 5519 u8 op_mod[0x10];
5520
b4ff3a36 5521 u8 reserved_at_40[0x8];
e281682b
SM		 5522 u8 qpn[0x18];
5523
b4ff3a36 5524 u8 reserved_at_60[0x20];
e281682b
SM		 5525
5526 u8 opt_param_mask[0x20];
5527
b4ff3a36 5528 u8 reserved_at_a0[0x20];
e281682b
SM		 5529
5530 struct mlx5_ifc_qpc_bits qpc;
5531
b4ff3a36 5532 u8 reserved_at_800[0x80];
e281682b
SM		 5533};
5534
5535struct mlx5_ifc_init2init_qp_out_bits {
5536 u8 status[0x8];
b4ff3a36 5537 u8 reserved_at_8[0x18];
e281682b
SM		 5538
5539 u8 syndrome[0x20];
5540
b4ff3a36 5541 u8 reserved_at_40[0x40];
e281682b
SM		 5542};
5543
5544struct mlx5_ifc_init2init_qp_in_bits {
5545 u8 opcode[0x10];
b4ff3a36 5546 u8 reserved_at_10[0x10];
e281682b 5547
b4ff3a36 5548 u8 reserved_at_20[0x10];
e281682b
SM		 5549 u8 op_mod[0x10];
5550
b4ff3a36 5551 u8 reserved_at_40[0x8];
e281682b
SM		 5552 u8 qpn[0x18];
5553
b4ff3a36 5554 u8 reserved_at_60[0x20];
e281682b
SM		 5555
5556 u8 opt_param_mask[0x20];
5557
b4ff3a36 5558 u8 reserved_at_a0[0x20];
e281682b
SM		 5559
5560 struct mlx5_ifc_qpc_bits qpc;
5561
b4ff3a36 5562 u8 reserved_at_800[0x80];
e281682b
SM		 5563};
5564
5565struct mlx5_ifc_get_dropped_packet_log_out_bits {
5566 u8 status[0x8];
b4ff3a36 5567 u8 reserved_at_8[0x18];
e281682b
SM		 5568
5569 u8 syndrome[0x20];
5570
b4ff3a36 5571 u8 reserved_at_40[0x40];
e281682b
SM		 5572
5573 u8 packet_headers_log[128][0x8];
5574
5575 u8 packet_syndrome[64][0x8];
5576};
5577
5578struct mlx5_ifc_get_dropped_packet_log_in_bits {
5579 u8 opcode[0x10];
b4ff3a36 5580 u8 reserved_at_10[0x10];
e281682b 5581
b4ff3a36 5582 u8 reserved_at_20[0x10];
e281682b
SM		 5583 u8 op_mod[0x10];
5584
b4ff3a36 5585 u8 reserved_at_40[0x40];
e281682b
SM		 5586};
5587
5588struct mlx5_ifc_gen_eqe_in_bits {
5589 u8 opcode[0x10];
b4ff3a36 5590 u8 reserved_at_10[0x10];
e281682b 5591
b4ff3a36 5592 u8 reserved_at_20[0x10];
e281682b
SM		 5593 u8 op_mod[0x10];
5594
b4ff3a36 5595 u8 reserved_at_40[0x18];
e281682b
SM		 5596 u8 eq_number[0x8];
5597
b4ff3a36 5598 u8 reserved_at_60[0x20];
e281682b
SM		 5599
5600 u8 eqe[64][0x8];
5601};
5602
5603struct mlx5_ifc_gen_eq_out_bits {
5604 u8 status[0x8];
b4ff3a36 5605 u8 reserved_at_8[0x18];
e281682b
SM		 5606
5607 u8 syndrome[0x20];
5608
b4ff3a36 5609 u8 reserved_at_40[0x40];
e281682b
SM		 5610};
5611
5612struct mlx5_ifc_enable_hca_out_bits {
5613 u8 status[0x8];
b4ff3a36 5614 u8 reserved_at_8[0x18];
e281682b
SM		 5615
5616 u8 syndrome[0x20];
5617
b4ff3a36 5618 u8 reserved_at_40[0x20];
e281682b
SM		 5619};
5620
5621struct mlx5_ifc_enable_hca_in_bits {
5622 u8 opcode[0x10];
b4ff3a36 5623 u8 reserved_at_10[0x10];
e281682b 5624
b4ff3a36 5625 u8 reserved_at_20[0x10];
e281682b
SM		 5626 u8 op_mod[0x10];
5627
b4ff3a36 5628 u8 reserved_at_40[0x10];
e281682b
SM		 5629 u8 function_id[0x10];
5630
b4ff3a36 5631 u8 reserved_at_60[0x20];
e281682b
SM		 5632};
5633
5634struct mlx5_ifc_drain_dct_out_bits {
5635 u8 status[0x8];
b4ff3a36 5636 u8 reserved_at_8[0x18];
e281682b
SM		 5637
5638 u8 syndrome[0x20];
5639
b4ff3a36 5640 u8 reserved_at_40[0x40];
e281682b
SM		 5641};
5642
5643struct mlx5_ifc_drain_dct_in_bits {
5644 u8 opcode[0x10];
b4ff3a36 5645 u8 reserved_at_10[0x10];
e281682b 5646
b4ff3a36 5647 u8 reserved_at_20[0x10];
e281682b
SM		 5648 u8 op_mod[0x10];
5649
b4ff3a36 5650 u8 reserved_at_40[0x8];
e281682b
SM		 5651 u8 dctn[0x18];
5652
b4ff3a36 5653 u8 reserved_at_60[0x20];
e281682b
SM		 5654};
5655
5656struct mlx5_ifc_disable_hca_out_bits {
5657 u8 status[0x8];
b4ff3a36 5658 u8 reserved_at_8[0x18];
e281682b
SM		 5659
5660 u8 syndrome[0x20];
5661
b4ff3a36 5662 u8 reserved_at_40[0x20];
e281682b
SM		 5663};
5664
5665struct mlx5_ifc_disable_hca_in_bits {
5666 u8 opcode[0x10];
b4ff3a36 5667 u8 reserved_at_10[0x10];
e281682b 5668
b4ff3a36 5669 u8 reserved_at_20[0x10];
e281682b
SM		 5670 u8 op_mod[0x10];
5671
b4ff3a36 5672 u8 reserved_at_40[0x10];
e281682b
SM		 5673 u8 function_id[0x10];
5674
b4ff3a36 5675 u8 reserved_at_60[0x20];
e281682b
SM		 5676};
5677
5678struct mlx5_ifc_detach_from_mcg_out_bits {
5679 u8 status[0x8];
b4ff3a36 5680 u8 reserved_at_8[0x18];
e281682b
SM		 5681
5682 u8 syndrome[0x20];
5683
b4ff3a36 5684 u8 reserved_at_40[0x40];
e281682b
SM		 5685};
5686
5687struct mlx5_ifc_detach_from_mcg_in_bits {
5688 u8 opcode[0x10];
b4ff3a36 5689 u8 reserved_at_10[0x10];
e281682b 5690
b4ff3a36 5691 u8 reserved_at_20[0x10];
e281682b
SM		 5692 u8 op_mod[0x10];
5693
b4ff3a36 5694 u8 reserved_at_40[0x8];
e281682b
SM		 5695 u8 qpn[0x18];
5696
b4ff3a36 5697 u8 reserved_at_60[0x20];
e281682b
SM		 5698
5699 u8 multicast_gid[16][0x8];
5700};
5701
7486216b
SM		 5702struct mlx5_ifc_destroy_xrq_out_bits {
5703 u8 status[0x8];
5704 u8 reserved_at_8[0x18];
5705
5706 u8 syndrome[0x20];
5707
5708 u8 reserved_at_40[0x40];
5709};
5710
5711struct mlx5_ifc_destroy_xrq_in_bits {
5712 u8 opcode[0x10];
5713 u8 reserved_at_10[0x10];
5714
5715 u8 reserved_at_20[0x10];
5716 u8 op_mod[0x10];
5717
5718 u8 reserved_at_40[0x8];
5719 u8 xrqn[0x18];
5720
5721 u8 reserved_at_60[0x20];
5722};
5723
e281682b
SM		 5724struct mlx5_ifc_destroy_xrc_srq_out_bits {
5725 u8 status[0x8];
b4ff3a36 5726 u8 reserved_at_8[0x18];
e281682b
SM		 5727
5728 u8 syndrome[0x20];
5729
b4ff3a36 5730 u8 reserved_at_40[0x40];
e281682b
SM		 5731};
5732
5733struct mlx5_ifc_destroy_xrc_srq_in_bits {
5734 u8 opcode[0x10];
b4ff3a36 5735 u8 reserved_at_10[0x10];
e281682b 5736
b4ff3a36 5737 u8 reserved_at_20[0x10];
e281682b
SM		 5738 u8 op_mod[0x10];
5739
b4ff3a36 5740 u8 reserved_at_40[0x8];
e281682b
SM		 5741 u8 xrc_srqn[0x18];
5742
b4ff3a36 5743 u8 reserved_at_60[0x20];
e281682b
SM		 5744};
5745
5746struct mlx5_ifc_destroy_tis_out_bits {
5747 u8 status[0x8];
b4ff3a36 5748 u8 reserved_at_8[0x18];
e281682b
SM		 5749
5750 u8 syndrome[0x20];
5751
b4ff3a36 5752 u8 reserved_at_40[0x40];
e281682b
SM		 5753};
5754
5755struct mlx5_ifc_destroy_tis_in_bits {
5756 u8 opcode[0x10];
b4ff3a36 5757 u8 reserved_at_10[0x10];
e281682b 5758
b4ff3a36 5759 u8 reserved_at_20[0x10];
e281682b
SM		 5760 u8 op_mod[0x10];
5761
b4ff3a36 5762 u8 reserved_at_40[0x8];
e281682b
SM		 5763 u8 tisn[0x18];
5764
b4ff3a36 5765 u8 reserved_at_60[0x20];
e281682b
SM		 5766};
5767
5768struct mlx5_ifc_destroy_tir_out_bits {
5769 u8 status[0x8];
b4ff3a36 5770 u8 reserved_at_8[0x18];
e281682b
SM		 5771
5772 u8 syndrome[0x20];
5773
b4ff3a36 5774 u8 reserved_at_40[0x40];
e281682b
SM		 5775};
5776
5777struct mlx5_ifc_destroy_tir_in_bits {
5778 u8 opcode[0x10];
b4ff3a36 5779 u8 reserved_at_10[0x10];
e281682b 5780
b4ff3a36 5781 u8 reserved_at_20[0x10];
e281682b
SM		 5782 u8 op_mod[0x10];
5783
b4ff3a36 5784 u8 reserved_at_40[0x8];
e281682b
SM		 5785 u8 tirn[0x18];
5786
b4ff3a36 5787 u8 reserved_at_60[0x20];
e281682b
SM		 5788};
5789
5790struct mlx5_ifc_destroy_srq_out_bits {
5791 u8 status[0x8];
b4ff3a36 5792 u8 reserved_at_8[0x18];
e281682b
SM		 5793
5794 u8 syndrome[0x20];
5795
b4ff3a36 5796 u8 reserved_at_40[0x40];
e281682b
SM		 5797};
5798
5799struct mlx5_ifc_destroy_srq_in_bits {
5800 u8 opcode[0x10];
b4ff3a36 5801 u8 reserved_at_10[0x10];
e281682b 5802
b4ff3a36 5803 u8 reserved_at_20[0x10];
e281682b
SM		 5804 u8 op_mod[0x10];
5805
b4ff3a36 5806 u8 reserved_at_40[0x8];
e281682b
SM		 5807 u8 srqn[0x18];
5808
b4ff3a36 5809 u8 reserved_at_60[0x20];
e281682b
SM		 5810};
5811
5812struct mlx5_ifc_destroy_sq_out_bits {
5813 u8 status[0x8];
b4ff3a36 5814 u8 reserved_at_8[0x18];
e281682b
SM		 5815
5816 u8 syndrome[0x20];
5817
b4ff3a36 5818 u8 reserved_at_40[0x40];
e281682b
SM		 5819};
5820
5821struct mlx5_ifc_destroy_sq_in_bits {
5822 u8 opcode[0x10];
b4ff3a36 5823 u8 reserved_at_10[0x10];
e281682b 5824
b4ff3a36 5825 u8 reserved_at_20[0x10];
e281682b
SM		 5826 u8 op_mod[0x10];
5827
b4ff3a36 5828 u8 reserved_at_40[0x8];
e281682b
SM		 5829 u8 sqn[0x18];
5830
b4ff3a36 5831 u8 reserved_at_60[0x20];
e281682b
SM		 5832};
5833
813f8540
MHY		 5834struct mlx5_ifc_destroy_scheduling_element_out_bits {
5835 u8 status[0x8];
5836 u8 reserved_at_8[0x18];
5837
5838 u8 syndrome[0x20];
5839
5840 u8 reserved_at_40[0x1c0];
5841};
5842
5843struct mlx5_ifc_destroy_scheduling_element_in_bits {
5844 u8 opcode[0x10];
5845 u8 reserved_at_10[0x10];
5846
5847 u8 reserved_at_20[0x10];
5848 u8 op_mod[0x10];
5849
5850 u8 scheduling_hierarchy[0x8];
5851 u8 reserved_at_48[0x18];
5852
5853 u8 scheduling_element_id[0x20];
5854
5855 u8 reserved_at_80[0x180];
5856};
5857
e281682b
SM		 5858struct mlx5_ifc_destroy_rqt_out_bits {
5859 u8 status[0x8];
b4ff3a36 5860 u8 reserved_at_8[0x18];
e281682b
SM		 5861
5862 u8 syndrome[0x20];
5863
b4ff3a36 5864 u8 reserved_at_40[0x40];
e281682b
SM		 5865};
5866
5867struct mlx5_ifc_destroy_rqt_in_bits {
5868 u8 opcode[0x10];
b4ff3a36 5869 u8 reserved_at_10[0x10];
e281682b 5870
b4ff3a36 5871 u8 reserved_at_20[0x10];
e281682b
SM		 5872 u8 op_mod[0x10];
5873
b4ff3a36 5874 u8 reserved_at_40[0x8];
e281682b
SM		 5875 u8 rqtn[0x18];
5876
b4ff3a36 5877 u8 reserved_at_60[0x20];
e281682b
SM		 5878};
5879
5880struct mlx5_ifc_destroy_rq_out_bits {
5881 u8 status[0x8];
b4ff3a36 5882 u8 reserved_at_8[0x18];
e281682b
SM		 5883
5884 u8 syndrome[0x20];
5885
b4ff3a36 5886 u8 reserved_at_40[0x40];
e281682b
SM		 5887};
5888
5889struct mlx5_ifc_destroy_rq_in_bits {
5890 u8 opcode[0x10];
b4ff3a36 5891 u8 reserved_at_10[0x10];
e281682b 5892
b4ff3a36 5893 u8 reserved_at_20[0x10];
e281682b
SM		 5894 u8 op_mod[0x10];
5895
b4ff3a36 5896 u8 reserved_at_40[0x8];
e281682b
SM		 5897 u8 rqn[0x18];
5898
b4ff3a36 5899 u8 reserved_at_60[0x20];
e281682b
SM		 5900};
5901
c1e0bfc1
MG		 5902struct mlx5_ifc_set_delay_drop_params_in_bits {
5903 u8 opcode[0x10];
5904 u8 reserved_at_10[0x10];
5905
5906 u8 reserved_at_20[0x10];
5907 u8 op_mod[0x10];
5908
5909 u8 reserved_at_40[0x20];
5910
5911 u8 reserved_at_60[0x10];
5912 u8 delay_drop_timeout[0x10];
5913};
5914
5915struct mlx5_ifc_set_delay_drop_params_out_bits {
5916 u8 status[0x8];
5917 u8 reserved_at_8[0x18];
5918
5919 u8 syndrome[0x20];
5920
5921 u8 reserved_at_40[0x40];
5922};
5923
e281682b
SM		 5924struct mlx5_ifc_destroy_rmp_out_bits {
5925 u8 status[0x8];
b4ff3a36 5926 u8 reserved_at_8[0x18];
e281682b
SM		 5927
5928 u8 syndrome[0x20];
5929
b4ff3a36 5930 u8 reserved_at_40[0x40];
e281682b
SM		 5931};
5932
5933struct mlx5_ifc_destroy_rmp_in_bits {
5934 u8 opcode[0x10];
b4ff3a36 5935 u8 reserved_at_10[0x10];
e281682b 5936
b4ff3a36 5937 u8 reserved_at_20[0x10];
e281682b
SM		 5938 u8 op_mod[0x10];
5939
b4ff3a36 5940 u8 reserved_at_40[0x8];
e281682b
SM		 5941 u8 rmpn[0x18];
5942
b4ff3a36 5943 u8 reserved_at_60[0x20];
e281682b
SM		 5944};
5945
5946struct mlx5_ifc_destroy_qp_out_bits {
5947 u8 status[0x8];
b4ff3a36 5948 u8 reserved_at_8[0x18];
e281682b
SM		 5949
5950 u8 syndrome[0x20];
5951
b4ff3a36 5952 u8 reserved_at_40[0x40];
e281682b
SM		 5953};
5954
5955struct mlx5_ifc_destroy_qp_in_bits {
5956 u8 opcode[0x10];
b4ff3a36 5957 u8 reserved_at_10[0x10];
e281682b 5958
b4ff3a36 5959 u8 reserved_at_20[0x10];
e281682b
SM		 5960 u8 op_mod[0x10];
5961
b4ff3a36 5962 u8 reserved_at_40[0x8];
e281682b
SM		 5963 u8 qpn[0x18];
5964
b4ff3a36 5965 u8 reserved_at_60[0x20];
e281682b
SM		 5966};
5967
5968struct mlx5_ifc_destroy_psv_out_bits {
5969 u8 status[0x8];
b4ff3a36 5970 u8 reserved_at_8[0x18];
e281682b
SM		 5971
5972 u8 syndrome[0x20];
5973
b4ff3a36 5974 u8 reserved_at_40[0x40];
e281682b
SM		 5975};
5976
5977struct mlx5_ifc_destroy_psv_in_bits {
5978 u8 opcode[0x10];
b4ff3a36 5979 u8 reserved_at_10[0x10];
e281682b 5980
b4ff3a36 5981 u8 reserved_at_20[0x10];
e281682b
SM		 5982 u8 op_mod[0x10];
5983
b4ff3a36 5984 u8 reserved_at_40[0x8];
e281682b
SM		 5985 u8 psvn[0x18];
5986
b4ff3a36 5987 u8 reserved_at_60[0x20];
e281682b
SM		 5988};
5989
5990struct mlx5_ifc_destroy_mkey_out_bits {
5991 u8 status[0x8];
b4ff3a36 5992 u8 reserved_at_8[0x18];
e281682b
SM		 5993
5994 u8 syndrome[0x20];
5995
b4ff3a36 5996 u8 reserved_at_40[0x40];
e281682b
SM		 5997};
5998
5999struct mlx5_ifc_destroy_mkey_in_bits {
6000 u8 opcode[0x10];
b4ff3a36 6001 u8 reserved_at_10[0x10];
e281682b 6002
b4ff3a36 6003 u8 reserved_at_20[0x10];
e281682b
SM		 6004 u8 op_mod[0x10];
6005
b4ff3a36 6006 u8 reserved_at_40[0x8];
e281682b
SM		 6007 u8 mkey_index[0x18];
6008
b4ff3a36 6009 u8 reserved_at_60[0x20];
e281682b
SM		 6010};
6011
6012struct mlx5_ifc_destroy_flow_table_out_bits {
6013 u8 status[0x8];
b4ff3a36 6014 u8 reserved_at_8[0x18];
e281682b
SM		 6015
6016 u8 syndrome[0x20];
6017
b4ff3a36 6018 u8 reserved_at_40[0x40];
e281682b
SM		 6019};
6020
6021struct mlx5_ifc_destroy_flow_table_in_bits {
6022 u8 opcode[0x10];
b4ff3a36 6023 u8 reserved_at_10[0x10];
e281682b 6024
b4ff3a36 6025 u8 reserved_at_20[0x10];
e281682b
SM		 6026 u8 op_mod[0x10];
6027
7d5e1423
SM		 6028 u8 other_vport[0x1];
6029 u8 reserved_at_41[0xf];
6030 u8 vport_number[0x10];
6031
6032 u8 reserved_at_60[0x20];
e281682b
SM		 6033
6034 u8 table_type[0x8];
b4ff3a36 6035 u8 reserved_at_88[0x18];
e281682b 6036
b4ff3a36 6037 u8 reserved_at_a0[0x8];
e281682b
SM		 6038 u8 table_id[0x18];
6039
b4ff3a36 6040 u8 reserved_at_c0[0x140];
e281682b
SM		 6041};
6042
6043struct mlx5_ifc_destroy_flow_group_out_bits {
6044 u8 status[0x8];
b4ff3a36 6045 u8 reserved_at_8[0x18];
e281682b
SM		 6046
6047 u8 syndrome[0x20];
6048
b4ff3a36 6049 u8 reserved_at_40[0x40];
e281682b
SM		 6050};
6051
6052struct mlx5_ifc_destroy_flow_group_in_bits {
6053 u8 opcode[0x10];
b4ff3a36 6054 u8 reserved_at_10[0x10];
e281682b 6055
b4ff3a36 6056 u8 reserved_at_20[0x10];
e281682b
SM		 6057 u8 op_mod[0x10];
6058
7d5e1423
SM		 6059 u8 other_vport[0x1];
6060 u8 reserved_at_41[0xf];
6061 u8 vport_number[0x10];
6062
6063 u8 reserved_at_60[0x20];
e281682b
SM		 6064
6065 u8 table_type[0x8];
b4ff3a36 6066 u8 reserved_at_88[0x18];
e281682b 6067
b4ff3a36 6068 u8 reserved_at_a0[0x8];
e281682b
SM		 6069 u8 table_id[0x18];
6070
6071 u8 group_id[0x20];
6072
b4ff3a36 6073 u8 reserved_at_e0[0x120];
e281682b
SM		 6074};
6075
6076struct mlx5_ifc_destroy_eq_out_bits {
6077 u8 status[0x8];
b4ff3a36 6078 u8 reserved_at_8[0x18];
e281682b
SM		 6079
6080 u8 syndrome[0x20];
6081
b4ff3a36 6082 u8 reserved_at_40[0x40];
e281682b
SM		 6083};
6084
6085struct mlx5_ifc_destroy_eq_in_bits {
6086 u8 opcode[0x10];
b4ff3a36 6087 u8 reserved_at_10[0x10];
e281682b 6088
b4ff3a36 6089 u8 reserved_at_20[0x10];
e281682b
SM		 6090 u8 op_mod[0x10];
6091
b4ff3a36 6092 u8 reserved_at_40[0x18];
e281682b
SM		 6093 u8 eq_number[0x8];
6094
b4ff3a36 6095 u8 reserved_at_60[0x20];
e281682b
SM		 6096};
6097
6098struct mlx5_ifc_destroy_dct_out_bits {
6099 u8 status[0x8];
b4ff3a36 6100 u8 reserved_at_8[0x18];
e281682b
SM		 6101
6102 u8 syndrome[0x20];
6103
b4ff3a36 6104 u8 reserved_at_40[0x40];
e281682b
SM		 6105};
6106
6107struct mlx5_ifc_destroy_dct_in_bits {
6108 u8 opcode[0x10];
b4ff3a36 6109 u8 reserved_at_10[0x10];
e281682b 6110
b4ff3a36 6111 u8 reserved_at_20[0x10];
e281682b
SM		 6112 u8 op_mod[0x10];
6113
b4ff3a36 6114 u8 reserved_at_40[0x8];
e281682b
SM		 6115 u8 dctn[0x18];
6116
b4ff3a36 6117 u8 reserved_at_60[0x20];
e281682b
SM		 6118};
6119
6120struct mlx5_ifc_destroy_cq_out_bits {
6121 u8 status[0x8];
b4ff3a36 6122 u8 reserved_at_8[0x18];
e281682b
SM		 6123
6124 u8 syndrome[0x20];
6125
b4ff3a36 6126 u8 reserved_at_40[0x40];
e281682b
SM		 6127};
6128
6129struct mlx5_ifc_destroy_cq_in_bits {
6130 u8 opcode[0x10];
b4ff3a36 6131 u8 reserved_at_10[0x10];
e281682b 6132
b4ff3a36 6133 u8 reserved_at_20[0x10];
e281682b
SM		 6134 u8 op_mod[0x10];
6135
b4ff3a36 6136 u8 reserved_at_40[0x8];
e281682b
SM		 6137 u8 cqn[0x18];
6138
b4ff3a36 6139 u8 reserved_at_60[0x20];
e281682b
SM		 6140};
6141
6142struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6143 u8 status[0x8];
b4ff3a36 6144 u8 reserved_at_8[0x18];
e281682b
SM		 6145
6146 u8 syndrome[0x20];
6147
b4ff3a36 6148 u8 reserved_at_40[0x40];
e281682b
SM		 6149};
6150
6151struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6152 u8 opcode[0x10];
b4ff3a36 6153 u8 reserved_at_10[0x10];
e281682b 6154
b4ff3a36 6155 u8 reserved_at_20[0x10];
e281682b
SM		 6156 u8 op_mod[0x10];
6157
b4ff3a36 6158 u8 reserved_at_40[0x20];
e281682b 6159
b4ff3a36 6160 u8 reserved_at_60[0x10];
e281682b
SM		 6161 u8 vxlan_udp_port[0x10];
6162};
6163
6164struct mlx5_ifc_delete_l2_table_entry_out_bits {
6165 u8 status[0x8];
b4ff3a36 6166 u8 reserved_at_8[0x18];
e281682b
SM		 6167
6168 u8 syndrome[0x20];
6169
b4ff3a36 6170 u8 reserved_at_40[0x40];
e281682b
SM		 6171};
6172
6173struct mlx5_ifc_delete_l2_table_entry_in_bits {
6174 u8 opcode[0x10];
b4ff3a36 6175 u8 reserved_at_10[0x10];
e281682b 6176
b4ff3a36 6177 u8 reserved_at_20[0x10];
e281682b
SM		 6178 u8 op_mod[0x10];
6179
b4ff3a36 6180 u8 reserved_at_40[0x60];
e281682b 6181
b4ff3a36 6182 u8 reserved_at_a0[0x8];
e281682b
SM		 6183 u8 table_index[0x18];
6184
b4ff3a36 6185 u8 reserved_at_c0[0x140];
e281682b
SM		 6186};
6187
6188struct mlx5_ifc_delete_fte_out_bits {
6189 u8 status[0x8];
b4ff3a36 6190 u8 reserved_at_8[0x18];
e281682b
SM		 6191
6192 u8 syndrome[0x20];
6193
b4ff3a36 6194 u8 reserved_at_40[0x40];
e281682b
SM		 6195};
6196
6197struct mlx5_ifc_delete_fte_in_bits {
6198 u8 opcode[0x10];
b4ff3a36 6199 u8 reserved_at_10[0x10];
e281682b 6200
b4ff3a36 6201 u8 reserved_at_20[0x10];
e281682b
SM		 6202 u8 op_mod[0x10];
6203
7d5e1423
SM		 6204 u8 other_vport[0x1];
6205 u8 reserved_at_41[0xf];
6206 u8 vport_number[0x10];
6207
6208 u8 reserved_at_60[0x20];
e281682b
SM		 6209
6210 u8 table_type[0x8];
b4ff3a36 6211 u8 reserved_at_88[0x18];
e281682b 6212
b4ff3a36 6213 u8 reserved_at_a0[0x8];
e281682b
SM		 6214 u8 table_id[0x18];
6215
b4ff3a36 6216 u8 reserved_at_c0[0x40];
e281682b
SM		 6217
6218 u8 flow_index[0x20];
6219
b4ff3a36 6220 u8 reserved_at_120[0xe0];
e281682b
SM		 6221};
6222
6223struct mlx5_ifc_dealloc_xrcd_out_bits {
6224 u8 status[0x8];
b4ff3a36 6225 u8 reserved_at_8[0x18];
e281682b
SM		 6226
6227 u8 syndrome[0x20];
6228
b4ff3a36 6229 u8 reserved_at_40[0x40];
e281682b
SM		 6230};
6231
6232struct mlx5_ifc_dealloc_xrcd_in_bits {
6233 u8 opcode[0x10];
b4ff3a36 6234 u8 reserved_at_10[0x10];
e281682b 6235
b4ff3a36 6236 u8 reserved_at_20[0x10];
e281682b
SM		 6237 u8 op_mod[0x10];
6238
b4ff3a36 6239 u8 reserved_at_40[0x8];
e281682b
SM		 6240 u8 xrcd[0x18];
6241
b4ff3a36 6242 u8 reserved_at_60[0x20];
e281682b
SM		 6243};
6244
6245struct mlx5_ifc_dealloc_uar_out_bits {
6246 u8 status[0x8];
b4ff3a36 6247 u8 reserved_at_8[0x18];
e281682b
SM		 6248
6249 u8 syndrome[0x20];
6250
b4ff3a36 6251 u8 reserved_at_40[0x40];
e281682b
SM		 6252};
6253
6254struct mlx5_ifc_dealloc_uar_in_bits {
6255 u8 opcode[0x10];
b4ff3a36 6256 u8 reserved_at_10[0x10];
e281682b 6257
b4ff3a36 6258 u8 reserved_at_20[0x10];
e281682b
SM		 6259 u8 op_mod[0x10];
6260
b4ff3a36 6261 u8 reserved_at_40[0x8];
e281682b
SM		 6262 u8 uar[0x18];
6263
b4ff3a36 6264 u8 reserved_at_60[0x20];
e281682b
SM		 6265};
6266
6267struct mlx5_ifc_dealloc_transport_domain_out_bits {
6268 u8 status[0x8];
b4ff3a36 6269 u8 reserved_at_8[0x18];
e281682b
SM		 6270
6271 u8 syndrome[0x20];
6272
b4ff3a36 6273 u8 reserved_at_40[0x40];
e281682b
SM		 6274};
6275
6276struct mlx5_ifc_dealloc_transport_domain_in_bits {
6277 u8 opcode[0x10];
b4ff3a36 6278 u8 reserved_at_10[0x10];
e281682b 6279
b4ff3a36 6280 u8 reserved_at_20[0x10];
e281682b
SM		 6281 u8 op_mod[0x10];
6282
b4ff3a36 6283 u8 reserved_at_40[0x8];
e281682b
SM		 6284 u8 transport_domain[0x18];
6285
b4ff3a36 6286 u8 reserved_at_60[0x20];
e281682b
SM		 6287};
6288
6289struct mlx5_ifc_dealloc_q_counter_out_bits {
6290 u8 status[0x8];
b4ff3a36 6291 u8 reserved_at_8[0x18];
e281682b
SM		 6292
6293 u8 syndrome[0x20];
6294
b4ff3a36 6295 u8 reserved_at_40[0x40];
e281682b
SM		 6296};
6297
6298struct mlx5_ifc_dealloc_q_counter_in_bits {
6299 u8 opcode[0x10];
b4ff3a36 6300 u8 reserved_at_10[0x10];
e281682b 6301
b4ff3a36 6302 u8 reserved_at_20[0x10];
e281682b
SM		 6303 u8 op_mod[0x10];
6304
b4ff3a36 6305 u8 reserved_at_40[0x18];
e281682b
SM		 6306 u8 counter_set_id[0x8];
6307
b4ff3a36 6308 u8 reserved_at_60[0x20];
e281682b
SM		 6309};
6310
6311struct mlx5_ifc_dealloc_pd_out_bits {
6312 u8 status[0x8];
b4ff3a36 6313 u8 reserved_at_8[0x18];
e281682b
SM		 6314
6315 u8 syndrome[0x20];
6316
b4ff3a36 6317 u8 reserved_at_40[0x40];
e281682b
SM		 6318};
6319
6320struct mlx5_ifc_dealloc_pd_in_bits {
6321 u8 opcode[0x10];
b4ff3a36 6322 u8 reserved_at_10[0x10];
e281682b 6323
b4ff3a36 6324 u8 reserved_at_20[0x10];
e281682b
SM		 6325 u8 op_mod[0x10];
6326
b4ff3a36 6327 u8 reserved_at_40[0x8];
e281682b
SM		 6328 u8 pd[0x18];
6329
b4ff3a36 6330 u8 reserved_at_60[0x20];
e281682b
SM		 6331};
6332
9dc0b289
AV		 6333struct mlx5_ifc_dealloc_flow_counter_out_bits {
6334 u8 status[0x8];
6335 u8 reserved_at_8[0x18];
6336
6337 u8 syndrome[0x20];
6338
6339 u8 reserved_at_40[0x40];
6340};
6341
6342struct mlx5_ifc_dealloc_flow_counter_in_bits {
6343 u8 opcode[0x10];
6344 u8 reserved_at_10[0x10];
6345
6346 u8 reserved_at_20[0x10];
6347 u8 op_mod[0x10];
6348
6349 u8 reserved_at_40[0x10];
6350 u8 flow_counter_id[0x10];
6351
6352 u8 reserved_at_60[0x20];
6353};
6354
7486216b
SM		 6355struct mlx5_ifc_create_xrq_out_bits {
6356 u8 status[0x8];
6357 u8 reserved_at_8[0x18];
6358
6359 u8 syndrome[0x20];
6360
6361 u8 reserved_at_40[0x8];
6362 u8 xrqn[0x18];
6363
6364 u8 reserved_at_60[0x20];
6365};
6366
6367struct mlx5_ifc_create_xrq_in_bits {
6368 u8 opcode[0x10];
6369 u8 reserved_at_10[0x10];
6370
6371 u8 reserved_at_20[0x10];
6372 u8 op_mod[0x10];
6373
6374 u8 reserved_at_40[0x40];
6375
6376 struct mlx5_ifc_xrqc_bits xrq_context;
6377};
6378
e281682b
SM		 6379struct mlx5_ifc_create_xrc_srq_out_bits {
6380 u8 status[0x8];
b4ff3a36 6381 u8 reserved_at_8[0x18];
e281682b
SM		 6382
6383 u8 syndrome[0x20];
6384
b4ff3a36 6385 u8 reserved_at_40[0x8];
e281682b
SM		 6386 u8 xrc_srqn[0x18];
6387
b4ff3a36 6388 u8 reserved_at_60[0x20];
e281682b
SM		 6389};
6390
6391struct mlx5_ifc_create_xrc_srq_in_bits {
6392 u8 opcode[0x10];
b4ff3a36 6393 u8 reserved_at_10[0x10];
e281682b 6394
b4ff3a36 6395 u8 reserved_at_20[0x10];
e281682b
SM		 6396 u8 op_mod[0x10];
6397
b4ff3a36 6398 u8 reserved_at_40[0x40];
e281682b
SM		 6399
6400 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6401
b4ff3a36 6402 u8 reserved_at_280[0x600];
e281682b
SM		 6403
6404 u8 pas[0][0x40];
6405};
6406
6407struct mlx5_ifc_create_tis_out_bits {
6408 u8 status[0x8];
b4ff3a36 6409 u8 reserved_at_8[0x18];
e281682b
SM		 6410
6411 u8 syndrome[0x20];
6412
b4ff3a36 6413 u8 reserved_at_40[0x8];
e281682b
SM		 6414 u8 tisn[0x18];
6415
b4ff3a36 6416 u8 reserved_at_60[0x20];
e281682b
SM		 6417};
6418
6419struct mlx5_ifc_create_tis_in_bits {
6420 u8 opcode[0x10];
b4ff3a36 6421 u8 reserved_at_10[0x10];
e281682b 6422
b4ff3a36 6423 u8 reserved_at_20[0x10];
e281682b
SM		 6424 u8 op_mod[0x10];
6425
b4ff3a36 6426 u8 reserved_at_40[0xc0];
e281682b
SM		 6427
6428 struct mlx5_ifc_tisc_bits ctx;
6429};
6430
6431struct mlx5_ifc_create_tir_out_bits {
6432 u8 status[0x8];
b4ff3a36 6433 u8 reserved_at_8[0x18];
e281682b
SM		 6434
6435 u8 syndrome[0x20];
6436
b4ff3a36 6437 u8 reserved_at_40[0x8];
e281682b
SM		 6438 u8 tirn[0x18];
6439
b4ff3a36 6440 u8 reserved_at_60[0x20];
e281682b
SM		 6441};
6442
6443struct mlx5_ifc_create_tir_in_bits {
6444 u8 opcode[0x10];
b4ff3a36 6445 u8 reserved_at_10[0x10];
e281682b 6446
b4ff3a36 6447 u8 reserved_at_20[0x10];
e281682b
SM		 6448 u8 op_mod[0x10];
6449
b4ff3a36 6450 u8 reserved_at_40[0xc0];
e281682b
SM		 6451
6452 struct mlx5_ifc_tirc_bits ctx;
6453};
6454
6455struct mlx5_ifc_create_srq_out_bits {
6456 u8 status[0x8];
b4ff3a36 6457 u8 reserved_at_8[0x18];
e281682b
SM		 6458
6459 u8 syndrome[0x20];
6460
b4ff3a36 6461 u8 reserved_at_40[0x8];
e281682b
SM		 6462 u8 srqn[0x18];
6463
b4ff3a36 6464 u8 reserved_at_60[0x20];
e281682b
SM		 6465};
6466
6467struct mlx5_ifc_create_srq_in_bits {
6468 u8 opcode[0x10];
b4ff3a36 6469 u8 reserved_at_10[0x10];
e281682b 6470
b4ff3a36 6471 u8 reserved_at_20[0x10];
e281682b
SM		 6472 u8 op_mod[0x10];
6473
b4ff3a36 6474 u8 reserved_at_40[0x40];
e281682b
SM		 6475
6476 struct mlx5_ifc_srqc_bits srq_context_entry;
6477
b4ff3a36 6478 u8 reserved_at_280[0x600];
e281682b
SM		 6479
6480 u8 pas[0][0x40];
6481};
6482
6483struct mlx5_ifc_create_sq_out_bits {
6484 u8 status[0x8];
b4ff3a36 6485 u8 reserved_at_8[0x18];
e281682b
SM		 6486
6487 u8 syndrome[0x20];
6488
b4ff3a36 6489 u8 reserved_at_40[0x8];
e281682b
SM		 6490 u8 sqn[0x18];
6491
b4ff3a36 6492 u8 reserved_at_60[0x20];
e281682b
SM		 6493};
6494
6495struct mlx5_ifc_create_sq_in_bits {
6496 u8 opcode[0x10];
b4ff3a36 6497 u8 reserved_at_10[0x10];
e281682b 6498
b4ff3a36 6499 u8 reserved_at_20[0x10];
e281682b
SM		 6500 u8 op_mod[0x10];
6501
b4ff3a36 6502 u8 reserved_at_40[0xc0];
e281682b
SM		 6503
6504 struct mlx5_ifc_sqc_bits ctx;
6505};
6506
813f8540
MHY		 6507struct mlx5_ifc_create_scheduling_element_out_bits {
6508 u8 status[0x8];
6509 u8 reserved_at_8[0x18];
6510
6511 u8 syndrome[0x20];
6512
6513 u8 reserved_at_40[0x40];
6514
6515 u8 scheduling_element_id[0x20];
6516
6517 u8 reserved_at_a0[0x160];
6518};
6519
6520struct mlx5_ifc_create_scheduling_element_in_bits {
6521 u8 opcode[0x10];
6522 u8 reserved_at_10[0x10];
6523
6524 u8 reserved_at_20[0x10];
6525 u8 op_mod[0x10];
6526
6527 u8 scheduling_hierarchy[0x8];
6528 u8 reserved_at_48[0x18];
6529
6530 u8 reserved_at_60[0xa0];
6531
6532 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6533
6534 u8 reserved_at_300[0x100];
6535};
6536
e281682b
SM		 6537struct mlx5_ifc_create_rqt_out_bits {
6538 u8 status[0x8];
b4ff3a36 6539 u8 reserved_at_8[0x18];
e281682b
SM		 6540
6541 u8 syndrome[0x20];
6542
b4ff3a36 6543 u8 reserved_at_40[0x8];
e281682b
SM		 6544 u8 rqtn[0x18];
6545
b4ff3a36 6546 u8 reserved_at_60[0x20];
e281682b
SM		 6547};
6548
6549struct mlx5_ifc_create_rqt_in_bits {
6550 u8 opcode[0x10];
b4ff3a36 6551 u8 reserved_at_10[0x10];
e281682b 6552
b4ff3a36 6553 u8 reserved_at_20[0x10];
e281682b
SM		 6554 u8 op_mod[0x10];
6555
b4ff3a36 6556 u8 reserved_at_40[0xc0];
e281682b
SM		 6557
6558 struct mlx5_ifc_rqtc_bits rqt_context;
6559};
6560
6561struct mlx5_ifc_create_rq_out_bits {
6562 u8 status[0x8];
b4ff3a36 6563 u8 reserved_at_8[0x18];
e281682b
SM		 6564
6565 u8 syndrome[0x20];
6566
b4ff3a36 6567 u8 reserved_at_40[0x8];
e281682b
SM		 6568 u8 rqn[0x18];
6569
b4ff3a36 6570 u8 reserved_at_60[0x20];
e281682b
SM		 6571};
6572
6573struct mlx5_ifc_create_rq_in_bits {
6574 u8 opcode[0x10];
b4ff3a36 6575 u8 reserved_at_10[0x10];
e281682b 6576
b4ff3a36 6577 u8 reserved_at_20[0x10];
e281682b
SM		 6578 u8 op_mod[0x10];
6579
b4ff3a36 6580 u8 reserved_at_40[0xc0];
e281682b
SM		 6581
6582 struct mlx5_ifc_rqc_bits ctx;
6583};
6584
6585struct mlx5_ifc_create_rmp_out_bits {
6586 u8 status[0x8];
b4ff3a36 6587 u8 reserved_at_8[0x18];
e281682b
SM		 6588
6589 u8 syndrome[0x20];
6590
b4ff3a36 6591 u8 reserved_at_40[0x8];
e281682b
SM		 6592 u8 rmpn[0x18];
6593
b4ff3a36 6594 u8 reserved_at_60[0x20];
e281682b
SM		 6595};
6596
6597struct mlx5_ifc_create_rmp_in_bits {
6598 u8 opcode[0x10];
b4ff3a36 6599 u8 reserved_at_10[0x10];
e281682b 6600
b4ff3a36 6601 u8 reserved_at_20[0x10];
e281682b
SM		 6602 u8 op_mod[0x10];
6603
b4ff3a36 6604 u8 reserved_at_40[0xc0];
e281682b
SM		 6605
6606 struct mlx5_ifc_rmpc_bits ctx;
6607};
6608
6609struct mlx5_ifc_create_qp_out_bits {
6610 u8 status[0x8];
b4ff3a36 6611 u8 reserved_at_8[0x18];
e281682b
SM		 6612
6613 u8 syndrome[0x20];
6614
b4ff3a36 6615 u8 reserved_at_40[0x8];
e281682b
SM		 6616 u8 qpn[0x18];
6617
b4ff3a36 6618 u8 reserved_at_60[0x20];
e281682b
SM		 6619};
6620
6621struct mlx5_ifc_create_qp_in_bits {
6622 u8 opcode[0x10];
b4ff3a36 6623 u8 reserved_at_10[0x10];
e281682b 6624
b4ff3a36 6625 u8 reserved_at_20[0x10];
e281682b
SM		 6626 u8 op_mod[0x10];
6627
b4ff3a36 6628 u8 reserved_at_40[0x40];
e281682b
SM		 6629
6630 u8 opt_param_mask[0x20];
6631
b4ff3a36 6632 u8 reserved_at_a0[0x20];
e281682b
SM		 6633
6634 struct mlx5_ifc_qpc_bits qpc;
6635
b4ff3a36 6636 u8 reserved_at_800[0x80];
e281682b
SM		 6637
6638 u8 pas[0][0x40];
6639};
6640
6641struct mlx5_ifc_create_psv_out_bits {
6642 u8 status[0x8];
b4ff3a36 6643 u8 reserved_at_8[0x18];
e281682b
SM		 6644
6645 u8 syndrome[0x20];
6646
b4ff3a36 6647 u8 reserved_at_40[0x40];
e281682b 6648
b4ff3a36 6649 u8 reserved_at_80[0x8];
e281682b
SM		 6650 u8 psv0_index[0x18];
6651
b4ff3a36 6652 u8 reserved_at_a0[0x8];
e281682b
SM		 6653 u8 psv1_index[0x18];
6654
b4ff3a36 6655 u8 reserved_at_c0[0x8];
e281682b
SM		 6656 u8 psv2_index[0x18];
6657
b4ff3a36 6658 u8 reserved_at_e0[0x8];
e281682b
SM		 6659 u8 psv3_index[0x18];
6660};
6661
6662struct mlx5_ifc_create_psv_in_bits {
6663 u8 opcode[0x10];
b4ff3a36 6664 u8 reserved_at_10[0x10];
e281682b 6665
b4ff3a36 6666 u8 reserved_at_20[0x10];
e281682b
SM		 6667 u8 op_mod[0x10];
6668
6669 u8 num_psv[0x4];
b4ff3a36 6670 u8 reserved_at_44[0x4];
e281682b
SM		 6671 u8 pd[0x18];
6672
b4ff3a36 6673 u8 reserved_at_60[0x20];
e281682b
SM		 6674};
6675
6676struct mlx5_ifc_create_mkey_out_bits {
6677 u8 status[0x8];
b4ff3a36 6678 u8 reserved_at_8[0x18];
e281682b
SM		 6679
6680 u8 syndrome[0x20];
6681
b4ff3a36 6682 u8 reserved_at_40[0x8];
e281682b
SM		 6683 u8 mkey_index[0x18];
6684
b4ff3a36 6685 u8 reserved_at_60[0x20];
e281682b
SM		 6686};
6687
6688struct mlx5_ifc_create_mkey_in_bits {
6689 u8 opcode[0x10];
b4ff3a36 6690 u8 reserved_at_10[0x10];
e281682b 6691
b4ff3a36 6692 u8 reserved_at_20[0x10];
e281682b
SM		 6693 u8 op_mod[0x10];
6694
b4ff3a36 6695 u8 reserved_at_40[0x20];
e281682b
SM		 6696
6697 u8 pg_access[0x1];
b4ff3a36 6698 u8 reserved_at_61[0x1f];
e281682b
SM		 6699
6700 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6701
b4ff3a36 6702 u8 reserved_at_280[0x80];
e281682b
SM		 6703
6704 u8 translations_octword_actual_size[0x20];
6705
b4ff3a36 6706 u8 reserved_at_320[0x560];
e281682b
SM		 6707
6708 u8 klm_pas_mtt[0][0x20];
6709};
6710
6711struct mlx5_ifc_create_flow_table_out_bits {
6712 u8 status[0x8];
b4ff3a36 6713 u8 reserved_at_8[0x18];
e281682b
SM		 6714
6715 u8 syndrome[0x20];
6716
b4ff3a36 6717 u8 reserved_at_40[0x8];
e281682b
SM		 6718 u8 table_id[0x18];
6719
b4ff3a36 6720 u8 reserved_at_60[0x20];
e281682b
SM		 6721};
6722
0c90e9c6
MG		 6723struct mlx5_ifc_flow_table_context_bits {
6724 u8 encap_en[0x1];
6725 u8 decap_en[0x1];
6726 u8 reserved_at_2[0x2];
6727 u8 table_miss_action[0x4];
6728 u8 level[0x8];
6729 u8 reserved_at_10[0x8];
6730 u8 log_size[0x8];
6731
6732 u8 reserved_at_20[0x8];
6733 u8 table_miss_id[0x18];
6734
6735 u8 reserved_at_40[0x8];
6736 u8 lag_master_next_table_id[0x18];
6737
6738 u8 reserved_at_60[0xe0];
6739};
6740
e281682b
SM		 6741struct mlx5_ifc_create_flow_table_in_bits {
6742 u8 opcode[0x10];
b4ff3a36 6743 u8 reserved_at_10[0x10];
e281682b 6744
b4ff3a36 6745 u8 reserved_at_20[0x10];
e281682b
SM		 6746 u8 op_mod[0x10];
6747
7d5e1423
SM		 6748 u8 other_vport[0x1];
6749 u8 reserved_at_41[0xf];
6750 u8 vport_number[0x10];
6751
6752 u8 reserved_at_60[0x20];
e281682b
SM		 6753
6754 u8 table_type[0x8];
b4ff3a36 6755 u8 reserved_at_88[0x18];
e281682b 6756
b4ff3a36 6757 u8 reserved_at_a0[0x20];
e281682b 6758
0c90e9c6 6759 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6760};
6761
6762struct mlx5_ifc_create_flow_group_out_bits {
6763 u8 status[0x8];
b4ff3a36 6764 u8 reserved_at_8[0x18];
e281682b
SM		 6765
6766 u8 syndrome[0x20];
6767
b4ff3a36 6768 u8 reserved_at_40[0x8];
e281682b
SM		 6769 u8 group_id[0x18];
6770
b4ff3a36 6771 u8 reserved_at_60[0x20];
e281682b
SM		 6772};
6773
6774enum {
6775 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6776 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6777 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6778};
6779
6780struct mlx5_ifc_create_flow_group_in_bits {
6781 u8 opcode[0x10];
b4ff3a36 6782 u8 reserved_at_10[0x10];
e281682b 6783
b4ff3a36 6784 u8 reserved_at_20[0x10];
e281682b
SM		 6785 u8 op_mod[0x10];
6786
7d5e1423
SM		 6787 u8 other_vport[0x1];
6788 u8 reserved_at_41[0xf];
6789 u8 vport_number[0x10];
6790
6791 u8 reserved_at_60[0x20];
e281682b
SM		 6792
6793 u8 table_type[0x8];
b4ff3a36 6794 u8 reserved_at_88[0x18];
e281682b 6795
b4ff3a36 6796 u8 reserved_at_a0[0x8];
e281682b
SM		 6797 u8 table_id[0x18];
6798
b4ff3a36 6799 u8 reserved_at_c0[0x20];
e281682b
SM		 6800
6801 u8 start_flow_index[0x20];
6802
b4ff3a36 6803 u8 reserved_at_100[0x20];
e281682b
SM		 6804
6805 u8 end_flow_index[0x20];
6806
b4ff3a36 6807 u8 reserved_at_140[0xa0];
e281682b 6808
b4ff3a36 6809 u8 reserved_at_1e0[0x18];
e281682b
SM		 6810 u8 match_criteria_enable[0x8];
6811
6812 struct mlx5_ifc_fte_match_param_bits match_criteria;
6813
b4ff3a36 6814 u8 reserved_at_1200[0xe00];
e281682b
SM		 6815};
6816
6817struct mlx5_ifc_create_eq_out_bits {
6818 u8 status[0x8];
b4ff3a36 6819 u8 reserved_at_8[0x18];
e281682b
SM		 6820
6821 u8 syndrome[0x20];
6822
b4ff3a36 6823 u8 reserved_at_40[0x18];
e281682b
SM		 6824 u8 eq_number[0x8];
6825
b4ff3a36 6826 u8 reserved_at_60[0x20];
e281682b
SM		 6827};
6828
6829struct mlx5_ifc_create_eq_in_bits {
6830 u8 opcode[0x10];
b4ff3a36 6831 u8 reserved_at_10[0x10];
e281682b 6832
b4ff3a36 6833 u8 reserved_at_20[0x10];
e281682b
SM		 6834 u8 op_mod[0x10];
6835
b4ff3a36 6836 u8 reserved_at_40[0x40];
e281682b
SM		 6837
6838 struct mlx5_ifc_eqc_bits eq_context_entry;
6839
b4ff3a36 6840 u8 reserved_at_280[0x40];
e281682b
SM		 6841
6842 u8 event_bitmask[0x40];
6843
b4ff3a36 6844 u8 reserved_at_300[0x580];
e281682b
SM		 6845
6846 u8 pas[0][0x40];
6847};
6848
6849struct mlx5_ifc_create_dct_out_bits {
6850 u8 status[0x8];
b4ff3a36 6851 u8 reserved_at_8[0x18];
e281682b
SM		 6852
6853 u8 syndrome[0x20];
6854
b4ff3a36 6855 u8 reserved_at_40[0x8];
e281682b
SM		 6856 u8 dctn[0x18];
6857
b4ff3a36 6858 u8 reserved_at_60[0x20];
e281682b
SM		 6859};
6860
6861struct mlx5_ifc_create_dct_in_bits {
6862 u8 opcode[0x10];
b4ff3a36 6863 u8 reserved_at_10[0x10];
e281682b 6864
b4ff3a36 6865 u8 reserved_at_20[0x10];
e281682b
SM		 6866 u8 op_mod[0x10];
6867
b4ff3a36 6868 u8 reserved_at_40[0x40];
e281682b
SM		 6869
6870 struct mlx5_ifc_dctc_bits dct_context_entry;
6871
b4ff3a36 6872 u8 reserved_at_280[0x180];
e281682b
SM		 6873};
6874
6875struct mlx5_ifc_create_cq_out_bits {
6876 u8 status[0x8];
b4ff3a36 6877 u8 reserved_at_8[0x18];
e281682b
SM		 6878
6879 u8 syndrome[0x20];
6880
b4ff3a36 6881 u8 reserved_at_40[0x8];
e281682b
SM		 6882 u8 cqn[0x18];
6883
b4ff3a36 6884 u8 reserved_at_60[0x20];
e281682b
SM		 6885};
6886
6887struct mlx5_ifc_create_cq_in_bits {
6888 u8 opcode[0x10];
b4ff3a36 6889 u8 reserved_at_10[0x10];
e281682b 6890
b4ff3a36 6891 u8 reserved_at_20[0x10];
e281682b
SM		 6892 u8 op_mod[0x10];
6893
b4ff3a36 6894 u8 reserved_at_40[0x40];
e281682b
SM		 6895
6896 struct mlx5_ifc_cqc_bits cq_context;
6897
b4ff3a36 6898 u8 reserved_at_280[0x600];
e281682b
SM		 6899
6900 u8 pas[0][0x40];
6901};
6902
6903struct mlx5_ifc_config_int_moderation_out_bits {
6904 u8 status[0x8];
b4ff3a36 6905 u8 reserved_at_8[0x18];
e281682b
SM		 6906
6907 u8 syndrome[0x20];
6908
b4ff3a36 6909 u8 reserved_at_40[0x4];
e281682b
SM		 6910 u8 min_delay[0xc];
6911 u8 int_vector[0x10];
6912
b4ff3a36 6913 u8 reserved_at_60[0x20];
e281682b
SM		 6914};
6915
6916enum {
6917 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6918 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6919};
6920
6921struct mlx5_ifc_config_int_moderation_in_bits {
6922 u8 opcode[0x10];
b4ff3a36 6923 u8 reserved_at_10[0x10];
e281682b 6924
b4ff3a36 6925 u8 reserved_at_20[0x10];
e281682b
SM		 6926 u8 op_mod[0x10];
6927
b4ff3a36 6928 u8 reserved_at_40[0x4];
e281682b
SM		 6929 u8 min_delay[0xc];
6930 u8 int_vector[0x10];
6931
b4ff3a36 6932 u8 reserved_at_60[0x20];
e281682b
SM		 6933};
6934
6935struct mlx5_ifc_attach_to_mcg_out_bits {
6936 u8 status[0x8];
b4ff3a36 6937 u8 reserved_at_8[0x18];
e281682b
SM		 6938
6939 u8 syndrome[0x20];
6940
b4ff3a36 6941 u8 reserved_at_40[0x40];
e281682b
SM		 6942};
6943
6944struct mlx5_ifc_attach_to_mcg_in_bits {
6945 u8 opcode[0x10];
b4ff3a36 6946 u8 reserved_at_10[0x10];
e281682b 6947
b4ff3a36 6948 u8 reserved_at_20[0x10];
e281682b
SM		 6949 u8 op_mod[0x10];
6950
b4ff3a36 6951 u8 reserved_at_40[0x8];
e281682b
SM		 6952 u8 qpn[0x18];
6953
b4ff3a36 6954 u8 reserved_at_60[0x20];
e281682b
SM		 6955
6956 u8 multicast_gid[16][0x8];
6957};
6958
7486216b
SM		 6959struct mlx5_ifc_arm_xrq_out_bits {
6960 u8 status[0x8];
6961 u8 reserved_at_8[0x18];
6962
6963 u8 syndrome[0x20];
6964
6965 u8 reserved_at_40[0x40];
6966};
6967
6968struct mlx5_ifc_arm_xrq_in_bits {
6969 u8 opcode[0x10];
6970 u8 reserved_at_10[0x10];
6971
6972 u8 reserved_at_20[0x10];
6973 u8 op_mod[0x10];
6974
6975 u8 reserved_at_40[0x8];
6976 u8 xrqn[0x18];
6977
6978 u8 reserved_at_60[0x10];
6979 u8 lwm[0x10];
6980};
6981
e281682b
SM		 6982struct mlx5_ifc_arm_xrc_srq_out_bits {
6983 u8 status[0x8];
b4ff3a36 6984 u8 reserved_at_8[0x18];
e281682b
SM		 6985
6986 u8 syndrome[0x20];
6987
b4ff3a36 6988 u8 reserved_at_40[0x40];
e281682b
SM		 6989};
6990
6991enum {
6992 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6993};
6994
6995struct mlx5_ifc_arm_xrc_srq_in_bits {
6996 u8 opcode[0x10];
b4ff3a36 6997 u8 reserved_at_10[0x10];
e281682b 6998
b4ff3a36 6999 u8 reserved_at_20[0x10];
e281682b
SM		 7000 u8 op_mod[0x10];
7001
b4ff3a36 7002 u8 reserved_at_40[0x8];
e281682b
SM		 7003 u8 xrc_srqn[0x18];
7004
b4ff3a36 7005 u8 reserved_at_60[0x10];
e281682b
SM		 7006 u8 lwm[0x10];
7007};
7008
7009struct mlx5_ifc_arm_rq_out_bits {
7010 u8 status[0x8];
b4ff3a36 7011 u8 reserved_at_8[0x18];
e281682b
SM		 7012
7013 u8 syndrome[0x20];
7014
b4ff3a36 7015 u8 reserved_at_40[0x40];
e281682b
SM		 7016};
7017
7018enum {
7486216b
SM		 7019 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7020 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7021};
7022
7023struct mlx5_ifc_arm_rq_in_bits {
7024 u8 opcode[0x10];
b4ff3a36 7025 u8 reserved_at_10[0x10];
e281682b 7026
b4ff3a36 7027 u8 reserved_at_20[0x10];
e281682b
SM		 7028 u8 op_mod[0x10];
7029
b4ff3a36 7030 u8 reserved_at_40[0x8];
e281682b
SM		 7031 u8 srq_number[0x18];
7032
b4ff3a36 7033 u8 reserved_at_60[0x10];
e281682b
SM		 7034 u8 lwm[0x10];
7035};
7036
7037struct mlx5_ifc_arm_dct_out_bits {
7038 u8 status[0x8];
b4ff3a36 7039 u8 reserved_at_8[0x18];
e281682b
SM		 7040
7041 u8 syndrome[0x20];
7042
b4ff3a36 7043 u8 reserved_at_40[0x40];
e281682b
SM		 7044};
7045
7046struct mlx5_ifc_arm_dct_in_bits {
7047 u8 opcode[0x10];
b4ff3a36 7048 u8 reserved_at_10[0x10];
e281682b 7049
b4ff3a36 7050 u8 reserved_at_20[0x10];
e281682b
SM		 7051 u8 op_mod[0x10];
7052
b4ff3a36 7053 u8 reserved_at_40[0x8];
e281682b
SM		 7054 u8 dct_number[0x18];
7055
b4ff3a36 7056 u8 reserved_at_60[0x20];
e281682b
SM		 7057};
7058
7059struct mlx5_ifc_alloc_xrcd_out_bits {
7060 u8 status[0x8];
b4ff3a36 7061 u8 reserved_at_8[0x18];
e281682b
SM		 7062
7063 u8 syndrome[0x20];
7064
b4ff3a36 7065 u8 reserved_at_40[0x8];
e281682b
SM		 7066 u8 xrcd[0x18];
7067
b4ff3a36 7068 u8 reserved_at_60[0x20];
e281682b
SM		 7069};
7070
7071struct mlx5_ifc_alloc_xrcd_in_bits {
7072 u8 opcode[0x10];
b4ff3a36 7073 u8 reserved_at_10[0x10];
e281682b 7074
b4ff3a36 7075 u8 reserved_at_20[0x10];
e281682b
SM		 7076 u8 op_mod[0x10];
7077
b4ff3a36 7078 u8 reserved_at_40[0x40];
e281682b
SM		 7079};
7080
7081struct mlx5_ifc_alloc_uar_out_bits {
7082 u8 status[0x8];
b4ff3a36 7083 u8 reserved_at_8[0x18];
e281682b
SM		 7084
7085 u8 syndrome[0x20];
7086
b4ff3a36 7087 u8 reserved_at_40[0x8];
e281682b
SM		 7088 u8 uar[0x18];
7089
b4ff3a36 7090 u8 reserved_at_60[0x20];
e281682b
SM		 7091};
7092
7093struct mlx5_ifc_alloc_uar_in_bits {
7094 u8 opcode[0x10];
b4ff3a36 7095 u8 reserved_at_10[0x10];
e281682b 7096
b4ff3a36 7097 u8 reserved_at_20[0x10];
e281682b
SM		 7098 u8 op_mod[0x10];
7099
b4ff3a36 7100 u8 reserved_at_40[0x40];
e281682b
SM		 7101};
7102
7103struct mlx5_ifc_alloc_transport_domain_out_bits {
7104 u8 status[0x8];
b4ff3a36 7105 u8 reserved_at_8[0x18];
e281682b
SM		 7106
7107 u8 syndrome[0x20];
7108
b4ff3a36 7109 u8 reserved_at_40[0x8];
e281682b
SM		 7110 u8 transport_domain[0x18];
7111
b4ff3a36 7112 u8 reserved_at_60[0x20];
e281682b
SM		 7113};
7114
7115struct mlx5_ifc_alloc_transport_domain_in_bits {
7116 u8 opcode[0x10];
b4ff3a36 7117 u8 reserved_at_10[0x10];
e281682b 7118
b4ff3a36 7119 u8 reserved_at_20[0x10];
e281682b
SM		 7120 u8 op_mod[0x10];
7121
b4ff3a36 7122 u8 reserved_at_40[0x40];
e281682b
SM		 7123};
7124
7125struct mlx5_ifc_alloc_q_counter_out_bits {
7126 u8 status[0x8];
b4ff3a36 7127 u8 reserved_at_8[0x18];
e281682b
SM		 7128
7129 u8 syndrome[0x20];
7130
b4ff3a36 7131 u8 reserved_at_40[0x18];
e281682b
SM		 7132 u8 counter_set_id[0x8];
7133
b4ff3a36 7134 u8 reserved_at_60[0x20];
e281682b
SM		 7135};
7136
7137struct mlx5_ifc_alloc_q_counter_in_bits {
7138 u8 opcode[0x10];
b4ff3a36 7139 u8 reserved_at_10[0x10];
e281682b 7140
b4ff3a36 7141 u8 reserved_at_20[0x10];
e281682b
SM		 7142 u8 op_mod[0x10];
7143
b4ff3a36 7144 u8 reserved_at_40[0x40];
e281682b
SM		 7145};
7146
7147struct mlx5_ifc_alloc_pd_out_bits {
7148 u8 status[0x8];
b4ff3a36 7149 u8 reserved_at_8[0x18];
e281682b
SM		 7150
7151 u8 syndrome[0x20];
7152
b4ff3a36 7153 u8 reserved_at_40[0x8];
e281682b
SM		 7154 u8 pd[0x18];
7155
b4ff3a36 7156 u8 reserved_at_60[0x20];
e281682b
SM		 7157};
7158
7159struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7160 u8 opcode[0x10];
7161 u8 reserved_at_10[0x10];
7162
7163 u8 reserved_at_20[0x10];
7164 u8 op_mod[0x10];
7165
7166 u8 reserved_at_40[0x40];
7167};
7168
7169struct mlx5_ifc_alloc_flow_counter_out_bits {
7170 u8 status[0x8];
7171 u8 reserved_at_8[0x18];
7172
7173 u8 syndrome[0x20];
7174
7175 u8 reserved_at_40[0x10];
7176 u8 flow_counter_id[0x10];
7177
7178 u8 reserved_at_60[0x20];
7179};
7180
7181struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7182 u8 opcode[0x10];
b4ff3a36 7183 u8 reserved_at_10[0x10];
e281682b 7184
b4ff3a36 7185 u8 reserved_at_20[0x10];
e281682b
SM		 7186 u8 op_mod[0x10];
7187
b4ff3a36 7188 u8 reserved_at_40[0x40];
e281682b
SM		 7189};
7190
7191struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7192 u8 status[0x8];
b4ff3a36 7193 u8 reserved_at_8[0x18];
e281682b
SM		 7194
7195 u8 syndrome[0x20];
7196
b4ff3a36 7197 u8 reserved_at_40[0x40];
e281682b
SM		 7198};
7199
7200struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7201 u8 opcode[0x10];
b4ff3a36 7202 u8 reserved_at_10[0x10];
e281682b 7203
b4ff3a36 7204 u8 reserved_at_20[0x10];
e281682b
SM		 7205 u8 op_mod[0x10];
7206
b4ff3a36 7207 u8 reserved_at_40[0x20];
e281682b 7208
b4ff3a36 7209 u8 reserved_at_60[0x10];
e281682b
SM		 7210 u8 vxlan_udp_port[0x10];
7211};
7212
7486216b
SM		 7213struct mlx5_ifc_set_rate_limit_out_bits {
7214 u8 status[0x8];
7215 u8 reserved_at_8[0x18];
7216
7217 u8 syndrome[0x20];
7218
7219 u8 reserved_at_40[0x40];
7220};
7221
7222struct mlx5_ifc_set_rate_limit_in_bits {
7223 u8 opcode[0x10];
7224 u8 reserved_at_10[0x10];
7225
7226 u8 reserved_at_20[0x10];
7227 u8 op_mod[0x10];
7228
7229 u8 reserved_at_40[0x10];
7230 u8 rate_limit_index[0x10];
7231
7232 u8 reserved_at_60[0x20];
7233
7234 u8 rate_limit[0x20];
7235};
7236
e281682b
SM		 7237struct mlx5_ifc_access_register_out_bits {
7238 u8 status[0x8];
b4ff3a36 7239 u8 reserved_at_8[0x18];
e281682b
SM		 7240
7241 u8 syndrome[0x20];
7242
b4ff3a36 7243 u8 reserved_at_40[0x40];
e281682b
SM		 7244
7245 u8 register_data[0][0x20];
7246};
7247
7248enum {
7249 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7250 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7251};
7252
7253struct mlx5_ifc_access_register_in_bits {
7254 u8 opcode[0x10];
b4ff3a36 7255 u8 reserved_at_10[0x10];
e281682b 7256
b4ff3a36 7257 u8 reserved_at_20[0x10];
e281682b
SM		 7258 u8 op_mod[0x10];
7259
b4ff3a36 7260 u8 reserved_at_40[0x10];
e281682b
SM		 7261 u8 register_id[0x10];
7262
7263 u8 argument[0x20];
7264
7265 u8 register_data[0][0x20];
7266};
7267
7268struct mlx5_ifc_sltp_reg_bits {
7269 u8 status[0x4];
7270 u8 version[0x4];
7271 u8 local_port[0x8];
7272 u8 pnat[0x2];
b4ff3a36 7273 u8 reserved_at_12[0x2];
e281682b 7274 u8 lane[0x4];
b4ff3a36 7275 u8 reserved_at_18[0x8];
e281682b 7276
b4ff3a36 7277 u8 reserved_at_20[0x20];
e281682b 7278
b4ff3a36 7279 u8 reserved_at_40[0x7];
e281682b
SM		 7280 u8 polarity[0x1];
7281 u8 ob_tap0[0x8];
7282 u8 ob_tap1[0x8];
7283 u8 ob_tap2[0x8];
7284
b4ff3a36 7285 u8 reserved_at_60[0xc];
e281682b
SM		 7286 u8 ob_preemp_mode[0x4];
7287 u8 ob_reg[0x8];
7288 u8 ob_bias[0x8];
7289
b4ff3a36 7290 u8 reserved_at_80[0x20];
e281682b
SM		 7291};
7292
7293struct mlx5_ifc_slrg_reg_bits {
7294 u8 status[0x4];
7295 u8 version[0x4];
7296 u8 local_port[0x8];
7297 u8 pnat[0x2];
b4ff3a36 7298 u8 reserved_at_12[0x2];
e281682b 7299 u8 lane[0x4];
b4ff3a36 7300 u8 reserved_at_18[0x8];
e281682b
SM		 7301
7302 u8 time_to_link_up[0x10];
b4ff3a36 7303 u8 reserved_at_30[0xc];
e281682b
SM		 7304 u8 grade_lane_speed[0x4];
7305
7306 u8 grade_version[0x8];
7307 u8 grade[0x18];
7308
b4ff3a36 7309 u8 reserved_at_60[0x4];
e281682b
SM		 7310 u8 height_grade_type[0x4];
7311 u8 height_grade[0x18];
7312
7313 u8 height_dz[0x10];
7314 u8 height_dv[0x10];
7315
b4ff3a36 7316 u8 reserved_at_a0[0x10];
e281682b
SM		 7317 u8 height_sigma[0x10];
7318
b4ff3a36 7319 u8 reserved_at_c0[0x20];
e281682b 7320
b4ff3a36 7321 u8 reserved_at_e0[0x4];
e281682b
SM		 7322 u8 phase_grade_type[0x4];
7323 u8 phase_grade[0x18];
7324
b4ff3a36 7325 u8 reserved_at_100[0x8];
e281682b 7326 u8 phase_eo_pos[0x8];
b4ff3a36 7327 u8 reserved_at_110[0x8];
e281682b
SM		 7328 u8 phase_eo_neg[0x8];
7329
7330 u8 ffe_set_tested[0x10];
7331 u8 test_errors_per_lane[0x10];
7332};
7333
7334struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7335 u8 reserved_at_0[0x8];
e281682b 7336 u8 local_port[0x8];
b4ff3a36 7337 u8 reserved_at_10[0x10];
e281682b 7338
b4ff3a36 7339 u8 reserved_at_20[0x1c];
e281682b
SM		 7340 u8 vl_hw_cap[0x4];
7341
b4ff3a36 7342 u8 reserved_at_40[0x1c];
e281682b
SM		 7343 u8 vl_admin[0x4];
7344
b4ff3a36 7345 u8 reserved_at_60[0x1c];
e281682b
SM		 7346 u8 vl_operational[0x4];
7347};
7348
7349struct mlx5_ifc_pude_reg_bits {
7350 u8 swid[0x8];
7351 u8 local_port[0x8];
b4ff3a36 7352 u8 reserved_at_10[0x4];
e281682b 7353 u8 admin_status[0x4];
b4ff3a36 7354 u8 reserved_at_18[0x4];
e281682b
SM		 7355 u8 oper_status[0x4];
7356
b4ff3a36 7357 u8 reserved_at_20[0x60];
e281682b
SM		 7358};
7359
7360struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7361 u8 reserved_at_0[0x1];
7486216b 7362 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7363 u8 an_disable_cap[0x1];
7364 u8 reserved_at_3[0x5];
e281682b 7365 u8 local_port[0x8];
b4ff3a36 7366 u8 reserved_at_10[0xd];
e281682b
SM		 7367 u8 proto_mask[0x3];
7368
7486216b
SM		 7369 u8 an_status[0x4];
7370 u8 reserved_at_24[0x3c];
e281682b
SM		 7371
7372 u8 eth_proto_capability[0x20];
7373
7374 u8 ib_link_width_capability[0x10];
7375 u8 ib_proto_capability[0x10];
7376
b4ff3a36 7377 u8 reserved_at_a0[0x20];
e281682b
SM		 7378
7379 u8 eth_proto_admin[0x20];
7380
7381 u8 ib_link_width_admin[0x10];
7382 u8 ib_proto_admin[0x10];
7383
b4ff3a36 7384 u8 reserved_at_100[0x20];
e281682b
SM		 7385
7386 u8 eth_proto_oper[0x20];
7387
7388 u8 ib_link_width_oper[0x10];
7389 u8 ib_proto_oper[0x10];
7390
5b4793f8
EBE		 7391 u8 reserved_at_160[0x1c];
7392 u8 connector_type[0x4];
e281682b
SM		 7393
7394 u8 eth_proto_lp_advertise[0x20];
7395
b4ff3a36 7396 u8 reserved_at_1a0[0x60];
e281682b
SM		 7397};
7398
7d5e1423
SM		 7399struct mlx5_ifc_mlcr_reg_bits {
7400 u8 reserved_at_0[0x8];
7401 u8 local_port[0x8];
7402 u8 reserved_at_10[0x20];
7403
7404 u8 beacon_duration[0x10];
7405 u8 reserved_at_40[0x10];
7406
7407 u8 beacon_remain[0x10];
7408};
7409
e281682b 7410struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7411 u8 reserved_at_0[0x20];
e281682b
SM		 7412
7413 u8 algorithm_options[0x10];
b4ff3a36 7414 u8 reserved_at_30[0x4];
e281682b
SM		 7415 u8 repetitions_mode[0x4];
7416 u8 num_of_repetitions[0x8];
7417
7418 u8 grade_version[0x8];
7419 u8 height_grade_type[0x4];
7420 u8 phase_grade_type[0x4];
7421 u8 height_grade_weight[0x8];
7422 u8 phase_grade_weight[0x8];
7423
7424 u8 gisim_measure_bits[0x10];
7425 u8 adaptive_tap_measure_bits[0x10];
7426
7427 u8 ber_bath_high_error_threshold[0x10];
7428 u8 ber_bath_mid_error_threshold[0x10];
7429
7430 u8 ber_bath_low_error_threshold[0x10];
7431 u8 one_ratio_high_threshold[0x10];
7432
7433 u8 one_ratio_high_mid_threshold[0x10];
7434 u8 one_ratio_low_mid_threshold[0x10];
7435
7436 u8 one_ratio_low_threshold[0x10];
7437 u8 ndeo_error_threshold[0x10];
7438
7439 u8 mixer_offset_step_size[0x10];
b4ff3a36 7440 u8 reserved_at_110[0x8];
e281682b
SM		 7441 u8 mix90_phase_for_voltage_bath[0x8];
7442
7443 u8 mixer_offset_start[0x10];
7444 u8 mixer_offset_end[0x10];
7445
b4ff3a36 7446 u8 reserved_at_140[0x15];
e281682b
SM		 7447 u8 ber_test_time[0xb];
7448};
7449
7450struct mlx5_ifc_pspa_reg_bits {
7451 u8 swid[0x8];
7452 u8 local_port[0x8];
7453 u8 sub_port[0x8];
b4ff3a36 7454 u8 reserved_at_18[0x8];
e281682b 7455
b4ff3a36 7456 u8 reserved_at_20[0x20];
e281682b
SM		 7457};
7458
7459struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7460 u8 reserved_at_0[0x8];
e281682b 7461 u8 local_port[0x8];
b4ff3a36 7462 u8 reserved_at_10[0x5];
e281682b 7463 u8 prio[0x3];
b4ff3a36 7464 u8 reserved_at_18[0x6];
e281682b
SM		 7465 u8 mode[0x2];
7466
b4ff3a36 7467 u8 reserved_at_20[0x20];
e281682b 7468
b4ff3a36 7469 u8 reserved_at_40[0x10];
e281682b
SM		 7470 u8 min_threshold[0x10];
7471
b4ff3a36 7472 u8 reserved_at_60[0x10];
e281682b
SM		 7473 u8 max_threshold[0x10];
7474
b4ff3a36 7475 u8 reserved_at_80[0x10];
e281682b
SM		 7476 u8 mark_probability_denominator[0x10];
7477
b4ff3a36 7478 u8 reserved_at_a0[0x60];
e281682b
SM		 7479};
7480
7481struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7482 u8 reserved_at_0[0x8];
e281682b 7483 u8 local_port[0x8];
b4ff3a36 7484 u8 reserved_at_10[0x10];
e281682b 7485
b4ff3a36 7486 u8 reserved_at_20[0x60];
e281682b 7487
b4ff3a36 7488 u8 reserved_at_80[0x1c];
e281682b
SM		 7489 u8 wrps_admin[0x4];
7490
b4ff3a36 7491 u8 reserved_at_a0[0x1c];
e281682b
SM		 7492 u8 wrps_status[0x4];
7493
b4ff3a36 7494 u8 reserved_at_c0[0x8];
e281682b 7495 u8 up_threshold[0x8];
b4ff3a36 7496 u8 reserved_at_d0[0x8];
e281682b
SM		 7497 u8 down_threshold[0x8];
7498
b4ff3a36 7499 u8 reserved_at_e0[0x20];
e281682b 7500
b4ff3a36 7501 u8 reserved_at_100[0x1c];
e281682b
SM		 7502 u8 srps_admin[0x4];
7503
b4ff3a36 7504 u8 reserved_at_120[0x1c];
e281682b
SM		 7505 u8 srps_status[0x4];
7506
b4ff3a36 7507 u8 reserved_at_140[0x40];
e281682b
SM		 7508};
7509
7510struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7511 u8 reserved_at_0[0x8];
e281682b 7512 u8 local_port[0x8];
b4ff3a36 7513 u8 reserved_at_10[0x10];
e281682b 7514
b4ff3a36 7515 u8 reserved_at_20[0x8];
e281682b 7516 u8 lb_cap[0x8];
b4ff3a36 7517 u8 reserved_at_30[0x8];
e281682b
SM		 7518 u8 lb_en[0x8];
7519};
7520
7521struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7522 u8 reserved_at_0[0x8];
e281682b 7523 u8 local_port[0x8];
b4ff3a36 7524 u8 reserved_at_10[0x10];
e281682b 7525
b4ff3a36 7526 u8 reserved_at_20[0x20];
e281682b
SM		 7527
7528 u8 port_profile_mode[0x8];
7529 u8 static_port_profile[0x8];
7530 u8 active_port_profile[0x8];
b4ff3a36 7531 u8 reserved_at_58[0x8];
e281682b
SM		 7532
7533 u8 retransmission_active[0x8];
7534 u8 fec_mode_active[0x18];
7535
b4ff3a36 7536 u8 reserved_at_80[0x20];
e281682b
SM		 7537};
7538
7539struct mlx5_ifc_ppcnt_reg_bits {
7540 u8 swid[0x8];
7541 u8 local_port[0x8];
7542 u8 pnat[0x2];
b4ff3a36 7543 u8 reserved_at_12[0x8];
e281682b
SM		 7544 u8 grp[0x6];
7545
7546 u8 clr[0x1];
b4ff3a36 7547 u8 reserved_at_21[0x1c];
e281682b
SM		 7548 u8 prio_tc[0x3];
7549
7550 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7551};
7552
8ed1a630
GP		 7553struct mlx5_ifc_mpcnt_reg_bits {
7554 u8 reserved_at_0[0x8];
7555 u8 pcie_index[0x8];
7556 u8 reserved_at_10[0xa];
7557 u8 grp[0x6];
7558
7559 u8 clr[0x1];
7560 u8 reserved_at_21[0x1f];
7561
7562 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7563};
7564
e281682b 7565struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7566 u8 reserved_at_0[0x3];
e281682b 7567 u8 single_mac[0x1];
b4ff3a36 7568 u8 reserved_at_4[0x4];
e281682b
SM		 7569 u8 local_port[0x8];
7570 u8 mac_47_32[0x10];
7571
7572 u8 mac_31_0[0x20];
7573
b4ff3a36 7574 u8 reserved_at_40[0x40];
e281682b
SM		 7575};
7576
7577struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7578 u8 reserved_at_0[0x8];
e281682b 7579 u8 local_port[0x8];
b4ff3a36 7580 u8 reserved_at_10[0x10];
e281682b
SM		 7581
7582 u8 max_mtu[0x10];
b4ff3a36 7583 u8 reserved_at_30[0x10];
e281682b
SM		 7584
7585 u8 admin_mtu[0x10];
b4ff3a36 7586 u8 reserved_at_50[0x10];
e281682b
SM		 7587
7588 u8 oper_mtu[0x10];
b4ff3a36 7589 u8 reserved_at_70[0x10];
e281682b
SM		 7590};
7591
7592struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7593 u8 reserved_at_0[0x8];
e281682b 7594 u8 module[0x8];
b4ff3a36 7595 u8 reserved_at_10[0x10];
e281682b 7596
b4ff3a36 7597 u8 reserved_at_20[0x18];
e281682b
SM		 7598 u8 attenuation_5g[0x8];
7599
b4ff3a36 7600 u8 reserved_at_40[0x18];
e281682b
SM		 7601 u8 attenuation_7g[0x8];
7602
b4ff3a36 7603 u8 reserved_at_60[0x18];
e281682b
SM		 7604 u8 attenuation_12g[0x8];
7605};
7606
7607struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7608 u8 reserved_at_0[0x8];
e281682b 7609 u8 module[0x8];
b4ff3a36 7610 u8 reserved_at_10[0xc];
e281682b
SM		 7611 u8 module_status[0x4];
7612
b4ff3a36 7613 u8 reserved_at_20[0x60];
e281682b
SM		 7614};
7615
7616struct mlx5_ifc_pmpc_reg_bits {
7617 u8 module_state_updated[32][0x8];
7618};
7619
7620struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7621 u8 reserved_at_0[0x4];
e281682b
SM		 7622 u8 mlpn_status[0x4];
7623 u8 local_port[0x8];
b4ff3a36 7624 u8 reserved_at_10[0x10];
e281682b
SM		 7625
7626 u8 e[0x1];
b4ff3a36 7627 u8 reserved_at_21[0x1f];
e281682b
SM		 7628};
7629
7630struct mlx5_ifc_pmlp_reg_bits {
7631 u8 rxtx[0x1];
b4ff3a36 7632 u8 reserved_at_1[0x7];
e281682b 7633 u8 local_port[0x8];
b4ff3a36 7634 u8 reserved_at_10[0x8];
e281682b
SM		 7635 u8 width[0x8];
7636
7637 u8 lane0_module_mapping[0x20];
7638
7639 u8 lane1_module_mapping[0x20];
7640
7641 u8 lane2_module_mapping[0x20];
7642
7643 u8 lane3_module_mapping[0x20];
7644
b4ff3a36 7645 u8 reserved_at_a0[0x160];
e281682b
SM		 7646};
7647
7648struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7649 u8 reserved_at_0[0x8];
e281682b 7650 u8 module[0x8];
b4ff3a36 7651 u8 reserved_at_10[0x4];
e281682b 7652 u8 admin_status[0x4];
b4ff3a36 7653 u8 reserved_at_18[0x4];
e281682b
SM		 7654 u8 oper_status[0x4];
7655
7656 u8 ase[0x1];
7657 u8 ee[0x1];
b4ff3a36 7658 u8 reserved_at_22[0x1c];
e281682b
SM		 7659 u8 e[0x2];
7660
b4ff3a36 7661 u8 reserved_at_40[0x40];
e281682b
SM		 7662};
7663
7664struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7665 u8 reserved_at_0[0x4];
e281682b 7666 u8 profile_id[0xc];
b4ff3a36 7667 u8 reserved_at_10[0x4];
e281682b 7668 u8 proto_mask[0x4];
b4ff3a36 7669 u8 reserved_at_18[0x8];
e281682b 7670
b4ff3a36 7671 u8 reserved_at_20[0x10];
e281682b
SM		 7672 u8 lane_speed[0x10];
7673
b4ff3a36 7674 u8 reserved_at_40[0x17];
e281682b
SM		 7675 u8 lpbf[0x1];
7676 u8 fec_mode_policy[0x8];
7677
7678 u8 retransmission_capability[0x8];
7679 u8 fec_mode_capability[0x18];
7680
7681 u8 retransmission_support_admin[0x8];
7682 u8 fec_mode_support_admin[0x18];
7683
7684 u8 retransmission_request_admin[0x8];
7685 u8 fec_mode_request_admin[0x18];
7686
b4ff3a36 7687 u8 reserved_at_c0[0x80];
e281682b
SM		 7688};
7689
7690struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7691 u8 reserved_at_0[0x8];
e281682b 7692 u8 local_port[0x8];
b4ff3a36 7693 u8 reserved_at_10[0x8];
e281682b
SM		 7694 u8 ib_port[0x8];
7695
b4ff3a36 7696 u8 reserved_at_20[0x60];
e281682b
SM		 7697};
7698
7699struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7700 u8 reserved_at_0[0x8];
e281682b 7701 u8 local_port[0x8];
b4ff3a36 7702 u8 reserved_at_10[0xd];
e281682b
SM		 7703 u8 lbf_mode[0x3];
7704
b4ff3a36 7705 u8 reserved_at_20[0x20];
e281682b
SM		 7706};
7707
7708struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7709 u8 reserved_at_0[0x8];
e281682b 7710 u8 local_port[0x8];
b4ff3a36 7711 u8 reserved_at_10[0x10];
e281682b
SM		 7712
7713 u8 dic[0x1];
b4ff3a36 7714 u8 reserved_at_21[0x19];
e281682b 7715 u8 ipg[0x4];
b4ff3a36 7716 u8 reserved_at_3e[0x2];
e281682b
SM		 7717};
7718
7719struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7720 u8 reserved_at_0[0x8];
e281682b 7721 u8 local_port[0x8];
b4ff3a36 7722 u8 reserved_at_10[0x10];
e281682b 7723
b4ff3a36 7724 u8 reserved_at_20[0xe0];
e281682b
SM		 7725
7726 u8 port_filter[8][0x20];
7727
7728 u8 port_filter_update_en[8][0x20];
7729};
7730
7731struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7732 u8 reserved_at_0[0x8];
e281682b 7733 u8 local_port[0x8];
b4ff3a36 7734 u8 reserved_at_10[0x10];
e281682b
SM		 7735
7736 u8 ppan[0x4];
b4ff3a36 7737 u8 reserved_at_24[0x4];
e281682b 7738 u8 prio_mask_tx[0x8];
b4ff3a36 7739 u8 reserved_at_30[0x8];
e281682b
SM		 7740 u8 prio_mask_rx[0x8];
7741
7742 u8 pptx[0x1];
7743 u8 aptx[0x1];
b4ff3a36 7744 u8 reserved_at_42[0x6];
e281682b 7745 u8 pfctx[0x8];
b4ff3a36 7746 u8 reserved_at_50[0x10];
e281682b
SM		 7747
7748 u8 pprx[0x1];
7749 u8 aprx[0x1];
b4ff3a36 7750 u8 reserved_at_62[0x6];
e281682b 7751 u8 pfcrx[0x8];
b4ff3a36 7752 u8 reserved_at_70[0x10];
e281682b 7753
b4ff3a36 7754 u8 reserved_at_80[0x80];
e281682b
SM		 7755};
7756
7757struct mlx5_ifc_pelc_reg_bits {
7758 u8 op[0x4];
b4ff3a36 7759 u8 reserved_at_4[0x4];
e281682b 7760 u8 local_port[0x8];
b4ff3a36 7761 u8 reserved_at_10[0x10];
e281682b
SM		 7762
7763 u8 op_admin[0x8];
7764 u8 op_capability[0x8];
7765 u8 op_request[0x8];
7766 u8 op_active[0x8];
7767
7768 u8 admin[0x40];
7769
7770 u8 capability[0x40];
7771
7772 u8 request[0x40];
7773
7774 u8 active[0x40];
7775
b4ff3a36 7776 u8 reserved_at_140[0x80];
e281682b
SM		 7777};
7778
7779struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7780 u8 reserved_at_0[0x8];
e281682b 7781 u8 local_port[0x8];
b4ff3a36 7782 u8 reserved_at_10[0x10];
e281682b 7783
b4ff3a36 7784 u8 reserved_at_20[0xc];
e281682b 7785 u8 error_count[0x4];
b4ff3a36 7786 u8 reserved_at_30[0x10];
e281682b 7787
b4ff3a36 7788 u8 reserved_at_40[0xc];
e281682b 7789 u8 lane[0x4];
b4ff3a36 7790 u8 reserved_at_50[0x8];
e281682b
SM		 7791 u8 error_type[0x8];
7792};
7793
cfdcbcea 7794struct mlx5_ifc_pcam_enhanced_features_bits {
5b4793f8 7795 u8 reserved_at_0[0x7c];
cfdcbcea 7796
5b4793f8
EBE		 7797 u8 ptys_connector_type[0x1];
7798 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 7799 u8 ppcnt_discard_group[0x1];
7800 u8 ppcnt_statistical_group[0x1];
7801};
7802
7803struct mlx5_ifc_pcam_reg_bits {
7804 u8 reserved_at_0[0x8];
7805 u8 feature_group[0x8];
7806 u8 reserved_at_10[0x8];
7807 u8 access_reg_group[0x8];
7808
7809 u8 reserved_at_20[0x20];
7810
7811 union {
7812 u8 reserved_at_0[0x80];
7813 } port_access_reg_cap_mask;
7814
7815 u8 reserved_at_c0[0x80];
7816
7817 union {
7818 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7819 u8 reserved_at_0[0x80];
7820 } feature_cap_mask;
7821
7822 u8 reserved_at_1c0[0xc0];
7823};
7824
7825struct mlx5_ifc_mcam_enhanced_features_bits {
7826 u8 reserved_at_0[0x7f];
7827
7828 u8 pcie_performance_group[0x1];
7829};
7830
0ab87743
OG		 7831struct mlx5_ifc_mcam_access_reg_bits {
7832 u8 reserved_at_0[0x1c];
7833 u8 mcda[0x1];
7834 u8 mcc[0x1];
7835 u8 mcqi[0x1];
7836 u8 reserved_at_1f[0x1];
7837
7838 u8 regs_95_to_64[0x20];
7839 u8 regs_63_to_32[0x20];
7840 u8 regs_31_to_0[0x20];
7841};
7842
cfdcbcea
GP		 7843struct mlx5_ifc_mcam_reg_bits {
7844 u8 reserved_at_0[0x8];
7845 u8 feature_group[0x8];
7846 u8 reserved_at_10[0x8];
7847 u8 access_reg_group[0x8];
7848
7849 u8 reserved_at_20[0x20];
7850
7851 union {
0ab87743 7852 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 7853 u8 reserved_at_0[0x80];
7854 } mng_access_reg_cap_mask;
7855
7856 u8 reserved_at_c0[0x80];
7857
7858 union {
7859 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7860 u8 reserved_at_0[0x80];
7861 } mng_feature_cap_mask;
7862
7863 u8 reserved_at_1c0[0x80];
7864};
7865
e281682b 7866struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7867 u8 reserved_at_0[0x8];
e281682b 7868 u8 local_port[0x8];
b4ff3a36 7869 u8 reserved_at_10[0x10];
e281682b
SM		 7870
7871 u8 port_capability_mask[4][0x20];
7872};
7873
7874struct mlx5_ifc_paos_reg_bits {
7875 u8 swid[0x8];
7876 u8 local_port[0x8];
b4ff3a36 7877 u8 reserved_at_10[0x4];
e281682b 7878 u8 admin_status[0x4];
b4ff3a36 7879 u8 reserved_at_18[0x4];
e281682b
SM		 7880 u8 oper_status[0x4];
7881
7882 u8 ase[0x1];
7883 u8 ee[0x1];
b4ff3a36 7884 u8 reserved_at_22[0x1c];
e281682b
SM		 7885 u8 e[0x2];
7886
b4ff3a36 7887 u8 reserved_at_40[0x40];
e281682b
SM		 7888};
7889
7890struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7891 u8 reserved_at_0[0x8];
e281682b 7892 u8 opamp_group[0x8];
b4ff3a36 7893 u8 reserved_at_10[0xc];
e281682b
SM		 7894 u8 opamp_group_type[0x4];
7895
7896 u8 start_index[0x10];
b4ff3a36 7897 u8 reserved_at_30[0x4];
e281682b
SM		 7898 u8 num_of_indices[0xc];
7899
7900 u8 index_data[18][0x10];
7901};
7902
7d5e1423
SM		 7903struct mlx5_ifc_pcmr_reg_bits {
7904 u8 reserved_at_0[0x8];
7905 u8 local_port[0x8];
7906 u8 reserved_at_10[0x2e];
7907 u8 fcs_cap[0x1];
7908 u8 reserved_at_3f[0x1f];
7909 u8 fcs_chk[0x1];
7910 u8 reserved_at_5f[0x1];
7911};
7912
e281682b 7913struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7914 u8 reserved_at_0[0x6];
e281682b 7915 u8 rx_lane[0x2];
b4ff3a36 7916 u8 reserved_at_8[0x6];
e281682b 7917 u8 tx_lane[0x2];
b4ff3a36 7918 u8 reserved_at_10[0x8];
e281682b
SM		 7919 u8 module[0x8];
7920};
7921
7922struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7923 u8 reserved_at_0[0x6];
e281682b
SM		 7924 u8 lossy[0x1];
7925 u8 epsb[0x1];
b4ff3a36 7926 u8 reserved_at_8[0xc];
e281682b
SM		 7927 u8 size[0xc];
7928
7929 u8 xoff_threshold[0x10];
7930 u8 xon_threshold[0x10];
7931};
7932
7933struct mlx5_ifc_set_node_in_bits {
7934 u8 node_description[64][0x8];
7935};
7936
7937struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7938 u8 reserved_at_0[0x18];
e281682b
SM		 7939 u8 power_settings_level[0x8];
7940
b4ff3a36 7941 u8 reserved_at_20[0x60];
e281682b
SM		 7942};
7943
7944struct mlx5_ifc_register_host_endianness_bits {
7945 u8 he[0x1];
b4ff3a36 7946 u8 reserved_at_1[0x1f];
e281682b 7947
b4ff3a36 7948 u8 reserved_at_20[0x60];
e281682b
SM		 7949};
7950
7951struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7952 u8 reserved_at_0[0x20];
e281682b
SM		 7953
7954 u8 mkey[0x20];
7955
7956 u8 addressh_63_32[0x20];
7957
7958 u8 addressl_31_0[0x20];
7959};
7960
7961struct mlx5_ifc_ud_adrs_vector_bits {
7962 u8 dc_key[0x40];
7963
7964 u8 ext[0x1];
b4ff3a36 7965 u8 reserved_at_41[0x7];
e281682b
SM		 7966 u8 destination_qp_dct[0x18];
7967
7968 u8 static_rate[0x4];
7969 u8 sl_eth_prio[0x4];
7970 u8 fl[0x1];
7971 u8 mlid[0x7];
7972 u8 rlid_udp_sport[0x10];
7973
b4ff3a36 7974 u8 reserved_at_80[0x20];
e281682b
SM		 7975
7976 u8 rmac_47_16[0x20];
7977
7978 u8 rmac_15_0[0x10];
7979 u8 tclass[0x8];
7980 u8 hop_limit[0x8];
7981
b4ff3a36 7982 u8 reserved_at_e0[0x1];
e281682b 7983 u8 grh[0x1];
b4ff3a36 7984 u8 reserved_at_e2[0x2];
e281682b
SM		 7985 u8 src_addr_index[0x8];
7986 u8 flow_label[0x14];
7987
7988 u8 rgid_rip[16][0x8];
7989};
7990
7991struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7992 u8 reserved_at_0[0x10];
e281682b
SM		 7993 u8 function_id[0x10];
7994
7995 u8 num_pages[0x20];
7996
b4ff3a36 7997 u8 reserved_at_40[0xa0];
e281682b
SM		 7998};
7999
8000struct mlx5_ifc_eqe_bits {
b4ff3a36 8001 u8 reserved_at_0[0x8];
e281682b 8002 u8 event_type[0x8];
b4ff3a36 8003 u8 reserved_at_10[0x8];
e281682b
SM		 8004 u8 event_sub_type[0x8];
8005
b4ff3a36 8006 u8 reserved_at_20[0xe0];
e281682b
SM		 8007
8008 union mlx5_ifc_event_auto_bits event_data;
8009
b4ff3a36 8010 u8 reserved_at_1e0[0x10];
e281682b 8011 u8 signature[0x8];
b4ff3a36 8012 u8 reserved_at_1f8[0x7];
e281682b
SM		 8013 u8 owner[0x1];
8014};
8015
8016enum {
8017 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8018};
8019
8020struct mlx5_ifc_cmd_queue_entry_bits {
8021 u8 type[0x8];
b4ff3a36 8022 u8 reserved_at_8[0x18];
e281682b
SM		 8023
8024 u8 input_length[0x20];
8025
8026 u8 input_mailbox_pointer_63_32[0x20];
8027
8028 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8029 u8 reserved_at_77[0x9];
e281682b
SM		 8030
8031 u8 command_input_inline_data[16][0x8];
8032
8033 u8 command_output_inline_data[16][0x8];
8034
8035 u8 output_mailbox_pointer_63_32[0x20];
8036
8037 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8038 u8 reserved_at_1b7[0x9];
e281682b
SM		 8039
8040 u8 output_length[0x20];
8041
8042 u8 token[0x8];
8043 u8 signature[0x8];
b4ff3a36 8044 u8 reserved_at_1f0[0x8];
e281682b
SM		 8045 u8 status[0x7];
8046 u8 ownership[0x1];
8047};
8048
8049struct mlx5_ifc_cmd_out_bits {
8050 u8 status[0x8];
b4ff3a36 8051 u8 reserved_at_8[0x18];
e281682b
SM		 8052
8053 u8 syndrome[0x20];
8054
8055 u8 command_output[0x20];
8056};
8057
8058struct mlx5_ifc_cmd_in_bits {
8059 u8 opcode[0x10];
b4ff3a36 8060 u8 reserved_at_10[0x10];
e281682b 8061
b4ff3a36 8062 u8 reserved_at_20[0x10];
e281682b
SM		 8063 u8 op_mod[0x10];
8064
8065 u8 command[0][0x20];
8066};
8067
8068struct mlx5_ifc_cmd_if_box_bits {
8069 u8 mailbox_data[512][0x8];
8070
b4ff3a36 8071 u8 reserved_at_1000[0x180];
e281682b
SM		 8072
8073 u8 next_pointer_63_32[0x20];
8074
8075 u8 next_pointer_31_10[0x16];
b4ff3a36 8076 u8 reserved_at_11b6[0xa];
e281682b
SM		 8077
8078 u8 block_number[0x20];
8079
b4ff3a36 8080 u8 reserved_at_11e0[0x8];
e281682b
SM		 8081 u8 token[0x8];
8082 u8 ctrl_signature[0x8];
8083 u8 signature[0x8];
8084};
8085
8086struct mlx5_ifc_mtt_bits {
8087 u8 ptag_63_32[0x20];
8088
8089 u8 ptag_31_8[0x18];
b4ff3a36 8090 u8 reserved_at_38[0x6];
e281682b
SM		 8091 u8 wr_en[0x1];
8092 u8 rd_en[0x1];
8093};
8094
928cfe87
TT		 8095struct mlx5_ifc_query_wol_rol_out_bits {
8096 u8 status[0x8];
8097 u8 reserved_at_8[0x18];
8098
8099 u8 syndrome[0x20];
8100
8101 u8 reserved_at_40[0x10];
8102 u8 rol_mode[0x8];
8103 u8 wol_mode[0x8];
8104
8105 u8 reserved_at_60[0x20];
8106};
8107
8108struct mlx5_ifc_query_wol_rol_in_bits {
8109 u8 opcode[0x10];
8110 u8 reserved_at_10[0x10];
8111
8112 u8 reserved_at_20[0x10];
8113 u8 op_mod[0x10];
8114
8115 u8 reserved_at_40[0x40];
8116};
8117
8118struct mlx5_ifc_set_wol_rol_out_bits {
8119 u8 status[0x8];
8120 u8 reserved_at_8[0x18];
8121
8122 u8 syndrome[0x20];
8123
8124 u8 reserved_at_40[0x40];
8125};
8126
8127struct mlx5_ifc_set_wol_rol_in_bits {
8128 u8 opcode[0x10];
8129 u8 reserved_at_10[0x10];
8130
8131 u8 reserved_at_20[0x10];
8132 u8 op_mod[0x10];
8133
8134 u8 rol_mode_valid[0x1];
8135 u8 wol_mode_valid[0x1];
8136 u8 reserved_at_42[0xe];
8137 u8 rol_mode[0x8];
8138 u8 wol_mode[0x8];
8139
8140 u8 reserved_at_60[0x20];
8141};
8142
e281682b
SM		 8143enum {
8144 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8145 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8146 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8147};
8148
8149enum {
8150 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8151 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8152 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8153};
8154
8155enum {
8156 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8157 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8158 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8159 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8160 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8161 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8162 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8163 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8164 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8165 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8166 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8167};
8168
8169struct mlx5_ifc_initial_seg_bits {
8170 u8 fw_rev_minor[0x10];
8171 u8 fw_rev_major[0x10];
8172
8173 u8 cmd_interface_rev[0x10];
8174 u8 fw_rev_subminor[0x10];
8175
b4ff3a36 8176 u8 reserved_at_40[0x40];
e281682b
SM		 8177
8178 u8 cmdq_phy_addr_63_32[0x20];
8179
8180 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8181 u8 reserved_at_b4[0x2];
e281682b
SM		 8182 u8 nic_interface[0x2];
8183 u8 log_cmdq_size[0x4];
8184 u8 log_cmdq_stride[0x4];
8185
8186 u8 command_doorbell_vector[0x20];
8187
b4ff3a36 8188 u8 reserved_at_e0[0xf00];
e281682b
SM		 8189
8190 u8 initializing[0x1];
b4ff3a36 8191 u8 reserved_at_fe1[0x4];
e281682b 8192 u8 nic_interface_supported[0x3];
b4ff3a36 8193 u8 reserved_at_fe8[0x18];
e281682b
SM		 8194
8195 struct mlx5_ifc_health_buffer_bits health_buffer;
8196
8197 u8 no_dram_nic_offset[0x20];
8198
b4ff3a36 8199 u8 reserved_at_1220[0x6e40];
e281682b 8200
b4ff3a36 8201 u8 reserved_at_8060[0x1f];
e281682b
SM		 8202 u8 clear_int[0x1];
8203
8204 u8 health_syndrome[0x8];
8205 u8 health_counter[0x18];
8206
b4ff3a36 8207 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8208};
8209
f9a1ef72
EE		 8210struct mlx5_ifc_mtpps_reg_bits {
8211 u8 reserved_at_0[0xc];
8212 u8 cap_number_of_pps_pins[0x4];
8213 u8 reserved_at_10[0x4];
8214 u8 cap_max_num_of_pps_in_pins[0x4];
8215 u8 reserved_at_18[0x4];
8216 u8 cap_max_num_of_pps_out_pins[0x4];
8217
8218 u8 reserved_at_20[0x24];
8219 u8 cap_pin_3_mode[0x4];
8220 u8 reserved_at_48[0x4];
8221 u8 cap_pin_2_mode[0x4];
8222 u8 reserved_at_50[0x4];
8223 u8 cap_pin_1_mode[0x4];
8224 u8 reserved_at_58[0x4];
8225 u8 cap_pin_0_mode[0x4];
8226
8227 u8 reserved_at_60[0x4];
8228 u8 cap_pin_7_mode[0x4];
8229 u8 reserved_at_68[0x4];
8230 u8 cap_pin_6_mode[0x4];
8231 u8 reserved_at_70[0x4];
8232 u8 cap_pin_5_mode[0x4];
8233 u8 reserved_at_78[0x4];
8234 u8 cap_pin_4_mode[0x4];
8235
8236 u8 reserved_at_80[0x80];
8237
8238 u8 enable[0x1];
8239 u8 reserved_at_101[0xb];
8240 u8 pattern[0x4];
8241 u8 reserved_at_110[0x4];
8242 u8 pin_mode[0x4];
8243 u8 pin[0x8];
8244
8245 u8 reserved_at_120[0x20];
8246
8247 u8 time_stamp[0x40];
8248
8249 u8 out_pulse_duration[0x10];
8250 u8 out_periodic_adjustment[0x10];
8251
8252 u8 reserved_at_1a0[0x60];
8253};
8254
8255struct mlx5_ifc_mtppse_reg_bits {
8256 u8 reserved_at_0[0x18];
8257 u8 pin[0x8];
8258 u8 event_arm[0x1];
8259 u8 reserved_at_21[0x1b];
8260 u8 event_generation_mode[0x4];
8261 u8 reserved_at_40[0x40];
8262};
8263
47176289
OG		 8264struct mlx5_ifc_mcqi_cap_bits {
8265 u8 supported_info_bitmask[0x20];
8266
8267 u8 component_size[0x20];
8268
8269 u8 max_component_size[0x20];
8270
8271 u8 log_mcda_word_size[0x4];
8272 u8 reserved_at_64[0xc];
8273 u8 mcda_max_write_size[0x10];
8274
8275 u8 rd_en[0x1];
8276 u8 reserved_at_81[0x1];
8277 u8 match_chip_id[0x1];
8278 u8 match_psid[0x1];
8279 u8 check_user_timestamp[0x1];
8280 u8 match_base_guid_mac[0x1];
8281 u8 reserved_at_86[0x1a];
8282};
8283
8284struct mlx5_ifc_mcqi_reg_bits {
8285 u8 read_pending_component[0x1];
8286 u8 reserved_at_1[0xf];
8287 u8 component_index[0x10];
8288
8289 u8 reserved_at_20[0x20];
8290
8291 u8 reserved_at_40[0x1b];
8292 u8 info_type[0x5];
8293
8294 u8 info_size[0x20];
8295
8296 u8 offset[0x20];
8297
8298 u8 reserved_at_a0[0x10];
8299 u8 data_size[0x10];
8300
8301 u8 data[0][0x20];
8302};
8303
8304struct mlx5_ifc_mcc_reg_bits {
8305 u8 reserved_at_0[0x4];
8306 u8 time_elapsed_since_last_cmd[0xc];
8307 u8 reserved_at_10[0x8];
8308 u8 instruction[0x8];
8309
8310 u8 reserved_at_20[0x10];
8311 u8 component_index[0x10];
8312
8313 u8 reserved_at_40[0x8];
8314 u8 update_handle[0x18];
8315
8316 u8 handle_owner_type[0x4];
8317 u8 handle_owner_host_id[0x4];
8318 u8 reserved_at_68[0x1];
8319 u8 control_progress[0x7];
8320 u8 error_code[0x8];
8321 u8 reserved_at_78[0x4];
8322 u8 control_state[0x4];
8323
8324 u8 component_size[0x20];
8325
8326 u8 reserved_at_a0[0x60];
8327};
8328
8329struct mlx5_ifc_mcda_reg_bits {
8330 u8 reserved_at_0[0x8];
8331 u8 update_handle[0x18];
8332
8333 u8 offset[0x20];
8334
8335 u8 reserved_at_40[0x10];
8336 u8 size[0x10];
8337
8338 u8 reserved_at_60[0x20];
8339
8340 u8 data[0][0x20];
8341};
8342
e281682b
SM		 8343union mlx5_ifc_ports_control_registers_document_bits {
8344 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8345 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8346 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8347 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8348 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8349 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8350 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8351 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8352 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8353 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8354 struct mlx5_ifc_paos_reg_bits paos_reg;
8355 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8356 struct mlx5_ifc_peir_reg_bits peir_reg;
8357 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8358 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8359 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8360 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8361 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8362 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8363 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8364 struct mlx5_ifc_plib_reg_bits plib_reg;
8365 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8366 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8367 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8368 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8369 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8370 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8371 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8372 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8373 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8374 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8375 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8376 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8377 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8378 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8379 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8380 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8381 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8382 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8383 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8384 struct mlx5_ifc_pude_reg_bits pude_reg;
8385 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8386 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8387 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8388 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8389 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8390 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8391 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8392 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8393 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8394 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8395 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8396 u8 reserved_at_0[0x60e0];
e281682b
SM		 8397};
8398
8399union mlx5_ifc_debug_enhancements_document_bits {
8400 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8401 u8 reserved_at_0[0x200];
e281682b
SM		 8402};
8403
8404union mlx5_ifc_uplink_pci_interface_document_bits {
8405 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8406 u8 reserved_at_0[0x20060];
b775516b
EC		 8407};
8408
2cc43b49
MG		 8409struct mlx5_ifc_set_flow_table_root_out_bits {
8410 u8 status[0x8];
b4ff3a36 8411 u8 reserved_at_8[0x18];
2cc43b49
MG		 8412
8413 u8 syndrome[0x20];
8414
b4ff3a36 8415 u8 reserved_at_40[0x40];
2cc43b49
MG		 8416};
8417
8418struct mlx5_ifc_set_flow_table_root_in_bits {
8419 u8 opcode[0x10];
b4ff3a36 8420 u8 reserved_at_10[0x10];
2cc43b49 8421
b4ff3a36 8422 u8 reserved_at_20[0x10];
2cc43b49
MG		 8423 u8 op_mod[0x10];
8424
7d5e1423
SM		 8425 u8 other_vport[0x1];
8426 u8 reserved_at_41[0xf];
8427 u8 vport_number[0x10];
8428
8429 u8 reserved_at_60[0x20];
2cc43b49
MG		 8430
8431 u8 table_type[0x8];
b4ff3a36 8432 u8 reserved_at_88[0x18];
2cc43b49 8433
b4ff3a36 8434 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8435 u8 table_id[0x18];
8436
500a3d0d
ES		 8437 u8 reserved_at_c0[0x8];
8438 u8 underlay_qpn[0x18];
8439 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8440};
8441
34a40e68 8442enum {
84df61eb
AH		 8443 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8444 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8445};
8446
8447struct mlx5_ifc_modify_flow_table_out_bits {
8448 u8 status[0x8];
b4ff3a36 8449 u8 reserved_at_8[0x18];
34a40e68
MG		 8450
8451 u8 syndrome[0x20];
8452
b4ff3a36 8453 u8 reserved_at_40[0x40];
34a40e68
MG		 8454};
8455
8456struct mlx5_ifc_modify_flow_table_in_bits {
8457 u8 opcode[0x10];
b4ff3a36 8458 u8 reserved_at_10[0x10];
34a40e68 8459
b4ff3a36 8460 u8 reserved_at_20[0x10];
34a40e68
MG		 8461 u8 op_mod[0x10];
8462
7d5e1423
SM		 8463 u8 other_vport[0x1];
8464 u8 reserved_at_41[0xf];
8465 u8 vport_number[0x10];
34a40e68 8466
b4ff3a36 8467 u8 reserved_at_60[0x10];
34a40e68
MG		 8468 u8 modify_field_select[0x10];
8469
8470 u8 table_type[0x8];
b4ff3a36 8471 u8 reserved_at_88[0x18];
34a40e68 8472
b4ff3a36 8473 u8 reserved_at_a0[0x8];
34a40e68
MG		 8474 u8 table_id[0x18];
8475
0c90e9c6 8476 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8477};
8478
4f3961ee
SM		 8479struct mlx5_ifc_ets_tcn_config_reg_bits {
8480 u8 g[0x1];
8481 u8 b[0x1];
8482 u8 r[0x1];
8483 u8 reserved_at_3[0x9];
8484 u8 group[0x4];
8485 u8 reserved_at_10[0x9];
8486 u8 bw_allocation[0x7];
8487
8488 u8 reserved_at_20[0xc];
8489 u8 max_bw_units[0x4];
8490 u8 reserved_at_30[0x8];
8491 u8 max_bw_value[0x8];
8492};
8493
8494struct mlx5_ifc_ets_global_config_reg_bits {
8495 u8 reserved_at_0[0x2];
8496 u8 r[0x1];
8497 u8 reserved_at_3[0x1d];
8498
8499 u8 reserved_at_20[0xc];
8500 u8 max_bw_units[0x4];
8501 u8 reserved_at_30[0x8];
8502 u8 max_bw_value[0x8];
8503};
8504
8505struct mlx5_ifc_qetc_reg_bits {
8506 u8 reserved_at_0[0x8];
8507 u8 port_number[0x8];
8508 u8 reserved_at_10[0x30];
8509
8510 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8511 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8512};
8513
8514struct mlx5_ifc_qtct_reg_bits {
8515 u8 reserved_at_0[0x8];
8516 u8 port_number[0x8];
8517 u8 reserved_at_10[0xd];
8518 u8 prio[0x3];
8519
8520 u8 reserved_at_20[0x1d];
8521 u8 tclass[0x3];
8522};
8523
7d5e1423
SM		 8524struct mlx5_ifc_mcia_reg_bits {
8525 u8 l[0x1];
8526 u8 reserved_at_1[0x7];
8527 u8 module[0x8];
8528 u8 reserved_at_10[0x8];
8529 u8 status[0x8];
8530
8531 u8 i2c_device_address[0x8];
8532 u8 page_number[0x8];
8533 u8 device_address[0x10];
8534
8535 u8 reserved_at_40[0x10];
8536 u8 size[0x10];
8537
8538 u8 reserved_at_60[0x20];
8539
8540 u8 dword_0[0x20];
8541 u8 dword_1[0x20];
8542 u8 dword_2[0x20];
8543 u8 dword_3[0x20];
8544 u8 dword_4[0x20];
8545 u8 dword_5[0x20];
8546 u8 dword_6[0x20];
8547 u8 dword_7[0x20];
8548 u8 dword_8[0x20];
8549 u8 dword_9[0x20];
8550 u8 dword_10[0x20];
8551 u8 dword_11[0x20];
8552};
8553
7486216b
SM		 8554struct mlx5_ifc_dcbx_param_bits {
8555 u8 dcbx_cee_cap[0x1];
8556 u8 dcbx_ieee_cap[0x1];
8557 u8 dcbx_standby_cap[0x1];
8558 u8 reserved_at_0[0x5];
8559 u8 port_number[0x8];
8560 u8 reserved_at_10[0xa];
8561 u8 max_application_table_size[6];
8562 u8 reserved_at_20[0x15];
8563 u8 version_oper[0x3];
8564 u8 reserved_at_38[5];
8565 u8 version_admin[0x3];
8566 u8 willing_admin[0x1];
8567 u8 reserved_at_41[0x3];
8568 u8 pfc_cap_oper[0x4];
8569 u8 reserved_at_48[0x4];
8570 u8 pfc_cap_admin[0x4];
8571 u8 reserved_at_50[0x4];
8572 u8 num_of_tc_oper[0x4];
8573 u8 reserved_at_58[0x4];
8574 u8 num_of_tc_admin[0x4];
8575 u8 remote_willing[0x1];
8576 u8 reserved_at_61[3];
8577 u8 remote_pfc_cap[4];
8578 u8 reserved_at_68[0x14];
8579 u8 remote_num_of_tc[0x4];
8580 u8 reserved_at_80[0x18];
8581 u8 error[0x8];
8582 u8 reserved_at_a0[0x160];
8583};
84df61eb
AH		 8584
8585struct mlx5_ifc_lagc_bits {
8586 u8 reserved_at_0[0x1d];
8587 u8 lag_state[0x3];
8588
8589 u8 reserved_at_20[0x14];
8590 u8 tx_remap_affinity_2[0x4];
8591 u8 reserved_at_38[0x4];
8592 u8 tx_remap_affinity_1[0x4];
8593};
8594
8595struct mlx5_ifc_create_lag_out_bits {
8596 u8 status[0x8];
8597 u8 reserved_at_8[0x18];
8598
8599 u8 syndrome[0x20];
8600
8601 u8 reserved_at_40[0x40];
8602};
8603
8604struct mlx5_ifc_create_lag_in_bits {
8605 u8 opcode[0x10];
8606 u8 reserved_at_10[0x10];
8607
8608 u8 reserved_at_20[0x10];
8609 u8 op_mod[0x10];
8610
8611 struct mlx5_ifc_lagc_bits ctx;
8612};
8613
8614struct mlx5_ifc_modify_lag_out_bits {
8615 u8 status[0x8];
8616 u8 reserved_at_8[0x18];
8617
8618 u8 syndrome[0x20];
8619
8620 u8 reserved_at_40[0x40];
8621};
8622
8623struct mlx5_ifc_modify_lag_in_bits {
8624 u8 opcode[0x10];
8625 u8 reserved_at_10[0x10];
8626
8627 u8 reserved_at_20[0x10];
8628 u8 op_mod[0x10];
8629
8630 u8 reserved_at_40[0x20];
8631 u8 field_select[0x20];
8632
8633 struct mlx5_ifc_lagc_bits ctx;
8634};
8635
8636struct mlx5_ifc_query_lag_out_bits {
8637 u8 status[0x8];
8638 u8 reserved_at_8[0x18];
8639
8640 u8 syndrome[0x20];
8641
8642 u8 reserved_at_40[0x40];
8643
8644 struct mlx5_ifc_lagc_bits ctx;
8645};
8646
8647struct mlx5_ifc_query_lag_in_bits {
8648 u8 opcode[0x10];
8649 u8 reserved_at_10[0x10];
8650
8651 u8 reserved_at_20[0x10];
8652 u8 op_mod[0x10];
8653
8654 u8 reserved_at_40[0x40];
8655};
8656
8657struct mlx5_ifc_destroy_lag_out_bits {
8658 u8 status[0x8];
8659 u8 reserved_at_8[0x18];
8660
8661 u8 syndrome[0x20];
8662
8663 u8 reserved_at_40[0x40];
8664};
8665
8666struct mlx5_ifc_destroy_lag_in_bits {
8667 u8 opcode[0x10];
8668 u8 reserved_at_10[0x10];
8669
8670 u8 reserved_at_20[0x10];
8671 u8 op_mod[0x10];
8672
8673 u8 reserved_at_40[0x40];
8674};
8675
8676struct mlx5_ifc_create_vport_lag_out_bits {
8677 u8 status[0x8];
8678 u8 reserved_at_8[0x18];
8679
8680 u8 syndrome[0x20];
8681
8682 u8 reserved_at_40[0x40];
8683};
8684
8685struct mlx5_ifc_create_vport_lag_in_bits {
8686 u8 opcode[0x10];
8687 u8 reserved_at_10[0x10];
8688
8689 u8 reserved_at_20[0x10];
8690 u8 op_mod[0x10];
8691
8692 u8 reserved_at_40[0x40];
8693};
8694
8695struct mlx5_ifc_destroy_vport_lag_out_bits {
8696 u8 status[0x8];
8697 u8 reserved_at_8[0x18];
8698
8699 u8 syndrome[0x20];
8700
8701 u8 reserved_at_40[0x40];
8702};
8703
8704struct mlx5_ifc_destroy_vport_lag_in_bits {
8705 u8 opcode[0x10];
8706 u8 reserved_at_10[0x10];
8707
8708 u8 reserved_at_20[0x10];
8709 u8 op_mod[0x10];
8710
8711 u8 reserved_at_40[0x40];
8712};
8713
d29b796a 8714#endif /* MLX5_IFC_H */
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