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1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
4352dfd5 GKH |
20 | /* Include the pci register defines */ |
21 | #include <linux/pci_regs.h> | |
1da177e4 | 22 | |
1da177e4 LT |
23 | /* |
24 | * The PCI interface treats multi-function devices as independent | |
25 | * devices. The slot/function address of each device is encoded | |
26 | * in a single byte as follows: | |
27 | * | |
28 | * 7:3 = slot | |
29 | * 2:0 = function | |
30 | */ | |
31 | #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) | |
32 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) | |
33 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
34 | ||
35 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
36 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
37 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
38 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
39 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
40 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
41 | ||
42 | #ifdef __KERNEL__ | |
43 | ||
778382e0 DW |
44 | #include <linux/mod_devicetable.h> |
45 | ||
1da177e4 | 46 | #include <linux/types.h> |
1da177e4 LT |
47 | #include <linux/ioport.h> |
48 | #include <linux/list.h> | |
4a7fb636 | 49 | #include <linux/compiler.h> |
1da177e4 | 50 | #include <linux/errno.h> |
bae94d02 | 51 | #include <asm/atomic.h> |
1da177e4 LT |
52 | #include <linux/device.h> |
53 | ||
7e7a43c3 AB |
54 | /* Include the ID list */ |
55 | #include <linux/pci_ids.h> | |
56 | ||
1da177e4 LT |
57 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
58 | enum pci_mmap_state { | |
59 | pci_mmap_io, | |
60 | pci_mmap_mem | |
61 | }; | |
62 | ||
63 | /* This defines the direction arg to the DMA mapping routines. */ | |
64 | #define PCI_DMA_BIDIRECTIONAL 0 | |
65 | #define PCI_DMA_TODEVICE 1 | |
66 | #define PCI_DMA_FROMDEVICE 2 | |
67 | #define PCI_DMA_NONE 3 | |
68 | ||
1da177e4 LT |
69 | #define DEVICE_COUNT_RESOURCE 12 |
70 | ||
71 | typedef int __bitwise pci_power_t; | |
72 | ||
4352dfd5 GKH |
73 | #define PCI_D0 ((pci_power_t __force) 0) |
74 | #define PCI_D1 ((pci_power_t __force) 1) | |
75 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
76 | #define PCI_D3hot ((pci_power_t __force) 3) |
77 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 78 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 79 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 80 | |
392a1ce7 LV |
81 | /** The pci_channel state describes connectivity between the CPU and |
82 | * the pci device. If some PCI bus between here and the pci device | |
83 | * has crashed or locked up, this info is reflected here. | |
84 | */ | |
85 | typedef unsigned int __bitwise pci_channel_state_t; | |
86 | ||
87 | enum pci_channel_state { | |
88 | /* I/O channel is in normal state */ | |
89 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
90 | ||
91 | /* I/O to channel is blocked */ | |
92 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
93 | ||
94 | /* PCI card is dead */ | |
95 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
96 | }; | |
97 | ||
f7bdd12d BK |
98 | typedef unsigned int __bitwise pcie_reset_state_t; |
99 | ||
100 | enum pcie_reset_state { | |
101 | /* Reset is NOT asserted (Use to deassert reset) */ | |
102 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
103 | ||
104 | /* Use #PERST to reset PCI-E device */ | |
105 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
106 | ||
107 | /* Use PCI-E Hot Reset to reset device */ | |
108 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
109 | }; | |
110 | ||
ba698ad4 DM |
111 | typedef unsigned short __bitwise pci_dev_flags_t; |
112 | enum pci_dev_flags { | |
113 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
114 | * generation too. | |
115 | */ | |
116 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
117 | }; | |
118 | ||
6e325a62 MT |
119 | typedef unsigned short __bitwise pci_bus_flags_t; |
120 | enum pci_bus_flags { | |
d556ad4b PO |
121 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
122 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
123 | }; |
124 | ||
41017f0c SL |
125 | struct pci_cap_saved_state { |
126 | struct hlist_node next; | |
127 | char cap_nr; | |
128 | u32 data[0]; | |
129 | }; | |
130 | ||
1da177e4 LT |
131 | /* |
132 | * The pci_dev structure is used to describe PCI devices. | |
133 | */ | |
134 | struct pci_dev { | |
135 | struct list_head global_list; /* node in list of all PCI devices */ | |
136 | struct list_head bus_list; /* node in per-bus list */ | |
137 | struct pci_bus *bus; /* bus this device is on */ | |
138 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
139 | ||
140 | void *sysdata; /* hook for sys-specific extension */ | |
141 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
142 | ||
143 | unsigned int devfn; /* encoded device & function index */ | |
144 | unsigned short vendor; | |
145 | unsigned short device; | |
146 | unsigned short subsystem_vendor; | |
147 | unsigned short subsystem_device; | |
148 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 149 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 150 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
994a65e2 | 151 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 152 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 153 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
154 | |
155 | struct pci_driver *driver; /* which driver has allocated this device */ | |
156 | u64 dma_mask; /* Mask of the bits of bus address this | |
157 | device implements. Normally this is | |
158 | 0xffffffff. You only need to change | |
159 | this if your device has broken DMA | |
160 | or supports 64-bit transfers. */ | |
161 | ||
162 | pci_power_t current_state; /* Current operating state. In ACPI-speak, | |
163 | this is D0-D3, D0 being fully functional, | |
164 | and D3 being off. */ | |
165 | ||
392a1ce7 | 166 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
167 | struct device dev; /* Generic device interface */ |
168 | ||
1da177e4 LT |
169 | int cfg_size; /* Size of configuration space */ |
170 | ||
171 | /* | |
172 | * Instead of touching interrupt line and base address registers | |
173 | * directly, use the values stored here. They might be different! | |
174 | */ | |
175 | unsigned int irq; | |
176 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
177 | ||
178 | /* These fields are used by common fixups */ | |
179 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
180 | unsigned int multifunction:1;/* Part of multi-function device */ | |
181 | /* keep track of device state */ | |
1da177e4 | 182 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 183 | unsigned int no_msi:1; /* device may not use msi */ |
ffadcc2f | 184 | unsigned int no_d1d2:1; /* only allow d0 or d3 */ |
e04b0ea2 | 185 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 186 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
99dc804d SL |
187 | unsigned int msi_enabled:1; |
188 | unsigned int msix_enabled:1; | |
9ac7849e | 189 | unsigned int is_managed:1; |
994a65e2 | 190 | unsigned int is_pcie:1; |
ba698ad4 | 191 | pci_dev_flags_t dev_flags; |
bae94d02 | 192 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 193 | |
1da177e4 | 194 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 195 | struct hlist_head saved_cap_space; |
1da177e4 LT |
196 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
197 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
198 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
ded86d8d | 199 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 200 | struct list_head msi_list; |
ded86d8d | 201 | #endif |
1da177e4 LT |
202 | }; |
203 | ||
65891215 ME |
204 | extern struct pci_dev *alloc_pci_dev(void); |
205 | ||
1da177e4 LT |
206 | #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list) |
207 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) | |
208 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
209 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
210 | ||
a7369f1f LV |
211 | static inline int pci_channel_offline(struct pci_dev *pdev) |
212 | { | |
213 | return (pdev->error_state != pci_channel_io_normal); | |
214 | } | |
215 | ||
41017f0c SL |
216 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
217 | struct pci_dev *pci_dev,char cap) | |
218 | { | |
219 | struct pci_cap_saved_state *tmp; | |
220 | struct hlist_node *pos; | |
221 | ||
222 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
223 | if (tmp->cap_nr == cap) | |
224 | return tmp; | |
225 | } | |
226 | return NULL; | |
227 | } | |
228 | ||
229 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
230 | struct pci_cap_saved_state *new_cap) | |
231 | { | |
232 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
233 | } | |
234 | ||
1da177e4 LT |
235 | /* |
236 | * For PCI devices, the region numbers are assigned this way: | |
237 | * | |
238 | * 0-5 standard PCI regions | |
239 | * 6 expansion ROM | |
240 | * 7-10 bridges: address space assigned to buses behind the bridge | |
241 | */ | |
242 | ||
4352dfd5 GKH |
243 | #define PCI_ROM_RESOURCE 6 |
244 | #define PCI_BRIDGE_RESOURCES 7 | |
245 | #define PCI_NUM_RESOURCES 11 | |
1da177e4 LT |
246 | |
247 | #ifndef PCI_BUS_NUM_RESOURCES | |
4352dfd5 | 248 | #define PCI_BUS_NUM_RESOURCES 8 |
1da177e4 | 249 | #endif |
4352dfd5 GKH |
250 | |
251 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
252 | |
253 | struct pci_bus { | |
254 | struct list_head node; /* node in list of buses */ | |
255 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
256 | struct list_head children; /* list of child buses */ | |
257 | struct list_head devices; /* list of devices on this bus */ | |
258 | struct pci_dev *self; /* bridge device as seen by parent */ | |
259 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; | |
260 | /* address space routed to this bus */ | |
261 | ||
262 | struct pci_ops *ops; /* configuration access functions */ | |
263 | void *sysdata; /* hook for sys-specific extension */ | |
264 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
265 | ||
266 | unsigned char number; /* bus number */ | |
267 | unsigned char primary; /* number of primary bridge */ | |
268 | unsigned char secondary; /* number of secondary bridge */ | |
269 | unsigned char subordinate; /* max number of subordinate buses */ | |
270 | ||
271 | char name[48]; | |
272 | ||
273 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 274 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 LT |
275 | struct device *bridge; |
276 | struct class_device class_dev; | |
277 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ | |
278 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
279 | }; | |
280 | ||
281 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
282 | #define to_pci_bus(n) container_of(n, struct pci_bus, class_dev) | |
283 | ||
284 | /* | |
285 | * Error values that may be returned by PCI functions. | |
286 | */ | |
287 | #define PCIBIOS_SUCCESSFUL 0x00 | |
288 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
289 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
290 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
291 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
292 | #define PCIBIOS_SET_FAILED 0x88 | |
293 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
294 | ||
295 | /* Low-level architecture-dependent routines */ | |
296 | ||
297 | struct pci_ops { | |
298 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
299 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
300 | }; | |
301 | ||
302 | struct pci_raw_ops { | |
303 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, | |
304 | int reg, int len, u32 *val); | |
305 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, | |
306 | int reg, int len, u32 val); | |
307 | }; | |
308 | ||
309 | extern struct pci_raw_ops *raw_pci_ops; | |
310 | ||
311 | struct pci_bus_region { | |
312 | unsigned long start; | |
313 | unsigned long end; | |
314 | }; | |
315 | ||
316 | struct pci_dynids { | |
317 | spinlock_t lock; /* protects list, index */ | |
318 | struct list_head list; /* for IDs added at runtime */ | |
319 | unsigned int use_driver_data:1; /* pci_driver->driver_data is used */ | |
320 | }; | |
321 | ||
392a1ce7 LV |
322 | /* ---------------------------------------------------------------- */ |
323 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 324 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 LV |
325 | * will be notified of PCI bus errors, and will be driven to recovery |
326 | * when an error occurs. | |
327 | */ | |
328 | ||
329 | typedef unsigned int __bitwise pci_ers_result_t; | |
330 | ||
331 | enum pci_ers_result { | |
332 | /* no result/none/not supported in device driver */ | |
333 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
334 | ||
335 | /* Device driver can recover without slot reset */ | |
336 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
337 | ||
338 | /* Device driver wants slot to be reset. */ | |
339 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
340 | ||
341 | /* Device has completely failed, is unrecoverable */ | |
342 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
343 | ||
344 | /* Device driver is fully recovered and operational */ | |
345 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
346 | }; | |
347 | ||
348 | /* PCI bus error event callbacks */ | |
349 | struct pci_error_handlers | |
350 | { | |
351 | /* PCI bus error detected on this device */ | |
352 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
353 | enum pci_channel_state error); | |
354 | ||
355 | /* MMIO has been re-enabled, but not DMA */ | |
356 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
357 | ||
358 | /* PCI Express link has been reset */ | |
359 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
360 | ||
361 | /* PCI slot has been reset */ | |
362 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
363 | ||
364 | /* Device driver may resume normal operations */ | |
365 | void (*resume)(struct pci_dev *dev); | |
366 | }; | |
367 | ||
368 | /* ---------------------------------------------------------------- */ | |
369 | ||
1da177e4 LT |
370 | struct module; |
371 | struct pci_driver { | |
372 | struct list_head node; | |
373 | char *name; | |
1da177e4 LT |
374 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
375 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
376 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
377 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
378 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
379 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 380 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 381 | void (*shutdown) (struct pci_dev *dev); |
1da177e4 | 382 | |
392a1ce7 | 383 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
384 | struct device_driver driver; |
385 | struct pci_dynids dynids; | |
386 | }; | |
387 | ||
388 | #define to_pci_driver(drv) container_of(drv,struct pci_driver, driver) | |
389 | ||
390 | /** | |
391 | * PCI_DEVICE - macro used to describe a specific pci device | |
392 | * @vend: the 16 bit PCI Vendor ID | |
393 | * @dev: the 16 bit PCI Device ID | |
394 | * | |
395 | * This macro is used to create a struct pci_device_id that matches a | |
396 | * specific device. The subvendor and subdevice fields will be set to | |
397 | * PCI_ANY_ID. | |
398 | */ | |
399 | #define PCI_DEVICE(vend,dev) \ | |
400 | .vendor = (vend), .device = (dev), \ | |
401 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
402 | ||
403 | /** | |
404 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
405 | * @dev_class: the class, subclass, prog-if triple for this device | |
406 | * @dev_class_mask: the class mask for this device | |
407 | * | |
408 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 409 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
410 | * fields will be set to PCI_ANY_ID. |
411 | */ | |
412 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
413 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
414 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
415 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
416 | ||
1597cacb AC |
417 | /** |
418 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
419 | * @vend: the vendor name | |
420 | * @dev: the 16 bit PCI Device ID | |
421 | * | |
422 | * This macro is used to create a struct pci_device_id that matches a | |
423 | * specific PCI device. The subvendor, and subdevice fields will be set | |
424 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
425 | * private data. | |
426 | */ | |
427 | ||
428 | #define PCI_VDEVICE(vendor, device) \ | |
429 | PCI_VENDOR_ID_##vendor, (device), \ | |
430 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
431 | ||
1da177e4 LT |
432 | /* these external functions are only available when PCI support is enabled */ |
433 | #ifdef CONFIG_PCI | |
434 | ||
435 | extern struct bus_type pci_bus_type; | |
436 | ||
437 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
438 | * code, or pci core code. */ | |
439 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
440 | extern struct list_head pci_devices; /* list of all devices */ | |
ed4aaadb ZY |
441 | /* Some device drivers need know if pci is initiated */ |
442 | extern int no_pci_devices(void); | |
1da177e4 LT |
443 | |
444 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 445 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
1da177e4 LT |
446 | char *pcibios_setup (char *str); |
447 | ||
448 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
449 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
450 | resource_size_t); | |
1da177e4 LT |
451 | void pcibios_update_irq(struct pci_dev *, int irq); |
452 | ||
453 | /* Generic PCI functions used internally */ | |
454 | ||
455 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c431ada4 | 456 | void pci_bus_add_devices(struct pci_bus *bus); |
1da177e4 LT |
457 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); |
458 | static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata) | |
459 | { | |
c431ada4 RS |
460 | struct pci_bus *root_bus; |
461 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
462 | if (root_bus) | |
463 | pci_bus_add_devices(root_bus); | |
464 | return root_bus; | |
1da177e4 | 465 | } |
cdb9b9f7 PM |
466 | struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); |
467 | struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); | |
1da177e4 LT |
468 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
469 | struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn); | |
cdb9b9f7 | 470 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 471 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 472 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 LT |
473 | void pci_read_bridge_bases(struct pci_bus *child); |
474 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res); | |
475 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); | |
476 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); | |
477 | extern void pci_dev_put(struct pci_dev *dev); | |
478 | extern void pci_remove_bus(struct pci_bus *b); | |
479 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 480 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 481 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 482 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
483 | |
484 | /* Generic PCI functions exported to card drivers */ | |
485 | ||
bd3989e0 | 486 | #ifdef CONFIG_PCI_LEGACY |
429538ad | 487 | struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from); |
adf809d0 | 488 | struct pci_dev __deprecated *pci_find_slot (unsigned int bus, unsigned int devfn); |
bd3989e0 JG |
489 | #endif /* CONFIG_PCI_LEGACY */ |
490 | ||
1da177e4 | 491 | int pci_find_capability (struct pci_dev *dev, int cap); |
24a4e377 | 492 | int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); |
3a720d72 | 493 | int pci_find_ext_capability (struct pci_dev *dev, int cap); |
687d5fe3 ME |
494 | int pci_find_ht_capability (struct pci_dev *dev, int ht_cap); |
495 | int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap); | |
4348a2dc | 496 | void pcie_wait_pending_transaction(struct pci_dev *dev); |
29f3eb64 | 497 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 498 | |
d42552c3 AM |
499 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
500 | struct pci_dev *from); | |
501 | struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device, | |
502 | struct pci_dev *from); | |
503 | ||
1da177e4 LT |
504 | struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device, |
505 | unsigned int ss_vendor, unsigned int ss_device, | |
506 | struct pci_dev *from); | |
507 | struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn); | |
29f3eb64 | 508 | struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn); |
1da177e4 LT |
509 | struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from); |
510 | int pci_dev_present(const struct pci_device_id *ids); | |
d86f90f9 | 511 | const struct pci_device_id *pci_find_present(const struct pci_device_id *ids); |
1da177e4 LT |
512 | |
513 | int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val); | |
514 | int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val); | |
515 | int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val); | |
516 | int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val); | |
517 | int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val); | |
518 | int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val); | |
519 | ||
520 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
521 | { | |
522 | return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val); | |
523 | } | |
524 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
525 | { | |
526 | return pci_bus_read_config_word (dev->bus, dev->devfn, where, val); | |
527 | } | |
528 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val) | |
529 | { | |
530 | return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val); | |
531 | } | |
532 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
533 | { | |
534 | return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val); | |
535 | } | |
536 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
537 | { | |
538 | return pci_bus_write_config_word (dev->bus, dev->devfn, where, val); | |
539 | } | |
540 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val) | |
541 | { | |
542 | return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val); | |
543 | } | |
544 | ||
4a7fb636 AM |
545 | int __must_check pci_enable_device(struct pci_dev *dev); |
546 | int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask); | |
0b62e13b | 547 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
548 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
549 | void pcim_pin_device(struct pci_dev *pdev); | |
550 | ||
551 | static inline int pci_is_managed(struct pci_dev *pdev) | |
552 | { | |
553 | return pdev->is_managed; | |
554 | } | |
555 | ||
1da177e4 LT |
556 | void pci_disable_device(struct pci_dev *dev); |
557 | void pci_set_master(struct pci_dev *dev); | |
f7bdd12d | 558 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
1da177e4 | 559 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 560 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 561 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 562 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 563 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 564 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
565 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
566 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
d556ad4b PO |
567 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
568 | int pcix_get_mmrbc(struct pci_dev *dev); | |
569 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 570 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 571 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
064b53db | 572 | void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); |
4a7fb636 AM |
573 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
574 | int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i); | |
c87deff7 | 575 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
576 | |
577 | /* ROM control related routines */ | |
144a50ea | 578 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 579 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
d7ad2254 | 580 | size_t pci_get_rom_size(void __iomem *rom, size_t size); |
1da177e4 LT |
581 | |
582 | /* Power management related routines */ | |
583 | int pci_save_state(struct pci_dev *dev); | |
584 | int pci_restore_state(struct pci_dev *dev); | |
9c8550ee LT |
585 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
586 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
587 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); | |
1da177e4 | 588 | |
ce5ccdef KG |
589 | /* Functions for PCI Hotplug drivers to use */ |
590 | int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); | |
591 | ||
1da177e4 LT |
592 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
593 | void pci_bus_assign_resources(struct pci_bus *bus); | |
594 | void pci_bus_size_bridges(struct pci_bus *bus); | |
595 | int pci_claim_resource(struct pci_dev *, int); | |
596 | void pci_assign_unassigned_resources(void); | |
597 | void pdev_enable_device(struct pci_dev *); | |
598 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
599 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), | |
600 | int (*)(struct pci_dev *, u8, u8)); | |
601 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 602 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
1da177e4 | 603 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 604 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 605 | void pci_release_region(struct pci_dev *, int); |
c87deff7 HS |
606 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
607 | void pci_release_selected_regions(struct pci_dev *, int); | |
1da177e4 LT |
608 | |
609 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
610 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
611 | struct resource *res, resource_size_t size, | |
612 | resource_size_t align, resource_size_t min, | |
613 | unsigned int type_mask, | |
614 | void (*alignf)(void *, struct resource *, | |
615 | resource_size_t, resource_size_t), | |
616 | void *alignf_data); | |
1da177e4 LT |
617 | void pci_enable_bridges(struct pci_bus *bus); |
618 | ||
863b18f4 | 619 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
620 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
621 | const char *mod_name); | |
4a7fb636 | 622 | static inline int __must_check pci_register_driver(struct pci_driver *driver) |
863b18f4 | 623 | { |
725522b5 | 624 | return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME); |
863b18f4 L |
625 | } |
626 | ||
1da177e4 LT |
627 | void pci_unregister_driver(struct pci_driver *); |
628 | void pci_remove_behind_bridge(struct pci_dev *); | |
629 | struct pci_driver *pci_dev_driver(const struct pci_dev *); | |
75865858 | 630 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev); |
1da177e4 LT |
631 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass); |
632 | ||
cecf4864 PM |
633 | void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), |
634 | void *userdata); | |
ac7dc65a | 635 | int pci_cfg_space_size(struct pci_dev *dev); |
b82db5ce | 636 | unsigned char pci_bus_max_busnr(struct pci_bus* bus); |
cecf4864 | 637 | |
1da177e4 LT |
638 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
639 | ||
640 | #include <linux/dmapool.h> | |
641 | ||
642 | #define pci_pool dma_pool | |
643 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
644 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
645 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
646 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
647 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
648 | ||
e24c2d96 DM |
649 | enum pci_dma_burst_strategy { |
650 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
651 | strategy_parameter is N/A */ | |
652 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
653 | byte boundaries */ | |
654 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
655 | strategy_parameter byte boundaries */ | |
656 | }; | |
657 | ||
1da177e4 LT |
658 | struct msix_entry { |
659 | u16 vector; /* kernel uses to write allocated vector */ | |
660 | u16 entry; /* driver uses to specify entry, OS writes */ | |
661 | }; | |
662 | ||
0366f8f7 | 663 | |
1da177e4 | 664 | #ifndef CONFIG_PCI_MSI |
1da177e4 LT |
665 | static inline int pci_enable_msi(struct pci_dev *dev) {return -1;} |
666 | static inline void pci_disable_msi(struct pci_dev *dev) {} | |
667 | static inline int pci_enable_msix(struct pci_dev* dev, | |
668 | struct msix_entry *entries, int nvec) {return -1;} | |
669 | static inline void pci_disable_msix(struct pci_dev *dev) {} | |
670 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {} | |
671 | #else | |
1da177e4 LT |
672 | extern int pci_enable_msi(struct pci_dev *dev); |
673 | extern void pci_disable_msi(struct pci_dev *dev); | |
674 | extern int pci_enable_msix(struct pci_dev* dev, | |
675 | struct msix_entry *entries, int nvec); | |
676 | extern void pci_disable_msix(struct pci_dev *dev); | |
677 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
678 | #endif | |
679 | ||
8b955b0d | 680 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
681 | /* The functions a driver should call */ |
682 | int ht_create_irq(struct pci_dev *dev, int idx); | |
683 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
684 | #endif /* CONFIG_HT_IRQ */ |
685 | ||
e04b0ea2 BK |
686 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
687 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
688 | ||
4352dfd5 GKH |
689 | /* |
690 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
691 | * a PCI domain is defined to be a set of PCI busses which share | |
692 | * configuration space. | |
693 | */ | |
32a2eea7 JG |
694 | #ifdef CONFIG_PCI_DOMAINS |
695 | extern int pci_domains_supported; | |
696 | #else | |
697 | enum { pci_domains_supported = 0 }; | |
4352dfd5 GKH |
698 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
699 | static inline int pci_proc_domain(struct pci_bus *bus) | |
700 | { | |
701 | return 0; | |
702 | } | |
32a2eea7 | 703 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 704 | |
4352dfd5 | 705 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
706 | |
707 | /* | |
708 | * If the system does not have PCI, clearly these return errors. Define | |
709 | * these as simple inline functions to avoid hair in drivers. | |
710 | */ | |
711 | ||
1da177e4 LT |
712 | #define _PCI_NOP(o,s,t) \ |
713 | static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \ | |
714 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } | |
715 | #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \ | |
716 | _PCI_NOP(o,word,u16 x) \ | |
717 | _PCI_NOP(o,dword,u32 x) | |
718 | _PCI_NOP_ALL(read, *) | |
719 | _PCI_NOP_ALL(write,) | |
720 | ||
721 | static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from) | |
722 | { return NULL; } | |
723 | ||
724 | static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn) | |
725 | { return NULL; } | |
726 | ||
d42552c3 AM |
727 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
728 | unsigned int device, struct pci_dev *from) | |
729 | { return NULL; } | |
730 | ||
731 | static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor, | |
732 | unsigned int device, struct pci_dev *from) | |
1da177e4 LT |
733 | { return NULL; } |
734 | ||
735 | static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device, | |
736 | unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from) | |
737 | { return NULL; } | |
738 | ||
739 | static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from) | |
740 | { return NULL; } | |
741 | ||
742 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 743 | #define no_pci_devices() (1) |
d86f90f9 | 744 | #define pci_find_present(ids) (NULL) |
1da177e4 LT |
745 | #define pci_dev_put(dev) do { } while (0) |
746 | ||
747 | static inline void pci_set_master(struct pci_dev *dev) { } | |
748 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } | |
749 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
750 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } | |
1da177e4 | 751 | static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;} |
863b18f4 | 752 | static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;} |
1da177e4 LT |
753 | static inline int pci_register_driver(struct pci_driver *drv) { return 0;} |
754 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
755 | static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; } | |
24a4e377 | 756 | static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; } |
3a720d72 | 757 | static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; } |
4348a2dc | 758 | static inline void pcie_wait_pending_transaction(struct pci_dev *dev) {} |
1da177e4 LT |
759 | |
760 | /* Power management related routines */ | |
761 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } | |
762 | static inline int pci_restore_state(struct pci_dev *dev) { return 0; } | |
763 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; } | |
438510f6 | 764 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; } |
1da177e4 LT |
765 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; } |
766 | ||
0da0ead9 SS |
767 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) { return -EIO; } |
768 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
769 | ||
a46e8126 KG |
770 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
771 | ||
e04b0ea2 BK |
772 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) { } |
773 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { } | |
774 | ||
d80d0217 RD |
775 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
776 | { return NULL; } | |
777 | ||
778 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
779 | unsigned int devfn) | |
780 | { return NULL; } | |
781 | ||
782 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
783 | unsigned int devfn) | |
784 | { return NULL; } | |
785 | ||
4352dfd5 | 786 | #endif /* CONFIG_PCI */ |
1da177e4 | 787 | |
4352dfd5 GKH |
788 | /* Include architecture-dependent settings and functions */ |
789 | ||
790 | #include <asm/pci.h> | |
1da177e4 LT |
791 | |
792 | /* these helpers provide future and backwards compatibility | |
793 | * for accessing popular PCI BAR info */ | |
794 | #define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start) | |
795 | #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end) | |
796 | #define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags) | |
797 | #define pci_resource_len(dev,bar) \ | |
798 | ((pci_resource_start((dev),(bar)) == 0 && \ | |
799 | pci_resource_end((dev),(bar)) == \ | |
800 | pci_resource_start((dev),(bar))) ? 0 : \ | |
801 | \ | |
802 | (pci_resource_end((dev),(bar)) - \ | |
803 | pci_resource_start((dev),(bar)) + 1)) | |
804 | ||
805 | /* Similar to the helpers above, these manipulate per-pci_dev | |
806 | * driver-specific data. They are really just a wrapper around | |
807 | * the generic device structure functions of these calls. | |
808 | */ | |
809 | static inline void *pci_get_drvdata (struct pci_dev *pdev) | |
810 | { | |
811 | return dev_get_drvdata(&pdev->dev); | |
812 | } | |
813 | ||
814 | static inline void pci_set_drvdata (struct pci_dev *pdev, void *data) | |
815 | { | |
816 | dev_set_drvdata(&pdev->dev, data); | |
817 | } | |
818 | ||
819 | /* If you want to know what to call your pci_dev, ask this function. | |
820 | * Again, it's a wrapper around the generic device. | |
821 | */ | |
822 | static inline char *pci_name(struct pci_dev *pdev) | |
823 | { | |
824 | return pdev->dev.bus_id; | |
825 | } | |
826 | ||
2311b1f2 ME |
827 | |
828 | /* Some archs don't want to expose struct resource to userland as-is | |
829 | * in sysfs and /proc | |
830 | */ | |
831 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
832 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
e31dd6e4 GKH |
833 | const struct resource *rsrc, resource_size_t *start, |
834 | resource_size_t *end) | |
2311b1f2 ME |
835 | { |
836 | *start = rsrc->start; | |
837 | *end = rsrc->end; | |
838 | } | |
839 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
840 | ||
841 | ||
1da177e4 LT |
842 | /* |
843 | * The world is not perfect and supplies us with broken PCI devices. | |
844 | * For at least a part of these bugs we need a work-around, so both | |
845 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
846 | * fixup hooks to be called for particular buggy devices. | |
847 | */ | |
848 | ||
849 | struct pci_fixup { | |
850 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
851 | void (*hook)(struct pci_dev *dev); | |
852 | }; | |
853 | ||
854 | enum pci_fixup_pass { | |
855 | pci_fixup_early, /* Before probing BARs */ | |
856 | pci_fixup_header, /* After reading configuration header */ | |
857 | pci_fixup_final, /* Final phase of device fixups */ | |
858 | pci_fixup_enable, /* pci_enable_device() time */ | |
1597cacb | 859 | pci_fixup_resume, /* pci_enable_device() time */ |
1da177e4 LT |
860 | }; |
861 | ||
862 | /* Anonymous variables would be nice... */ | |
863 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 864 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
865 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
866 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
867 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
868 | vendor##device##hook, vendor, device, hook) | |
869 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
870 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
871 | vendor##device##hook, vendor, device, hook) | |
872 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
873 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
874 | vendor##device##hook, vendor, device, hook) | |
875 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
876 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
877 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
878 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
879 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
880 | resume##vendor##device##hook, vendor, device, hook) | |
1da177e4 LT |
881 | |
882 | ||
883 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); | |
884 | ||
5ea81769 AV |
885 | void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
886 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); | |
887 | void __iomem * const * pcim_iomap_table(struct pci_dev *pdev); | |
888 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); | |
ec04b075 | 889 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 890 | |
1da177e4 | 891 | extern int pci_pci_problems; |
236561e5 | 892 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
893 | #define PCIPCI_TRITON 2 |
894 | #define PCIPCI_NATOMA 4 | |
895 | #define PCIPCI_VIAETBF 8 | |
896 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
897 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
898 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 899 | |
4516a618 AN |
900 | extern unsigned long pci_cardbus_io_size; |
901 | extern unsigned long pci_cardbus_mem_size; | |
902 | ||
a2cd52ca | 903 | extern int pcibios_add_platform_entries(struct pci_dev *dev); |
575e3348 | 904 | |
1da177e4 LT |
905 | #endif /* __KERNEL__ */ |
906 | #endif /* LINUX_PCI_H */ |