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58bc67fc RQ |
1 | /* |
2 | * OMAP GPMC Platform data | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments, Inc. - http://www.ti.com | |
5 | * Roger Quadros <rogerq@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef _GPMC_OMAP_H_ | |
13 | #define _GPMC_OMAP_H_ | |
14 | ||
15 | /* Maximum Number of Chip Selects */ | |
16 | #define GPMC_CS_NUM 8 | |
17 | ||
fabe7d77 RQ |
18 | /* bool type time settings */ |
19 | struct gpmc_bool_timings { | |
20 | bool cycle2cyclediffcsen; | |
21 | bool cycle2cyclesamecsen; | |
22 | bool we_extra_delay; | |
23 | bool oe_extra_delay; | |
24 | bool adv_extra_delay; | |
25 | bool cs_extra_delay; | |
26 | bool time_para_granularity; | |
27 | }; | |
28 | ||
29 | /* | |
30 | * Note that all values in this struct are in nanoseconds except sync_clk | |
31 | * (which is in picoseconds), while the register values are in gpmc_fck cycles. | |
32 | */ | |
33 | struct gpmc_timings { | |
34 | /* Minimum clock period for synchronous mode (in picoseconds) */ | |
35 | u32 sync_clk; | |
36 | ||
37 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | |
38 | u32 cs_on; /* Assertion time */ | |
39 | u32 cs_rd_off; /* Read deassertion time */ | |
40 | u32 cs_wr_off; /* Write deassertion time */ | |
41 | ||
42 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | |
43 | u32 adv_on; /* Assertion time */ | |
44 | u32 adv_rd_off; /* Read deassertion time */ | |
45 | u32 adv_wr_off; /* Write deassertion time */ | |
46 | u32 adv_aad_mux_on; /* ADV assertion time for AAD */ | |
47 | u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */ | |
48 | u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */ | |
49 | ||
50 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | |
51 | u32 we_on; /* WE assertion time */ | |
52 | u32 we_off; /* WE deassertion time */ | |
53 | ||
54 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | |
55 | u32 oe_on; /* OE assertion time */ | |
56 | u32 oe_off; /* OE deassertion time */ | |
57 | u32 oe_aad_mux_on; /* OE assertion time for AAD */ | |
58 | u32 oe_aad_mux_off; /* OE deassertion time for AAD */ | |
59 | ||
60 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | |
61 | u32 page_burst_access; /* Multiple access word delay */ | |
62 | u32 access; /* Start-cycle to first data valid delay */ | |
63 | u32 rd_cycle; /* Total read cycle time */ | |
64 | u32 wr_cycle; /* Total write cycle time */ | |
65 | ||
66 | u32 bus_turnaround; | |
67 | u32 cycle2cycle_delay; | |
68 | ||
69 | u32 wait_monitoring; | |
70 | u32 clk_activation; | |
71 | ||
72 | /* The following are only on OMAP3430 */ | |
73 | u32 wr_access; /* WRACCESSTIME */ | |
74 | u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */ | |
75 | ||
76 | struct gpmc_bool_timings bool_timings; | |
77 | }; | |
78 | ||
79 | /* Device timings in picoseconds */ | |
80 | struct gpmc_device_timings { | |
81 | u32 t_ceasu; /* address setup to CS valid */ | |
82 | u32 t_avdasu; /* address setup to ADV valid */ | |
83 | /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is | |
84 | * of tusb using these timings even for sync whilst | |
85 | * ideally for adv_rd/(wr)_off it should have considered | |
86 | * t_avdh instead. This indirectly necessitates r/w | |
87 | * variations of t_avdp as it is possible to have one | |
88 | * sync & other async | |
89 | */ | |
90 | u32 t_avdp_r; /* ADV low time (what about t_cer ?) */ | |
91 | u32 t_avdp_w; | |
92 | u32 t_aavdh; /* address hold time */ | |
93 | u32 t_oeasu; /* address setup to OE valid */ | |
94 | u32 t_aa; /* access time from ADV assertion */ | |
95 | u32 t_iaa; /* initial access time */ | |
96 | u32 t_oe; /* access time from OE assertion */ | |
97 | u32 t_ce; /* access time from CS asertion */ | |
98 | u32 t_rd_cycle; /* read cycle time */ | |
99 | u32 t_cez_r; /* read CS deassertion to high Z */ | |
100 | u32 t_cez_w; /* write CS deassertion to high Z */ | |
101 | u32 t_oez; /* OE deassertion to high Z */ | |
102 | u32 t_weasu; /* address setup to WE valid */ | |
103 | u32 t_wpl; /* write assertion time */ | |
104 | u32 t_wph; /* write deassertion time */ | |
105 | u32 t_wr_cycle; /* write cycle time */ | |
106 | ||
107 | u32 clk; | |
108 | u32 t_bacc; /* burst access valid clock to output delay */ | |
109 | u32 t_ces; /* CS setup time to clk */ | |
110 | u32 t_avds; /* ADV setup time to clk */ | |
111 | u32 t_avdh; /* ADV hold time from clk */ | |
112 | u32 t_ach; /* address hold time from clk */ | |
113 | u32 t_rdyo; /* clk to ready valid */ | |
114 | ||
115 | u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */ | |
116 | u32 t_ce_avd; /* CS on to ADV on delay */ | |
117 | ||
118 | /* XXX: check the possibility of combining | |
119 | * cyc_aavhd_oe & cyc_aavdh_we | |
120 | */ | |
121 | u8 cyc_aavdh_oe;/* read address hold time in cycles */ | |
122 | u8 cyc_aavdh_we;/* write address hold time in cycles */ | |
123 | u8 cyc_oe; /* access time from OE assertion in cycles */ | |
124 | u8 cyc_wpl; /* write deassertion time in cycles */ | |
125 | u32 cyc_iaa; /* initial access time in cycles */ | |
126 | ||
127 | /* extra delays */ | |
128 | bool ce_xdelay; | |
129 | bool avd_xdelay; | |
130 | bool oe_xdelay; | |
131 | bool we_xdelay; | |
132 | }; | |
133 | ||
134 | #define GPMC_BURST_4 4 /* 4 word burst */ | |
135 | #define GPMC_BURST_8 8 /* 8 word burst */ | |
136 | #define GPMC_BURST_16 16 /* 16 word burst */ | |
137 | #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */ | |
138 | #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */ | |
139 | #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ | |
140 | #define GPMC_MUX_AD 2 /* Addr-Data multiplex */ | |
141 | ||
142 | struct gpmc_settings { | |
143 | bool burst_wrap; /* enables wrap bursting */ | |
144 | bool burst_read; /* enables read page/burst mode */ | |
145 | bool burst_write; /* enables write page/burst mode */ | |
146 | bool device_nand; /* device is NAND */ | |
147 | bool sync_read; /* enables synchronous reads */ | |
148 | bool sync_write; /* enables synchronous writes */ | |
149 | bool wait_on_read; /* monitor wait on reads */ | |
150 | bool wait_on_write; /* monitor wait on writes */ | |
151 | u32 burst_len; /* page/burst length */ | |
152 | u32 device_width; /* device bus width (8 or 16 bit) */ | |
153 | u32 mux_add_data; /* multiplex address & data */ | |
154 | u32 wait_pin; /* wait-pin to be used */ | |
155 | }; | |
156 | ||
58bc67fc RQ |
157 | /* Data for each chip select */ |
158 | struct gpmc_omap_cs_data { | |
159 | bool valid; /* data is valid */ | |
160 | bool is_nand; /* device within this CS is NAND */ | |
fabe7d77 RQ |
161 | struct gpmc_settings *settings; |
162 | struct gpmc_device_timings *device_timings; | |
163 | struct gpmc_timings *gpmc_timings; | |
58bc67fc RQ |
164 | struct platform_device *pdev; /* device within this CS region */ |
165 | unsigned int pdata_size; | |
166 | }; | |
167 | ||
168 | struct gpmc_omap_platform_data { | |
169 | struct gpmc_omap_cs_data cs[GPMC_CS_NUM]; | |
170 | }; | |
171 | ||
172 | #endif /* _GPMC_OMAP_H */ |