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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2016 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 | 31 | */ |
e8f1cb50 | 32 | |
05fafbfb YM |
33 | #ifndef _COMMON_HSI_H |
34 | #define _COMMON_HSI_H | |
35 | #include <linux/types.h> | |
36 | #include <asm/byteorder.h> | |
37 | #include <linux/bitops.h> | |
38 | #include <linux/slab.h> | |
39 | ||
40 | /* dma_addr_t manip */ | |
f1ff8666 YM |
41 | #define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) |
42 | #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) | |
43 | #define DMA_REGPAIR_LE(x, val) do { \ | |
44 | (x).hi = DMA_HI_LE((val)); \ | |
45 | (x).lo = DMA_LO_LE((val)); \ | |
46 | } while (0) | |
05fafbfb YM |
47 | |
48 | #define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) | |
f1ff8666 | 49 | #define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64) |
05fafbfb | 50 | #define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo)) |
f1ff8666 | 51 | #define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) |
fe56b9e6 YM |
52 | |
53 | #ifndef __COMMON_HSI__ | |
54 | #define __COMMON_HSI__ | |
55 | ||
76a9a364 | 56 | |
fc48b7a6 | 57 | #define X_FINAL_CLEANUP_AGG_INT 1 |
05fafbfb YM |
58 | |
59 | #define EVENT_RING_PAGE_SIZE_BYTES 4096 | |
60 | ||
7a9b6b8f | 61 | #define NUM_OF_GLOBAL_QUEUES 128 |
05fafbfb YM |
62 | #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 |
63 | ||
64 | #define ISCSI_CDU_TASK_SEG_TYPE 0 | |
65 | #define RDMA_CDU_TASK_SEG_TYPE 1 | |
66 | ||
67 | #define FW_ASSERT_GENERAL_ATTN_IDX 32 | |
68 | ||
69 | #define MAX_PINNED_CCFC 32 | |
fc48b7a6 | 70 | |
351a4ded YM |
71 | /* Queue Zone sizes in bytes */ |
72 | #define TSTORM_QZONE_SIZE 8 | |
05fafbfb | 73 | #define MSTORM_QZONE_SIZE 16 |
351a4ded YM |
74 | #define USTORM_QZONE_SIZE 8 |
75 | #define XSTORM_QZONE_SIZE 8 | |
76 | #define YSTORM_QZONE_SIZE 0 | |
77 | #define PSTORM_QZONE_SIZE 0 | |
78 | ||
05fafbfb YM |
79 | #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 |
80 | #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 | |
81 | #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 | |
82 | #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 | |
83 | ||
84 | /********************************/ | |
85 | /* CORE (LIGHT L2) FW CONSTANTS */ | |
86 | /********************************/ | |
87 | ||
88 | #define CORE_LL2_MAX_RAMROD_PER_CON 8 | |
89 | #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 | |
90 | #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 | |
91 | #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 | |
92 | #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 | |
93 | ||
94 | #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 | |
95 | ||
96 | #define CORE_SPQE_PAGE_SIZE_BYTES 4096 | |
97 | ||
98 | #define MAX_NUM_LL2_RX_QUEUES 32 | |
99 | #define MAX_NUM_LL2_TX_STATS_COUNTERS 32 | |
351a4ded | 100 | |
fe56b9e6 | 101 | #define FW_MAJOR_VERSION 8 |
351a4ded | 102 | #define FW_MINOR_VERSION 10 |
05fafbfb | 103 | #define FW_REVISION_VERSION 10 |
fe56b9e6 YM |
104 | #define FW_ENGINEERING_VERSION 0 |
105 | ||
106 | /***********************/ | |
107 | /* COMMON HW CONSTANTS */ | |
108 | /***********************/ | |
109 | ||
110 | /* PCI functions */ | |
111 | #define MAX_NUM_PORTS_K2 (4) | |
112 | #define MAX_NUM_PORTS_BB (2) | |
113 | #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) | |
114 | ||
115 | #define MAX_NUM_PFS_K2 (16) | |
116 | #define MAX_NUM_PFS_BB (8) | |
117 | #define MAX_NUM_PFS (MAX_NUM_PFS_K2) | |
118 | #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ | |
119 | ||
120 | #define MAX_NUM_VFS_K2 (192) | |
121 | #define MAX_NUM_VFS_BB (120) | |
122 | #define MAX_NUM_VFS (MAX_NUM_VFS_K2) | |
123 | ||
124 | #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) | |
125 | #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS) | |
126 | ||
127 | #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) | |
128 | #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS) | |
129 | ||
130 | #define MAX_NUM_VPORTS_K2 (208) | |
131 | #define MAX_NUM_VPORTS_BB (160) | |
132 | #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) | |
133 | ||
134 | #define MAX_NUM_L2_QUEUES_K2 (320) | |
135 | #define MAX_NUM_L2_QUEUES_BB (256) | |
136 | #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) | |
137 | ||
138 | /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ | |
139 | #define NUM_PHYS_TCS_4PORT_K2 (4) | |
140 | #define NUM_OF_PHYS_TCS (8) | |
141 | ||
142 | #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) | |
143 | #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) | |
144 | ||
145 | #define LB_TC (NUM_OF_PHYS_TCS) | |
146 | ||
147 | /* Num of possible traffic priority values */ | |
148 | #define NUM_OF_PRIO (8) | |
149 | ||
150 | #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) | |
151 | #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) | |
152 | #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) | |
153 | #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) | |
154 | ||
155 | /* CIDs */ | |
156 | #define NUM_OF_CONNECTION_TYPES (8) | |
157 | #define NUM_OF_LCIDS (320) | |
158 | #define NUM_OF_LTIDS (320) | |
159 | ||
05fafbfb YM |
160 | /* Clock values */ |
161 | #define MASTER_CLK_FREQ_E4 (375e6) | |
162 | #define STORM_CLK_FREQ_E4 (1000e6) | |
163 | #define CLK25M_CLK_FREQ_E4 (25e6) | |
164 | ||
165 | /* Global PXP windows (GTT) */ | |
166 | #define NUM_OF_GTT 19 | |
167 | #define GTT_DWORD_SIZE_BITS 10 | |
168 | #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) | |
169 | #define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) | |
170 | ||
c965db44 TT |
171 | /* Tools Version */ |
172 | #define TOOLS_VERSION 10 | |
173 | ||
fe56b9e6 YM |
174 | /*****************/ |
175 | /* CDU CONSTANTS */ | |
176 | /*****************/ | |
177 | ||
178 | #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) | |
179 | #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) | |
180 | ||
05fafbfb YM |
181 | #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) |
182 | #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) | |
fe56b9e6 YM |
183 | /*****************/ |
184 | /* DQ CONSTANTS */ | |
185 | /*****************/ | |
186 | ||
187 | /* DEMS */ | |
188 | #define DQ_DEMS_LEGACY 0 | |
189 | ||
190 | /* XCM agg val selection */ | |
191 | #define DQ_XCM_AGG_VAL_SEL_WORD2 0 | |
192 | #define DQ_XCM_AGG_VAL_SEL_WORD3 1 | |
193 | #define DQ_XCM_AGG_VAL_SEL_WORD4 2 | |
194 | #define DQ_XCM_AGG_VAL_SEL_WORD5 3 | |
195 | #define DQ_XCM_AGG_VAL_SEL_REG3 4 | |
196 | #define DQ_XCM_AGG_VAL_SEL_REG4 5 | |
197 | #define DQ_XCM_AGG_VAL_SEL_REG5 6 | |
198 | #define DQ_XCM_AGG_VAL_SEL_REG6 7 | |
199 | ||
200 | /* XCM agg val selection */ | |
351a4ded YM |
201 | #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 |
202 | #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 | |
203 | #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 | |
204 | #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 | |
205 | #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 | |
206 | #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 | |
207 | #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 | |
05fafbfb YM |
208 | #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 |
209 | #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 | |
210 | #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 | |
211 | #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 | |
212 | #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 | |
351a4ded YM |
213 | |
214 | /* UCM agg val selection (HW) */ | |
215 | #define DQ_UCM_AGG_VAL_SEL_WORD0 0 | |
216 | #define DQ_UCM_AGG_VAL_SEL_WORD1 1 | |
217 | #define DQ_UCM_AGG_VAL_SEL_WORD2 2 | |
218 | #define DQ_UCM_AGG_VAL_SEL_WORD3 3 | |
219 | #define DQ_UCM_AGG_VAL_SEL_REG0 4 | |
220 | #define DQ_UCM_AGG_VAL_SEL_REG1 5 | |
221 | #define DQ_UCM_AGG_VAL_SEL_REG2 6 | |
222 | #define DQ_UCM_AGG_VAL_SEL_REG3 7 | |
223 | ||
224 | /* UCM agg val selection (FW) */ | |
225 | #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 | |
226 | #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 | |
227 | #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 | |
228 | #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 | |
229 | ||
230 | /* TCM agg val selection (HW) */ | |
231 | #define DQ_TCM_AGG_VAL_SEL_WORD0 0 | |
232 | #define DQ_TCM_AGG_VAL_SEL_WORD1 1 | |
233 | #define DQ_TCM_AGG_VAL_SEL_WORD2 2 | |
234 | #define DQ_TCM_AGG_VAL_SEL_WORD3 3 | |
235 | #define DQ_TCM_AGG_VAL_SEL_REG1 4 | |
236 | #define DQ_TCM_AGG_VAL_SEL_REG2 5 | |
237 | #define DQ_TCM_AGG_VAL_SEL_REG6 6 | |
238 | #define DQ_TCM_AGG_VAL_SEL_REG9 7 | |
239 | ||
240 | /* TCM agg val selection (FW) */ | |
241 | #define DQ_TCM_L2B_BD_PROD_CMD \ | |
242 | DQ_TCM_AGG_VAL_SEL_WORD1 | |
243 | #define DQ_TCM_ROCE_RQ_PROD_CMD \ | |
244 | DQ_TCM_AGG_VAL_SEL_WORD0 | |
fe56b9e6 YM |
245 | |
246 | /* XCM agg counter flag selection */ | |
351a4ded YM |
247 | #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 |
248 | #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 | |
249 | #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 | |
250 | #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 | |
251 | #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 | |
252 | #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 | |
253 | #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 | |
254 | #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 | |
fe56b9e6 YM |
255 | |
256 | /* XCM agg counter flag selection */ | |
05fafbfb YM |
257 | #define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) |
258 | #define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) | |
259 | #define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) | |
260 | #define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) | |
261 | #define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) | |
262 | #define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) | |
263 | #define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) | |
264 | #define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) | |
265 | #define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) | |
266 | #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) | |
351a4ded YM |
267 | |
268 | /* UCM agg counter flag selection (HW) */ | |
269 | #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 | |
270 | #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 | |
271 | #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 | |
272 | #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 | |
273 | #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 | |
274 | #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 | |
275 | #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 | |
276 | #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 | |
277 | ||
278 | /* UCM agg counter flag selection (FW) */ | |
05fafbfb YM |
279 | #define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) |
280 | #define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) | |
281 | #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4) | |
282 | #define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5) | |
283 | ||
284 | /* TCM agg counter flag selection (HW) */ | |
285 | #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 | |
286 | #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 | |
287 | #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 | |
288 | #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 | |
289 | #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 | |
290 | #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 | |
291 | #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 | |
292 | #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 | |
293 | /* TCM agg counter flag selection (FW) */ | |
294 | #define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) | |
295 | #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) | |
296 | ||
297 | /* PWM address mapping */ | |
298 | #define DQ_PWM_OFFSET_DPM_BASE 0x0 | |
299 | #define DQ_PWM_OFFSET_DPM_END 0x27 | |
300 | #define DQ_PWM_OFFSET_XCM16_BASE 0x40 | |
301 | #define DQ_PWM_OFFSET_XCM32_BASE 0x44 | |
302 | #define DQ_PWM_OFFSET_UCM16_BASE 0x48 | |
303 | #define DQ_PWM_OFFSET_UCM32_BASE 0x4C | |
304 | #define DQ_PWM_OFFSET_UCM16_4 0x50 | |
305 | #define DQ_PWM_OFFSET_TCM16_BASE 0x58 | |
306 | #define DQ_PWM_OFFSET_TCM32_BASE 0x5C | |
307 | #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 | |
308 | #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 | |
309 | #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B | |
310 | ||
311 | #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) | |
312 | #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) | |
313 | #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) | |
314 | #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) | |
315 | #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) | |
316 | #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) | |
317 | #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) | |
351a4ded YM |
318 | #define DQ_REGION_SHIFT (12) |
319 | ||
320 | /* DPM */ | |
321 | #define DQ_DPM_WQE_BUFF_SIZE (320) | |
322 | ||
323 | /* Conn type ranges */ | |
324 | #define DQ_CONN_TYPE_RANGE_SHIFT (4) | |
fe56b9e6 YM |
325 | |
326 | /*****************/ | |
327 | /* QM CONSTANTS */ | |
328 | /*****************/ | |
329 | ||
330 | /* number of TX queues in the QM */ | |
331 | #define MAX_QM_TX_QUEUES_K2 512 | |
332 | #define MAX_QM_TX_QUEUES_BB 448 | |
333 | #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 | |
334 | ||
335 | /* number of Other queues in the QM */ | |
336 | #define MAX_QM_OTHER_QUEUES_BB 64 | |
337 | #define MAX_QM_OTHER_QUEUES_K2 128 | |
338 | #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 | |
339 | ||
340 | /* number of queues in a PF queue group */ | |
341 | #define QM_PF_QUEUE_GROUP_SIZE 8 | |
342 | ||
fc48b7a6 YM |
343 | /* the size of a single queue element in bytes */ |
344 | #define QM_PQ_ELEMENT_SIZE 4 | |
345 | ||
fe56b9e6 YM |
346 | /* base number of Tx PQs in the CM PQ representation. |
347 | * should be used when storing PQ IDs in CM PQ registers and context | |
348 | */ | |
349 | #define CM_TX_PQ_BASE 0x200 | |
350 | ||
05fafbfb YM |
351 | /* number of global Vport/QCN rate limiters */ |
352 | #define MAX_QM_GLOBAL_RLS 256 | |
fe56b9e6 YM |
353 | /* QM registers data */ |
354 | #define QM_LINE_CRD_REG_WIDTH 16 | |
05fafbfb | 355 | #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) |
fe56b9e6 | 356 | #define QM_BYTE_CRD_REG_WIDTH 24 |
05fafbfb | 357 | #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1)) |
fe56b9e6 | 358 | #define QM_WFQ_CRD_REG_WIDTH 32 |
05fafbfb | 359 | #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1)) |
fe56b9e6 | 360 | #define QM_RL_CRD_REG_WIDTH 32 |
05fafbfb | 361 | #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1)) |
fe56b9e6 YM |
362 | |
363 | /*****************/ | |
364 | /* CAU CONSTANTS */ | |
365 | /*****************/ | |
366 | ||
367 | #define CAU_FSM_ETH_RX 0 | |
368 | #define CAU_FSM_ETH_TX 1 | |
369 | ||
370 | /* Number of Protocol Indices per Status Block */ | |
371 | #define PIS_PER_SB 12 | |
372 | ||
373 | #define CAU_HC_STOPPED_STATE 3 | |
374 | #define CAU_HC_DISABLE_STATE 4 | |
375 | #define CAU_HC_ENABLE_STATE 0 | |
376 | ||
377 | /*****************/ | |
378 | /* IGU CONSTANTS */ | |
379 | /*****************/ | |
380 | ||
381 | #define MAX_SB_PER_PATH_K2 (368) | |
382 | #define MAX_SB_PER_PATH_BB (288) | |
383 | #define MAX_TOT_SB_PER_PATH \ | |
384 | MAX_SB_PER_PATH_K2 | |
385 | ||
386 | #define MAX_SB_PER_PF_MIMD 129 | |
387 | #define MAX_SB_PER_PF_SIMD 64 | |
388 | #define MAX_SB_PER_VF 64 | |
389 | ||
390 | /* Memory addresses on the BAR for the IGU Sub Block */ | |
391 | #define IGU_MEM_BASE 0x0000 | |
392 | ||
393 | #define IGU_MEM_MSIX_BASE 0x0000 | |
394 | #define IGU_MEM_MSIX_UPPER 0x0101 | |
395 | #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff | |
396 | ||
397 | #define IGU_MEM_PBA_MSIX_BASE 0x0200 | |
398 | #define IGU_MEM_PBA_MSIX_UPPER 0x0202 | |
399 | #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff | |
400 | ||
401 | #define IGU_CMD_INT_ACK_BASE 0x0400 | |
402 | #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ | |
403 | MAX_TOT_SB_PER_PATH - \ | |
404 | 1) | |
405 | #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff | |
406 | ||
407 | #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 | |
408 | #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 | |
409 | #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 | |
410 | ||
411 | #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 | |
412 | #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 | |
413 | #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 | |
414 | #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 | |
415 | ||
416 | #define IGU_CMD_PROD_UPD_BASE 0x0600 | |
417 | #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ | |
418 | MAX_TOT_SB_PER_PATH - \ | |
419 | 1) | |
420 | #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff | |
421 | ||
422 | /*****************/ | |
423 | /* PXP CONSTANTS */ | |
424 | /*****************/ | |
425 | ||
05fafbfb YM |
426 | /* Bars for Blocks */ |
427 | #define PXP_BAR_GRC 0 | |
428 | #define PXP_BAR_TSDM 0 | |
429 | #define PXP_BAR_USDM 0 | |
430 | #define PXP_BAR_XSDM 0 | |
431 | #define PXP_BAR_MSDM 0 | |
432 | #define PXP_BAR_YSDM 0 | |
433 | #define PXP_BAR_PSDM 0 | |
434 | #define PXP_BAR_IGU 0 | |
435 | #define PXP_BAR_DQ 1 | |
436 | ||
fe56b9e6 YM |
437 | /* PTT and GTT */ |
438 | #define PXP_NUM_PF_WINDOWS 12 | |
439 | #define PXP_PER_PF_ENTRY_SIZE 8 | |
440 | #define PXP_NUM_GLOBAL_WINDOWS 243 | |
441 | #define PXP_GLOBAL_ENTRY_SIZE 4 | |
442 | #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 | |
443 | #define PXP_PF_WINDOW_ADMIN_START 0 | |
444 | #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 | |
445 | #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ | |
446 | PXP_PF_WINDOW_ADMIN_LENGTH - 1) | |
447 | #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 | |
448 | #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ | |
449 | PXP_PER_PF_ENTRY_SIZE) | |
450 | #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ | |
451 | PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) | |
452 | #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 | |
453 | #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ | |
454 | PXP_GLOBAL_ENTRY_SIZE) | |
455 | #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ | |
456 | (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ | |
457 | PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) | |
458 | #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 | |
459 | #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 | |
460 | #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 | |
461 | #define PXP_PF_ME_CONCRETE_ADDR 0x1fc | |
462 | ||
463 | #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 | |
464 | #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS | |
465 | #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 | |
466 | #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ | |
467 | (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ | |
468 | PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) | |
469 | #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ | |
470 | (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ | |
471 | PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) | |
472 | ||
473 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ | |
474 | (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) | |
475 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS | |
476 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 | |
477 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ | |
478 | (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ | |
479 | PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) | |
480 | #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ | |
481 | (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ | |
482 | PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) | |
483 | ||
05fafbfb YM |
484 | /* PF BAR */ |
485 | #define PXP_BAR0_START_GRC 0x0000 | |
486 | #define PXP_BAR0_GRC_LENGTH 0x1C00000 | |
487 | #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ | |
488 | PXP_BAR0_GRC_LENGTH - 1) | |
489 | ||
490 | #define PXP_BAR0_START_IGU 0x1C00000 | |
491 | #define PXP_BAR0_IGU_LENGTH 0x10000 | |
492 | #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ | |
493 | PXP_BAR0_IGU_LENGTH - 1) | |
494 | ||
495 | #define PXP_BAR0_START_TSDM 0x1C80000 | |
496 | #define PXP_BAR0_SDM_LENGTH 0x40000 | |
497 | #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 | |
498 | #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ | |
499 | PXP_BAR0_SDM_LENGTH - 1) | |
500 | ||
501 | #define PXP_BAR0_START_MSDM 0x1D00000 | |
502 | #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ | |
503 | PXP_BAR0_SDM_LENGTH - 1) | |
504 | ||
505 | #define PXP_BAR0_START_USDM 0x1D80000 | |
506 | #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ | |
507 | PXP_BAR0_SDM_LENGTH - 1) | |
508 | ||
509 | #define PXP_BAR0_START_XSDM 0x1E00000 | |
510 | #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ | |
511 | PXP_BAR0_SDM_LENGTH - 1) | |
512 | ||
513 | #define PXP_BAR0_START_YSDM 0x1E80000 | |
514 | #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ | |
515 | PXP_BAR0_SDM_LENGTH - 1) | |
516 | ||
517 | #define PXP_BAR0_START_PSDM 0x1F00000 | |
518 | #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ | |
519 | PXP_BAR0_SDM_LENGTH - 1) | |
520 | ||
521 | #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) | |
522 | ||
523 | /* VF BAR */ | |
524 | #define PXP_VF_BAR0 0 | |
525 | ||
526 | #define PXP_VF_BAR0_START_GRC 0x3E00 | |
527 | #define PXP_VF_BAR0_GRC_LENGTH 0x200 | |
528 | #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ | |
529 | PXP_VF_BAR0_GRC_LENGTH - 1) | |
fe56b9e6 | 530 | |
1408cc1f YM |
531 | #define PXP_VF_BAR0_START_IGU 0 |
532 | #define PXP_VF_BAR0_IGU_LENGTH 0x3000 | |
533 | #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ | |
534 | PXP_VF_BAR0_IGU_LENGTH - 1) | |
535 | ||
536 | #define PXP_VF_BAR0_START_DQ 0x3000 | |
537 | #define PXP_VF_BAR0_DQ_LENGTH 0x200 | |
538 | #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 | |
539 | #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ | |
540 | PXP_VF_BAR0_DQ_OPAQUE_OFFSET) | |
541 | #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ | |
542 | + 4) | |
543 | #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ | |
544 | PXP_VF_BAR0_DQ_LENGTH - 1) | |
545 | ||
546 | #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 | |
547 | #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 | |
548 | #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ | |
549 | + \ | |
550 | PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ | |
551 | - 1) | |
552 | ||
553 | #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 | |
554 | #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ | |
555 | + \ | |
556 | PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ | |
557 | - 1) | |
558 | ||
559 | #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 | |
560 | #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ | |
561 | + \ | |
562 | PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ | |
563 | - 1) | |
564 | ||
565 | #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 | |
566 | #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ | |
567 | + \ | |
568 | PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ | |
569 | - 1) | |
570 | ||
571 | #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 | |
572 | #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ | |
573 | + \ | |
574 | PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ | |
575 | - 1) | |
576 | ||
577 | #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 | |
578 | #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \ | |
579 | + \ | |
580 | PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ | |
581 | - 1) | |
582 | ||
583 | #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 | |
584 | #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 | |
585 | ||
586 | #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 | |
587 | ||
351a4ded YM |
588 | #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 |
589 | #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 | |
590 | ||
fe56b9e6 YM |
591 | /* ILT Records */ |
592 | #define PXP_NUM_ILT_RECORDS_BB 7600 | |
593 | #define PXP_NUM_ILT_RECORDS_K2 11000 | |
594 | #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) | |
05fafbfb YM |
595 | #define PXP_QUEUES_ZONE_MAX_NUM 320 |
596 | /*****************/ | |
597 | /* PRM CONSTANTS */ | |
598 | /*****************/ | |
599 | #define PRM_DMA_PAD_BYTES_NUM 2 | |
600 | /******************/ | |
601 | /* SDMs CONSTANTS */ | |
602 | /******************/ | |
603 | #define SDM_OP_GEN_TRIG_NONE 0 | |
604 | #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 | |
605 | #define SDM_OP_GEN_TRIG_AGG_INT 2 | |
606 | #define SDM_OP_GEN_TRIG_LOADER 4 | |
607 | #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 | |
608 | #define SDM_OP_GEN_TRIG_RELEASE_THREAD 7 | |
fe56b9e6 | 609 | |
fc48b7a6 YM |
610 | #define SDM_COMP_TYPE_NONE 0 |
611 | #define SDM_COMP_TYPE_WAKE_THREAD 1 | |
612 | #define SDM_COMP_TYPE_AGG_INT 2 | |
613 | #define SDM_COMP_TYPE_CM 3 | |
614 | #define SDM_COMP_TYPE_LOADER 4 | |
615 | #define SDM_COMP_TYPE_PXP 5 | |
616 | #define SDM_COMP_TYPE_INDICATE_ERROR 6 | |
617 | #define SDM_COMP_TYPE_RELEASE_THREAD 7 | |
618 | #define SDM_COMP_TYPE_RAM 8 | |
619 | ||
fe56b9e6 YM |
620 | /******************/ |
621 | /* PBF CONSTANTS */ | |
622 | /******************/ | |
623 | ||
624 | /* Number of PBF command queue lines. Each line is 32B. */ | |
625 | #define PBF_MAX_CMD_LINES 3328 | |
626 | ||
627 | /* Number of BTB blocks. Each block is 256B. */ | |
628 | #define BTB_MAX_BLOCKS 1440 | |
629 | ||
630 | /*****************/ | |
631 | /* PRS CONSTANTS */ | |
632 | /*****************/ | |
633 | ||
05fafbfb YM |
634 | #define PRS_GFT_CAM_LINES_NO_MATCH 31 |
635 | ||
fe56b9e6 YM |
636 | /* Async data KCQ CQE */ |
637 | struct async_data { | |
638 | __le32 cid; | |
639 | __le16 itid; | |
640 | u8 error_code; | |
641 | u8 fw_debug_param; | |
642 | }; | |
643 | ||
351a4ded YM |
644 | struct coalescing_timeset { |
645 | u8 value; | |
646 | #define COALESCING_TIMESET_TIMESET_MASK 0x7F | |
647 | #define COALESCING_TIMESET_TIMESET_SHIFT 0 | |
648 | #define COALESCING_TIMESET_VALID_MASK 0x1 | |
649 | #define COALESCING_TIMESET_VALID_SHIFT 7 | |
650 | }; | |
651 | ||
351a4ded YM |
652 | struct common_queue_zone { |
653 | __le16 ring_drv_data_consumer; | |
654 | __le16 reserved; | |
655 | }; | |
656 | ||
657 | struct eth_rx_prod_data { | |
658 | __le16 bd_prod; | |
659 | __le16 cqe_prod; | |
660 | }; | |
661 | ||
fe56b9e6 YM |
662 | struct regpair { |
663 | __le32 lo; | |
664 | __le32 hi; | |
665 | }; | |
666 | ||
37bff2b9 YM |
667 | struct vf_pf_channel_eqe_data { |
668 | struct regpair msg_addr; | |
669 | }; | |
670 | ||
05fafbfb YM |
671 | struct iscsi_eqe_data { |
672 | __le32 cid; | |
673 | __le16 conn_id; | |
674 | u8 error_code; | |
675 | u8 error_pdu_opcode_reserved; | |
676 | #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F | |
677 | #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 | |
678 | #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 | |
679 | #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 | |
680 | #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 | |
681 | #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 | |
682 | }; | |
683 | ||
351a4ded YM |
684 | struct malicious_vf_eqe_data { |
685 | u8 vf_id; | |
686 | u8 err_id; | |
687 | __le16 reserved[3]; | |
688 | }; | |
689 | ||
690 | struct initial_cleanup_eqe_data { | |
691 | u8 vf_id; | |
692 | u8 reserved[7]; | |
693 | }; | |
694 | ||
fe56b9e6 YM |
695 | /* Event Data Union */ |
696 | union event_ring_data { | |
351a4ded YM |
697 | u8 bytes[8]; |
698 | struct vf_pf_channel_eqe_data vf_pf_channel; | |
05fafbfb | 699 | struct iscsi_eqe_data iscsi_info; |
351a4ded YM |
700 | struct malicious_vf_eqe_data malicious_vf; |
701 | struct initial_cleanup_eqe_data vf_init_cleanup; | |
51ff1725 | 702 | struct regpair roce_handle; |
fe56b9e6 YM |
703 | }; |
704 | ||
705 | /* Event Ring Entry */ | |
706 | struct event_ring_entry { | |
707 | u8 protocol_id; | |
708 | u8 opcode; | |
709 | __le16 reserved0; | |
710 | __le16 echo; | |
711 | u8 fw_return_code; | |
712 | u8 flags; | |
713 | #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 | |
714 | #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 | |
715 | #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F | |
716 | #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 | |
717 | union event_ring_data data; | |
718 | }; | |
719 | ||
720 | /* Multi function mode */ | |
721 | enum mf_mode { | |
fc48b7a6 | 722 | ERROR_MODE /* Unsupported mode */, |
fe56b9e6 YM |
723 | MF_OVLAN, |
724 | MF_NPAR, | |
725 | MAX_MF_MODE | |
726 | }; | |
727 | ||
728 | /* Per-protocol connection types */ | |
729 | enum protocol_type { | |
c5ac9319 | 730 | PROTOCOLID_ISCSI, |
fe56b9e6 | 731 | PROTOCOLID_RESERVED2, |
c5ac9319 | 732 | PROTOCOLID_ROCE, |
fe56b9e6 YM |
733 | PROTOCOLID_CORE, |
734 | PROTOCOLID_ETH, | |
735 | PROTOCOLID_RESERVED4, | |
736 | PROTOCOLID_RESERVED5, | |
737 | PROTOCOLID_PREROCE, | |
738 | PROTOCOLID_COMMON, | |
739 | PROTOCOLID_RESERVED6, | |
740 | MAX_PROTOCOL_TYPE | |
741 | }; | |
742 | ||
351a4ded YM |
743 | struct ustorm_eth_queue_zone { |
744 | struct coalescing_timeset int_coalescing_timeset; | |
745 | u8 reserved[3]; | |
746 | }; | |
747 | ||
748 | struct ustorm_queue_zone { | |
749 | struct ustorm_eth_queue_zone eth; | |
750 | struct common_queue_zone common; | |
751 | }; | |
752 | ||
fe56b9e6 YM |
753 | /* status block structure */ |
754 | struct cau_pi_entry { | |
755 | u32 prod; | |
756 | #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF | |
757 | #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 | |
758 | #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F | |
759 | #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 | |
760 | #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 | |
761 | #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 | |
762 | #define CAU_PI_ENTRY_RESERVED_MASK 0xFF | |
763 | #define CAU_PI_ENTRY_RESERVED_SHIFT 24 | |
764 | }; | |
765 | ||
766 | /* status block structure */ | |
767 | struct cau_sb_entry { | |
768 | u32 data; | |
769 | #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF | |
770 | #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 | |
771 | #define CAU_SB_ENTRY_STATE0_MASK 0xF | |
772 | #define CAU_SB_ENTRY_STATE0_SHIFT 24 | |
773 | #define CAU_SB_ENTRY_STATE1_MASK 0xF | |
774 | #define CAU_SB_ENTRY_STATE1_SHIFT 28 | |
775 | u32 params; | |
776 | #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F | |
777 | #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 | |
778 | #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F | |
779 | #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 | |
780 | #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 | |
781 | #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 | |
782 | #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 | |
783 | #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 | |
784 | #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF | |
785 | #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 | |
786 | #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 | |
787 | #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 | |
788 | #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF | |
789 | #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 | |
790 | #define CAU_SB_ENTRY_TPH_MASK 0x1 | |
791 | #define CAU_SB_ENTRY_TPH_SHIFT 31 | |
792 | }; | |
793 | ||
794 | /* core doorbell data */ | |
795 | struct core_db_data { | |
796 | u8 params; | |
797 | #define CORE_DB_DATA_DEST_MASK 0x3 | |
798 | #define CORE_DB_DATA_DEST_SHIFT 0 | |
799 | #define CORE_DB_DATA_AGG_CMD_MASK 0x3 | |
800 | #define CORE_DB_DATA_AGG_CMD_SHIFT 2 | |
801 | #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 | |
802 | #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 | |
803 | #define CORE_DB_DATA_RESERVED_MASK 0x1 | |
804 | #define CORE_DB_DATA_RESERVED_SHIFT 5 | |
805 | #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 | |
806 | #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 | |
807 | u8 agg_flags; | |
808 | __le16 spq_prod; | |
809 | }; | |
810 | ||
811 | /* Enum of doorbell aggregative command selection */ | |
812 | enum db_agg_cmd_sel { | |
813 | DB_AGG_CMD_NOP, | |
814 | DB_AGG_CMD_SET, | |
815 | DB_AGG_CMD_ADD, | |
816 | DB_AGG_CMD_MAX, | |
817 | MAX_DB_AGG_CMD_SEL | |
818 | }; | |
819 | ||
820 | /* Enum of doorbell destination */ | |
821 | enum db_dest { | |
822 | DB_DEST_XCM, | |
823 | DB_DEST_UCM, | |
824 | DB_DEST_TCM, | |
825 | DB_NUM_DESTINATIONS, | |
826 | MAX_DB_DEST | |
827 | }; | |
828 | ||
05fafbfb YM |
829 | /* Enum of doorbell DPM types */ |
830 | enum db_dpm_type { | |
831 | DPM_LEGACY, | |
832 | DPM_ROCE, | |
833 | DPM_L2_INLINE, | |
834 | DPM_L2_BD, | |
835 | MAX_DB_DPM_TYPE | |
836 | }; | |
837 | ||
838 | /* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */ | |
839 | struct db_l2_dpm_data { | |
840 | __le16 icid; | |
841 | __le16 bd_prod; | |
842 | __le32 params; | |
843 | #define DB_L2_DPM_DATA_SIZE_MASK 0x3F | |
844 | #define DB_L2_DPM_DATA_SIZE_SHIFT 0 | |
845 | #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 | |
846 | #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 | |
847 | #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF | |
848 | #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 | |
849 | #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF | |
850 | #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 | |
851 | #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 | |
852 | #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 | |
853 | #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 | |
854 | #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 | |
855 | #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 | |
856 | #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 | |
857 | }; | |
858 | ||
859 | /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */ | |
860 | struct db_l2_dpm_sge { | |
861 | struct regpair addr; | |
862 | __le16 nbytes; | |
863 | __le16 bitfields; | |
864 | #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF | |
865 | #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 | |
866 | #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 | |
867 | #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 | |
868 | #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 | |
869 | #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 | |
870 | #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF | |
871 | #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 | |
872 | __le32 reserved2; | |
873 | }; | |
874 | ||
fe56b9e6 YM |
875 | /* Structure for doorbell address, in legacy mode */ |
876 | struct db_legacy_addr { | |
877 | __le32 addr; | |
878 | #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 | |
879 | #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 | |
880 | #define DB_LEGACY_ADDR_DEMS_MASK 0x7 | |
881 | #define DB_LEGACY_ADDR_DEMS_SHIFT 2 | |
882 | #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF | |
883 | #define DB_LEGACY_ADDR_ICID_SHIFT 5 | |
884 | }; | |
885 | ||
05fafbfb YM |
886 | /* Structure for doorbell address, in PWM mode */ |
887 | struct db_pwm_addr { | |
888 | __le32 addr; | |
889 | #define DB_PWM_ADDR_RESERVED0_MASK 0x7 | |
890 | #define DB_PWM_ADDR_RESERVED0_SHIFT 0 | |
891 | #define DB_PWM_ADDR_OFFSET_MASK 0x7F | |
892 | #define DB_PWM_ADDR_OFFSET_SHIFT 3 | |
893 | #define DB_PWM_ADDR_WID_MASK 0x3 | |
894 | #define DB_PWM_ADDR_WID_SHIFT 10 | |
895 | #define DB_PWM_ADDR_DPI_MASK 0xFFFF | |
896 | #define DB_PWM_ADDR_DPI_SHIFT 12 | |
897 | #define DB_PWM_ADDR_RESERVED1_MASK 0xF | |
898 | #define DB_PWM_ADDR_RESERVED1_SHIFT 28 | |
899 | }; | |
900 | ||
901 | /* Parameters to RoCE firmware, passed in EDPM doorbell */ | |
902 | struct db_roce_dpm_params { | |
903 | __le32 params; | |
904 | #define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F | |
905 | #define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0 | |
906 | #define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3 | |
907 | #define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6 | |
908 | #define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF | |
909 | #define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8 | |
910 | #define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF | |
911 | #define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16 | |
912 | #define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1 | |
913 | #define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27 | |
914 | #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 | |
915 | #define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 | |
916 | #define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1 | |
917 | #define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29 | |
918 | #define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3 | |
919 | #define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30 | |
920 | }; | |
921 | ||
922 | /* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */ | |
923 | struct db_roce_dpm_data { | |
924 | __le16 icid; | |
925 | __le16 prod_val; | |
926 | struct db_roce_dpm_params params; | |
927 | }; | |
928 | ||
fe56b9e6 YM |
929 | /* Igu interrupt command */ |
930 | enum igu_int_cmd { | |
931 | IGU_INT_ENABLE = 0, | |
932 | IGU_INT_DISABLE = 1, | |
933 | IGU_INT_NOP = 2, | |
934 | IGU_INT_NOP2 = 3, | |
935 | MAX_IGU_INT_CMD | |
936 | }; | |
937 | ||
938 | /* IGU producer or consumer update command */ | |
939 | struct igu_prod_cons_update { | |
940 | u32 sb_id_and_flags; | |
941 | #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF | |
942 | #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 | |
943 | #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 | |
944 | #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 | |
945 | #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 | |
946 | #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 | |
947 | #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 | |
948 | #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 | |
949 | #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 | |
950 | #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 | |
951 | #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 | |
952 | #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 | |
953 | #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 | |
954 | #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 | |
955 | u32 reserved1; | |
956 | }; | |
957 | ||
958 | /* Igu segments access for default status block only */ | |
959 | enum igu_seg_access { | |
960 | IGU_SEG_ACCESS_REG = 0, | |
961 | IGU_SEG_ACCESS_ATTN = 1, | |
962 | MAX_IGU_SEG_ACCESS | |
963 | }; | |
964 | ||
965 | struct parsing_and_err_flags { | |
966 | __le16 flags; | |
967 | #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 | |
968 | #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 | |
969 | #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 | |
970 | #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 | |
971 | #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 | |
972 | #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 | |
973 | #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 | |
974 | #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 | |
975 | #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 | |
976 | #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 | |
977 | #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 | |
978 | #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 | |
979 | #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 | |
980 | #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 | |
981 | #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 | |
982 | #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 | |
983 | #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 | |
984 | #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 | |
985 | #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 | |
986 | #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 | |
987 | #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 | |
988 | #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 | |
989 | #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 | |
990 | #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 | |
991 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 | |
992 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 | |
993 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 | |
994 | #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 | |
995 | }; | |
996 | ||
7a9b6b8f YM |
997 | struct pb_context { |
998 | __le32 crc[4]; | |
999 | }; | |
1000 | ||
fe56b9e6 YM |
1001 | struct pxp_concrete_fid { |
1002 | __le16 fid; | |
1003 | #define PXP_CONCRETE_FID_PFID_MASK 0xF | |
1004 | #define PXP_CONCRETE_FID_PFID_SHIFT 0 | |
1005 | #define PXP_CONCRETE_FID_PORT_MASK 0x3 | |
1006 | #define PXP_CONCRETE_FID_PORT_SHIFT 4 | |
1007 | #define PXP_CONCRETE_FID_PATH_MASK 0x1 | |
1008 | #define PXP_CONCRETE_FID_PATH_SHIFT 6 | |
1009 | #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 | |
1010 | #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 | |
1011 | #define PXP_CONCRETE_FID_VFID_MASK 0xFF | |
1012 | #define PXP_CONCRETE_FID_VFID_SHIFT 8 | |
1013 | }; | |
1014 | ||
1015 | struct pxp_pretend_concrete_fid { | |
1016 | __le16 fid; | |
1017 | #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF | |
1018 | #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 | |
1019 | #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 | |
1020 | #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 | |
1021 | #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 | |
1022 | #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 | |
1023 | #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF | |
1024 | #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 | |
1025 | }; | |
1026 | ||
1027 | union pxp_pretend_fid { | |
1028 | struct pxp_pretend_concrete_fid concrete_fid; | |
1029 | __le16 opaque_fid; | |
1030 | }; | |
1031 | ||
1032 | /* Pxp Pretend Command Register. */ | |
1033 | struct pxp_pretend_cmd { | |
1034 | union pxp_pretend_fid fid; | |
1035 | __le16 control; | |
1036 | #define PXP_PRETEND_CMD_PATH_MASK 0x1 | |
1037 | #define PXP_PRETEND_CMD_PATH_SHIFT 0 | |
1038 | #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 | |
1039 | #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 | |
1040 | #define PXP_PRETEND_CMD_PORT_MASK 0x3 | |
1041 | #define PXP_PRETEND_CMD_PORT_SHIFT 2 | |
1042 | #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF | |
1043 | #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 | |
1044 | #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF | |
1045 | #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 | |
1046 | #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 | |
1047 | #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 | |
1048 | #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 | |
1049 | #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 | |
1050 | #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 | |
1051 | #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 | |
1052 | #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 | |
1053 | #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 | |
1054 | }; | |
1055 | ||
1056 | /* PTT Record in PXP Admin Window. */ | |
1057 | struct pxp_ptt_entry { | |
1058 | __le32 offset; | |
1059 | #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF | |
1060 | #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 | |
1061 | #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF | |
1062 | #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 | |
1063 | struct pxp_pretend_cmd pretend; | |
1064 | }; | |
1065 | ||
05fafbfb YM |
1066 | /* VF Zone A Permission Register. */ |
1067 | struct pxp_vf_zone_a_permission { | |
1068 | __le32 control; | |
1069 | #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF | |
1070 | #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 | |
1071 | #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 | |
1072 | #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 | |
1073 | #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F | |
1074 | #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 | |
1075 | #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF | |
1076 | #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 | |
1077 | }; | |
1078 | ||
fe56b9e6 | 1079 | /* RSS hash type */ |
7a9b6b8f YM |
1080 | struct rdif_task_context { |
1081 | __le32 initial_ref_tag; | |
1082 | __le16 app_tag_value; | |
1083 | __le16 app_tag_mask; | |
1084 | u8 flags0; | |
1085 | #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 | |
1086 | #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 | |
1087 | #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 | |
1088 | #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 | |
1089 | #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 | |
1090 | #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 | |
1091 | #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 | |
1092 | #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 | |
1093 | #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 | |
1094 | #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 | |
1095 | #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 | |
1096 | #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 | |
1097 | #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 | |
1098 | #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 | |
1099 | u8 partial_dif_data[7]; | |
1100 | __le16 partial_crc_value; | |
1101 | __le16 partial_checksum_value; | |
1102 | __le32 offset_in_io; | |
1103 | __le16 flags1; | |
1104 | #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 | |
1105 | #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 | |
1106 | #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 | |
1107 | #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 | |
1108 | #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 | |
1109 | #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 | |
1110 | #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 | |
1111 | #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 | |
1112 | #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 | |
1113 | #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 | |
1114 | #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 | |
1115 | #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 | |
1116 | #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 | |
1117 | #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 | |
1118 | #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 | |
1119 | #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 | |
1120 | #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 | |
1121 | #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 | |
1122 | #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 | |
1123 | #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 | |
1124 | #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 | |
1125 | #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 | |
1126 | #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 | |
1127 | #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 | |
1128 | #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 | |
1129 | #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 | |
1130 | __le16 state; | |
1131 | #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF | |
1132 | #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 | |
1133 | #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF | |
1134 | #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 | |
1135 | #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 | |
1136 | #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 | |
1137 | #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 | |
1138 | #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 | |
1139 | #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF | |
1140 | #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 | |
1141 | #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 | |
1142 | #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 | |
1143 | __le32 reserved2; | |
1144 | }; | |
1145 | ||
05fafbfb | 1146 | /* RSS hash type */ |
fe56b9e6 YM |
1147 | enum rss_hash_type { |
1148 | RSS_HASH_TYPE_DEFAULT = 0, | |
1149 | RSS_HASH_TYPE_IPV4 = 1, | |
1150 | RSS_HASH_TYPE_TCP_IPV4 = 2, | |
1151 | RSS_HASH_TYPE_IPV6 = 3, | |
1152 | RSS_HASH_TYPE_TCP_IPV6 = 4, | |
1153 | RSS_HASH_TYPE_UDP_IPV4 = 5, | |
1154 | RSS_HASH_TYPE_UDP_IPV6 = 6, | |
1155 | MAX_RSS_HASH_TYPE | |
1156 | }; | |
1157 | ||
1158 | /* status block structure */ | |
1159 | struct status_block { | |
1160 | __le16 pi_array[PIS_PER_SB]; | |
1161 | __le32 sb_num; | |
1162 | #define STATUS_BLOCK_SB_NUM_MASK 0x1FF | |
1163 | #define STATUS_BLOCK_SB_NUM_SHIFT 0 | |
1164 | #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F | |
1165 | #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 | |
1166 | #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF | |
1167 | #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 | |
1168 | __le32 prod_index; | |
1169 | #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF | |
1170 | #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 | |
1171 | #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF | |
1172 | #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 | |
1173 | }; | |
1174 | ||
7a9b6b8f YM |
1175 | struct tdif_task_context { |
1176 | __le32 initial_ref_tag; | |
1177 | __le16 app_tag_value; | |
1178 | __le16 app_tag_mask; | |
1179 | __le16 partial_crc_valueB; | |
1180 | __le16 partial_checksum_valueB; | |
1181 | __le16 stateB; | |
1182 | #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF | |
1183 | #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 | |
1184 | #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF | |
1185 | #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 | |
1186 | #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 | |
1187 | #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 | |
1188 | #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 | |
1189 | #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 | |
1190 | #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F | |
1191 | #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 | |
1192 | u8 reserved1; | |
1193 | u8 flags0; | |
1194 | #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 | |
1195 | #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 | |
1196 | #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 | |
1197 | #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 | |
1198 | #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 | |
1199 | #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 | |
1200 | #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 | |
1201 | #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 | |
1202 | #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 | |
1203 | #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 | |
1204 | #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 | |
1205 | #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 | |
1206 | #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 | |
1207 | #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 | |
1208 | __le32 flags1; | |
1209 | #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 | |
1210 | #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 | |
1211 | #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 | |
1212 | #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 | |
1213 | #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 | |
1214 | #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 | |
1215 | #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 | |
1216 | #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 | |
1217 | #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 | |
1218 | #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 | |
1219 | #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 | |
1220 | #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 | |
1221 | #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 | |
1222 | #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 | |
1223 | #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 | |
1224 | #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 | |
1225 | #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 | |
1226 | #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 | |
1227 | #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 | |
1228 | #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 | |
1229 | #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 | |
1230 | #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 | |
1231 | #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF | |
1232 | #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 | |
1233 | #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF | |
1234 | #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 | |
1235 | #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 | |
1236 | #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 | |
1237 | #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 | |
1238 | #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 | |
1239 | #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF | |
1240 | #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 | |
1241 | #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 | |
1242 | #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 | |
1243 | #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 | |
1244 | #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 | |
1245 | #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 | |
1246 | #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 | |
1247 | #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 | |
1248 | #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 | |
1249 | __le32 offset_in_iob; | |
1250 | __le16 partial_crc_value_a; | |
1251 | __le16 partial_checksum_valuea_; | |
1252 | __le32 offset_in_ioa; | |
1253 | u8 partial_dif_data_a[8]; | |
1254 | u8 partial_dif_data_b[8]; | |
1255 | }; | |
1256 | ||
1257 | struct timers_context { | |
05fafbfb | 1258 | __le32 logical_client_0; |
7a9b6b8f YM |
1259 | #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF |
1260 | #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 | |
1261 | #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 | |
1262 | #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 | |
1263 | #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 | |
1264 | #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 | |
1265 | #define TIMERS_CONTEXT_RESERVED0_MASK 0x3 | |
1266 | #define TIMERS_CONTEXT_RESERVED0_SHIFT 30 | |
05fafbfb | 1267 | __le32 logical_client_1; |
7a9b6b8f YM |
1268 | #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF |
1269 | #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 | |
1270 | #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 | |
1271 | #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 | |
1272 | #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 | |
1273 | #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 | |
1274 | #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 | |
1275 | #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 | |
05fafbfb | 1276 | __le32 logical_client_2; |
7a9b6b8f YM |
1277 | #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF |
1278 | #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 | |
1279 | #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 | |
1280 | #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 | |
1281 | #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 | |
1282 | #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 | |
1283 | #define TIMERS_CONTEXT_RESERVED2_MASK 0x3 | |
1284 | #define TIMERS_CONTEXT_RESERVED2_SHIFT 30 | |
1285 | __le32 host_expiration_fields; | |
1286 | #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0xFFFFFFF | |
1287 | #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 | |
1288 | #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 | |
1289 | #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 | |
1290 | #define TIMERS_CONTEXT_RESERVED3_MASK 0x7 | |
1291 | #define TIMERS_CONTEXT_RESERVED3_SHIFT 29 | |
1292 | }; | |
fe56b9e6 | 1293 | #endif /* __COMMON_HSI__ */ |
05fafbfb | 1294 | #endif |