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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
fe56b9e6 | 9 | * |
e8f1cb50 MY |
10 | * Redistribution and use in source and binary forms, with or |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #ifndef _QED_IF_H | |
34 | #define _QED_IF_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/skbuff.h> | |
41 | #include <linux/types.h> | |
42 | #include <asm/byteorder.h> | |
43 | #include <linux/io.h> | |
44 | #include <linux/compiler.h> | |
45 | #include <linux/kernel.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/slab.h> | |
48 | #include <linux/qed/common_hsi.h> | |
49 | #include <linux/qed/qed_chain.h> | |
50 | ||
39651abd SRK |
51 | enum dcbx_protocol_type { |
52 | DCBX_PROTOCOL_ISCSI, | |
53 | DCBX_PROTOCOL_FCOE, | |
54 | DCBX_PROTOCOL_ROCE, | |
55 | DCBX_PROTOCOL_ROCE_V2, | |
56 | DCBX_PROTOCOL_ETH, | |
57 | DCBX_MAX_PROTOCOL_TYPE | |
58 | }; | |
59 | ||
51ff1725 RA |
60 | #define QED_ROCE_PROTOCOL_INDEX (3) |
61 | ||
6ad8c632 SRK |
62 | #define QED_LLDP_CHASSIS_ID_STAT_LEN 4 |
63 | #define QED_LLDP_PORT_ID_STAT_LEN 4 | |
64 | #define QED_DCBX_MAX_APP_PROTOCOL 32 | |
65 | #define QED_MAX_PFC_PRIORITIES 8 | |
66 | #define QED_DCBX_DSCP_SIZE 64 | |
67 | ||
68 | struct qed_dcbx_lldp_remote { | |
69 | u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; | |
70 | u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN]; | |
71 | bool enable_rx; | |
72 | bool enable_tx; | |
73 | u32 tx_interval; | |
74 | u32 max_credit; | |
75 | }; | |
76 | ||
77 | struct qed_dcbx_lldp_local { | |
78 | u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN]; | |
79 | u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN]; | |
80 | }; | |
81 | ||
82 | struct qed_dcbx_app_prio { | |
83 | u8 roce; | |
84 | u8 roce_v2; | |
85 | u8 fcoe; | |
86 | u8 iscsi; | |
87 | u8 eth; | |
88 | }; | |
89 | ||
90 | struct qed_dbcx_pfc_params { | |
91 | bool willing; | |
92 | bool enabled; | |
93 | u8 prio[QED_MAX_PFC_PRIORITIES]; | |
94 | u8 max_tc; | |
95 | }; | |
96 | ||
59bcb797 SRK |
97 | enum qed_dcbx_sf_ieee_type { |
98 | QED_DCBX_SF_IEEE_ETHTYPE, | |
99 | QED_DCBX_SF_IEEE_TCP_PORT, | |
100 | QED_DCBX_SF_IEEE_UDP_PORT, | |
101 | QED_DCBX_SF_IEEE_TCP_UDP_PORT | |
102 | }; | |
103 | ||
6ad8c632 SRK |
104 | struct qed_app_entry { |
105 | bool ethtype; | |
59bcb797 | 106 | enum qed_dcbx_sf_ieee_type sf_ieee; |
6ad8c632 SRK |
107 | bool enabled; |
108 | u8 prio; | |
109 | u16 proto_id; | |
110 | enum dcbx_protocol_type proto_type; | |
111 | }; | |
112 | ||
113 | struct qed_dcbx_params { | |
114 | struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL]; | |
115 | u16 num_app_entries; | |
116 | bool app_willing; | |
117 | bool app_valid; | |
118 | bool app_error; | |
119 | bool ets_willing; | |
120 | bool ets_enabled; | |
121 | bool ets_cbs; | |
122 | bool valid; | |
123 | u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES]; | |
124 | u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES]; | |
125 | u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES]; | |
126 | struct qed_dbcx_pfc_params pfc; | |
127 | u8 max_ets_tc; | |
128 | }; | |
129 | ||
130 | struct qed_dcbx_admin_params { | |
131 | struct qed_dcbx_params params; | |
132 | bool valid; | |
133 | }; | |
134 | ||
135 | struct qed_dcbx_remote_params { | |
136 | struct qed_dcbx_params params; | |
137 | bool valid; | |
138 | }; | |
139 | ||
140 | struct qed_dcbx_operational_params { | |
141 | struct qed_dcbx_app_prio app_prio; | |
142 | struct qed_dcbx_params params; | |
143 | bool valid; | |
144 | bool enabled; | |
145 | bool ieee; | |
146 | bool cee; | |
49632b58 | 147 | bool local; |
6ad8c632 SRK |
148 | u32 err; |
149 | }; | |
150 | ||
151 | struct qed_dcbx_get { | |
152 | struct qed_dcbx_operational_params operational; | |
153 | struct qed_dcbx_lldp_remote lldp_remote; | |
154 | struct qed_dcbx_lldp_local lldp_local; | |
155 | struct qed_dcbx_remote_params remote; | |
156 | struct qed_dcbx_admin_params local; | |
157 | }; | |
6ad8c632 | 158 | |
20675b37 MY |
159 | enum qed_nvm_images { |
160 | QED_NVM_IMAGE_ISCSI_CFG, | |
161 | QED_NVM_IMAGE_FCOE_CFG, | |
162 | }; | |
163 | ||
645874e5 SRK |
164 | struct qed_link_eee_params { |
165 | u32 tx_lpi_timer; | |
166 | #define QED_EEE_1G_ADV BIT(0) | |
167 | #define QED_EEE_10G_ADV BIT(1) | |
168 | ||
169 | /* Capabilities are represented using QED_EEE_*_ADV values */ | |
170 | u8 adv_caps; | |
171 | u8 lp_adv_caps; | |
172 | bool enable; | |
173 | bool tx_lpi_enable; | |
174 | }; | |
175 | ||
91420b83 SK |
176 | enum qed_led_mode { |
177 | QED_LED_MODE_OFF, | |
178 | QED_LED_MODE_ON, | |
179 | QED_LED_MODE_RESTORE | |
180 | }; | |
181 | ||
fe56b9e6 YM |
182 | #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \ |
183 | (void __iomem *)(reg_addr)) | |
184 | ||
185 | #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr)) | |
186 | ||
41822878 | 187 | #define QED_COALESCE_MAX 0x1FF |
0e191827 | 188 | #define QED_DEFAULT_RX_USECS 12 |
bf5a94bf | 189 | #define QED_DEFAULT_TX_USECS 48 |
fe56b9e6 YM |
190 | |
191 | /* forward */ | |
192 | struct qed_dev; | |
193 | ||
194 | struct qed_eth_pf_params { | |
195 | /* The following parameters are used during HW-init | |
196 | * and these parameters need to be passed as arguments | |
197 | * to update_pf_params routine invoked before slowpath start | |
198 | */ | |
199 | u16 num_cons; | |
d51e4af5 | 200 | |
08bc8f15 MY |
201 | /* per-VF number of CIDs */ |
202 | u8 num_vf_cons; | |
203 | #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32) | |
204 | ||
d51e4af5 CM |
205 | /* To enable arfs, previous to HW-init a positive number needs to be |
206 | * set [as filters require allocated searcher ILT memory]. | |
207 | * This will set the maximal number of configured steering-filters. | |
208 | */ | |
209 | u32 num_arfs_filters; | |
fe56b9e6 YM |
210 | }; |
211 | ||
1e128c81 AE |
212 | struct qed_fcoe_pf_params { |
213 | /* The following parameters are used during protocol-init */ | |
214 | u64 glbl_q_params_addr; | |
215 | u64 bdq_pbl_base_addr[2]; | |
216 | ||
217 | /* The following parameters are used during HW-init | |
218 | * and these parameters need to be passed as arguments | |
219 | * to update_pf_params routine invoked before slowpath start | |
220 | */ | |
221 | u16 num_cons; | |
222 | u16 num_tasks; | |
223 | ||
224 | /* The following parameters are used during protocol-init */ | |
225 | u16 sq_num_pbl_pages; | |
226 | ||
227 | u16 cq_num_entries; | |
228 | u16 cmdq_num_entries; | |
229 | u16 rq_buffer_log_size; | |
230 | u16 mtu; | |
231 | u16 dummy_icid; | |
232 | u16 bdq_xoff_threshold[2]; | |
233 | u16 bdq_xon_threshold[2]; | |
234 | u16 rq_buffer_size; | |
235 | u8 num_cqs; /* num of global CQs */ | |
236 | u8 log_page_size; | |
237 | u8 gl_rq_pi; | |
238 | u8 gl_cmd_pi; | |
239 | u8 debug_mode; | |
240 | u8 is_target; | |
241 | u8 bdq_pbl_num_entries[2]; | |
242 | }; | |
243 | ||
c5ac9319 YM |
244 | /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */ |
245 | struct qed_iscsi_pf_params { | |
246 | u64 glbl_q_params_addr; | |
247 | u64 bdq_pbl_base_addr[2]; | |
248 | u32 max_cwnd; | |
249 | u16 cq_num_entries; | |
250 | u16 cmdq_num_entries; | |
fc831825 | 251 | u32 two_msl_timer; |
c5ac9319 YM |
252 | u16 dup_ack_threshold; |
253 | u16 tx_sws_timer; | |
254 | u16 min_rto; | |
255 | u16 min_rto_rt; | |
256 | u16 max_rto; | |
257 | ||
258 | /* The following parameters are used during HW-init | |
259 | * and these parameters need to be passed as arguments | |
260 | * to update_pf_params routine invoked before slowpath start | |
261 | */ | |
262 | u16 num_cons; | |
263 | u16 num_tasks; | |
264 | ||
265 | /* The following parameters are used during protocol-init */ | |
266 | u16 half_way_close_timeout; | |
267 | u16 bdq_xoff_threshold[2]; | |
268 | u16 bdq_xon_threshold[2]; | |
269 | u16 cmdq_xoff_threshold; | |
270 | u16 cmdq_xon_threshold; | |
271 | u16 rq_buffer_size; | |
272 | ||
273 | u8 num_sq_pages_in_ring; | |
274 | u8 num_r2tq_pages_in_ring; | |
275 | u8 num_uhq_pages_in_ring; | |
276 | u8 num_queues; | |
277 | u8 log_page_size; | |
278 | u8 rqe_log_size; | |
279 | u8 max_fin_rt; | |
280 | u8 gl_rq_pi; | |
281 | u8 gl_cmd_pi; | |
282 | u8 debug_mode; | |
283 | u8 ll2_ooo_queue_id; | |
284 | u8 ooo_enable; | |
285 | ||
286 | u8 is_target; | |
287 | u8 bdq_pbl_num_entries[2]; | |
288 | }; | |
289 | ||
290 | struct qed_rdma_pf_params { | |
291 | /* Supplied to QED during resource allocation (may affect the ILT and | |
292 | * the doorbell BAR). | |
293 | */ | |
294 | u32 min_dpis; /* number of requested DPIs */ | |
c5ac9319 YM |
295 | u32 num_qps; /* number of requested Queue Pairs */ |
296 | u32 num_srqs; /* number of requested SRQ */ | |
297 | u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */ | |
298 | u8 gl_pi; /* protocol index */ | |
299 | ||
300 | /* Will allocate rate limiters to be used with QPs */ | |
301 | u8 enable_dcqcn; | |
302 | }; | |
303 | ||
fe56b9e6 YM |
304 | struct qed_pf_params { |
305 | struct qed_eth_pf_params eth_pf_params; | |
1e128c81 | 306 | struct qed_fcoe_pf_params fcoe_pf_params; |
c5ac9319 YM |
307 | struct qed_iscsi_pf_params iscsi_pf_params; |
308 | struct qed_rdma_pf_params rdma_pf_params; | |
fe56b9e6 YM |
309 | }; |
310 | ||
311 | enum qed_int_mode { | |
312 | QED_INT_MODE_INTA, | |
313 | QED_INT_MODE_MSIX, | |
314 | QED_INT_MODE_MSI, | |
315 | QED_INT_MODE_POLL, | |
316 | }; | |
317 | ||
318 | struct qed_sb_info { | |
319 | struct status_block *sb_virt; | |
320 | dma_addr_t sb_phys; | |
321 | u32 sb_ack; /* Last given ack */ | |
322 | u16 igu_sb_id; | |
323 | void __iomem *igu_addr; | |
324 | u8 flags; | |
325 | #define QED_SB_INFO_INIT 0x1 | |
326 | #define QED_SB_INFO_SETUP 0x2 | |
327 | ||
328 | struct qed_dev *cdev; | |
329 | }; | |
330 | ||
9c79ddaa MY |
331 | enum qed_dev_type { |
332 | QED_DEV_TYPE_BB, | |
333 | QED_DEV_TYPE_AH, | |
334 | }; | |
335 | ||
fe56b9e6 YM |
336 | struct qed_dev_info { |
337 | unsigned long pci_mem_start; | |
338 | unsigned long pci_mem_end; | |
339 | unsigned int pci_irq; | |
340 | u8 num_hwfns; | |
341 | ||
342 | u8 hw_mac[ETH_ALEN]; | |
fc48b7a6 | 343 | bool is_mf_default; |
fe56b9e6 YM |
344 | |
345 | /* FW version */ | |
346 | u16 fw_major; | |
347 | u16 fw_minor; | |
348 | u16 fw_rev; | |
349 | u16 fw_eng; | |
350 | ||
351 | /* MFW version */ | |
352 | u32 mfw_rev; | |
ae33666a TT |
353 | #define QED_MFW_VERSION_0_MASK 0x000000FF |
354 | #define QED_MFW_VERSION_0_OFFSET 0 | |
355 | #define QED_MFW_VERSION_1_MASK 0x0000FF00 | |
356 | #define QED_MFW_VERSION_1_OFFSET 8 | |
357 | #define QED_MFW_VERSION_2_MASK 0x00FF0000 | |
358 | #define QED_MFW_VERSION_2_OFFSET 16 | |
359 | #define QED_MFW_VERSION_3_MASK 0xFF000000 | |
360 | #define QED_MFW_VERSION_3_OFFSET 24 | |
fe56b9e6 YM |
361 | |
362 | u32 flash_size; | |
363 | u8 mf_mode; | |
831bfb0e | 364 | bool tx_switching; |
cee9fbd8 | 365 | bool rdma_supported; |
0fefbfba | 366 | u16 mtu; |
14d39648 MY |
367 | |
368 | bool wol_support; | |
9c79ddaa | 369 | |
ae33666a TT |
370 | /* MBI version */ |
371 | u32 mbi_version; | |
372 | #define QED_MBI_VERSION_0_MASK 0x000000FF | |
373 | #define QED_MBI_VERSION_0_OFFSET 0 | |
374 | #define QED_MBI_VERSION_1_MASK 0x0000FF00 | |
375 | #define QED_MBI_VERSION_1_OFFSET 8 | |
376 | #define QED_MBI_VERSION_2_MASK 0x00FF0000 | |
377 | #define QED_MBI_VERSION_2_OFFSET 16 | |
378 | ||
9c79ddaa | 379 | enum qed_dev_type dev_type; |
19489c7f CM |
380 | |
381 | /* Output parameters for qede */ | |
382 | bool vxlan_enable; | |
383 | bool gre_enable; | |
384 | bool geneve_enable; | |
3c5da942 MY |
385 | |
386 | u8 abs_pf_id; | |
fe56b9e6 YM |
387 | }; |
388 | ||
389 | enum qed_sb_type { | |
390 | QED_SB_TYPE_L2_QUEUE, | |
51ff1725 | 391 | QED_SB_TYPE_CNQ, |
fc831825 | 392 | QED_SB_TYPE_STORAGE, |
fe56b9e6 YM |
393 | }; |
394 | ||
395 | enum qed_protocol { | |
396 | QED_PROTOCOL_ETH, | |
c5ac9319 | 397 | QED_PROTOCOL_ISCSI, |
1e128c81 | 398 | QED_PROTOCOL_FCOE, |
fe56b9e6 YM |
399 | }; |
400 | ||
054c67d1 SRK |
401 | enum qed_link_mode_bits { |
402 | QED_LM_FIBRE_BIT = BIT(0), | |
403 | QED_LM_Autoneg_BIT = BIT(1), | |
404 | QED_LM_Asym_Pause_BIT = BIT(2), | |
405 | QED_LM_Pause_BIT = BIT(3), | |
406 | QED_LM_1000baseT_Half_BIT = BIT(4), | |
407 | QED_LM_1000baseT_Full_BIT = BIT(5), | |
408 | QED_LM_10000baseKR_Full_BIT = BIT(6), | |
409 | QED_LM_25000baseKR_Full_BIT = BIT(7), | |
410 | QED_LM_40000baseLR4_Full_BIT = BIT(8), | |
411 | QED_LM_50000baseKR2_Full_BIT = BIT(9), | |
412 | QED_LM_100000baseKR4_Full_BIT = BIT(10), | |
413 | QED_LM_COUNT = 11 | |
414 | }; | |
415 | ||
fe56b9e6 YM |
416 | struct qed_link_params { |
417 | bool link_up; | |
418 | ||
419 | #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0) | |
420 | #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) | |
421 | #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) | |
422 | #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) | |
03dc76ca | 423 | #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4) |
645874e5 | 424 | #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) |
fe56b9e6 YM |
425 | u32 override_flags; |
426 | bool autoneg; | |
427 | u32 adv_speeds; | |
428 | u32 forced_speed; | |
429 | #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) | |
430 | #define QED_LINK_PAUSE_RX_ENABLE BIT(1) | |
431 | #define QED_LINK_PAUSE_TX_ENABLE BIT(2) | |
432 | u32 pause_config; | |
03dc76ca SRK |
433 | #define QED_LINK_LOOPBACK_NONE BIT(0) |
434 | #define QED_LINK_LOOPBACK_INT_PHY BIT(1) | |
435 | #define QED_LINK_LOOPBACK_EXT_PHY BIT(2) | |
436 | #define QED_LINK_LOOPBACK_EXT BIT(3) | |
437 | #define QED_LINK_LOOPBACK_MAC BIT(4) | |
438 | u32 loopback_mode; | |
645874e5 | 439 | struct qed_link_eee_params eee; |
fe56b9e6 YM |
440 | }; |
441 | ||
442 | struct qed_link_output { | |
443 | bool link_up; | |
444 | ||
d194fd26 YM |
445 | /* In QED_LM_* defs */ |
446 | u32 supported_caps; | |
447 | u32 advertised_caps; | |
448 | u32 lp_caps; | |
449 | ||
fe56b9e6 YM |
450 | u32 speed; /* In Mb/s */ |
451 | u8 duplex; /* In DUPLEX defs */ | |
452 | u8 port; /* In PORT defs */ | |
453 | bool autoneg; | |
454 | u32 pause_config; | |
645874e5 SRK |
455 | |
456 | /* EEE - capability & param */ | |
457 | bool eee_supported; | |
458 | bool eee_active; | |
459 | u8 sup_caps; | |
460 | struct qed_link_eee_params eee; | |
fe56b9e6 YM |
461 | }; |
462 | ||
1408cc1f YM |
463 | struct qed_probe_params { |
464 | enum qed_protocol protocol; | |
465 | u32 dp_module; | |
466 | u8 dp_level; | |
467 | bool is_vf; | |
468 | }; | |
469 | ||
fe56b9e6 YM |
470 | #define QED_DRV_VER_STR_SIZE 12 |
471 | struct qed_slowpath_params { | |
472 | u32 int_mode; | |
473 | u8 drv_major; | |
474 | u8 drv_minor; | |
475 | u8 drv_rev; | |
476 | u8 drv_eng; | |
477 | u8 name[QED_DRV_VER_STR_SIZE]; | |
478 | }; | |
479 | ||
480 | #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */ | |
481 | ||
482 | struct qed_int_info { | |
483 | struct msix_entry *msix; | |
484 | u8 msix_cnt; | |
485 | ||
486 | /* This should be updated by the protocol driver */ | |
487 | u8 used_cnt; | |
488 | }; | |
489 | ||
490 | struct qed_common_cb_ops { | |
d51e4af5 | 491 | void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc); |
fe56b9e6 YM |
492 | void (*link_update)(void *dev, |
493 | struct qed_link_output *link); | |
1e128c81 | 494 | void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type); |
fe56b9e6 YM |
495 | }; |
496 | ||
03dc76ca SRK |
497 | struct qed_selftest_ops { |
498 | /** | |
499 | * @brief selftest_interrupt - Perform interrupt test | |
500 | * | |
501 | * @param cdev | |
502 | * | |
503 | * @return 0 on success, error otherwise. | |
504 | */ | |
505 | int (*selftest_interrupt)(struct qed_dev *cdev); | |
506 | ||
507 | /** | |
508 | * @brief selftest_memory - Perform memory test | |
509 | * | |
510 | * @param cdev | |
511 | * | |
512 | * @return 0 on success, error otherwise. | |
513 | */ | |
514 | int (*selftest_memory)(struct qed_dev *cdev); | |
515 | ||
516 | /** | |
517 | * @brief selftest_register - Perform register test | |
518 | * | |
519 | * @param cdev | |
520 | * | |
521 | * @return 0 on success, error otherwise. | |
522 | */ | |
523 | int (*selftest_register)(struct qed_dev *cdev); | |
524 | ||
525 | /** | |
526 | * @brief selftest_clock - Perform clock test | |
527 | * | |
528 | * @param cdev | |
529 | * | |
530 | * @return 0 on success, error otherwise. | |
531 | */ | |
532 | int (*selftest_clock)(struct qed_dev *cdev); | |
7a4b21b7 MY |
533 | |
534 | /** | |
535 | * @brief selftest_nvram - Perform nvram test | |
536 | * | |
537 | * @param cdev | |
538 | * | |
539 | * @return 0 on success, error otherwise. | |
540 | */ | |
541 | int (*selftest_nvram) (struct qed_dev *cdev); | |
03dc76ca SRK |
542 | }; |
543 | ||
fe56b9e6 | 544 | struct qed_common_ops { |
03dc76ca SRK |
545 | struct qed_selftest_ops *selftest; |
546 | ||
fe56b9e6 | 547 | struct qed_dev* (*probe)(struct pci_dev *dev, |
1408cc1f | 548 | struct qed_probe_params *params); |
fe56b9e6 YM |
549 | |
550 | void (*remove)(struct qed_dev *cdev); | |
551 | ||
552 | int (*set_power_state)(struct qed_dev *cdev, | |
553 | pci_power_t state); | |
554 | ||
712c3cbf | 555 | void (*set_name) (struct qed_dev *cdev, char name[]); |
fe56b9e6 YM |
556 | |
557 | /* Client drivers need to make this call before slowpath_start. | |
558 | * PF params required for the call before slowpath_start is | |
559 | * documented within the qed_pf_params structure definition. | |
560 | */ | |
561 | void (*update_pf_params)(struct qed_dev *cdev, | |
562 | struct qed_pf_params *params); | |
563 | int (*slowpath_start)(struct qed_dev *cdev, | |
564 | struct qed_slowpath_params *params); | |
565 | ||
566 | int (*slowpath_stop)(struct qed_dev *cdev); | |
567 | ||
568 | /* Requests to use `cnt' interrupts for fastpath. | |
569 | * upon success, returns number of interrupts allocated for fastpath. | |
570 | */ | |
571 | int (*set_fp_int)(struct qed_dev *cdev, | |
572 | u16 cnt); | |
573 | ||
574 | /* Fills `info' with pointers required for utilizing interrupts */ | |
575 | int (*get_fp_int)(struct qed_dev *cdev, | |
576 | struct qed_int_info *info); | |
577 | ||
578 | u32 (*sb_init)(struct qed_dev *cdev, | |
579 | struct qed_sb_info *sb_info, | |
580 | void *sb_virt_addr, | |
581 | dma_addr_t sb_phy_addr, | |
582 | u16 sb_id, | |
583 | enum qed_sb_type type); | |
584 | ||
585 | u32 (*sb_release)(struct qed_dev *cdev, | |
586 | struct qed_sb_info *sb_info, | |
587 | u16 sb_id); | |
588 | ||
589 | void (*simd_handler_config)(struct qed_dev *cdev, | |
590 | void *token, | |
591 | int index, | |
592 | void (*handler)(void *)); | |
593 | ||
594 | void (*simd_handler_clean)(struct qed_dev *cdev, | |
595 | int index); | |
1e128c81 AE |
596 | int (*dbg_grc)(struct qed_dev *cdev, |
597 | void *buffer, u32 *num_dumped_bytes); | |
598 | ||
599 | int (*dbg_grc_size)(struct qed_dev *cdev); | |
fe7cd2bf | 600 | |
e0971c83 TT |
601 | int (*dbg_all_data) (struct qed_dev *cdev, void *buffer); |
602 | ||
603 | int (*dbg_all_data_size) (struct qed_dev *cdev); | |
604 | ||
fe7cd2bf YM |
605 | /** |
606 | * @brief can_link_change - can the instance change the link or not | |
607 | * | |
608 | * @param cdev | |
609 | * | |
610 | * @return true if link-change is allowed, false otherwise. | |
611 | */ | |
612 | bool (*can_link_change)(struct qed_dev *cdev); | |
613 | ||
fe56b9e6 YM |
614 | /** |
615 | * @brief set_link - set links according to params | |
616 | * | |
617 | * @param cdev | |
618 | * @param params - values used to override the default link configuration | |
619 | * | |
620 | * @return 0 on success, error otherwise. | |
621 | */ | |
622 | int (*set_link)(struct qed_dev *cdev, | |
623 | struct qed_link_params *params); | |
624 | ||
625 | /** | |
626 | * @brief get_link - returns the current link state. | |
627 | * | |
628 | * @param cdev | |
629 | * @param if_link - structure to be filled with current link configuration. | |
630 | */ | |
631 | void (*get_link)(struct qed_dev *cdev, | |
632 | struct qed_link_output *if_link); | |
633 | ||
634 | /** | |
635 | * @brief - drains chip in case Tx completions fail to arrive due to pause. | |
636 | * | |
637 | * @param cdev | |
638 | */ | |
639 | int (*drain)(struct qed_dev *cdev); | |
640 | ||
641 | /** | |
642 | * @brief update_msglvl - update module debug level | |
643 | * | |
644 | * @param cdev | |
645 | * @param dp_module | |
646 | * @param dp_level | |
647 | */ | |
648 | void (*update_msglvl)(struct qed_dev *cdev, | |
649 | u32 dp_module, | |
650 | u8 dp_level); | |
651 | ||
652 | int (*chain_alloc)(struct qed_dev *cdev, | |
653 | enum qed_chain_use_mode intended_use, | |
654 | enum qed_chain_mode mode, | |
a91eb52a YM |
655 | enum qed_chain_cnt_type cnt_type, |
656 | u32 num_elems, | |
fe56b9e6 | 657 | size_t elem_size, |
1a4a6975 MY |
658 | struct qed_chain *p_chain, |
659 | struct qed_chain_ext_pbl *ext_pbl); | |
fe56b9e6 YM |
660 | |
661 | void (*chain_free)(struct qed_dev *cdev, | |
662 | struct qed_chain *p_chain); | |
91420b83 | 663 | |
20675b37 MY |
664 | /** |
665 | * @brief nvm_get_image - reads an entire image from nvram | |
666 | * | |
667 | * @param cdev | |
668 | * @param type - type of the request nvram image | |
669 | * @param buf - preallocated buffer to fill with the image | |
670 | * @param len - length of the allocated buffer | |
671 | * | |
672 | * @return 0 on success, error otherwise | |
673 | */ | |
674 | int (*nvm_get_image)(struct qed_dev *cdev, | |
675 | enum qed_nvm_images type, u8 *buf, u16 len); | |
676 | ||
722003ac SRK |
677 | /** |
678 | * @brief set_coalesce - Configure Rx coalesce value in usec | |
679 | * | |
680 | * @param cdev | |
681 | * @param rx_coal - Rx coalesce value in usec | |
682 | * @param tx_coal - Tx coalesce value in usec | |
683 | * @param qid - Queue index | |
684 | * @param sb_id - Status Block Id | |
685 | * | |
686 | * @return 0 on success, error otherwise. | |
687 | */ | |
477f2d14 RV |
688 | int (*set_coalesce)(struct qed_dev *cdev, |
689 | u16 rx_coal, u16 tx_coal, void *handle); | |
722003ac | 690 | |
91420b83 SK |
691 | /** |
692 | * @brief set_led - Configure LED mode | |
693 | * | |
694 | * @param cdev | |
695 | * @param mode - LED mode | |
696 | * | |
697 | * @return 0 on success, error otherwise. | |
698 | */ | |
699 | int (*set_led)(struct qed_dev *cdev, | |
700 | enum qed_led_mode mode); | |
0fefbfba SK |
701 | |
702 | /** | |
703 | * @brief update_drv_state - API to inform the change in the driver state. | |
704 | * | |
705 | * @param cdev | |
706 | * @param active | |
707 | * | |
708 | */ | |
709 | int (*update_drv_state)(struct qed_dev *cdev, bool active); | |
710 | ||
711 | /** | |
712 | * @brief update_mac - API to inform the change in the mac address | |
713 | * | |
714 | * @param cdev | |
715 | * @param mac | |
716 | * | |
717 | */ | |
718 | int (*update_mac)(struct qed_dev *cdev, u8 *mac); | |
719 | ||
720 | /** | |
721 | * @brief update_mtu - API to inform the change in the mtu | |
722 | * | |
723 | * @param cdev | |
724 | * @param mtu | |
725 | * | |
726 | */ | |
727 | int (*update_mtu)(struct qed_dev *cdev, u16 mtu); | |
14d39648 MY |
728 | |
729 | /** | |
730 | * @brief update_wol - update of changes in the WoL configuration | |
731 | * | |
732 | * @param cdev | |
733 | * @param enabled - true iff WoL should be enabled. | |
734 | */ | |
735 | int (*update_wol) (struct qed_dev *cdev, bool enabled); | |
fe56b9e6 YM |
736 | }; |
737 | ||
fe56b9e6 YM |
738 | #define MASK_FIELD(_name, _value) \ |
739 | ((_value) &= (_name ## _MASK)) | |
740 | ||
741 | #define FIELD_VALUE(_name, _value) \ | |
742 | ((_value & _name ## _MASK) << _name ## _SHIFT) | |
743 | ||
744 | #define SET_FIELD(value, name, flag) \ | |
745 | do { \ | |
746 | (value) &= ~(name ## _MASK << name ## _SHIFT); \ | |
747 | (value) |= (((u64)flag) << (name ## _SHIFT)); \ | |
748 | } while (0) | |
749 | ||
750 | #define GET_FIELD(value, name) \ | |
751 | (((value) >> (name ## _SHIFT)) & name ## _MASK) | |
752 | ||
753 | /* Debug print definitions */ | |
9d7650c2 MY |
754 | #define DP_ERR(cdev, fmt, ...) \ |
755 | do { \ | |
756 | pr_err("[%s:%d(%s)]" fmt, \ | |
757 | __func__, __LINE__, \ | |
758 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
759 | ## __VA_ARGS__); \ | |
760 | } while (0) | |
fe56b9e6 YM |
761 | |
762 | #define DP_NOTICE(cdev, fmt, ...) \ | |
763 | do { \ | |
764 | if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \ | |
765 | pr_notice("[%s:%d(%s)]" fmt, \ | |
766 | __func__, __LINE__, \ | |
767 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
768 | ## __VA_ARGS__); \ | |
769 | \ | |
770 | } \ | |
771 | } while (0) | |
772 | ||
773 | #define DP_INFO(cdev, fmt, ...) \ | |
774 | do { \ | |
775 | if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \ | |
776 | pr_notice("[%s:%d(%s)]" fmt, \ | |
777 | __func__, __LINE__, \ | |
778 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
779 | ## __VA_ARGS__); \ | |
780 | } \ | |
781 | } while (0) | |
782 | ||
783 | #define DP_VERBOSE(cdev, module, fmt, ...) \ | |
784 | do { \ | |
785 | if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \ | |
786 | ((cdev)->dp_module & module))) { \ | |
787 | pr_notice("[%s:%d(%s)]" fmt, \ | |
788 | __func__, __LINE__, \ | |
789 | DP_NAME(cdev) ? DP_NAME(cdev) : "", \ | |
790 | ## __VA_ARGS__); \ | |
791 | } \ | |
792 | } while (0) | |
793 | ||
794 | enum DP_LEVEL { | |
795 | QED_LEVEL_VERBOSE = 0x0, | |
796 | QED_LEVEL_INFO = 0x1, | |
797 | QED_LEVEL_NOTICE = 0x2, | |
798 | QED_LEVEL_ERR = 0x3, | |
799 | }; | |
800 | ||
801 | #define QED_LOG_LEVEL_SHIFT (30) | |
802 | #define QED_LOG_VERBOSE_MASK (0x3fffffff) | |
803 | #define QED_LOG_INFO_MASK (0x40000000) | |
804 | #define QED_LOG_NOTICE_MASK (0x80000000) | |
805 | ||
806 | enum DP_MODULE { | |
807 | QED_MSG_SPQ = 0x10000, | |
808 | QED_MSG_STATS = 0x20000, | |
809 | QED_MSG_DCB = 0x40000, | |
810 | QED_MSG_IOV = 0x80000, | |
811 | QED_MSG_SP = 0x100000, | |
812 | QED_MSG_STORAGE = 0x200000, | |
813 | QED_MSG_CXT = 0x800000, | |
0a7fb11c | 814 | QED_MSG_LL2 = 0x1000000, |
fe56b9e6 | 815 | QED_MSG_ILT = 0x2000000, |
51ff1725 | 816 | QED_MSG_RDMA = 0x4000000, |
fe56b9e6 YM |
817 | QED_MSG_DEBUG = 0x8000000, |
818 | /* to be added...up to 0x8000000 */ | |
819 | }; | |
820 | ||
fc48b7a6 YM |
821 | enum qed_mf_mode { |
822 | QED_MF_DEFAULT, | |
823 | QED_MF_OVLAN, | |
824 | QED_MF_NPAR, | |
825 | }; | |
826 | ||
9c79ddaa | 827 | struct qed_eth_stats_common { |
fe56b9e6 YM |
828 | u64 no_buff_discards; |
829 | u64 packet_too_big_discard; | |
830 | u64 ttl0_discard; | |
831 | u64 rx_ucast_bytes; | |
832 | u64 rx_mcast_bytes; | |
833 | u64 rx_bcast_bytes; | |
834 | u64 rx_ucast_pkts; | |
835 | u64 rx_mcast_pkts; | |
836 | u64 rx_bcast_pkts; | |
837 | u64 mftag_filter_discards; | |
838 | u64 mac_filter_discards; | |
839 | u64 tx_ucast_bytes; | |
840 | u64 tx_mcast_bytes; | |
841 | u64 tx_bcast_bytes; | |
842 | u64 tx_ucast_pkts; | |
843 | u64 tx_mcast_pkts; | |
844 | u64 tx_bcast_pkts; | |
845 | u64 tx_err_drop_pkts; | |
846 | u64 tpa_coalesced_pkts; | |
847 | u64 tpa_coalesced_events; | |
848 | u64 tpa_aborts_num; | |
849 | u64 tpa_not_coalesced_pkts; | |
850 | u64 tpa_coalesced_bytes; | |
851 | ||
852 | /* port */ | |
853 | u64 rx_64_byte_packets; | |
d4967cf3 YM |
854 | u64 rx_65_to_127_byte_packets; |
855 | u64 rx_128_to_255_byte_packets; | |
856 | u64 rx_256_to_511_byte_packets; | |
857 | u64 rx_512_to_1023_byte_packets; | |
858 | u64 rx_1024_to_1518_byte_packets; | |
fe56b9e6 YM |
859 | u64 rx_crc_errors; |
860 | u64 rx_mac_crtl_frames; | |
861 | u64 rx_pause_frames; | |
862 | u64 rx_pfc_frames; | |
863 | u64 rx_align_errors; | |
864 | u64 rx_carrier_errors; | |
865 | u64 rx_oversize_packets; | |
866 | u64 rx_jabbers; | |
867 | u64 rx_undersize_packets; | |
868 | u64 rx_fragments; | |
869 | u64 tx_64_byte_packets; | |
870 | u64 tx_65_to_127_byte_packets; | |
871 | u64 tx_128_to_255_byte_packets; | |
872 | u64 tx_256_to_511_byte_packets; | |
873 | u64 tx_512_to_1023_byte_packets; | |
874 | u64 tx_1024_to_1518_byte_packets; | |
fe56b9e6 YM |
875 | u64 tx_pause_frames; |
876 | u64 tx_pfc_frames; | |
fe56b9e6 YM |
877 | u64 brb_truncates; |
878 | u64 brb_discards; | |
879 | u64 rx_mac_bytes; | |
880 | u64 rx_mac_uc_packets; | |
881 | u64 rx_mac_mc_packets; | |
882 | u64 rx_mac_bc_packets; | |
883 | u64 rx_mac_frames_ok; | |
884 | u64 tx_mac_bytes; | |
885 | u64 tx_mac_uc_packets; | |
886 | u64 tx_mac_mc_packets; | |
887 | u64 tx_mac_bc_packets; | |
888 | u64 tx_mac_ctrl_frames; | |
889 | }; | |
890 | ||
9c79ddaa MY |
891 | struct qed_eth_stats_bb { |
892 | u64 rx_1519_to_1522_byte_packets; | |
893 | u64 rx_1519_to_2047_byte_packets; | |
894 | u64 rx_2048_to_4095_byte_packets; | |
895 | u64 rx_4096_to_9216_byte_packets; | |
896 | u64 rx_9217_to_16383_byte_packets; | |
897 | u64 tx_1519_to_2047_byte_packets; | |
898 | u64 tx_2048_to_4095_byte_packets; | |
899 | u64 tx_4096_to_9216_byte_packets; | |
900 | u64 tx_9217_to_16383_byte_packets; | |
901 | u64 tx_lpi_entry_count; | |
902 | u64 tx_total_collisions; | |
903 | }; | |
904 | ||
905 | struct qed_eth_stats_ah { | |
906 | u64 rx_1519_to_max_byte_packets; | |
907 | u64 tx_1519_to_max_byte_packets; | |
908 | }; | |
909 | ||
910 | struct qed_eth_stats { | |
911 | struct qed_eth_stats_common common; | |
912 | ||
913 | union { | |
914 | struct qed_eth_stats_bb bb; | |
915 | struct qed_eth_stats_ah ah; | |
916 | }; | |
917 | }; | |
918 | ||
fe56b9e6 YM |
919 | #define QED_SB_IDX 0x0002 |
920 | ||
921 | #define RX_PI 0 | |
922 | #define TX_PI(tc) (RX_PI + 1 + tc) | |
923 | ||
4ac801b7 | 924 | struct qed_sb_cnt_info { |
726fdbe9 MY |
925 | /* Original, current, and free SBs for PF */ |
926 | int orig; | |
927 | int cnt; | |
928 | int free_cnt; | |
929 | ||
930 | /* Original, current and free SBS for child VFs */ | |
931 | int iov_orig; | |
932 | int iov_cnt; | |
933 | int free_cnt_iov; | |
4ac801b7 YM |
934 | }; |
935 | ||
fe56b9e6 YM |
936 | static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info) |
937 | { | |
938 | u32 prod = 0; | |
939 | u16 rc = 0; | |
940 | ||
941 | prod = le32_to_cpu(sb_info->sb_virt->prod_index) & | |
942 | STATUS_BLOCK_PROD_INDEX_MASK; | |
943 | if (sb_info->sb_ack != prod) { | |
944 | sb_info->sb_ack = prod; | |
945 | rc |= QED_SB_IDX; | |
946 | } | |
947 | ||
948 | /* Let SB update */ | |
949 | mmiowb(); | |
950 | return rc; | |
951 | } | |
952 | ||
953 | /** | |
954 | * | |
955 | * @brief This function creates an update command for interrupts that is | |
956 | * written to the IGU. | |
957 | * | |
958 | * @param sb_info - This is the structure allocated and | |
959 | * initialized per status block. Assumption is | |
960 | * that it was initialized using qed_sb_init | |
961 | * @param int_cmd - Enable/Disable/Nop | |
962 | * @param upd_flg - whether igu consumer should be | |
963 | * updated. | |
964 | * | |
965 | * @return inline void | |
966 | */ | |
967 | static inline void qed_sb_ack(struct qed_sb_info *sb_info, | |
968 | enum igu_int_cmd int_cmd, | |
969 | u8 upd_flg) | |
970 | { | |
971 | struct igu_prod_cons_update igu_ack = { 0 }; | |
972 | ||
973 | igu_ack.sb_id_and_flags = | |
974 | ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | | |
975 | (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | | |
976 | (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | | |
977 | (IGU_SEG_ACCESS_REG << | |
978 | IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); | |
979 | ||
980 | DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); | |
981 | ||
982 | /* Both segments (interrupts & acks) are written to same place address; | |
983 | * Need to guarantee all commands will be received (in-order) by HW. | |
984 | */ | |
985 | mmiowb(); | |
986 | barrier(); | |
987 | } | |
988 | ||
989 | static inline void __internal_ram_wr(void *p_hwfn, | |
990 | void __iomem *addr, | |
991 | int size, | |
992 | u32 *data) | |
993 | ||
994 | { | |
995 | unsigned int i; | |
996 | ||
997 | for (i = 0; i < size / sizeof(*data); i++) | |
998 | DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]); | |
999 | } | |
1000 | ||
1001 | static inline void internal_ram_wr(void __iomem *addr, | |
1002 | int size, | |
1003 | u32 *data) | |
1004 | { | |
1005 | __internal_ram_wr(NULL, addr, size, data); | |
1006 | } | |
1007 | ||
8c5ebd0c SRK |
1008 | enum qed_rss_caps { |
1009 | QED_RSS_IPV4 = 0x1, | |
1010 | QED_RSS_IPV6 = 0x2, | |
1011 | QED_RSS_IPV4_TCP = 0x4, | |
1012 | QED_RSS_IPV6_TCP = 0x8, | |
1013 | QED_RSS_IPV4_UDP = 0x10, | |
1014 | QED_RSS_IPV6_UDP = 0x20, | |
1015 | }; | |
1016 | ||
1017 | #define QED_RSS_IND_TABLE_SIZE 128 | |
1018 | #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */ | |
fe56b9e6 | 1019 | #endif |