[mirror_ubuntu-zesty-kernel.git] / include / media / i2c / adv7842.h

/*
 * adv7842 - Analog Devices ADV7842 video decoder driver
 *
 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
 *
 * This program is free software; you may redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _ADV7842_
#define _ADV7842_

/* Analog input muxing modes (AFE register 0x02, [2:0]) */
enum adv7842_ain_sel {
	ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
	ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
	ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
	ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
	ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
};

/*
 * Bus rotation and reordering. This is used to specify component reordering on
 * the board and describes the components order on the bus when the ADV7842
 * outputs RGB.
 */
enum adv7842_bus_order {
	ADV7842_BUS_ORDER_RGB,		/* No operation	*/
	ADV7842_BUS_ORDER_GRB,		/* Swap 1-2	*/
	ADV7842_BUS_ORDER_RBG,		/* Swap 2-3	*/
	ADV7842_BUS_ORDER_BGR,		/* Swap 1-3	*/
	ADV7842_BUS_ORDER_BRG,		/* Rotate right	*/
	ADV7842_BUS_ORDER_GBR,		/* Rotate left	*/
};

/* Input Color Space (IO register 0x02, [7:4]) */
enum adv7842_inp_color_space {
	ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
	ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
	ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
	ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
	ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
	ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
	ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
	ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
	ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
};

/* Select output format (IO register 0x03, [4:2]) */
enum adv7842_op_format_mode_sel {
	ADV7842_OP_FORMAT_MODE0 = 0x00,
	ADV7842_OP_FORMAT_MODE1 = 0x04,
	ADV7842_OP_FORMAT_MODE2 = 0x08,
};

/* Mode of operation */
enum adv7842_mode {
	ADV7842_MODE_SDP,
	ADV7842_MODE_COMP,
	ADV7842_MODE_RGB,
	ADV7842_MODE_HDMI
};

/* Video standard select (IO register 0x00, [5:0]) */
enum adv7842_vid_std_select {
	/* SDP */
	ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
	ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
	/* RGB */
	ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
	/* HDMI GR */
	ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
	/* HDMI COMP */
	ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
};

enum adv7842_select_input {
	ADV7842_SELECT_HDMI_PORT_A,
	ADV7842_SELECT_HDMI_PORT_B,
	ADV7842_SELECT_VGA_RGB,
	ADV7842_SELECT_VGA_COMP,
	ADV7842_SELECT_SDP_CVBS,
	ADV7842_SELECT_SDP_YC,
};

enum adv7842_drive_strength {
	ADV7842_DR_STR_LOW = 0,
	ADV7842_DR_STR_MEDIUM_LOW = 1,
	ADV7842_DR_STR_MEDIUM_HIGH = 2,
	ADV7842_DR_STR_HIGH = 3,
};

struct adv7842_sdp_csc_coeff {
	bool manual;
	u16 scaling;
	u16 A1;
	u16 A2;
	u16 A3;
	u16 A4;
	u16 B1;
	u16 B2;
	u16 B3;
	u16 B4;
	u16 C1;
	u16 C2;
	u16 C3;
	u16 C4;
};

struct adv7842_sdp_io_sync_adjustment {
	bool adjust;
	u16 hs_beg;
	u16 hs_width;
	u16 de_beg;
	u16 de_end;
	u8 vs_beg_o;
	u8 vs_beg_e;
	u8 vs_end_o;
	u8 vs_end_e;
	u8 de_v_beg_o;
	u8 de_v_beg_e;
	u8 de_v_end_o;
	u8 de_v_end_e;
};

/* Platform dependent definition */
struct adv7842_platform_data {
	/* chip reset during probe */
	unsigned chip_reset:1;

	/* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
	unsigned disable_pwrdnb:1;

	/* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
	unsigned disable_cable_det_rst:1;

	/* Analog input muxing mode */
	enum adv7842_ain_sel ain_sel;

	/* Bus rotation and reordering */
	enum adv7842_bus_order bus_order;

	/* Select output format mode */
	enum adv7842_op_format_mode_sel op_format_mode_sel;

	/* Default mode */
	enum adv7842_mode mode;

	/* Default input */
	unsigned input;

	/* Video standard */
	enum adv7842_vid_std_select vid_std_select;

	/* IO register 0x02 */
	unsigned alt_gamma:1;

	/* IO register 0x05 */
	unsigned blank_data:1;
	unsigned insert_av_codes:1;
	unsigned replicate_av_codes:1;

	/* IO register 0x30 */
	unsigned output_bus_lsb_to_msb:1;

	/* IO register 0x14 */
	enum adv7842_drive_strength dr_str_data;
	enum adv7842_drive_strength dr_str_clk;
	enum adv7842_drive_strength dr_str_sync;

	/*
	 * IO register 0x19: Adjustment to the LLC DLL phase in
	 * increments of 1/32 of a clock period.
	 */
	unsigned llc_dll_phase:5;

	/* External RAM for 3-D comb or frame synchronizer */
	unsigned sd_ram_size; /* ram size in MB */
	unsigned sd_ram_ddr:1; /* ddr or sdr sdram */

	/* HDMI free run, CP-reg 0xBA */
	unsigned hdmi_free_run_enable:1;
	/* 0 = Mode 0: run when there is no TMDS clock
	   1 = Mode 1: run when there is no TMDS clock or the
	       video resolution does not match programmed one. */
	unsigned hdmi_free_run_mode:1;

	/* SDP free run, CP-reg 0xDD */
	unsigned sdp_free_run_auto:1;
	unsigned sdp_free_run_man_col_en:1;
	unsigned sdp_free_run_cbar_en:1;
	unsigned sdp_free_run_force:1;

	/* HPA manual (0) or auto (1), affects HDMI register 0x69 */
	unsigned hpa_auto:1;

	struct adv7842_sdp_csc_coeff sdp_csc_coeff;

	struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
	struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;

	/* i2c addresses */
	u8 i2c_sdp_io;
	u8 i2c_sdp;
	u8 i2c_cp;
	u8 i2c_vdp;
	u8 i2c_afe;
	u8 i2c_hdmi;
	u8 i2c_repeater;
	u8 i2c_edid;
	u8 i2c_infoframe;
	u8 i2c_cec;
	u8 i2c_avlink;
};

#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE	(V4L2_CID_DV_CLASS_BASE + 0x1000)
#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL	(V4L2_CID_DV_CLASS_BASE + 0x1001)
#define V4L2_CID_ADV_RX_FREE_RUN_COLOR		(V4L2_CID_DV_CLASS_BASE + 0x1002)

/* custom ioctl, used to test the external RAM that's used by the
 * deinterlacer. */
#define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)

#define ADV7842_EDID_PORT_A   0
#define ADV7842_EDID_PORT_B   1
#define ADV7842_EDID_PORT_VGA 2
#define ADV7842_PAD_SOURCE    3

#endif
Commit	Line	Data
a89bcd4c HV	1	/*
	2	* adv7842 - Analog Devices ADV7842 video decoder driver
	3	*
	4	* Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
	5	*
	6	* This program is free software; you may redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; version 2 of the License.
	9	*
	10	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	11	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	12	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	13	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	14	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	15	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	16	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	17	* SOFTWARE.
	18	*
	19	*/
	20
	21	#ifndef _ADV7842_
	22	#define _ADV7842_
	23
	24	/* Analog input muxing modes (AFE register 0x02, [2:0]) */
	25	enum adv7842_ain_sel {
	26	ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
	27	ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
	28	ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
	29	ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
	30	ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
	31	};
	32
f888ae7e HV	33	/*
	34	* Bus rotation and reordering. This is used to specify component reordering on
	35	* the board and describes the components order on the bus when the ADV7842
	36	* outputs RGB.
	37	*/
	38	enum adv7842_bus_order {
	39	ADV7842_BUS_ORDER_RGB, /* No operation */
	40	ADV7842_BUS_ORDER_GRB, /* Swap 1-2 */
	41	ADV7842_BUS_ORDER_RBG, /* Swap 2-3 */
	42	ADV7842_BUS_ORDER_BGR, /* Swap 1-3 */
	43	ADV7842_BUS_ORDER_BRG, /* Rotate right */
	44	ADV7842_BUS_ORDER_GBR, /* Rotate left */
	45	};
	46
	47	/* Input Color Space (IO register 0x02, [7:4]) */
	48	enum adv7842_inp_color_space {
	49	ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
	50	ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
	51	ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
	52	ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
	53	ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
	54	ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
	55	ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
	56	ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
	57	ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
	58	};
	59
	60	/* Select output format (IO register 0x03, [4:2]) */
	61	enum adv7842_op_format_mode_sel {
	62	ADV7842_OP_FORMAT_MODE0 = 0x00,
	63	ADV7842_OP_FORMAT_MODE1 = 0x04,
	64	ADV7842_OP_FORMAT_MODE2 = 0x08,
a89bcd4c HV	65	};
	66
	67	/* Mode of operation */
	68	enum adv7842_mode {
	69	ADV7842_MODE_SDP,
	70	ADV7842_MODE_COMP,
	71	ADV7842_MODE_RGB,
	72	ADV7842_MODE_HDMI
	73	};
	74
	75	/* Video standard select (IO register 0x00, [5:0]) */
	76	enum adv7842_vid_std_select {
	77	/* SDP */
	78	ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
	79	ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
	80	/* RGB */
	81	ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
	82	/* HDMI GR */
	83	ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
	84	/* HDMI COMP */
	85	ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
	86	};
	87
a89bcd4c HV	88	enum adv7842_select_input {
	89	ADV7842_SELECT_HDMI_PORT_A,
	90	ADV7842_SELECT_HDMI_PORT_B,
	91	ADV7842_SELECT_VGA_RGB,
	92	ADV7842_SELECT_VGA_COMP,
	93	ADV7842_SELECT_SDP_CVBS,
	94	ADV7842_SELECT_SDP_YC,
	95	};
	96
7f95c904 HV	97	enum adv7842_drive_strength {
	98	ADV7842_DR_STR_LOW = 0,
	99	ADV7842_DR_STR_MEDIUM_LOW = 1,
	100	ADV7842_DR_STR_MEDIUM_HIGH = 2,
	101	ADV7842_DR_STR_HIGH = 3,
	102	};
	103
a89bcd4c HV	104	struct adv7842_sdp_csc_coeff {
a89bcd4c HV	105	bool manual;
28a769f1 HV	106	u16 scaling;
	107	u16 A1;
	108	u16 A2;
	109	u16 A3;
	110	u16 A4;
	111	u16 B1;
	112	u16 B2;
	113	u16 B3;
	114	u16 B4;
	115	u16 C1;
	116	u16 C2;
	117	u16 C3;
	118	u16 C4;
a89bcd4c HV	119	};
	120
	121	struct adv7842_sdp_io_sync_adjustment {
	122	bool adjust;
28a769f1 HV	123	u16 hs_beg;
	124	u16 hs_width;
	125	u16 de_beg;
	126	u16 de_end;
	127	u8 vs_beg_o;
	128	u8 vs_beg_e;
	129	u8 vs_end_o;
	130	u8 vs_end_e;
	131	u8 de_v_beg_o;
	132	u8 de_v_beg_e;
	133	u8 de_v_end_o;
	134	u8 de_v_end_e;
a89bcd4c HV	135	};
	136
	137	/* Platform dependent definition */
	138	struct adv7842_platform_data {
a89bcd4c HV	139	/* chip reset during probe */
	140	unsigned chip_reset:1;
	141
	142	/* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
	143	unsigned disable_pwrdnb:1;
	144
	145	/* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
	146	unsigned disable_cable_det_rst:1;
	147
	148	/* Analog input muxing mode */
	149	enum adv7842_ain_sel ain_sel;
	150
	151	/* Bus rotation and reordering */
f888ae7e HV	152	enum adv7842_bus_order bus_order;
	153
	154	/* Select output format mode */
	155	enum adv7842_op_format_mode_sel op_format_mode_sel;
a89bcd4c HV	156
	157	/* Default mode */
	158	enum adv7842_mode mode;
	159
8e4e3631 MB	160	/* Default input */
	161	unsigned input;
	162
a89bcd4c HV	163	/* Video standard */
	164	enum adv7842_vid_std_select vid_std_select;
	165
a89bcd4c HV	166	/* IO register 0x02 */
a89bcd4c HV	167	unsigned alt_gamma:1;
a89bcd4c HV	168
	169	/* IO register 0x05 */
	170	unsigned blank_data:1;
	171	unsigned insert_av_codes:1;
	172	unsigned replicate_av_codes:1;
a89bcd4c HV	173
	174	/* IO register 0x30 */
	175	unsigned output_bus_lsb_to_msb:1;
	176
	177	/* IO register 0x14 */
7f95c904 HV	178	enum adv7842_drive_strength dr_str_data;
	179	enum adv7842_drive_strength dr_str_clk;
	180	enum adv7842_drive_strength dr_str_sync;
a89bcd4c	181
fe808f3c HV	182	/*
	183	* IO register 0x19: Adjustment to the LLC DLL phase in
	184	* increments of 1/32 of a clock period.
	185	*/
	186	unsigned llc_dll_phase:5;
	187
a89bcd4c HV	188	/* External RAM for 3-D comb or frame synchronizer */
	189	unsigned sd_ram_size; /* ram size in MB */
	190	unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
	191
f0ec1742 MB	192	/* HDMI free run, CP-reg 0xBA */
	193	unsigned hdmi_free_run_enable:1;
	194	/* 0 = Mode 0: run when there is no TMDS clock
	195	1 = Mode 1: run when there is no TMDS clock or the
	196	video resolution does not match programmed one. */
	197	unsigned hdmi_free_run_mode:1;
	198
	199	/* SDP free run, CP-reg 0xDD */
	200	unsigned sdp_free_run_auto:1;
	201	unsigned sdp_free_run_man_col_en:1;
	202	unsigned sdp_free_run_cbar_en:1;
	203	unsigned sdp_free_run_force:1;
a89bcd4c	204
ce2d2b2d MB	205	/* HPA manual (0) or auto (1), affects HDMI register 0x69 */
	206	unsigned hpa_auto:1;
	207
a89bcd4c HV	208	struct adv7842_sdp_csc_coeff sdp_csc_coeff;
a89bcd4c HV	209
3c4da74f MB	210	struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
3c4da74f MB	211	struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;
a89bcd4c HV	212
	213	/* i2c addresses */
	214	u8 i2c_sdp_io;
	215	u8 i2c_sdp;
	216	u8 i2c_cp;
	217	u8 i2c_vdp;
	218	u8 i2c_afe;
	219	u8 i2c_hdmi;
	220	u8 i2c_repeater;
	221	u8 i2c_edid;
	222	u8 i2c_infoframe;
	223	u8 i2c_cec;
	224	u8 i2c_avlink;
	225	};
	226
	227	#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
	228	#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
	229	#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
	230
a89bcd4c HV	231	/* custom ioctl, used to test the external RAM that's used by the
	232	* deinterlacer. */
	233	#define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)
	234
7de6fab1 MR	235	#define ADV7842_EDID_PORT_A 0
	236	#define ADV7842_EDID_PORT_B 1
	237	#define ADV7842_EDID_PORT_VGA 2
f888ae7e	238	#define ADV7842_PAD_SOURCE 3
7de6fab1	239
a89bcd4c	240	#endif